binutils-gdb/sim/testsuite/aarch64/fcsel.s

# mach: aarch64

# Check the FP Conditional Select instruction: fcsel.
# Check 1/1 eq/neg, and 1/2 lt/gt.

.include "testutils.inc"

	start
	fmov s0, #1.0
	fmov s1, #1.0
	fmov s2, #-1.0
	fcmp s0, s1
	fcsel s3, s0, s2, eq
	fcmp s3, s0
	bne .Lfailure
	fcsel s3, s0, s2, ne
	fcmp s3, s2
	bne .Lfailure

	fmov s0, #1.0
	fmov s1, #2.0
	fcmp s0, s1
	fcsel s3, s0, s2, lt
	fcmp s3, s0
	bne .Lfailure
	fcsel s3, s0, s2, gt
	fcmp s3, s2
	bne .Lfailure

	fmov d0, #1.0
	fmov d1, #1.0
	fmov d2, #-1.0
	fcmp d0, d1
	fcsel d3, d0, d2, eq
	fcmp d3, d0
	bne .Lfailure
	fcsel d3, d0, d2, ne
	fcmp d3, d2
	bne .Lfailure

	fmov d0, #1.0
	fmov d1, #2.0
	fcmp d0, d1
	fcsel d3, d0, d2, lt
	fcmp d3, d0
	bne .Lfailure
	fcsel d3, d0, d2, gt
	fcmp d3, d2
	bne .Lfailure

	pass
.Lfailure:
	fail
Five fixes, for fcsel, fcvtz, fminnm, mls, and non-widening mul. sim/aarch64/ * cpustate.c: Include math.h. (aarch64_set_FP_float): Use signbit to check for signed zero. (aarch64_set_FP_double): Likewise. * simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break. (do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth args same size as third arg. (fmaxnm): Use isnan instead of fpclassify. (fminnm, dmaxnm, dminnm): Likewise. (do_vec_MLS): Reverse order of subtraction operands. (dexSimpleFPCondSelect): Call aarch64_get_FP_double or aarch64_get_FP_float to get source register contents. (UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN, DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN, DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New. (do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in raise_exception calls. sim/testsuite/sim/aarch64/ * fcsel.s: New. * fcvtz.s: New. * fminnm.s: New. * mls.s: New. * mul.s: New. 2017-01-05 08:05:27 +08:00			`# mach: aarch64`

			`# Check the FP Conditional Select instruction: fcsel.`
			`# Check 1/1 eq/neg, and 1/2 lt/gt.`

			`.include "testutils.inc"`

			`start`
			`fmov s0, #1.0`
			`fmov s1, #1.0`
			`fmov s2, #-1.0`
			`fcmp s0, s1`
			`fcsel s3, s0, s2, eq`
			`fcmp s3, s0`
			`bne .Lfailure`
			`fcsel s3, s0, s2, ne`
			`fcmp s3, s2`
			`bne .Lfailure`

			`fmov s0, #1.0`
			`fmov s1, #2.0`
			`fcmp s0, s1`
			`fcsel s3, s0, s2, lt`
			`fcmp s3, s0`
			`bne .Lfailure`
			`fcsel s3, s0, s2, gt`
			`fcmp s3, s2`
			`bne .Lfailure`

			`fmov d0, #1.0`
			`fmov d1, #1.0`
			`fmov d2, #-1.0`
			`fcmp d0, d1`
			`fcsel d3, d0, d2, eq`
			`fcmp d3, d0`
			`bne .Lfailure`
			`fcsel d3, d0, d2, ne`
			`fcmp d3, d2`
			`bne .Lfailure`

			`fmov d0, #1.0`
			`fmov d1, #2.0`
			`fcmp d0, d1`
			`fcsel d3, d0, d2, lt`
			`fcmp d3, d0`
			`bne .Lfailure`
			`fcsel d3, d0, d2, gt`
			`fcmp d3, d2`
			`bne .Lfailure`

			`pass`
			`.Lfailure:`
			`fail`