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binutils-gdb/gdb/riscv-tdep.h

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Minor formatting fixes in riscv-tdep.h This fixes some minor formatting issues in riscv-tdep.h, including one pointed out by ARI. ChangeLog 2018-08-09 Tom Tromey <tom@tromey.com> * riscv-tdep.h: Minor formatting fixes.
2018-08-10 00:46:01 +08:00
/* Target-dependent header for the RISC-V architecture, for GDB, the
GNU Debugger.
gdb: Initial baremetal riscv support This commit introduces basic support for baremetal RiscV as a GDB target. This target is currently only tested against the RiscV software simulator, which is not included as part of this commit. The target has been tested against the following RiscV variants: rv32im, rv32imc, rv32imf, rv32imfc, rv64im, rv64imc, rv64imfd, rv64imfdc. Across these variants we pass on average 34858 tests, and fail 272 tests, which is ~0.8%. The RiscV has a feature of its ABI where structures with a single floating point field, a single complex float field, or one float and one integer field are treated differently for argument passing. The new test gdb.base/infcall-nested-structs.exp is added to cover this feature. As passing these structures should work on all targets then I've made the test as a generic one, even though, for most targets, there's probably nothing special about any of these cases. gdb/ChangeLog: * Makefile.in (ALL_TARGET_OBS): Add riscv-tdep.o (HFILES_NO_SRCDIR): Add riscv-tdep.h. (ALLDEPFILES): Add riscv-tdep.c * configure.tgt: Add riscv support. * riscv-tdep.c: New file. * riscv-tdep.h: New file. * NEWS: Mention new target. * MAINTAINERS: Add entry for riscv. gdb/testsuite/ChangeLog: * gdb.base/infcall-nested-structs.exp: New file. * gdb.base/infcall-nested-structs.c: New file. * gdb.base/float.exp: Add riscv support.
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Copyright (C) 2018 Free Software Foundation, Inc.
This file is part of GDB.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
#ifndef RISCV_TDEP_H
#define RISCV_TDEP_H
/* RiscV register numbers. */
enum
{
RISCV_ZERO_REGNUM = 0, /* Read-only register, always 0. */
RISCV_RA_REGNUM = 1, /* Return Address. */
RISCV_SP_REGNUM = 2, /* Stack Pointer. */
RISCV_GP_REGNUM = 3, /* Global Pointer. */
RISCV_TP_REGNUM = 4, /* Thread Pointer. */
RISCV_FP_REGNUM = 8, /* Frame Pointer. */
RISCV_A0_REGNUM = 10, /* First argument. */
RISCV_A1_REGNUM = 11, /* Second argument. */
RISCV_PC_REGNUM = 32, /* Program Counter. */
gdb/riscv: Provide non-DWARF stack unwinder Collects information during the prologue scan and uses this to unwind registers when no DWARF information is available. This patch has been tested by disabling the DWARF stack unwinders, and running the complete GDB testsuite against a range of RISC-V targets. The results are comparable to running with the DWARF unwinders in place. gdb/ChangeLog: * riscv-tdep.c: Add 'prologue-value.h' include. (struct riscv_unwind_cache): New struct. (riscv_debug_unwinder): New global. (riscv_scan_prologue): Update arguments, capture register details from prologue scan. (riscv_skip_prologue): Reformat arguments line, move end of prologue calculation into riscv_scan_prologue. (riscv_frame_cache): Update return type, create riscv_unwind_cache, scan the prologue, and fill in remaining cache details. (riscv_frame_this_id): Use frame id computed in riscv_frame_cache. (riscv_frame_prev_register): Use the trad_frame within the riscv_unwind_cache. (_initialize_riscv_tdep): Add 'set/show debug riscv unwinder' flag.
2018-07-17 22:22:39 +08:00
RISCV_NUM_INTEGER_REGS = 32,
gdb: Initial baremetal riscv support This commit introduces basic support for baremetal RiscV as a GDB target. This target is currently only tested against the RiscV software simulator, which is not included as part of this commit. The target has been tested against the following RiscV variants: rv32im, rv32imc, rv32imf, rv32imfc, rv64im, rv64imc, rv64imfd, rv64imfdc. Across these variants we pass on average 34858 tests, and fail 272 tests, which is ~0.8%. The RiscV has a feature of its ABI where structures with a single floating point field, a single complex float field, or one float and one integer field are treated differently for argument passing. The new test gdb.base/infcall-nested-structs.exp is added to cover this feature. As passing these structures should work on all targets then I've made the test as a generic one, even though, for most targets, there's probably nothing special about any of these cases. gdb/ChangeLog: * Makefile.in (ALL_TARGET_OBS): Add riscv-tdep.o (HFILES_NO_SRCDIR): Add riscv-tdep.h. (ALLDEPFILES): Add riscv-tdep.c * configure.tgt: Add riscv support. * riscv-tdep.c: New file. * riscv-tdep.h: New file. * NEWS: Mention new target. * MAINTAINERS: Add entry for riscv. gdb/testsuite/ChangeLog: * gdb.base/infcall-nested-structs.exp: New file. * gdb.base/infcall-nested-structs.c: New file. * gdb.base/float.exp: Add riscv support.
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RISCV_FIRST_FP_REGNUM = 33, /* First Floating Point Register */
RISCV_FA0_REGNUM = 43,
RISCV_FA1_REGNUM = RISCV_FA0_REGNUM + 1,
RISCV_LAST_FP_REGNUM = 64, /* Last Floating Point Register */
RISCV_FIRST_CSR_REGNUM = 65, /* First CSR */
Minor formatting fixes in riscv-tdep.h This fixes some minor formatting issues in riscv-tdep.h, including one pointed out by ARI. ChangeLog 2018-08-09 Tom Tromey <tom@tromey.com> * riscv-tdep.h: Minor formatting fixes.
2018-08-10 00:46:01 +08:00
#define DECLARE_CSR(name, num) \
RISCV_ ## num ## _REGNUM = RISCV_FIRST_CSR_REGNUM + num,
gdb: Initial baremetal riscv support This commit introduces basic support for baremetal RiscV as a GDB target. This target is currently only tested against the RiscV software simulator, which is not included as part of this commit. The target has been tested against the following RiscV variants: rv32im, rv32imc, rv32imf, rv32imfc, rv64im, rv64imc, rv64imfd, rv64imfdc. Across these variants we pass on average 34858 tests, and fail 272 tests, which is ~0.8%. The RiscV has a feature of its ABI where structures with a single floating point field, a single complex float field, or one float and one integer field are treated differently for argument passing. The new test gdb.base/infcall-nested-structs.exp is added to cover this feature. As passing these structures should work on all targets then I've made the test as a generic one, even though, for most targets, there's probably nothing special about any of these cases. gdb/ChangeLog: * Makefile.in (ALL_TARGET_OBS): Add riscv-tdep.o (HFILES_NO_SRCDIR): Add riscv-tdep.h. (ALLDEPFILES): Add riscv-tdep.c * configure.tgt: Add riscv support. * riscv-tdep.c: New file. * riscv-tdep.h: New file. * NEWS: Mention new target. * MAINTAINERS: Add entry for riscv. gdb/testsuite/ChangeLog: * gdb.base/infcall-nested-structs.exp: New file. * gdb.base/infcall-nested-structs.c: New file. * gdb.base/float.exp: Add riscv support.
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#include "opcode/riscv-opc.h"
#undef DECLARE_CSR
RISCV_LAST_CSR_REGNUM = 4160,
RISC-V: Correct legacy misa register number. gdb/ * riscv-tdep.h (DECLARE_CSR): Use RISCV_FIRST_CSR_REGNUM instead of RISCV_LAST_FP_REGNUM + 1. (RSICV_CSR_LEGACY_MISA_REGNUM): Add RISCV_FIRST_CSR_REGNUM.
2018-07-18 00:42:23 +08:00
RISCV_CSR_LEGACY_MISA_REGNUM = 0xf10 + RISCV_FIRST_CSR_REGNUM,
gdb: Initial baremetal riscv support This commit introduces basic support for baremetal RiscV as a GDB target. This target is currently only tested against the RiscV software simulator, which is not included as part of this commit. The target has been tested against the following RiscV variants: rv32im, rv32imc, rv32imf, rv32imfc, rv64im, rv64imc, rv64imfd, rv64imfdc. Across these variants we pass on average 34858 tests, and fail 272 tests, which is ~0.8%. The RiscV has a feature of its ABI where structures with a single floating point field, a single complex float field, or one float and one integer field are treated differently for argument passing. The new test gdb.base/infcall-nested-structs.exp is added to cover this feature. As passing these structures should work on all targets then I've made the test as a generic one, even though, for most targets, there's probably nothing special about any of these cases. gdb/ChangeLog: * Makefile.in (ALL_TARGET_OBS): Add riscv-tdep.o (HFILES_NO_SRCDIR): Add riscv-tdep.h. (ALLDEPFILES): Add riscv-tdep.c * configure.tgt: Add riscv support. * riscv-tdep.c: New file. * riscv-tdep.h: New file. * NEWS: Mention new target. * MAINTAINERS: Add entry for riscv. gdb/testsuite/ChangeLog: * gdb.base/infcall-nested-structs.exp: New file. * gdb.base/infcall-nested-structs.c: New file. * gdb.base/float.exp: Add riscv support.
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RISCV_PRIV_REGNUM = 4161,
RISCV_LAST_REGNUM = RISCV_PRIV_REGNUM
};
/* RISC-V specific per-architecture information. */
struct gdbarch_tdep
{
union
{
/* Provide access to the whole ABI in one value. */
unsigned value;
struct
{
/* Encode the base machine length following the same rules as in the
MISA register. */
unsigned base_len : 2;
/* Encode which floating point ABI is in use following the same rules
as the ELF e_flags field. */
unsigned float_abi : 2;
} fields;
} abi;
/* Only the least significant 26 bits are (possibly) valid, and indicate
features that are supported on the target. These could be cached from
the target, or read from the executable when available. */
unsigned core_features;
};
RISC-V: Make riscv_isa_xlen a global function. This allows the function to be used from riscv OS files, which also need to depend on XLEN size. gdb/ * riscv-tdep.c (riscv_isa_xlen): Drop static. * riscv-tdep.h (riscv_isa_xlen): Add extern declaration.
2018-08-09 01:48:09 +08:00
/* Return the width in bytes of the general purpose registers for GDBARCH. */
extern int riscv_isa_xlen (struct gdbarch *gdbarch);
RISC-V: Add software single step support. This adds software single step support that is needed by the linux native port. This is modeled after equivalent code in the MIPS port. This also fixes a few bugs in the compressed instruction decode support. Some instructions are RV32/RV64 specific, and this wasn't being checked. Also, a few instructions were accidentally using the non-compressed is_* function. This has been tested on a HiFive Unleashed running Fedora, by putting a breakpoint on start, typing stepi, and then holding down the return key until it finishes, and observing that I see everything I expect to see along the way. There is a problem in _dl_addr where I get into an infinite loop, but it seems to be some synchronization code that doesn't agree with single step, so I have to find the end of the loop, put a breakpoint there, continue, and then single step again until the end. gdb/ * riscv-tdep.c (enum opcode): Add jump, branch, lr, and sc opcodes. (decode_register_index_short): New. (decode_j_type_insn, decode_cj_type_insn): New. (decode_b_type_insn, decode_cb_type_insn): New. (riscv_insn::decode): Add support for jumps, branches, lr, and sc. New local xlen. Check xlen when decoding ambiguous compressed insns. In compressed decode, use is_c_lui_insn instead of is_lui_insn, and is_c_sw_insn instead of is_sw_insn. (riscv_next_pc, riscv_next_pc_atomic_sequence): New. (riscv_software_single_step): New. * riscv-tdep.h (riscv_software_single_step): Declare.
2018-08-09 01:53:12 +08:00
/* Single step based on where the current instruction will take us. */
Minor formatting fixes in riscv-tdep.h This fixes some minor formatting issues in riscv-tdep.h, including one pointed out by ARI. ChangeLog 2018-08-09 Tom Tromey <tom@tromey.com> * riscv-tdep.h: Minor formatting fixes.
2018-08-10 00:46:01 +08:00
extern std::vector<CORE_ADDR> riscv_software_single_step
(struct regcache *regcache);
RISC-V: Add software single step support. This adds software single step support that is needed by the linux native port. This is modeled after equivalent code in the MIPS port. This also fixes a few bugs in the compressed instruction decode support. Some instructions are RV32/RV64 specific, and this wasn't being checked. Also, a few instructions were accidentally using the non-compressed is_* function. This has been tested on a HiFive Unleashed running Fedora, by putting a breakpoint on start, typing stepi, and then holding down the return key until it finishes, and observing that I see everything I expect to see along the way. There is a problem in _dl_addr where I get into an infinite loop, but it seems to be some synchronization code that doesn't agree with single step, so I have to find the end of the loop, put a breakpoint there, continue, and then single step again until the end. gdb/ * riscv-tdep.c (enum opcode): Add jump, branch, lr, and sc opcodes. (decode_register_index_short): New. (decode_j_type_insn, decode_cj_type_insn): New. (decode_b_type_insn, decode_cb_type_insn): New. (riscv_insn::decode): Add support for jumps, branches, lr, and sc. New local xlen. Check xlen when decoding ambiguous compressed insns. In compressed decode, use is_c_lui_insn instead of is_lui_insn, and is_c_sw_insn instead of is_sw_insn. (riscv_next_pc, riscv_next_pc_atomic_sequence): New. (riscv_software_single_step): New. * riscv-tdep.h (riscv_software_single_step): Declare.
2018-08-09 01:53:12 +08:00
gdb: Initial baremetal riscv support This commit introduces basic support for baremetal RiscV as a GDB target. This target is currently only tested against the RiscV software simulator, which is not included as part of this commit. The target has been tested against the following RiscV variants: rv32im, rv32imc, rv32imf, rv32imfc, rv64im, rv64imc, rv64imfd, rv64imfdc. Across these variants we pass on average 34858 tests, and fail 272 tests, which is ~0.8%. The RiscV has a feature of its ABI where structures with a single floating point field, a single complex float field, or one float and one integer field are treated differently for argument passing. The new test gdb.base/infcall-nested-structs.exp is added to cover this feature. As passing these structures should work on all targets then I've made the test as a generic one, even though, for most targets, there's probably nothing special about any of these cases. gdb/ChangeLog: * Makefile.in (ALL_TARGET_OBS): Add riscv-tdep.o (HFILES_NO_SRCDIR): Add riscv-tdep.h. (ALLDEPFILES): Add riscv-tdep.c * configure.tgt: Add riscv support. * riscv-tdep.c: New file. * riscv-tdep.h: New file. * NEWS: Mention new target. * MAINTAINERS: Add entry for riscv. gdb/testsuite/ChangeLog: * gdb.base/infcall-nested-structs.exp: New file. * gdb.base/infcall-nested-structs.c: New file. * gdb.base/float.exp: Add riscv support.
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#endif /* RISCV_TDEP_H */
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