2018-06-05 01:01:34 +08:00
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2018-06-04 H.J. Lu <hongjiu.lu@intel.com>
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* diagnostics.h (DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION): Always
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define for GCC.
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2018-06-04 21:33:07 +08:00
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2018-06-04 H.J. Lu <hongjiu.lu@intel.com>
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* diagnostics.h (DIAGNOSTIC_STRINGIFY_1): New.
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(DIAGNOSTIC_STRINGIFY): Likewise.
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(DIAGNOSTIC_IGNORE): Replace STRINGIFY with DIAGNOSTIC_STRINGIFY.
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(DIAGNOSTIC_IGNORE_SELF_MOVE): Define empty if not defined.
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(DIAGNOSTIC_IGNORE_DEPRECATED_REGISTER): Likewise.
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(DIAGNOSTIC_IGNORE_UNUSED_FUNCTION): Likewise.
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(DIAGNOSTIC_IGNORE_SWITCH_DIFFERENT_ENUM_TYPES): Likewise.
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(DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION): New.
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2018-06-02 00:38:22 +08:00
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2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
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* diagnostics.h: Moved from ../gdb/common/diagnostics.h.
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2018-05-29 02:21:23 +08:00
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2018-05-28 Bernd Edlinger <bernd.edlinger@hotmail.de>
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* splay-tree.h (splay_tree_compare_strings,
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splay_tree_delete_pointers): Declare new utility functions.
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Remove fake operand handling for extended mnemonics.
opcodes/
* ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
(insert_bab, extract_bab, insert_btab, extract_btab,
insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
(BAT, BBA VBA RBS XB6S): Delete macros.
(BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
(BB, BD, RBX, XC6): Update for new macros.
(powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
* ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
include/
* opcode/ppc.h (PPC_OPERAND_FAKE): Delete macro.
gas/
* config/tc-ppc.c (md_assemble): Delete handling of fake operands.
* testsuite/gas/ppc/common.s (crmove, cror, or., or, nor., nor): Add
test of extended mnemonics.
* testsuite/gas/ppc/common.d: Likewise. Don't match instruction offset.
* testsuite/gas/ppc/spe.s (evor, evnor): Add test of extended mnemonics.
* testsuite/gas/ppc/spe.d: Likewise. Don't match instruction offset.
2018-05-22 06:31:07 +08:00
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2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
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* opcode/ppc.h (PPC_OPERAND_FAKE): Delete macro.
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2018-05-19 05:03:18 +08:00
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2018-05-18 Kito Cheng <kito.cheng@gmail.com>
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* elf/riscv.h (EF_RISCV_RVE): New define.
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2018-05-18 22:26:18 +08:00
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2018-05-18 John Darrington <john@darrington.wattle.id.au>
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* elf/s12z.h: New header.
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Implement Read/Write constraints on system registers on AArch64
This patch adds constraints for read and write only system registers with the
msr and mrs instructions. The code will treat having both flags set and none
set as the same. These flags add constraints that must be matched up. e.g. a
system register with a READ only flag set, can only be used with mrs. If The
constraint fails a warning is emitted.
Examples of the warnings generated:
test.s: Assembler messages:
test.s:5: Warning: specified register cannot be written to at operand 1 -- `msr dbgdtrrx_el0,x3'
test.s:7: Warning: specified register cannot be read from at operand 2 -- `mrs x3,dbgdtrtx_el0'
test.s:8: Warning: specified register cannot be written to at operand 1 -- `msr midr_el1,x3'
and disassembly notes:
0000000000000000 <main>:
0: d5130503 msr dbgdtrtx_el0, x3
4: d5130503 msr dbgdtrtx_el0, x3
8: d5330503 mrs x3, dbgdtrrx_el0
c: d5330503 mrs x3, dbgdtrrx_el0
10: d5180003 msr midr_el1, x3 ; note: writing to a read-only register.
Note that because dbgdtrrx_el0 and dbgdtrtx_el0 have the same encoding, during
disassembly the constraints are use to disambiguate between the two. An exact
constraint match is always prefered over partial ones if available.
As always the warnings can be suppressed with -w and also be made errors using
warnings as errors.
binutils/
PR binutils/21446
* doc/binutils.texi (-M): Document AArch64 options.
gas/
PR binutils/21446
* testsuite/gas/aarch64/illegal-sysreg-2.s: Fix pmbidr_el1 test.
* testsuite/gas/aarch64/illegal-sysreg-2.l: Likewise.
* testsuite/gas/aarch64/illegal-sysreg-2.d: Likewise.
* testsuite/gas/aarch64/sysreg-diagnostic.s: New.
* testsuite/gas/aarch64/sysreg-diagnostic.l: New.
* testsuite/gas/aarch64/sysreg-diagnostic.d: New.
include/
PR binutils/21446
* opcode/aarch64.h (F_SYS_READ, F_SYS_WRITE): New.
opcodes/
PR binutils/21446
* aarch64-asm.c (opintl.h): Include.
(aarch64_ins_sysreg): Enforce read/write constraints.
* aarch64-dis.c (aarch64_ext_sysreg): Likewise.
* aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
(F_REG_READ, F_REG_WRITE): New.
* aarch64-opc.c (aarch64_print_operand): Generate notes for
AARCH64_OPND_SYSREG.
(F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
(aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
* aarch64-tbl.h (aarch64_opcode_table): Add constraints to
msr (F_SYS_WRITE), mrs (F_SYS_READ).
2018-05-15 23:37:20 +08:00
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2018-05-15 Tamar Christina <tamar.christina@arm.com>
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PR binutils/21446
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* opcode/aarch64.h (F_SYS_READ, F_SYS_WRITE): New.
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2018-05-15 23:34:54 +08:00
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2018-05-15 Tamar Christina <tamar.christina@arm.com>
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PR binutils/21446
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* opcode/aarch64.h (aarch64_operand_error): Add non_fatal.
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(aarch64_print_operand): Support notes.
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Modify AArch64 Assembly and disassembly functions to be able to fail and report why.
This patch if the first patch in a series to add the ability to add constraints
to system registers that an instruction must adhere to in order for the register
to be usable with that instruction.
These constraints can also be used to disambiguate between registers with the
same encoding during disassembly.
This patch adds a new flags entry in the sysreg structures and ensures it is
filled in and read out during assembly/disassembly. It also adds the ability for
the assemble and disassemble functions to be able to gracefully fail and re-use
the existing error reporting infrastructure.
The return type of these functions are changed to a boolean to denote success or
failure and the error structure is passed around to them. This requires
aarch64-gen changes so a lot of the changes here are just mechanical.
gas/
PR binutils/21446
* config/tc-aarch64.c (parse_sys_reg): Return register flags.
(parse_operands): Fill in register flags.
gdb/
PR binutils/21446
* aarch64-tdep.c (aarch64_analyze_prologue,
aarch64_software_single_step, aarch64_displaced_step_copy_insn):
Indicate not interested in errors.
include/
PR binutils/21446
* opcode/aarch64.h (aarch64_opnd_info): Change sysreg to struct.
(aarch64_decode_insn): Accept error struct.
opcodes/
PR binutils/21446
* aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
and take error struct.
* aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
aarch64_ins_reglist, aarch64_ins_ldst_reglist,
aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
* aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
* aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
aarch64_ext_reglist, aarch64_ext_ldst_reglist,
aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
(determine_disassembling_preference, aarch64_decode_insn,
print_insn_aarch64_word, print_insn_data): Take errors struct.
(print_insn_aarch64): Use errors.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-gen.c (print_operand_inserter): Use errors and change type to
boolean in aarch64_insert_operan.
(print_operand_extractor): Likewise.
* aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
2018-05-15 23:11:42 +08:00
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2018-05-15 Tamar Christina <tamar.christina@arm.com>
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PR binutils/21446
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* opcode/aarch64.h (aarch64_opnd_info): Change sysreg to struct.
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(aarch64_decode_insn): Accept error struct.
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2018-05-15 20:28:06 +08:00
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2018-05-15 Francois H. Theron <francois.theron@netronome.com>
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* opcode/nfp.h: Use uint64_t instead of bfd_vma.
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2018-05-10 19:51:42 +08:00
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2018-05-10 John Darrington <john@darrington.wattle.id.au>
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* elf/common.h (EM_S12Z): New macro.
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2018-05-09 14:20:29 +08:00
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2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
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* mach-o/unwind.h (MACH_O_UNWIND_X86_64_RBP_FRAME_REGISTERS):
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Rename from MACH_O_UNWIND_X86_64_RBP_FRAME_REGSITERS.
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(MACH_O_UNWIND_X86_EBP_FRAME_REGISTERS): Rename from
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MACH_O_UNWIND_X86_EBP_FRAME_REGSITERS.
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RISC-V: Add missing hint instructions from RV128I.
gas/
* testsuite/gas/riscv/c-zero-imm.d: Add more tests.
* testsuite/gas/riscv/c-zero-imm.s: Likewise.
* testsuite/gas/riscv/c-zero-reg.d: Fix typo in test. Add disabled
future test for RV128 support.
* testsuite/gas/riscv/c-zero-reg.s: Likewise.
include/
* opcode/riscv-opc.h (MATCH_C_SRLI64, MASK_C_SRLI64): New.
(MATCH_C_SRAI64, MASK_C_SRAI64): New.
(MATCH_C_SLLI64, MASK_C_SLLI64): New.
opcodes/
* riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
(match_c_slli64, match_srxi_as_c_srxi): New.
(riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
<srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
<c.slli, c.srli, c.srai>: Use match_s_slli.
<c.slli64, c.srli64, c.srai64>: New.
2018-05-09 06:46:19 +08:00
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2018-05-08 Jim Wilson <jimw@sifive.com>
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* opcode/riscv-opc.h (MATCH_C_SRLI64, MASK_C_SRLI64): New.
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(MATCH_C_SRAI64, MASK_C_SRAI64): New.
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(MATCH_C_SLLI64, MASK_C_SLLI64): New.
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2018-05-07 22:40:59 +08:00
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2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
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* opcode/ppc.h (powerpc_num_opcodes): Change type to unsigned.
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(vle_num_opcodes): Likewise.
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(spe2_num_opcodes): Likewise.
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2018-04-27 08:12:11 +08:00
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2018-05-04 Alan Modra <amodra@gmail.com>
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* ansidecl.h: Import from gcc.
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* coff/internal.h (struct internal_scnhdr): Add ATTRIBUTE_NONSTRING
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to s_name.
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(struct internal_syment): Add ATTRIBUTE_NONSTRING to _n_name.
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2018-05-01 00:02:59 +08:00
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2018-04-30 Francois H. Theron <francois.theron@netronome.com>
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* dis-asm.h: Added print_nfp_disassembler_options prototype.
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* elf/common.h: Added EM_NFP, officially assigned. See Google Group
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Generic System V Application Binary Interface.
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* elf/nfp.h: New, for NFP support.
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* opcode/nfp.h: New, for NFP support.
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[ARM] Add TLS relocations for FDPIC.
Define and handle TLS relocations for FDPIC in BFD and gas.
In gas, the new relocations are rejected if the --fdpic option was not
specified.
We also define the __tdata_start symbol to mark the start of the
.tdata section. This allows FDPIC static binaries to find the start of
.tdata section, since phdr->p_vaddr of TLS segment is not a valid
value for FDPIC.
2018-04-25 Christophe Lyon <christophe.lyon@st.com>
Mickaël Guêné <mickael.guene@st.com>
bfd/:
* bfd-in2.h (BFD_RELOC_ARM_TLS_GD32_FDPIC)
(BFD_RELOC_ARM_TLS_LDM32_FDPIC, BFD_RELOC_ARM_TLS_IE32_FDPIC): New
relocations.
* elf32-arm.c (elf32_arm_howto_table_2): Add R_ARM_TLS_GD32_FDPIC,
R_ARM_TLS_LDM32_FDPIC, R_ARM_TLS_IE32_FDPIC relocations.
(elf32_arm_reloc_map): Add R_ARM_TLS_GD32_FDPIC,
R_ARM_TLS_LDM32_FDPIC, R_ARM_TLS_IE32_FDPIC.
(struct elf32_arm_link_hash_table): Update comment.
(elf32_arm_final_link_relocate): Handle TLS FDPIC relocations.
(IS_ARM_TLS_RELOC): Likewise.
(elf32_arm_check_relocs): Likewise.
(allocate_dynrelocs_for_symbol): Likewise.
(elf32_arm_size_dynamic_sections): Update comment.
* reloc.c: Add BFD_RELOC_ARM_TLS_GD32_FDPIC,
BFD_RELOC_ARM_TLS_LDM32_FDPIC, BFD_RELOC_ARM_TLS_IE32_FDPIC.
gas/
* config/tc-arm.c (reloc_names): Add TLSGD_FDPIC, TLSLDM_FDPIC,
GOTTPOFF_FDIC relocations.
(md_apply_fix): Handle the new TLS FDPIC relocations.
(tc_gen_reloc): Likewise.
(arm_fix_adjustable): Likewise.
include/
* elf/arm.h: Add R_ARM_TLS_GD32_FDPIC, R_ARM_TLS_LDM32_FDPIC,
R_ARM_TLS_IE32_FDPIC.
ld/
* scripttempl/elf.sc: Define __tdata_start for .tdata section.
2018-03-20 17:55:29 +08:00
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2018-04-25 Christophe Lyon <christophe.lyon@st.com>
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Mickaël Guêné <mickael.guene@st.com>
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* elf/arm.h: Add R_ARM_TLS_GD32_FDPIC, R_ARM_TLS_LDM32_FDPIC,
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R_ARM_TLS_IE32_FDPIC.
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[ARM] Add FDPIC relocations definitions
Add FDPIC relocation definitions in BFD and gas.
Gas rejects them if the --fdpic option was not specified.
2018-04-25 Christophe Lyon <christophe.lyon@st.com>
Mickaël Guêné <mickael.guene@st.com>
bfd/
* bfd-in2.c (BFD_RELOC_ARM_GOTFUNCDESC)
(BFD_RELOC_ARM_GOTOFFFUNCDESC, BFD_RELOC_ARM_FUNCDESC)
(BFD_RELOC_ARM_FUNCDESC_VALUE): New.
* elf32-arm.c (elf32_arm_howto_table_2): Add R_ARM_GOTFUNCDESC,
R_ARM_GOTOFFFUNCDESC, R_ARM_FUNCDESC, R_ARM_FUNCDESC_VALUE.
(elf32_arm_howto_from_type): Take new members of
elf32_arm_howto_table_2 into account.
(elf32_arm_reloc_map): Add BFD_RELOC_ARM_GOTFUNCDESC,
BFD_RELOC_ARM_GOTOFFFUNCDESC, BFD_RELOC_ARM_FUNCDESC,
BFD_RELOC_ARM_FUNCDESC_VALUE.
* reloc.c: Add BFD_RELOC_ARM_GOTFUNCDESC,
BFD_RELOC_ARM_GOTOFFFUNCDESC, BFD_RELOC_ARM_FUNCDESC,
BFD_RELOC_ARM_FUNCDESC_VALUE.
gas/
* config/tc-arm.c (reloc_names): Add gotfuncdesc, gotofffuncdesc,
funcdesc.
(md_apply_fix): Support the new relocations.
(tc_gen_reloc): Likewise.
* testsuite/gas/arm/reloc-fdpic.d: New.
* testsuite/gas/arm/reloc-fdpic.s: New.
include/
* elf/arm.h (R_ARM_GOTFUNCDESC, R_ARM_GOTOFFFUNCDESC)
(R_ARM_FUNCDESC)
(R_ARM_FUNCDESC_VALUE): Define new relocations.
2018-03-20 17:54:59 +08:00
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2018-04-25 Christophe Lyon <christophe.lyon@st.com>
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Mickaël Guêné <mickael.guene@st.com>
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* elf/arm.h (R_ARM_GOTFUNCDESC, R_ARM_GOTOFFFUNCDESC)
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(R_ARM_FUNCDESC)
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(R_ARM_FUNCDESC_VALUE): Define new relocations.
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2018-03-20 17:54:50 +08:00
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2018-04-25 Christophe Lyon <christophe.lyon@st.com>
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Mickaël Guêné <mickael.guene@st.com>
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* elf/arm.h (EF_ARM_FDPIC): New.
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2018-04-18 14:09:34 +08:00
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2018-04-18 Alan Modra <amodra@gmail.com>
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* coff/mipspe.h: Delete.
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|
2018-04-16 20:44:01 +08:00
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|
2018-04-18 Alan Modra <amodra@gmail.com>
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* aout/dynix3.h: Delete.
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|
2018-04-18 08:00:17 +08:00
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2018-04-17 Andrew Sadek <andrew.sadek.se@gmail.com>
|
2018-04-18 05:47:13 +08:00
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Microblaze Target: PIC data text relative
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* bfdlink.h (Add flag): Add new flag @ 'bfd_link_info' struct.
|
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|
|
* elf/microblaze.h (Add 3 new relocations):
|
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|
|
R_MICROBLAZE_TEXTPCREL_64, R_MICROBLAZE_TEXTREL_64
|
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and R_MICROBLAZE_TEXTREL_32_LO for relax function.
|
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2018-04-17 07:30:57 +08:00
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2018-04-17 Alan Modra <amodra@gmail.com>
|
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* elf/i370.h: Revert removal.
|
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* elf/i860.h: Likewise.
|
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* elf/i960.h: Likewise.
|
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|
2018-04-16 18:55:42 +08:00
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|
2018-04-16 Alan Modra <amodra@gmail.com>
|
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* coff/sparc.h: Delete.
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|
2018-04-16 14:01:36 +08:00
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2018-04-16 Alan Modra <amodra@gmail.com>
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* aout/host.h: Remove m68k-aout and m68k-coff support.
|
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* aout/hp300hpux.h: Delete.
|
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* coff/apollo.h: Delete.
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* coff/aux-coff.h: Delete.
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* coff/m68k.h: Delete.
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2018-04-16 13:59:39 +08:00
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2018-04-16 Alan Modra <amodra@gmail.com>
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* dis-asm.h: Remove sh5 and sh64 support.
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2018-04-16 13:56:05 +08:00
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2018-04-16 Alan Modra <amodra@gmail.com>
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* coff/internal.h: Remove w65 support.
|
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* coff/w65.h: Delete.
|
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|
2018-04-16 13:54:43 +08:00
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2018-04-16 Alan Modra <amodra@gmail.com>
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* coff/we32k.h: Delete.
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2018-04-16 13:53:38 +08:00
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2018-04-16 Alan Modra <amodra@gmail.com>
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* coff/internal.h: Remove m88k support.
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* coff/m88k.h: Delete.
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* opcode/m88k.h: Delete.
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2018-04-16 13:51:56 +08:00
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2018-04-16 Alan Modra <amodra@gmail.com>
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* elf/i370.h: Delete.
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* opcode/i370.h: Delete.
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2018-04-16 13:49:41 +08:00
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2018-04-16 Alan Modra <amodra@gmail.com>
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* coff/h8500.h: Delete.
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* coff/internal.h: Remove h8500 support.
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2018-04-16 13:47:57 +08:00
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2018-04-16 Alan Modra <amodra@gmail.com>
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* coff/h8300.h: Delete.
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2018-04-16 13:46:00 +08:00
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2018-04-16 Alan Modra <amodra@gmail.com>
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* ieee.h: Delete.
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2018-04-16 13:43:07 +08:00
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2018-04-16 Alan Modra <amodra@gmail.com>
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* aout/host.h: Remove newsos3 support.
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2018-04-16 13:41:22 +08:00
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2018-04-16 Alan Modra <amodra@gmail.com>
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* nlm/ChangeLog-9315: Delete.
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* nlm/alpha-ext.h: Delete.
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* nlm/common.h: Delete.
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* nlm/external.h: Delete.
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* nlm/i386-ext.h: Delete.
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* nlm/internal.h: Delete.
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* nlm/ppc-ext.h: Delete.
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* nlm/sparc32-ext.h: Delete.
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2018-04-16 13:38:40 +08:00
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2018-04-16 Alan Modra <amodra@gmail.com>
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* opcode/tahoe.h: Delete.
|
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|
Remove i860, i960, bout and aout-adobe targets
Plus remove a few leftovers from the 29k support.
include/
* aout/adobe.h: Delete.
* aout/reloc.h: Delete.
* coff/i860.h: Delete.
* coff/i960.h: Delete.
* elf/i860.h: Delete.
* elf/i960.h: Delete.
* opcode/i860.h: Delete.
* opcode/i960.h: Delete.
* aout/aout64.h (enum reloc_type): Trim off 29k and other unused values.
* aout/ar.h (ARMAGB): Remove.
* coff/internal.h (struct internal_aouthdr, struct internal_scnhdr,
union internal_auxent): Remove i960 support.
bfd/
* aout-adobe.c: Delete.
* bout.c: Delete.
* coff-i860.c: Delete.
* coff-i960.c: Delete.
* cpu-i860.c: Delete.
* cpu-i960.c: Delete.
* elf32-i860.c: Delete.
* elf32-i960.c: Delete.
* hosts/i860mach3.h: Delete.
* Makefile.am: Remove i860, i960, bout, and adobe support.
* archures.c: Remove i860 and i960 support.
* coffcode.h: Likewise.
* reloc.c: Likewise.
* aoutx.h: Comment updates.
* archive.c: Remove BOUT and i960 support.
* bfd.c: Remove BOUT support.
* coffswap.h: Remove i960 support.
* config.bfd: Remove i860, i960 and adobe targets.
* configure.ac: Remove adode, bout, i860, i960, icoff targets.
* targets.c: Likewise.
* ieee.c: Remove i960 support.
* mach-o.c: Remove i860 support.
* Makefile.in: Regenerate.
* bfd-in2.h: Regenerate.
* configure: Regenerate.
* libbfd.h: Regenerate.
* po/SRC-POTFILES.in: Regenerate.
opcodes/
* opcodes/i860-dis.c: Delete.
* opcodes/i960-dis.c: Delete.
* Makefile.am: Remove i860 and i960 support.
* configure.ac: Likewise.
* disassemble.c: Likewise.
* disassemble.h: Likewise.
* Makefile.in: Regenerate.
* configure: Regenerate.
* po/POTFILES.in: Regenerate.
binutils/
* ieee.c: Remove i960 support.
* od-macho.c: Remove i860 support.
* readelf.c: Remove i860 and i960 support.
* testsuite/binutils-all/objcopy.exp: Likewise.
* testsuite/binutils-all/objdump.exp: Likewise.
* testsuite/lib/binutils-common.exp: Likewise.
gas/
* config/aout_gnu.h: Delete.
* config/tc-i860.c: Delete.
* config/tc-i860.h: Delete.
* config/tc-i960.c: Delete.
* config/tc-i960.h: Delete.
* doc/c-i860.texi: Delete.
* doc/c-i960.texi: Delete.
* testsuite/gas/i860/README.i860: Delete.
* testsuite/gas/i860/bitwise.d: Delete.
* testsuite/gas/i860/bitwise.s: Delete.
* testsuite/gas/i860/branch.d: Delete.
* testsuite/gas/i860/branch.s: Delete.
* testsuite/gas/i860/bte.d: Delete.
* testsuite/gas/i860/bte.s: Delete.
* testsuite/gas/i860/dir-align01.d: Delete.
* testsuite/gas/i860/dir-align01.s: Delete.
* testsuite/gas/i860/dir-intel01.d: Delete.
* testsuite/gas/i860/dir-intel01.s: Delete.
* testsuite/gas/i860/dir-intel02.d: Delete.
* testsuite/gas/i860/dir-intel02.s: Delete.
* testsuite/gas/i860/dir-intel03-err.l: Delete.
* testsuite/gas/i860/dir-intel03-err.s: Delete.
* testsuite/gas/i860/dual01.d: Delete.
* testsuite/gas/i860/dual01.s: Delete.
* testsuite/gas/i860/dual02-err.l: Delete.
* testsuite/gas/i860/dual02-err.s: Delete.
* testsuite/gas/i860/dual03.d: Delete.
* testsuite/gas/i860/dual03.s: Delete.
* testsuite/gas/i860/fldst01.d: Delete.
* testsuite/gas/i860/fldst01.s: Delete.
* testsuite/gas/i860/fldst02.d: Delete.
* testsuite/gas/i860/fldst02.s: Delete.
* testsuite/gas/i860/fldst03.d: Delete.
* testsuite/gas/i860/fldst03.s: Delete.
* testsuite/gas/i860/fldst04.d: Delete.
* testsuite/gas/i860/fldst04.s: Delete.
* testsuite/gas/i860/fldst05.d: Delete.
* testsuite/gas/i860/fldst05.s: Delete.
* testsuite/gas/i860/fldst06.d: Delete.
* testsuite/gas/i860/fldst06.s: Delete.
* testsuite/gas/i860/fldst07.d: Delete.
* testsuite/gas/i860/fldst07.s: Delete.
* testsuite/gas/i860/fldst08.d: Delete.
* testsuite/gas/i860/fldst08.s: Delete.
* testsuite/gas/i860/float01.d: Delete.
* testsuite/gas/i860/float01.s: Delete.
* testsuite/gas/i860/float02.d: Delete.
* testsuite/gas/i860/float02.s: Delete.
* testsuite/gas/i860/float03.d: Delete.
* testsuite/gas/i860/float03.s: Delete.
* testsuite/gas/i860/float04.d: Delete.
* testsuite/gas/i860/float04.s: Delete.
* testsuite/gas/i860/form.d: Delete.
* testsuite/gas/i860/form.s: Delete.
* testsuite/gas/i860/i860.exp: Delete.
* testsuite/gas/i860/iarith.d: Delete.
* testsuite/gas/i860/iarith.s: Delete.
* testsuite/gas/i860/ldst01.d: Delete.
* testsuite/gas/i860/ldst01.s: Delete.
* testsuite/gas/i860/ldst02.d: Delete.
* testsuite/gas/i860/ldst02.s: Delete.
* testsuite/gas/i860/ldst03.d: Delete.
* testsuite/gas/i860/ldst03.s: Delete.
* testsuite/gas/i860/ldst04.d: Delete.
* testsuite/gas/i860/ldst04.s: Delete.
* testsuite/gas/i860/ldst05.d: Delete.
* testsuite/gas/i860/ldst05.s: Delete.
* testsuite/gas/i860/ldst06.d: Delete.
* testsuite/gas/i860/ldst06.s: Delete.
* testsuite/gas/i860/pfam.d: Delete.
* testsuite/gas/i860/pfam.s: Delete.
* testsuite/gas/i860/pfmam.d: Delete.
* testsuite/gas/i860/pfmam.s: Delete.
* testsuite/gas/i860/pfmsm.d: Delete.
* testsuite/gas/i860/pfmsm.s: Delete.
* testsuite/gas/i860/pfsm.d: Delete.
* testsuite/gas/i860/pfsm.s: Delete.
* testsuite/gas/i860/pseudo-ops01.d: Delete.
* testsuite/gas/i860/pseudo-ops01.s: Delete.
* testsuite/gas/i860/regress01.d: Delete.
* testsuite/gas/i860/regress01.s: Delete.
* testsuite/gas/i860/shift.d: Delete.
* testsuite/gas/i860/shift.s: Delete.
* testsuite/gas/i860/simd.d: Delete.
* testsuite/gas/i860/simd.s: Delete.
* testsuite/gas/i860/system.d: Delete.
* testsuite/gas/i860/system.s: Delete.
* testsuite/gas/i860/xp.d: Delete.
* testsuite/gas/i860/xp.s: Delete.
* Makefile.am: Remove i860 and i960 support.
* configure.tgt: Likewise.
* doc/Makefile.am: Likewise.
* doc/all.texi: Likewise.
* testsuite/gas/all/gas.exp
* config/obj-coff.h: Remove i960 support.
* doc/internals.texi: Likewise.
* expr.c: Likewise.
* read.c: Likewise.
* write.c: Likewise.
* write.h: Likewise.
* testsuite/gas/lns/lns.exp: Likewise.
* testsuite/gas/symver/symver.exp: Likewise.
* config/tc-m68k.c: Remove BOUT support.
* config/tc-score.c: Likewise.
* config/tc-score7.c: Likewise.
* config/tc-sparc.c: Likewise.
* symbols.c: Likewise.
* doc/h8.texi: Likewise.
* configure.ac: Remove BOUT and i860 support.
* doc/as.texinfo: Remove BOUT, i860 and i960 support
* Makefile.in: Regenerate.
* config.in: Regenerate.
* configure: Regenerate.
* doc/Makefile.in: Regenerate.
* po/POTFILES.in: Regenerate.
ld/
* emulparams/coff_i860.sh: Delete.
* emulparams/elf32_i860.sh: Delete.
* emulparams/elf32_i960.sh: Delete.
* emulparams/gld960.sh: Delete.
* emulparams/gld960coff.sh: Delete.
* emulparams/lnk960.sh: Delete.
* emultempl/gld960.em: Delete.
* emultempl/gld960c.em: Delete.
* emultempl/lnk960.em: Delete.
* scripttempl/i860coff.sc: Delete.
* scripttempl/i960.sc: Delete.
* ld.texinfo: Remove i960 support.
* Makefile.am: Remove i860 and i960 support.
* configure.tgt: Likewise.
* testsuite/ld-discard/extern.d: Likewise.
* testsuite/ld-discard/start.d: Likewise.
* testsuite/ld-discard/static.d: Likewise.
* testsuite/ld-elf/compressed1d.d: Likewise.
* testsuite/ld-elf/group1.d: Likewise.
* testsuite/ld-elf/group3b.d: Likewise.
* testsuite/ld-elf/group8a.d: Likewise.
* testsuite/ld-elf/group8b.d: Likewise.
* testsuite/ld-elf/group9a.d: Likewise.
* testsuite/ld-elf/group9b.d: Likewise.
* testsuite/ld-elf/linkonce2.d: Likewise.
* testsuite/ld-elf/merge.d: Likewise.
* testsuite/ld-elf/merge2.d: Likewise.
* testsuite/ld-elf/merge3.d: Likewise.
* testsuite/ld-elf/orphan-10.d: Likewise.
* testsuite/ld-elf/orphan-11.d: Likewise.
* testsuite/ld-elf/orphan-12.d: Likewise.
* testsuite/ld-elf/orphan-9.d: Likewise.
* testsuite/ld-elf/orphan-region.d: Likewise.
* testsuite/ld-elf/orphan.d: Likewise.
* testsuite/ld-elf/orphan3.d: Likewise.
* testsuite/ld-elf/pr12851.d: Likewise.
* testsuite/ld-elf/pr12975.d: Likewise.
* testsuite/ld-elf/pr13177.d: Likewise.
* testsuite/ld-elf/pr13195.d: Likewise.
* testsuite/ld-elf/pr17550a.d: Likewise.
* testsuite/ld-elf/pr17550b.d: Likewise.
* testsuite/ld-elf/pr17550c.d: Likewise.
* testsuite/ld-elf/pr17550d.d: Likewise.
* testsuite/ld-elf/pr17615.d: Likewise.
* testsuite/ld-elf/pr20528a.d: Likewise.
* testsuite/ld-elf/pr20528b.d: Likewise.
* testsuite/ld-elf/pr21562a.d: Likewise.
* testsuite/ld-elf/pr21562b.d: Likewise.
* testsuite/ld-elf/pr21562c.d: Likewise.
* testsuite/ld-elf/pr21562d.d: Likewise.
* testsuite/ld-elf/pr21562i.d: Likewise.
* testsuite/ld-elf/pr21562j.d: Likewise.
* testsuite/ld-elf/pr21562k.d: Likewise.
* testsuite/ld-elf/pr21562l.d: Likewise.
* testsuite/ld-elf/pr21562m.d: Likewise.
* testsuite/ld-elf/pr21562n.d: Likewise.
* testsuite/ld-elf/pr22677.d: Likewise.
* testsuite/ld-elf/pr22836-1a.d: Likewise.
* testsuite/ld-elf/pr22836-1b.d: Likewise.
* testsuite/ld-elf/pr349.d: Likewise.
* testsuite/ld-elf/sec-to-seg.exp: Likewise.
* testsuite/ld-elf/sec64k.exp: Likewise.
* testsuite/ld-elf/warn1.d: Likewise.
* testsuite/ld-elf/warn2.d: Likewise.
* testsuite/ld-elf/warn3.d: Likewise.
* testsuite/lib/ld-lib.exp: Likewise.
* Makefile.in: Regenerate.
* po/BLD-POTFILES.in: Regenerate.
2018-04-11 17:16:05 +08:00
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2018-04-11 Alan Modra <amodra@gmail.com>
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* aout/adobe.h: Delete.
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* aout/reloc.h: Delete.
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* coff/i860.h: Delete.
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* coff/i960.h: Delete.
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* elf/i860.h: Delete.
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* elf/i960.h: Delete.
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* opcode/i860.h: Delete.
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* opcode/i960.h: Delete.
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* aout/aout64.h (enum reloc_type): Trim off 29k and other unused values.
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* aout/ar.h (ARMAGB): Remove.
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* coff/internal.h (struct internal_aouthdr, struct internal_scnhdr,
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union internal_auxent): Remove i960 support.
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PowerPC inline PLT call support
In addition to the existing relocs we need two more to mark all
instructions in the call sequence, PLTCALL on the call itself (plus
the toc restore insn for ppc64), and PLTSEQ on others. All
relocations in a particular sequence have the same symbol.
Example ppc64 ELFv2 assembly:
.reloc .,R_PPC64_PLTSEQ,puts
std 2,24(1)
addis 12,2,puts@plt@ha # .reloc .,R_PPC64_PLT16_HA,puts
ld 12,puts@plt@l(12) # .reloc .,R_PPC64_PLT16_LO_DS,puts
.reloc .,R_PPC64_PLTSEQ,puts
mtctr 12
.reloc .,R_PPC64_PLTCALL,puts
bctrl
ld 2,24(1)
Example ppc32 -fPIC assembly:
addis 12,30,puts+32768@plt@ha # .reloc .,R_PPC_PLT16_HA,puts+0x8000
lwz 12,12,puts+32768@plt@l # .reloc .,R_PPC_PLT16_LO,puts+0x8000
.reloc .,R_PPC_PLTSEQ,puts+32768
mtctr 12
.reloc .,R_PPC_PLTCALL,puts+32768
bctrl
Marking sequences like this allows the linker to convert them to nops
and a direct call if the target symbol turns out to be local.
When the call is __tls_get_addr, each relocation shown above is paired
with an R_PPC*_TLSLD or R_PPC*_TLSGD reloc to additionally mark the
sequence for possible TLS optimization. The TLSLD or TLSGD relocs are
emitted first.
include/
* elf/ppc.h (R_PPC_PLTSEQ, R_PPC_PLTCALL): Define.
* elf/ppc64.h (R_PPC64_PLTSEQ, R_PPC64_PLTCALL): Define.
bfd/
* elf32-ppc.c (ppc_elf_howto_raw): Add PLTSEQ and PLTCALL howtos.
(is_plt_seq_reloc): New function.
(ppc_elf_check_relocs): Handle PLTSEQ and PLTCALL relocs.
(ppc_elf_tls_optimize): Handle inline plt call sequence.
(ppc_elf_relax_section): Handle PLTCALL reloc.
(ppc_elf_relocate_section): Nop out inline plt call sequence when
resolving locally.
* elf64-ppc.c (ppc64_elf_howto_raw): Add R_PPC64_PLTSEQ and
R_PPC64_PLTCALL entries. Comment R_PPC64_TOCSAVE.
(has_tls_get_addr_call): Correct comment.
(is_branch_reloc): Add PLTCALL.
(is_plt_seq_reloc): New function.
(ppc64_elf_check_relocs): Handle PLT16_LO_DS reloc. Set
has_tls_reloc for R_PPC64_TLSGD and R_PPC64_TLSLD. Create plt
entry for R_PPC64_PLTCALL.
(ppc64_elf_tls_optimize): Handle inline plt call sequence.
(ppc_type_of_stub): Handle PLTCALL reloc.
(toc_adjusting_stub_needed): Likewise.
(ppc64_elf_relocate_section): Set "can_plt_call" for PLTCALL
reloc insn. Nop out inline plt call sequence when resolving
locally. Handle __tls_get_addr inline plt call optimization.
elfcpp/
* powerpc.h (R_POWERPC_PLTSEQ, R_POWERPC_PLTCALL): Define.
gold/
* powerpc.cc (Target_powerpc::Track_tls::maybe_skip_tls_get_addr_call):
Handle inline plt sequence relocs.
(Stub_table::Plt_stub_key::Plt_stub_key): Likewise.
(Target_powerpc::Scan::reloc_needs_plt_for_ifunc): Likewise.
(Target_powerpc::Relocate::relocate): Likewise.
2018-04-09 07:55:10 +08:00
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2018-04-09 Alan Modra <amodra@gmail.com>
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* elf/ppc.h (R_PPC_PLTSEQ, R_PPC_PLTCALL): Define.
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* elf/ppc64.h (R_PPC64_PLTSEQ, R_PPC64_PLTCALL): Define.
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2018-03-29 01:03:55 +08:00
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2018-03-28 Renlin Li <renlin.li@arm.com>
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PR ld/22970
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* elf/aarch64.h: Add relocation number for
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R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12,
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R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12_NC,
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R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12,
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R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12_NC,
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R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12,
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R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12_NC,
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R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12,
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R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12_NC.
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2018-03-28 16:44:45 +08:00
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2018-03-28 Nick Clifton <nickc@redhat.com>
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PR 22988
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* opcode/aarch64.h (enum aarch64_opnd): Add
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AARCH64_OPND_SVE_ADDR_R.
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2018-03-22 03:55:40 +08:00
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2018-03-21 H.J. Lu <hongjiu.lu@intel.com>
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* elf/common.h (DF_1_KMOD): New.
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(DF_1_WEAKFILTER): Likewise.
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(DF_1_NOCOMMON): Likewise.
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2018-03-15 07:04:03 +08:00
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2018-03-14 Kito Cheng <kito.cheng@gmail.com>
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* opcode/riscv.h (OP_MASK_FUNCT3): New.
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(OP_SH_FUNCT3): Likewise.
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(OP_MASK_FUNCT7): Likewise.
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(OP_SH_FUNCT7): Likewise.
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(OP_MASK_OP2): Likewise.
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(OP_SH_OP2): Likewise.
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(OP_MASK_CFUNCT4): Likewise.
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(OP_SH_CFUNCT4): Likewise.
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(OP_MASK_CFUNCT3): Likewise.
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(OP_SH_CFUNCT3): Likewise.
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(riscv_insn_types): Likewise.
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2018-03-13 22:02:52 +08:00
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2018-03-13 Nick Clifton <nickc@redhat.com>
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PR 22113
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* coff/pe.h (struct pex64_unwind_info): Add a rawUnwindCodesEnd
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field.
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2018-03-08 22:31:32 +08:00
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2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
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* opcode/i386 (OLDGCC_COMPAT): Removed.
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2018-02-28 00:40:45 +08:00
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2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
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* opcode/arm.h (ARM_FEATURE_COPY): Remove macro definition.
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2018-02-21 04:51:36 +08:00
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|
2018-02-20 Maciej W. Rozycki <macro@mips.com>
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* opcode/mips.h: Remove `M' operand code.
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2018-02-12 21:12:45 +08:00
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2018-02-12 Zebediah Figura <z.figura12@gmail.com>
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* coff/msdos.h: New header.
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* coff/pe.h: Move common defines to msdos.h.
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* coff/powerpc.h: Likewise.
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2018-01-13 21:26:38 +08:00
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2018-01-13 Nick Clifton <nickc@redhat.com>
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2.30 branch created.
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2018-01-12 11:01:39 +08:00
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2018-01-11 H.J. Lu <hongjiu.lu@intel.com>
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PR ld/22393
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* bfdlink.h (bfd_link_info): Add separate_code.
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2018-01-05 06:17:53 +08:00
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|
2018-01-04 Jim Wilson <jimw@sifive.com>
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* opcode/riscv-opc.h (CSR_SBADADDR): Rename to CSR_STVAL. Rename
|
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|
|
DECLARE_CSR entry. Add alias to map sbadaddr to CSR_STVAL.
|
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(CSR_MBADADDR): Rename to CSR_MTVAL. Rename DECLARE_CSR entry.
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Add alias to map mbadaddr to CSR_MTVAL.
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2018-01-03 13:17:27 +08:00
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2018-01-03 Alan Modra <amodra@gmail.com>
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|
Update year range in copyright notice of all files.
|
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2018-01-03 13:15:17 +08:00
|
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For older changes see ChangeLog-2017
|
2016-01-01 18:44:31 +08:00
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2018-01-03 13:15:17 +08:00
|
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Copyright (C) 2018 Free Software Foundation, Inc.
|
2016-01-01 18:44:31 +08:00
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
|
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notice and this notice are preserved.
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Local Variables:
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mode: change-log
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left-margin: 8
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fill-column: 74
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version-control: never
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End:
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