2016-12-04 09:29:44 +08:00
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2016-12-03 Jim Wilson <jim.wilson@linaro.org>
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* simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting.
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(dexTestBranchImmediate): Shift high bit of pos by 5 not 4.
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2016-12-02 01:06:07 +08:00
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2016-12-01 Jim Wilson <jim.wilson@linaro.org>
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2016-12-02 01:07:55 +08:00
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* simulator.c (fsturs): Switch use of rn and st variables.
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2016-12-02 01:06:07 +08:00
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(fsturd, fsturq): Likewise
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2016-01-22 11:17:59 +08:00
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2016-08-15 Mike Frysinger <vapier@gentoo.org>
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* interp.c: Include bfd.h.
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(symcount, symtab, aarch64_get_sym_value): Delete.
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(remove_useless_symbols): Change count type to long.
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(aarch64_get_func): Add SIM_DESC to arg list. Add symcount
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and symtab local variables.
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(sim_create_inferior): Delete storage. Replace symbol code
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with a call to trace_load_symbols.
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* memory.c: Delete bfd.h, elf/internal.h, and elf/common.h
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includes.
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(aarch64_get_heap_start): Change aarch64_get_sym_value to
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trace_sym_value.
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* memory.h: Delete bfd.h include.
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(mem_add_blk): Delete unused prototype.
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* simulator.c (bl, blr): Pass SIM_DESC to aarch64_get_func.
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* simulator.c (aarch64_get_func): Add SIM_DESC to arg list.
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(aarch64_get_sym_value): Delete.
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2016-08-12 18:35:32 +08:00
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2016-08-12 Nick Clifton <nickc@redhat.com>
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* simulator.c (aarch64_step): Revert pervious delta.
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(aarch64_run): Call sim_events_tick after each
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instruction is simulated, and if necessary call
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sim_events_process.
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* simulator.h: Revert previous delta.
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2016-08-11 22:04:40 +08:00
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2016-08-11 Nick Clifton <nickc@redhat.com>
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* interp.c (sim_create_inferior): Allow for being called with a
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NULL abfd parameter. If a bfd is provided, initialise the sim
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with that start address.
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* simulator.c (HALT_NYI): Just print out the numeric value of the
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instruction when not tracing.
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2016-08-12 18:35:32 +08:00
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(aarch64_step): Change from static to global.
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* simulator.h: Add a prototype for aarch64_step().
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2016-08-11 22:04:40 +08:00
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2016-07-27 07:30:03 +08:00
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2016-07-27 Alan Modra <amodra@gmail.com>
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* memory.c: Don't include libbfd.h.
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2016-07-21 16:17:54 +08:00
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2016-07-21 Nick Clifton <nickc@redhat.com>
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2016-07-21 16:23:16 +08:00
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* simulator.c (fsqrts): Use sqrtf rather than sqrt.
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2016-07-21 16:17:54 +08:00
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2016-06-30 16:10:41 +08:00
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2016-06-30 Jim Wilson <jim.wilson@linaro.org>
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* cpustate.h: Include config.h.
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(union GRegisterValue): Add WORDS_BIGENDIAN check. For big endian code
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use anonymous structs to align members.
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* simulator.c (aarch64_step): Use sim_core_read_buffer and
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endian_le2h_4 to read instruction from pc.
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2016-05-06 17:35:33 +08:00
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2016-05-06 Nick Clifton <nickc@redhat.com>
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* simulator.c (do_FMLA_by_element): New function.
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(do_vec_op2): Call it.
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2016-04-27 18:39:14 +08:00
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2016-04-27 Nick Clifton <nickc@redhat.com>
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* simulator.c: Add TRACE_DECODE statements to all emulation
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functions.
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2016-03-30 17:27:21 +08:00
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2016-03-30 Nick Clifton <nickc@redhat.com>
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* cpustate.c (aarch64_set_reg_s32): New function.
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(aarch64_set_reg_u32): New function.
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(aarch64_get_FP_half): Place half precision value into the correct
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slot of the union.
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(aarch64_set_FP_half): Likewise.
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* cpustate.h: Add prototypes for aarch64_set_reg_s32 and
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aarch64_set_reg_u32.
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* memory.c (FETCH_FUNC): Cast the read value to the access type
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before converting it to the return type. Rename to FETCH_FUNC64.
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(FETCH_FUNC32): New macro. Duplicates FETCH_FUNC64 but for 32-bit
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accesses. Use for 32-bit memory access functions.
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* simulator.c (ldrsb_wb): Use sign extension not zero extension.
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(ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise.
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(ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise.
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(ldrsh_scale_ext, ldrsw_abs): Likewise.
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(ldrh32_abs): Store 32 bit value not 64-bits.
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(ldrh32_wb, ldrh32_scale_ext): Likewise.
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(do_vec_MOV_immediate): Fix computation of val.
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(do_vec_MVNI): Likewise.
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(DO_VEC_WIDENING_MUL): New macro.
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(do_vec_mull): Use new macro.
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(do_vec_mul): Use new macro.
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(do_vec_MLA): Read values before writing.
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(do_vec_xtl): Likewise.
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(do_vec_SSHL): Select correct shift value.
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(do_vec_USHL): Likewise.
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(do_scalar_UCVTF): New function.
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(do_scalar_vec): Call new function.
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(store_pair_u64): Treat reads of SP as reads of XZR.
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2016-03-29 18:34:22 +08:00
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2016-03-29 Nick Clifton <nickc@redhat.com>
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* cpustate.c: Remove space after asterisk in function parameters.
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* decode.h (greg): Delete unused function.
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(vreg, shift, extension, scaling, writeback, condcode): Likewise.
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* simulator.c: Use INSTR macro in more places.
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(HALT_NYI): Use sim_io_eprintf in place of fprintf.
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Remove extraneous whitespace.
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2016-03-24 01:37:30 +08:00
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2016-03-23 Nick Clifton <nickc@redhat.com>
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* cpustate.c (aarch64_get_FP_half): New function. Read a vector
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register as a half precision floating point number.
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(aarch64_set_FP_half): New function. Similar, but for setting
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a half precision register.
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(aarch64_get_thread_id): New function. Returns the value of the
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CPU's TPIDR register.
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(aarch64_get_FPCR): New function. Returns the value of the CPU's
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floating point control register.
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(aarch64_set_FPCR): New function. Set the value of the CPU's FPCR
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register.
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* cpustate.h: Add prototypes for new functions.
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* sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields.
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* memory.c: Use unaligned core access functions for all memory
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reads and writes.
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* simulator.c (HALT_NYI): Generate an error message if tracing
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will not tell the user why the simulator is halting.
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(HALT_UNREACHABLE): Delete. Delete (unneeded) uses of the macro.
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(INSTR): New time-saver macro.
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(fldrb_abs): New function. Loads an 8-bit value using a scaled
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offset.
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(fldrh_abs): New function. Likewise for 16-bit values.
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(do_vec_SSHL): Allow for negative shift values.
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(do_vec_USHL): Likewise.
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(do_vec_SHL): Correct computation of shift amount.
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(do_vec_SSHR_USHR): Correct decision of signed vs unsigned
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shifts and computation of shift value.
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(clz): New function. Counts leading zero bits.
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(do_vec_CLZ): New function. Implements CLZ (vector).
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(do_vec_MOV_element): Call do_vec_CLZ.
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(dexSimpleFPCondCompare): Implement.
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(do_FCVT_half_to_single): New function. Implements one of the
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FCVT operations.
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(do_FCVT_half_to_double): New function. Likewise.
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(do_FCVT_single_to_half): New function. Likewise.
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(do_FCVT_double_to_half): New function. Likewise.
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(dexSimpleFPDataProc1Source): Call new FCVT functions.
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(do_scalar_SHL): Handle negative shifts.
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(do_scalar_shift): Handle SSHR.
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(do_scalar_USHL): New function.
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(do_double_add): Simplify to just performing a double precision
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add operation. Move remaining code into...
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(do_scalar_vec): ... New function.
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(dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs
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functions.
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(system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR
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registers.
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(system_set): New function.
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(do_MSR_immediate): New function. Stub for now.
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(do_MSR_reg): New function. Likewise. Partially implements MSR
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instruction.
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(do_SYS): New function. Stub for now,
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(dexSystem): Call new functions.
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Add simulation of MUL and NEG instructions to AArch64 simulator.
* cpustate.c: Remove spurious spaces from TRACE strings.
Print hex equivalents of floats and doubles.
Check element number against array size when accessing vector
registers.
* memory.c: Trace memory reads when --trace-memory is enabled.
Remove float and double load and store functions.
* memory.h (aarch64_get_mem_float): Delete prototype.
(aarch64_get_mem_double): Likewise.
(aarch64_set_mem_float): Likewise.
(aarch64_set_mem_double): Likewise.
* simulator (IS_SET): Always return either 0 or 1.
(IS_CLEAR): Likewise.
(fldrs_pcrel): Load and store floats using 32-bit memory accesses
and doubles using 64-bit memory accesses.
(fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise.
(fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise.
(fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise.
(fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise.
(store_pair_double, load_pair_float, load_pair_double): Likewise.
(do_vec_MUL_by_element): New function.
(do_vec_op2): Call do_vec_MUL_by_element.
(do_scalar_NEG): New function.
(do_double_add): Call do_scalar_NEG.
2016-03-18 17:32:32 +08:00
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2016-03-18 Nick Clifton <nickc@redhat.com>
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* cpustate.c: Remove spurious spaces from TRACE strings.
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Print hex equivalents of floats and doubles.
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Check element number against array size when accessing vector
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registers.
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2016-03-18 22:44:27 +08:00
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(GET_VEC_ELEMENT): Fix off by one error checking for an invalid
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element index.
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(SET_VEC_ELEMENT): Likewise.
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2016-03-19 01:08:27 +08:00
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(GET_VEC_ELEMENT): And fix thinko using macro arguments.
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2016-03-18 22:44:27 +08:00
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Add simulation of MUL and NEG instructions to AArch64 simulator.
* cpustate.c: Remove spurious spaces from TRACE strings.
Print hex equivalents of floats and doubles.
Check element number against array size when accessing vector
registers.
* memory.c: Trace memory reads when --trace-memory is enabled.
Remove float and double load and store functions.
* memory.h (aarch64_get_mem_float): Delete prototype.
(aarch64_get_mem_double): Likewise.
(aarch64_set_mem_float): Likewise.
(aarch64_set_mem_double): Likewise.
* simulator (IS_SET): Always return either 0 or 1.
(IS_CLEAR): Likewise.
(fldrs_pcrel): Load and store floats using 32-bit memory accesses
and doubles using 64-bit memory accesses.
(fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise.
(fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise.
(fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise.
(fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise.
(store_pair_double, load_pair_float, load_pair_double): Likewise.
(do_vec_MUL_by_element): New function.
(do_vec_op2): Call do_vec_MUL_by_element.
(do_scalar_NEG): New function.
(do_double_add): Call do_scalar_NEG.
2016-03-18 17:32:32 +08:00
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* memory.c: Trace memory reads when --trace-memory is enabled.
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Remove float and double load and store functions.
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* memory.h (aarch64_get_mem_float): Delete prototype.
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(aarch64_get_mem_double): Likewise.
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(aarch64_set_mem_float): Likewise.
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(aarch64_set_mem_double): Likewise.
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* simulator (IS_SET): Always return either 0 or 1.
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(IS_CLEAR): Likewise.
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(fldrs_pcrel): Load and store floats using 32-bit memory accesses
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and doubles using 64-bit memory accesses.
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(fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise.
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(fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise.
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(fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise.
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(fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise.
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(store_pair_double, load_pair_float, load_pair_double): Likewise.
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(do_vec_MUL_by_element): New function.
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(do_vec_op2): Call do_vec_MUL_by_element.
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(do_scalar_NEG): New function.
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(do_double_add): Call do_scalar_NEG.
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2016-03-03 23:14:35 +08:00
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2016-03-03 Nick Clifton <nickc@redhat.com>
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* simulator.c (set_flags_for_sub32): Correct type of signbit.
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(CondCompare): Swap interpretation of bit 30.
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(DO_ADDP): Delete macro.
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(do_vec_ADDP): Copy source registers before starting to update
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destination register.
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(do_vec_FADDP): Likewise.
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(do_vec_load_store): Fix computation of sizeof_operation.
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(rbit64): Fix type of constant.
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(aarch64_step): When displaying insn value, display all 32 bits.
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2016-01-09 17:09:35 +08:00
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2016-01-10 Mike Frysinger <vapier@gentoo.org>
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* config.in, configure: Regenerate.
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2016-01-11 06:49:48 +08:00
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2016-01-10 Mike Frysinger <vapier@gentoo.org>
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* configure: Regenerate.
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2016-01-11 05:52:25 +08:00
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2016-01-10 Mike Frysinger <vapier@gentoo.org>
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* configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call.
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* configure: Regenerate.
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2016-01-10 16:50:08 +08:00
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2016-01-10 Mike Frysinger <vapier@gentoo.org>
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* configure: Regenerate.
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2016-01-11 04:55:44 +08:00
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2016-01-10 Mike Frysinger <vapier@gentoo.org>
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* configure: Regenerate.
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2016-01-10 16:50:08 +08:00
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2016-01-09 18:58:01 +08:00
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2016-01-10 Mike Frysinger <vapier@gentoo.org>
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* configure.ac (SIM_AC_OPTION_INLINE): Delete call.
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* configure: Regenerate.
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2016-01-09 17:00:53 +08:00
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2016-01-10 Mike Frysinger <vapier@gentoo.org>
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* configure: Regenerate.
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2016-01-09 18:13:37 +08:00
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2016-01-10 Mike Frysinger <vapier@gentoo.org>
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* configure: Regenerate.
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2016-01-09 09:23:37 +08:00
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2016-01-09 Mike Frysinger <vapier@gentoo.org>
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* config.in, configure: Regenerate.
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2016-01-03 14:51:44 +08:00
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2016-01-06 Mike Frysinger <vapier@gentoo.org>
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* interp.c (sim_create_inferior): Mark argv and env const.
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(sim_open): Mark argv const.
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2015-12-31 12:26:05 +08:00
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2016-01-05 Mike Frysinger <vapier@gentoo.org>
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* interp.c: Delete dis-asm.h include.
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(info, opbuf, op_printf, aarch64_print_insn, sim_dis_read): Delete.
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(sim_create_inferior): Delete disassemble init logic.
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(OPTION_DISAS, aarch64_option_handler, aarch64_options): Delete.
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(sim_open): Delete sim_add_option_table call.
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* memory.c (mem_error): Delete disas check.
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* simulator.c: Delete dis-asm.h include.
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(disas): Delete.
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(HALT_UNALLOC): Replace disassembly logic with TRACE_DISASM.
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(HALT_NYI): Likewise.
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(handle_halt): Delete disas call.
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(aarch64_step): Replace disas logic with TRACE_DISASM.
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* simulator.h: Delete dis-asm.h include.
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(aarch64_print_insn): Delete.
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2016-01-05 11:24:03 +08:00
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2016-01-04 Mike Frysinger <vapier@gentoo.org>
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* simulator.c (MAX, MIN): Delete.
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(do_vec_maxv): Change MAX to max and MIN to min.
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(do_vec_fminmaxV): Likewise.
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2015-12-09 19:34:45 +08:00
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2016-01-04 Tristan Gingold <gingold@adacore.com>
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* simulator.c: Remove syscall.h include.
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2016-01-04 17:06:01 +08:00
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2016-01-04 Mike Frysinger <vapier@gentoo.org>
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* configure: Regenerate.
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2016-01-03 13:36:13 +08:00
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2016-01-03 Mike Frysinger <vapier@gentoo.org>
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* configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
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* configure: Regenerate.
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2016-01-03 06:46:16 +08:00
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2016-01-02 Mike Frysinger <vapier@gentoo.org>
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* configure: Regenerate.
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2015-12-27 14:41:27 +08:00
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2015-12-27 Mike Frysinger <vapier@gentoo.org>
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* interp.c (sim_dis_read): Change private_data to application_data.
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(sim_create_inferior): Likewise.
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2015-04-11 07:40:34 +08:00
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2015-12-27 Mike Frysinger <vapier@gentoo.org>
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* Makefile.in (SIM_OBJS): Delete sim-hload.o.
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2015-12-27 09:20:23 +08:00
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2015-12-26 Mike Frysinger <vapier@gentoo.org>
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* config.in, configure: Regenerate.
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2015-12-26 20:05:41 +08:00
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2015-12-26 Mike Frysinger <vapier@gentoo.org>
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* interp.c (sim_create_inferior): Update comment and argv check.
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2015-12-26 20:12:13 +08:00
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2015-12-14 Nick Clifton <nickc@redhat.com>
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* simulator.c (system_get): New function. Provides read
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access to the dczid system register.
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(do_mrs): New function - implements the MRS instruction.
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(dexSystem): Call do_mrs for the MRS instruction. Halt on
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unimplemented system instructions.
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2015-11-24 Nick Clifton <nickc@redhat.com>
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* configure.ac: New configure template.
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* aclocal.m4: Generate.
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* config.in: Generate.
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* configure: Generate.
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* cpustate.c: New file - functions for accessing AArch64 registers.
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* cpustate.h: New header.
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* decode.h: New header.
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* interp.c: New file - interface between GDB and simulator.
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* Makefile.in: New makefile template.
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* memory.c: New file - functions for simulating aarch64 memory
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accesses.
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* memory.h: New header.
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* sim-main.h: New header.
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* simulator.c: New file - aarch64 simulator functions.
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* simulator.h: New header.
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