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[gas][arm] Add -mwarn-restrict-it Add a -m{no-}warn-restrict-it option to control IT related warnings in ARMv8-A and ARMv8-R. This is disabled by default. Committed on behalf of Wilco Dijkstra. gas/ChangeLog: 2019-12-11 Wilco Dijkstra <wdijkstr@arm.com> * config/tc-arm.c (warn_on_restrict_it): Add new variable. (it_fsm_post_encode): Check warn_on_restrict_it. (arm_option_table): Add -mwarn-restrict-it/-mno-warn-restrict-it. * testsuite/gas/arm/armv8-2-fp16-scalar-bad.d: Add -mwarn-restrict-it. * testsuite/gas/arm/armv8-2-fp16-scalar-bad-ext.d: Likewise. * testsuite/gas/arm/armv8-a-bad.d: Likewise. * testsuite/gas/arm/armv8-a-it-bad.d: Likewise. * testsuite/gas/arm/armv8-r-bad.d: Likewise. * testsuite/gas/arm/armv8-r-it-bad.d: Likewise. * testsuite/gas/arm/sp-pc-validations-bad-t-v8a.d: Likewise. * testsuite/gas/arm/udf.d: Likewise.
2019-12-11 23:53:26 +08:00
2019-12-11 Wilco Dijkstra <wdijkstr@arm.com>
* config/tc-arm.c (warn_on_restrict_it): Add new variable.
(it_fsm_post_encode): Check warn_on_restrict_it.
(arm_option_table): Add -mwarn-restrict-it/-mno-warn-restrict-it.
* testsuite/gas/arm/armv8-2-fp16-scalar-bad.d: Add -mwarn-restrict-it.
* testsuite/gas/arm/armv8-2-fp16-scalar-bad-ext.d: Likewise.
* testsuite/gas/arm/armv8-a-bad.d: Likewise.
* testsuite/gas/arm/armv8-a-it-bad.d: Likewise.
* testsuite/gas/arm/armv8-r-bad.d: Likewise.
* testsuite/gas/arm/armv8-r-it-bad.d: Likewise.
* testsuite/gas/arm/sp-pc-validations-bad-t-v8a.d: Likewise.
* testsuite/gas/arm/udf.d: Likewise.
x86: further refine SSE check (SSE4a, SHA, GFNI) In ("x86: extend SSE check to PCLMULQDQ, AES, and GFNI insns") I went both a little too far and not quite far enough: - GFNI insns also have AVX512 variants, which also shouldn't get diagnosed, - SSE4a insns should get diagnosed just like SSE4.x ones, - SHA insns should get diagnosed just like PCLMULQDQ or AES ones.
2019-12-11 16:42:29 +08:00
2018-12-11 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (md_assemble): Extend SSE check conditional.
* testsuite/gas/i386/sse-check.s: Add SSE4a and SHA tests.
Extend GFNI tests.
* testsuite/gas/i386/sse-check.d: Adjust expectations.
* testsuite/gas/i386/sse-check-error.l,
testsuite/gas/i386/x86-64-sse-check-error.l: Likewise.
* testsuite/gas/i386/sse-check-warn.e: Likewise.
[gas][arm] Set context table for '.arch_extension' This patch fixes .arch_extension behaviour. Currently, context table for '.arch_extension' is only set while "-march" processing, but it is not set while .arch processing, so following code is rejected .syntax unified .thumb .arch armv8.1-m.main .arch_extension mve.fp unless -march=armv8.1-m.main is given. Committing on behalf of Vladimir Murzin gas/ChangeLog: 2019-12-10 Vladimir Murzin <vladimir.murzin@arm.com> * config/tc-arm.c (s_arm_arch): Set selected_ctx_ext_table. * testsuite/gas/arm/mve-arch-ext.s: New. * testsuite/gas/arm/mve-arch-ext.d: New.
2019-12-11 00:10:17 +08:00
2019-12-10 Vladimir Murzin <vladimir.murzin@arm.com>
* config/tc-arm.c (s_arm_arch): Set selected_ctx_ext_table.
* testsuite/gas/arm/mve-arch-ext.s: New.
* testsuite/gas/arm/mve-arch-ext.d: New.
x86/Intel: fold "xmmword" with "oword" These are full aliases of one another, so there's no real need to use distinct O_md* values for them.
2019-12-09 20:32:11 +08:00
2019-12-09 Jan Beulich <jbeulich@suse.com>
* config/tc-i386-intel.c (O_oword_ptr): Move.
(O_xmmword_ptr): Alias to O_oword_ptr.
(O_fword_ptr, O_tbyte_ptr, O_ymmword_ptr, O_zmmword_ptr): Adjust
expansion.
(i386_intel_simplify, i386_intel_operand): Fold O_oword_ptr and
O_xmmword_ptr cases, leaving comments.
x86/Intel: support "mmword ptr" This is an alias of "qword ptr", commonly used with MMX insns. At this occasion also test (alongside the newly supported "mmword") - "zmmword" used as expression, - PADDB with "oword ptr" (aliasing "xmmword ptr").
2019-12-09 20:31:39 +08:00
2019-12-09 Jan Beulich <jbeulich@suse.com>
* config/tc-i386-intel.c (O_mmword_ptr): Define.
(i386_types): Add mmword entry.
(i386_intel_simplify, i386_intel_operand): Add comment.
* testsuite/gas/i386/intel-expr.s: Also test mmword and zmmword.
* testsuite/gas/i386/intelok.s: Also test "mmword ptr".
* testsuite/gas/i386/intel-expr.d, testsuite/gas/i386/intelok.d,
testsuite/gas/i386/intelok.e: Adjust expectations.
x86/Intel: fix "near ptr" / "far ptr" handling Commit dc2be329b950 ("i386: Only check suffix in instruction mnemonic") broke rejecting of these for floating point insns. Fix this by setting the "byte" operand attribute, which will now (again) cause an error. Furthermore the diagnostic for the "far ptr" case in general and for the "near ptr" case in the non-float cases became "invalid instruction suffix" instead of the intended "operand size mismatch". Fix this by also setting the "tbyte" operand attribute (no insn template accepts both byte and tbyte operands).
2019-12-09 20:31:07 +08:00
2019-12-09 Jan Beulich <jbeulich@suse.com>
* config/tc-i386-intel.c (i386_intel_operand): Set "byte"
attribute suffix instead of suffix for floating point insns when
handling O_near_ptr / O_far_ptr.
* testsuite/gas/i386/intelbad.s: Add FPU tests.
* testsuite/gas/i386/intelbad.l: Adjust expectations.
x86/Intel: drop pointless suffix setting for "tbyte ptr" There are extremely few insns accepting "tbyte ptr" operand, so the "tbyte" operand flag checking done by match_operand_size() is already sufficient; the setting of the suffix has become meaningless anyway with dc2be329b950 ("i386: Only check suffix in instruction mnemonic"). Fold the code with that setting the "byte" operand flag to force an error (no insn at all accepts both "byte ptr" and tbyte ptr" operands, except for AnySize ones where the two (conflicting) recorded types don't matter (operand_size_match() doesn't call match_operand_size() in this case).
2019-12-09 20:29:44 +08:00
2019-12-09 Jan Beulich <jbeulich@suse.com>
* config/tc-i386-intel.c (i386_intel_operand): Set "byte"
attribute suffix instead of suffix uniformly for insns not
possibly accepting "tbyte ptr" explicitly.
x86/Intel: drop pointless suffix setting for "fword ptr" No floating point insn accepts an "fword ptr" operand, so the "fword" operand flag checking done by match_mem_size() is already sufficient; the setting of the suffix has become meaningless anyway with dc2be329b950 ("i386: Only check suffix in instruction mnemonic").
2019-12-09 20:29:14 +08:00
2019-12-09 Jan Beulich <jbeulich@suse.com>
* config/tc-i386-intel.c (i386_intel_operand): Don't set suffix
for floating point insns when handling O_fword_ptr.
x86/Intel: drop pointless special casing of LxS LDS et al don't accept "word ptr" operands anyway, as per their insn templates. Hence there's no need to special case this here; the check has become dysfunctional anyway by dc2be329b950 ("i386: Only check suffix in instruction mnemonic").
2019-12-09 20:28:43 +08:00
2019-12-09 Jan Beulich <jbeulich@suse.com>
* config/tc-i386-intel.c (i386_intel_operand): Don't special
case LDS et al when handling O_word_ptr.
aarch64*-*-*ilp32 gas tests The new pac_negate_ra_state test adds yet another failure on aarch64 ipl32 targets. This patch fixes that particular problem and a few more that are trivial to fix. * testsuite/gas/aarch64/bfloat16.d: Match 32-bit and 64-bit output. * testsuite/gas/aarch64/dgh.d: Likewise. * testsuite/gas/aarch64/f32mm.d: Likewise. * testsuite/gas/aarch64/f64mm.d: Likewise. * testsuite/gas/aarch64/i8mm.d: Likewise. * testsuite/gas/aarch64/pac_ab_key.d: Likewise. * testsuite/gas/aarch64/pac_negate_ra_state.d: Likewise. * testsuite/gas/aarch64/reloc-prel_g0.d: Likewise. * testsuite/gas/aarch64/reloc-prel_g0_nc.d: Likewise. * testsuite/gas/aarch64/reloc-prel_g1.d: Likewise. * testsuite/gas/aarch64/sve-bfloat-movprfx.d: Likewise. * testsuite/gas/aarch64/sve-movprfx-mm.d: Likewise. * testsuite/gas/aarch64/sve2.d: Likewise.
2019-12-07 20:01:43 +08:00
2019-12-08 Alan Modra <amodra@gmail.com>
* testsuite/gas/aarch64/bfloat16.d: Match 32-bit and 64-bit output.
* testsuite/gas/aarch64/dgh.d: Likewise.
* testsuite/gas/aarch64/f32mm.d: Likewise.
* testsuite/gas/aarch64/f64mm.d: Likewise.
* testsuite/gas/aarch64/i8mm.d: Likewise.
* testsuite/gas/aarch64/pac_ab_key.d: Likewise.
* testsuite/gas/aarch64/pac_negate_ra_state.d: Likewise.
* testsuite/gas/aarch64/reloc-prel_g0.d: Likewise.
* testsuite/gas/aarch64/reloc-prel_g0_nc.d: Likewise.
* testsuite/gas/aarch64/reloc-prel_g1.d: Likewise.
* testsuite/gas/aarch64/sve-bfloat-movprfx.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx-mm.d: Likewise.
* testsuite/gas/aarch64/sve2.d: Likewise.
[gas] Implement .cfi_negate_ra_state directive This patch implements the .cfi_negate_ra_state to be consistent with LLVM (https://reviews.llvm.org/D50136). The relevant DWARF code DW_CFA_AARCH64_negate_ra_state is multiplexed on top of DW_CFA_GNU_window_save, as per https://gcc.gnu.org/ml/gcc-patches/2017-08/msg00753.html I believe this is the simplest patch implementing this and is needed to allow users to build, for example, the Linux kernel with Armv8.3-A pointer authentication support with Clang while using gas as the assembler, which is a common usecase. gas/ 2019-12-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * dw2gencfi.c (cfi_pseudo_table): Add cfi_negate_ra_state. * testsuite/gas/aarch64/pac_negate_ra_state.s: New file. * testsuite/gas/aarch64/pac_negate_ra_state.d: Likewise.
2019-12-06 18:46:32 +08:00
2019-12-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* dw2gencfi.c (cfi_pseudo_table): Add cfi_negate_ra_state.
* testsuite/gas/aarch64/pac_negate_ra_state.s: New file.
* testsuite/gas/aarch64/pac_negate_ra_state.d: Likewise.
Arm64: simplify Crypto arch extension handling This, at the assembler level, is just a "brace" feature covering both AES and SHA2. Hence there's no need for it to have a separate feature flag, freeing up a bit for future re-use. Along these lines there are also a number of dead definitions/variables in the opcode table file.
2019-12-05 15:44:22 +08:00
2019-12-05 Jan Beulich <jbeulich@suse.com>
* config/tc-aarch64.c (aarch64_features): Drop redundant AES and
SHA2 flags from "crypto" entry.
Arm64: correct "sha3" arch-extension directive handling SHA2 is a prereq to SHA3, not part of it aiui. Hence disabling the latter should not also disable the former. In the course of adding respective tests also do away with the duplication of crypto.d's contents in crypto-directive.d.
2019-12-05 15:43:03 +08:00
2019-12-05 Jan Beulich <jbeulich@suse.com>
* config/tc-aarch64.c (aarch64_features): Make SHA2 a prereq of
SHA3.
* testsuite/gas/aarch64/crypto.s
* testsuite/gas/aarch64/crypto-directive.d: Refer to crypto.d
for actual output.
* testsuite/gas/aarch64/illegal-crypto-nofp.l: Relax
expectations.
* testsuite/gas/aarch64/crypto-directive2.d,
testsuite/gas/aarch64/crypto-directive3.d: New.
x86-64: accept 64-bit LFS/LGS/LSS forms with suffix or operand size specifier Since we accept these without suffix / operand size specifier, we should also do so with one. (The fact that we unilaterally accept these, other than far branches, rather than limiting them to Intel64 mode, will be taken care of later on.) Also take the opportunity and make sure "lfs <reg>, tbyte ptr <mem>" et al get rejected outside of 64-bit mode. This became broken by dc2be329b950 ("i386: Only check suffix in instruction mnemonic"). Furthermore cover lgdt et al in the Intel syntax handling as well, which continued to work after said commit just by coincidence.
2019-12-04 17:45:17 +08:00
2019-12-04 Jan Beulich <jbeulich@suse.com>
* config/tc-i386-intel.c (i386_intel_operand): Handle LFS et al
as well as LGDT at al when processing O_tbyte_ptr.
* testsuite/gas/i386/intelbad.s: Add LDS et al cases.
* testsuite/gas/i386/x86-64-intel64.s,
* testsuite/gas/i386/x86-64-opcode.s: Add LFS et al cases.
* testsuite/gas/i386/ilp32/x86-64-intel64.d: Add -mintel64
command line option and fold expectations with parent dir test.
* testsuite/gas/i386/x86-64-intel64.d: Add -mintel64 command
line option and adjust expectations.
* testsuite/gas/i386/intelbad.l,
testsuite/gas/i386/x86-64-opcode.d: Adjust expectations.
x86-64/Intel: fix CALL/JMP with dword operand While dc2be329b950 ("i386: Only check suffix in instruction mnemonic") has made the assembler accept these in the first place (they were wrongly rejected before), the generated code was still wrong in that it lacked an operand size override. (In 64-bit code, other than in 16- and 32-bit ones, CALL and JMP with memory operands are all entirely unambiguous: No operand size can have two meanings.)
2019-12-04 17:44:27 +08:00
2019-12-04 Jan Beulich <jbeulich@suse.com>
* config/tc-i386-intel.c (i386_intel_operand): Also handle DWORD
with 64-bit mode branches.
* testsuite/gas/i386/x86-64-jump.s: Extend Intel syntax branch
operand coverage.
* testsuite/gas/i386/x86-64-jump.d: Adjust expectations.
x86: consolidate tracking of MMX register use Just like for XMM/YMM/ZMM don't key this to any Cpu* flags. Instead include the two special insns (not having register operands) explicitly.
2019-12-04 17:43:50 +08:00
2019-12-04 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (output_insn): Don't consider Cpu* settings
when setting GNU_PROPERTY_X86_FEATURE_2_MMX.
x86/Intel: extend MOVDIRI testing Test also memory operands with operand size specifier, which was broken prior to dc2be329b950 ("i386: Only check suffix in instruction mnemonic"), due to the template not permitting any suffixes. Note that this uncovered a disassembler issue, which is being fixed here as well.
2019-12-04 17:41:43 +08:00
2019-12-04 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/movdir.s: Add Intel syntax case with
operand size specifier.
* testsuite/gas/i386/x86-64-movdir.s: Add Intel syntax cases
with operand size specifier and wit 32-bit operands.
* testsuite/gas/i386/movdir-intel.d,
testsuite/gas/i386/movdir.d,
testsuite/gas/i386/x86-64-movdir-intel.d,
testsuite/gas/i386/x86-64-movdir.d: Adjust expectations.
x86: make sure all PUSH/POP honor DefaultSize While segment registers are registers, their use doesn't allow sizing of insns without suffix / explicit operand size specifier. Prevent PUSH and POP of segment registers from entering that path, instead allowing them to observe the stackop_size setting just like other PUSH/POP and alike do.
2019-12-04 17:40:40 +08:00
2019-12-04 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (process_suffix): Arrange for insns with a
single non-GPR register operand to not have its suffix guessed
from GPR operands. Extend DefaultSize handling to cover PUSH/POP
of segment registers.
* testsuite/gas/i386/general.s: Add PUSH/POP sreg to .code16gcc
set of insns.
* testsuite/gas/i386/general.l: Adjust expectations.
x86: drop some stray/bogus DefaultSize Insns permitting only GPR operands (and hence implicit sizing when there's no suffix) don't ever have their DefaultSize attribute inspected, so it shouldn't be there in the first place. Additionally XBEGIN is like JMP, not CALL, and hence shouldn't be converted to 32-bit operand size in .code16gcc mode. While the same is true for SYSRET, it permitting more than one suffix makes it FLDENV- like, and hence rather than dropping the attribute, for now add it to the exclusion list to avoid it getting an operand size prefix emitted in .code16gcc mode. (This will be dealt with later, perhaps together with FLDENV and friends.)
2019-12-04 17:40:02 +08:00
2019-12-04 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (process_suffix): Exclude SYSRET alongside
FLDENV et al.
* testsuite/gas/i386/general.s: Expand .code16gcc set of insns.
* testsuite/gas/i386/general.l: Adjust expectations.
gas/riscv: Produce version 3 DWARF CIE by default The flag controlling the default DWARF CIE version to produce now starts with the value -1. This can be modified with the command line flag as before, but after command line flag processing, in md_after_parse_args targets can, if the global still has the value -1, override this value. This gives a target specific default. If a CIE version is not select either by command line flag, or a target specific default, then some new code in dwarf2_init now select a global default. This remains as version 1 to match previous behaviour. This RISC-V has a target specific default of version provided, this make the return column uleb128, which means we can use all DWARF registers include CSRs. I chose to switch to version 3 rather than version 4 as this is most similar to the global default (version 1). Switching to version 4 adds additional columns to the CIE header. gas/ChangeLog: * as.c (flag_dwarf_cie_version): Change initial value to -1, and update comment. * config/tc-riscv.c (riscv_after_parse_args): Set flag_dwarf_cie_version if it has not already been set. * dwarf2dbg.c (dwarf2_init): Initialise flag_dwarf_cie_version if needed. * testsuite/gas/riscv/default-cie-version.d: New file. * testsuite/gas/riscv/default-cie-version.s: New file. ld/ChangeLog: * testsuite/ld-elf/eh5.d: Accept version 3 DWARF CIE. Change-Id: Ibbfe8f0979fba480bf0a359978b09d2b3055555e
2019-11-05 07:03:10 +08:00
2019-11-22 Andrew Burgess <andrew.burgess@embecosm.com>
* as.c (flag_dwarf_cie_version): Change initial value to -1, and
update comment.
* config/tc-riscv.c (riscv_after_parse_args): Set
flag_dwarf_cie_version if it has not already been set.
* dwarf2dbg.c (dwarf2_init): Initialise flag_dwarf_cie_version if
needed.
* testsuite/gas/riscv/default-cie-version.d: New file.
* testsuite/gas/riscv/default-cie-version.s: New file.
gas: Check for overflow on return column in version 1 CIE DWARF In version 1 of DWARF CIE format, the return register column is just a single byte. For targets with large numbers of DWARF registers, any use of a register with a high number for the return column will (currently) silently overflow giving incorrect DWARF. This commit adds an error when the overflow occurs. gas/ChangeLog: * dw2gencfi.c (output_cie): Error on return column overflow. * testsuite/gas/riscv/cie-rtn-col-1.d: New file. * testsuite/gas/riscv/cie-rtn-col-3.d: New file. * testsuite/gas/riscv/cie-rtn-col.s: New file. Change-Id: I1809f739ba7771737ec012807f0260e1a3ed5e64
2019-11-05 06:44:48 +08:00
2019-11-22 Andrew Burgess <andrew.burgess@embecosm.com>
* dw2gencfi.c (output_cie): Error on return column overflow.
* testsuite/gas/riscv/cie-rtn-col-1.d: New file.
* testsuite/gas/riscv/cie-rtn-col-3.d: New file.
* testsuite/gas/riscv/cie-rtn-col.s: New file.
binutils/gas/riscv: Add DWARF register numbers for CSRs This commit gives DWARF register numbers to the RISC-V CSRs inline with the RISC-V ELF specification here: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md The CSRs are defined being numbered from 4096 to 8191. This adds support to the assembler, required in order to reference CSRs in, for example .cfi directives. I have then extended dwarf.c in order to support printing CSR names in the dumped DWARF output. As the CSR name space is quite large and only sparsely populated, I have provided a new function to perform RISC-V DWARF register name lookup which uses a switch statement rather than the table base approach that other architectures use. Any CSR that does not have a known name will return a name based on 'csr%d' with the %d being replaced by the offset of the CSR from 4096. gas/ChangeLog: * config/tc-riscv.c (tc_riscv_regname_to_dw2regnum): Lookup CSR names too. * testsuite/gas/riscv/csr-dw-regnums.d: New file. * testsuite/gas/riscv/csr-dw-regnums.s: New file. binutils/ChangeLog: * dwarf.c (regname_internal_riscv): New function. (init_dwarf_regnames_riscv): Use new function. Change-Id: I3f70bc24fa8b3c75744e6775eeeb87db70c7ecfb
2019-11-19 00:00:59 +08:00
2019-11-22 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-riscv.c (tc_riscv_regname_to_dw2regnum): Lookup CSR
names too.
* testsuite/gas/riscv/csr-dw-regnums.d: New file.
* testsuite/gas/riscv/csr-dw-regnums.s: New file.
gas/riscv: Remove unneeded structure We build a hash table of all register classes and numbers. The hash key is the register name and the hash value is the class and number encoded into a single value, which is of type 'void *'. When we pull the values out of the hash we cast them to be a pointer to a structure, however, we never access the fields of that structure, we just decode the register class and number from the pointer value itself. This commit removes the structure and treats the encoded class and number as a 'void *' during hash lookup. gas/ChangeLog: * config/tc-riscv.c (struct regname): Delete. (hash_reg_names): Handle value as 'void *'. Change-Id: Ie7d8f46ca3798f56f4af94395279de684f87f9cc
2019-10-29 20:56:50 +08:00
2019-11-22 Andrew Burgess <andrew.burgess@embecosm.com>
* config/tc-riscv.c (struct regname): Delete.
(hash_reg_names): Handle value as 'void *'.
Fix "psb CSYNC" and "bti C". psb CYSNC was not finding that CSYNC was a correct spelling. The problem was upper case version was being put in the wrong hashtable. This fixes the problem by using the correct hashtable. Also adds testcases for the upper case versions. * config/tc-aarch64.c (md_begin): Use correct hash table for uppercase version of hint. * testsuite/gas/aarch64/system-2.s: Extend psb case to uppercase. * testsuite/gas/aarch64/system-2.d: Update. Change-Id: If43f8b85cacd24840d596c3092b0345e5f212766
2019-11-22 04:53:02 +08:00
2019-11-25 Andrew Pinski <apinski@marvell.com>
* config/tc-aarch64.c (md_begin): Use correct
hash table for uppercase version of hint.
* testsuite/gas/aarch64/system-2.s: Extend psb case to uppercase.
* testsuite/gas/aarch64/system-2.d: Update.
Introduce new section flag: SEC_ELF_OCTETS All symbols, sizes and relocations in this section are octets instead of bytes. Required for DWARF debug sections as DWARF information is organized in octets, not bytes. bfd/ * section.c (struct bfd_section): New flag SEC_ELF_OCTETS. * archures.c (bfd_octets_per_byte): New parameter sec. If section is not NULL and SEC_ELF_OCTETS is set, one octet es returned [ELF targets only]. * bfd.c (bfd_get_section_limit): Provide section parameter to bfd_octets_per_byte. * bfd-in2.h: regenerate. * binary.c (binary_set_section_contents): Move call to bfd_octets_per_byte into section loop. Provide section parameter to bfd_octets_per_byte. * coff-arm.c (coff_arm_reloc): Provide section parameter to bfd_octets_per_byte. * coff-i386.c (coff_i386_reloc): likewise. * coff-mips.c (mips_reflo_reloc): likewise. * coff-x86_64.c (coff_amd64_reloc): likewise. * cofflink.c (_bfd_coff_link_input_bfd): likewise. (_bfd_coff_reloc_link_order): likewise. * elf.c (_bfd_elf_section_offset): likewise. (_bfd_elf_make_section_from_shdr): likewise. Set SEC_ELF_OCTETS for sections with names .gnu.build.attributes, .debug*, .zdebug* and .note.gnu*. * elf32-msp430.c (rl78_sym_diff_handler): Provide section parameter to bfd_octets_per_byte. * elf32-nds.c (nds32_elf_get_relocated_section_contents): likewise. * elf32-ppc.c (ppc_elf_addr16_ha_reloc): likewise. * elf32-pru.c (pru_elf32_do_ldi32_relocate): likewise. * elf32-s12z.c (opru18_reloc): likewise. * elf32-sh.c (sh_elf_reloc): likewise. * elf32-spu.c (spu_elf_rel9): likewise. * elf32-xtensa.c (bfd_elf_xtensa_reloc): likewise * elf64-ppc.c (ppc64_elf_brtaken_reloc): likewise. (ppc64_elf_addr16_ha_reloc): likewise. (ppc64_elf_toc64_reloc): likewise. * elflink.c (bfd_elf_final_link): likewise. (bfd_elf_perform_complex_relocation): likewise. (elf_fixup_link_order): likewise. (elf_link_input_bfd): likewise. (elf_link_sort_relocs): likewise. (elf_reloc_link_order): likewise. (resolve_section): likewise. * linker.c (_bfd_generic_reloc_link_order): likewise. (bfd_generic_define_common_symbol): likewise. (default_data_link_order): likewise. (default_indirect_link_order): likewise. * srec.c (srec_set_section_contents): likewise. (srec_write_section): likewise. * syms.c (_bfd_stab_section_find_nearest_line): likewise. * reloc.c (_bfd_final_link_relocate): likewise. (bfd_generic_get_relocated_section_contents): likewise. (bfd_install_relocation): likewise. For section which have SEC_ELF_OCTETS set, multiply output_base and output_offset with bfd_octets_per_byte. (bfd_perform_relocation): likewise. include/ * coff/ti.h (GET_SCNHDR_SIZE, PUT_SCNHDR_SIZE, GET_SCN_SCNLEN), (PUT_SCN_SCNLEN): Adjust bfd_octets_per_byte calls. binutils/ * objdump.c (disassemble_data): Provide section parameter to bfd_octets_per_byte. (dump_section): likewise (dump_section_header): likewise. Show SEC_ELF_OCTETS flag if set. gas/ * as.h: Define SEC_OCTETS as SEC_ELF_OCTETS if OBJ_ELF. * dwarf2dbg.c: (dwarf2_finish): Set section flag SEC_OCTETS for .debug_line, .debug_info, .debug_abbrev, .debug_aranges, .debug_str and .debug_ranges sections. * write.c (maybe_generate_build_notes): Set section flag SEC_OCTETS for .gnu.build.attributes section. * frags.c (frag_now_fix): Don't divide by OCTETS_PER_BYTE if SEC_OCTETS is set. * symbols.c (resolve_symbol_value): Likewise. ld/ * ldexp.c (fold_name): Provide section parameter to bfd_octets_per_byte. * ldlang (init_opb): New argument s. Set opb_shift to 0 if SEC_ELF_OCTETS for the current section is set. (print_input_section): Pass current section to init_opb. (print_data_statement,print_reloc_statement, print_padding_statement): Likewise. (lang_check_section_addresses): Call init_opb for each section. (lang_size_sections_1,lang_size_sections_1, lang_do_assignments_1): Likewise. (lang_process): Pass NULL to init_opb.
2019-11-22 05:17:29 +08:00
2019-11-25 Christian Eggers <ceggers@gmx.de>
* as.h: Define SEC_OCTETS as SEC_ELF_OCTETS if OBJ_ELF.
* dwarf2dbg.c: (dwarf2_finish): Set section flag SEC_OCTETS for
.debug_line, .debug_info, .debug_abbrev, .debug_aranges, .debug_str
and .debug_ranges sections.
* write.c (maybe_generate_build_notes): Set section flag
SEC_OCTETS for .gnu.build.attributes section.
* frags.c (frag_now_fix): Don't divide by OCTETS_PER_BYTE if
SEC_OCTETS is set.
* symbols.c (resolve_symbol_value): Likewise.
Reverts patches providing octet support in dwarf Reverts "dwarf2: Align relocation within .debug_line section" commit 204f543cae7a5dc908264b49d558191d0ceb989c, Reverts "dwarf2: Pad size of .debug_line section." commit 145c4477d239fef4e31a457ff8a1ba7153e9a448, Reverts "dwarf2: Use octets for .debug_line prologue" commit 38c24f42c97af59ad83505ed735e689c63d3ca45, Mostly reverts "dwarf2: Use octets for dwarf2 headers" commit 7235427998571b6d8267e7ac72a52d7b082f4c2b, Mostly reverts "Symbols with octets value" commit d18d199917337537713f9fc4b7ae4d6568f740cf. * dwarf2dbg.c (out_set_addr): Revert 2019-03-13 change. (out_debug_line, out_debug_aranges, out_debug_info): Likewise. * symbols.h (symbol_set_value_now_octets, symbol_octets_p): Remove. * symbols.c (struct symbol_flags): Remove member sy_octets. (symbol_temp_new_now_octets): Don't set symbol_flags::sy_octets. (resolve_symbol_value): Revert: Return octets instead of bytes if sy_octets is set. (symbol_set_value_now_octets): Remove. (symbol_octets_p): Remove.
2019-11-22 05:17:24 +08:00
2019-11-25 Christian Eggers <ceggers@gmx.de>
* dwarf2dbg.c (out_set_addr): Revert 2019-03-13 change.
(out_debug_line, out_debug_aranges, out_debug_info): Likewise.
* symbols.h (symbol_set_value_now_octets, symbol_octets_p): Remove.
* symbols.c (struct symbol_flags): Remove member sy_octets.
(symbol_temp_new_now_octets): Don't set symbol_flags::sy_octets.
(resolve_symbol_value): Revert: Return octets instead of bytes if
sy_octets is set.
(symbol_set_value_now_octets): Remove.
(symbol_octets_p): Remove.
Arm: Change CRC from fpu feature to archititectural extension This patch changes the CRC extension to use the core feature bits instead of the coproc/fpu feature bits. CRC is not an fpu feature and it causes issues with the new fpu reset patch (f439988037a589de3798f44e7268301adaec21a9). CRC can be set using the '.arch_extension' directive, which sets bits in the coproc bitfield. When a '.fpu' directive is encountered, the CRC feature bit gets removed and there is no way to set it back using '.fpu'. With this patch, CRC will be marked in the feature core bits, which prevents it from getting removed when setting/changing the fpu options. gas/ChangeLog: * config/tc-arm.c (arm_ext_crc): New. (crc_ext_armv8): Remove. (insns): Rename crc_ext_armv8 to arm_ext_crc. (arm_cpus): Replace CRC_EXT_ARMV8 with ARM_EXT2_CRC. (armv8a_ext_table, armv8r_ext_table, arm_option_extension_value_table): Redefine the crc extension in terms of ARM_EXT2_CRC. * gas/testsuite/gas/arm/crc-ext.s: New. * gas/testsuite/gas/arm/crc-ext.d: New. include/ChangeLog: * opcode/arm.h (ARM_EXT2_CRC): New extension feature to replace CRC_EXT_ARMV8. (CRC_EXT_ARMV8): Remove and mark bit as unused. (ARM_ARCH_V8A_CRC, ARM_ARCH_V8_1A, ARM_ARCH_V8_2A, ARM_ARCH_V8_3A, ARM_ARCH_V8_4A, ARM_ARCH_V8_5A, ARM_ARCH_V8_6A): Redefine using ARM_EXT2_CRC instead of CRC_EXT_ARMV8. opcodes/ChangeLog: * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes): Change the coproc CRC conditions to use the extension feature set, second word, base on ARM_EXT2_CRC.
2019-11-22 21:44:17 +08:00
2019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
* config/tc-arm.c (arm_ext_crc): New.
(crc_ext_armv8): Remove.
(insns): Rename crc_ext_armv8 to arm_ext_crc.
(arm_cpus): Replace CRC_EXT_ARMV8 with ARM_EXT2_CRC.
(armv8a_ext_table, armv8r_ext_table,
arm_option_extension_value_table): Redefine the crc
extension in terms of ARM_EXT2_CRC.
* gas/testsuite/gas/arm/crc-ext.s: New.
* gas/testsuite/gas/arm/crc-ext.d: New.
PR24944, gas doesn't read enough digits when parsing a floating point number PR 24944 * atof-generic.c (atof_generic): Increase decimal guard digits. * testsuite/gas/i386/fp.s: Add more tests. * testsuite/gas/i386/fp.d: Update.
2019-11-20 19:24:07 +08:00
2019-11-20 Alan Modra <amodra@gmail.com>
PR 24944
* atof-generic.c (atof_generic): Increase decimal guard digits.
* testsuite/gas/i386/fp.s: Add more tests.
* testsuite/gas/i386/fp.d: Update.
gas: Add --gdwarf-cie-version command line flag Add a flag to control the version of CIE that is generated. By default gas produces CIE version 1, and this continues to be the default after this patch. However, a user can now provide --gdwarf-cie-version=NUMBER to switch to either version 3 or version 4 of CIE, version 2 was never released, and so causes an error as does any number less than 1 or greater than 4. Producing version 4 CIE requires two new fields to be added to the CIE, an address size field, and an segment selector field. For a flat address space the DWARF specification indicates that the segment selector should be 0, and the address size fields just contains the address size in bytes. For now we support 4 or 8 byte addresses, and the segment selector is always produced as 0. At some future time we might need to allow targets to override this. gas/ChangeLog: * as.c (parse_args): Parse --gdwarf-cie-version option. (flag_dwarf_cie_version): New variable. * as.h (flag_dwarf_cie_version): Declare. * dw2gencfi.c (output_cie): Switch from DW_CIE_VERSION to flag_dwarf_cie_version. * doc/as.texi (Overview): Document --gdwarf-cie-version. * NEWS: Likewise. * testsuite/gas/cfi/cfi.exp: Add new tests. * testsuite/gas/cfi/cie-version-0.d: New file. * testsuite/gas/cfi/cie-version-1.d: New file. * testsuite/gas/cfi/cie-version-2.d: New file. * testsuite/gas/cfi/cie-version-3.d: New file. * testsuite/gas/cfi/cie-version-4.d: New file. * testsuite/gas/cfi/cie-version.s: New file. include/ChangeLog: * dwarf2.h (DW_CIE_VERSION): Delete. Change-Id: I9de19461aeb8332b5a57bbfe802953d0725a7ae8
2019-11-04 20:27:45 +08:00
2019-11-18 Andrew Burgess <andrew.burgess@embecosm.com>
* as.c (parse_args): Parse --gdwarf-cie-version option.
(flag_dwarf_cie_version): New variable.
* as.h (flag_dwarf_cie_version): Declare.
* dw2gencfi.c (output_cie): Switch from DW_CIE_VERSION to
flag_dwarf_cie_version.
* doc/as.texi (Overview): Document --gdwarf-cie-version.
* NEWS: Likewise.
* testsuite/gas/cfi/cfi.exp: Add new tests.
* testsuite/gas/cfi/cie-version-0.d: New file.
* testsuite/gas/cfi/cie-version-1.d: New file.
* testsuite/gas/cfi/cie-version-2.d: New file.
* testsuite/gas/cfi/cie-version-3.d: New file.
* testsuite/gas/cfi/cie-version-4.d: New file.
* testsuite/gas/cfi/cie-version.s: New file.
x86: fold individual Jump* attributes into a single Jump one ..., taking just 3 bits instead of 5. No two of them are used together.
2019-11-14 15:47:44 +08:00
2019-11-14 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (operand_size_match, md_assemble,
parse_insn, match_template, process_suffix, output_jump,
output_insn, i386_displacement): Adjust jump* field use/
handling.
* config/tc-i386-intel.c (i386_intel_operand): Likewise.
x86: make JumpAbsolute an insn attribute ... instead of an operand one: There's only ever one operand here anyway.
2019-11-14 15:47:03 +08:00
2019-11-14 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (struct _i386_insn): Add jumpabsolute field.
(operand_type_match): Drop jumpabsolute use.
(type_names): Remove OPERAND_TYPE_JUMPABSOLUTE entry.
(process_suffix, i386_displacement): Adjust jumpabsolute uses.
(match_template, i386_att_operand): Adjust jumpabsolute
handling.
* config/tc-i386-intel.c (i386_intel_operand): Likewise.
x86: make AnySize an insn attribute ... instead of an operand one. Which operand it applies to can be determined from other operand properties, but as it turns out the only place it is actually used at doesn't even need further qualification.
2019-11-14 15:46:19 +08:00
2019-11-14 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (operand_size_match): Adjust anysize use.
x86/Intel: correct CMPSD test cases' regexp closing paren placement The CMPS test case derivation from their MOVS counterparts I did in d241b91073 ("x86/Intel: correct MOVSD and CMPSD handling") ended up with misplaced closing parentheses in som regexps. Correct this.
2019-11-14 15:45:26 +08:00
2019-11-14 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/intel-cmps32.d,
testsuite/gas/i386/intel-cmps64.d: Correct regexp closing
parentheses placement.
x86/Intel: extend MOVSD/CMPSD testsuite coverage This is still in the context of PR/gas 25167.
2019-11-14 15:44:57 +08:00
2019-11-14 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/intel-cmps.s,
testsuite/gas/i386/intel-movs.s: Extend.
* testsuite/gas/i386/intel-cmps32.d,
testsuite/gas/i386/intel-cmps64.d,
testsuite/gas/i386/intel-movs32.d,
testsuite/gas/i386/intel-movs64.d: Adjust expectations.
* testsuite/gas/i386/intel-cmps16.d,
testsuite/gas/i386/intel-movs16.d: New.
* testsuite/gas/i386/i386.exp: Run new tests.
RISC-V: Support the INSN_CLASS.*F.* classes for .insn directive. We have to enable the f extension through -march or ELF attribute if we use the FPR in .insn directive. The behavior is same as the riscv_opcodes. 2019-11-12 Nelson Chu <nelson.chu@sifive.com> opcodes/ * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we use the floating point register (FPR). gas/ * testsuite/gas/riscv/insn.d: Add the f extension to -march option. Change-Id: I4f59d04c82673ef84c56ecd2659ad8ce164dd626
2019-11-13 08:13:00 +08:00
2019-11-12 Nelson Chu <nelson.chu@sifive.com>
* testsuite/gas/riscv/insn.d: Add the f extension to -march option.
[gas][arm] Enable VLDM, VSTM, VPUSH, VPOP for MVE This patch enables a few instructions for Armv8.1-M MVE. Currently VLDM, VSTM, VSTR, VLDR, VPUSH and VPOP are enabled only when the Armv8-M Floating-point Extension is enabled. According to the ARMv8.1-M ARM, section A.1.4.2[1], they can be enabled by having "Armv8-M Floating-point Extension and/or Armv8.1-M MVE". [1]https://developer.arm.com/docs/ddi0553/bh/armv81-m-architecture-reference-manual 2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com> * config/tc-arm.c (do_vfp_nsyn_push): Move in order to enable it for both fpu_vfp_ext_v1xd and mve_ext and add call to the aliased vstm instruction for mve_ext. (do_vfp_nsyn_pop): Move in order to enable it for both fpu_vfp_ext_v1xd and mve_ext and add call to the aliased vldm instruction for mve_ext. (do_neon_ldm_stm): Add fpu_vfp_ext_v1 and mve_ext checks. (insns): Enable vldm, vldmia, vldmdb, vstm, vstmia, vstmdb, vpop, vpush, and fldd, fstd, flds, fsts for arm_ext_v6t2 instead of fpu_vfp_ext_v1xd. * testsuite/gas/arm/v8_1m-mve.s: New. * testsuite/gas/arm/v8_1m-mve.d: New.
2019-11-12 21:57:20 +08:00
2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
* config/tc-arm.c (do_vfp_nsyn_push): Move in order to enable it for
both fpu_vfp_ext_v1xd and mve_ext and add call to the aliased vstm
instruction for mve_ext.
(do_vfp_nsyn_pop): Move in order to enable it for both
fpu_vfp_ext_v1xd and mve_ext and add call to the aliased vldm
instruction for mve_ext.
(do_neon_ldm_stm): Add fpu_vfp_ext_v1 and mve_ext checks.
(insns): Enable vldm, vldmia, vldmdb, vstm, vstmia, vstmdb, vpop,
vpush, and fldd, fstd, flds, fsts for arm_ext_v6t2 instead
of fpu_vfp_ext_v1xd.
* testsuite/gas/arm/v8_1m-mve.s: New.
* testsuite/gas/arm/v8_1m-mve.d: New.
[binutils][arm] Update the decoding of MVE VMOV, VMVN This patch updates the decoding of the VMOV and VMVN instructions which depend on cmode. Previously VMOV and VMVN with cmode 1101 were not allowed. The cmode changes also required updating of the MVE conflict checking. Now instructions with opcodes 0xef800d50 and 0xef800e70 correctly get decoded as VMOV and VMVN, respectively. 2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com> * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with cmode 1101. (is_mve_encoding_conflict): Update cmode conflict checks for MVE_VMVN_IMM. 2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com> * gas/config/tc-arm.c (do_neon_mvn): Allow mve_ext cmode=0xd. * testsuite/gas/arm/mve-vmov-vmvn-vorr-vbic.s: New test. * testsuite/gas/arm/mve-vmov-vmvn-vorr-vbic.d: Likewise.
2019-11-12 21:55:37 +08:00
2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
* gas/config/tc-arm.c (do_neon_mvn): Allow mve_ext cmode=0xd.
* testsuite/gas/arm/mve-vmov-vmvn-vorr-vbic.s: New test.
* testsuite/gas/arm/mve-vmov-vmvn-vorr-vbic.d: Likewise.
[gas][arm] Make .fpu reset the FPU/Coprocessor feature bits This patch is fixes the '.fpu' behaviour. Currently, using '.fpu' resets the previously selected '.fpu' options (by overwriting them), but does not reset previous FPU options selected by other means (ie. when using '.arch_extension fp' in conjunction with '.fpu <x>', the FPU is not reset). Example: .arch armv8-a @ SET BASE .arch_extension fp @ ADD FP-ARMV8 .fpu vfpv2 @ ADD (already existing bits, does not reset) vfms.f32 s0, s1, s2 @ OK .arch armv8-a @ RESET .fpu fp-armv8 @ ADD FP-ARMV8 vfms.f32 s0, s1, s2 @ OK .fpu vfpv2 @ RESET to VFPV2 vfms.f32 s0, s1, s2 @ ERROR After the patch this becomes: .arch armv8-a @ SET BASE .arch_extension fp @ ADD FP-ARMV8 .fpu vfpv2 @ RESET TO VFPV2 vfms.f32 s0, s1, s2 @ ERROR .arch armv8-a @ RESET .fpu fp-armv8 @ ADD FP-ARMV8 vfms.f32 s0, s1, s2 @ OK .fpu vfpv2 @ RESET to VFPV2 vfms.f32 s0, s1, s2 @ ERROR gas/ChangeLog: 2019-11-11 Mihail Ionescu <mihail.ionescu@arm.com> * config/tc-arm.c (s_arm_fpu): Clear selected_cpu fpu bits. (fpu_any): Remove OBJ_ELF guards. * gas/testsuite/gas/arm/fpu-rst.s: New. * gas/testsuite/gas/arm/fpu-rst.d: New. * gas/testsuite/gas/arm/fpu-rst.l: New.
2019-11-12 21:53:06 +08:00
2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
* config/tc-arm.c (s_arm_fpu): Clear selected_cpu fpu bits.
(fpu_any): Remove OBJ_ELF guards.
* testsuite/gas/arm/fpu-rst.s: New.
* testsuite/gas/arm/fpu-rst.d: New.
* testsuite/gas/arm/fpu-rst.l: New.
x86: fold EsSeg into IsString EsSeg (a per-operand bit) is used with IsString (a per-insn attribute) only. Extend the attribute to 2 bits, thus allowing to encode - not a string insn, - string insn with neither operand requiring use of %es:, - string insn with 1st operand requiring use of %es:, - string insn with 2nd operand requiring use of %es:, which covers all possible cases, allowing to drop EsSeg. The (transient) need to comment out the OTUnused #define did uncover an oversight in the earlier OTMax -> OTNum conversion, which is being taken care of here.
2019-11-12 16:09:31 +08:00
2019-11-12 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (type_names): Remove OPERAND_TYPE_ESSEG
entry.
(md_assemble): Adjust isstring field use. Add assertion.
(check_string): Mostly re-write.
(i386_index_check): Adjust isstring field use and related code.
x86: eliminate ImmExt abuse Drop the remaining instances left in place by commit c3949f432f ("x86: limit ImmExt abuse), now that we have a way to specify specific GPRs. Take the opportunity and also introduce proper 16-bit forms of applicable SVME insns as well as 1-operand forms of CLZERO.
2019-11-12 16:08:32 +08:00
2019-11-12 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (process_immext): Remove SSE3, SVME, and
MWAITX special case logic.
(process_suffix): Replace immext field uses by instance ones.
* testsuite/gas/i386/arch-13.s,
testsuite/gas/i386/x86-64-arch-3.s: Add CLZERO with operand
cases.
* testsuite/gas/i386/svme.s: Add 16-bit operand cases.
* testsuite/gas/i386/x86-64-specific-reg.s: Drop FIXME comments.
* testsuite/gas/i386/arch-13.d,
testsuite/gas/i386/mwaitx-reg.l, testsuite/gas/i386/svme.d,
testsuite/gas/i386/x86-64-arch-3.d,
testsuite/gas/i386/x86-64-mwaitx-reg.l,
testsuite/gas/i386/x86-64-specific-reg.l: Adjust expectations.
x86: introduce operand type "instance" Special register "class" instances can't be combined with one another (neither in templates nor in register entries), and hence it is not a good use of resources (memory as well as execution time) to represent them as individual bits of a bit field. Furthermore the generalization becoming possible will allow improvements to the handling of insns accepting only individual registers as their operands.
2019-11-12 16:07:34 +08:00
2019-11-12 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (operand_type_set, operand_type_and,
operand_type_and_not, operand_type_or, operand_type_xor): Handle
"instance" field specially.
(operand_size_match, md_assemble, match_template, process_suffix,
check_byte_reg, check_long_reg, check_qword_reg, check_word_reg,
process_operands, build_modrm_byte): Use "instance" instead of
"acc" / "inoutportreg" / "shiftcount" fields.
(optimize_imm): Adjust comment.
Arm64: SVE2's smaxp/sminp require operands 1 and 3 to be the same register This is just like for their umaxp/uminp and fmaxp/fminp counterparts.
2019-11-11 20:28:35 +08:00
2019-11-11 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/aarch64/illegal-sve2.s: Add smaxp/sminp cases
with mismatched 1st and 3rd operands.
* testsuite/gas/aarch64/illegal-sve2.l: Adjust expectations.
i386: Only check suffix in instruction mnemonic We should check suffix in instruction mnemonic when matching instruction. In Intel syntax, normally we check for memory operand size. But the same mnemonic with 2 different encodings can have the same memory operand size and i.suffix is set to LONG_DOUBLE_MNEM_SUFFIX from memory operand size in Intel syntax to distinguish them. When there is no suffix in mnemonic, we check LONG_DOUBLE_MNEM_SUFFIX in i.suffix for mnemonic suffix. gas/ PR gas/25167 * config/tc-i386.c (match_template): Don't check instruction suffix set from operand. * testsuite/gas/i386/code16.d: New file. * testsuite/gas/i386/code16.s: Likewise. * testsuite/gas/i386/i386.exp: Run code16. * testsuite/gas/i386/x86-64-branch-4.l: Updated. opcodes/ PR gas/25167 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd. * i386-tbl.h: Regenerated.
2019-11-09 01:31:06 +08:00
2019-11-08 H.J. Lu <hongjiu.lu@intel.com>
PR gas/25167
* config/tc-i386.c (match_template): Don't check instruction
suffix set from operand.
* testsuite/gas/i386/code16.d: New file.
* testsuite/gas/i386/code16.s: Likewise.
* testsuite/gas/i386/i386.exp: Run code16.
x86: convert RegMask and RegBND from bitfield to enumerator This is to further shrink the operand type representation.
2019-11-08 16:06:24 +08:00
2019-11-08 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (optimize_encoding, build_modrm_byte,
check_VecOperations, parse_real_register): Use "class" instead
of "regmask" and "regbnd" fields.
x86: convert RegSIMD and RegMMX from bitfield to enumerator This is to further shrink the operand type representation.
2019-11-08 16:05:36 +08:00
2019-11-08 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (match_mem_size, operand_size_match,
operand_type_register_match, pi, check_VecOperands, match_template,
check_byte_reg, check_long_reg, check_qword_reg, process_operands,
build_modrm_byte, parse_real_register): Use "class" instead of
"regsimd" / "regmmx" fields.
x86: convert Control/Debug/Test from bitfield to enumerator This is to further shrink the operand type representation.
2019-11-08 16:04:53 +08:00
2019-11-08 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (pi, check_byte_reg, build_modrm_byte,
parse_real_register): Use "class" instead of "control"/"debug"/
"test" fields.
x86: convert SReg from bitfield to enumerator This is to further shrink the operand type representation.
2019-11-08 16:04:09 +08:00
2019-11-08 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (pi, check_byte_reg, process_operands,
build_modrm_byte, i386_att_operand, parse_real_register): Use
"class" instead of "sreg" field.
* config/tc-i386-intel.c (i386_intel_simplify_register,
i386_intel_operand): Likewise.
x86: introduce operand type "class" Many operand types, in particular the various kinds of registers, can't be combined with one another (neither in templates nor in register entries), and hence it is not a good use of resources (memory as well as execution time) to represent them as individual bits of a bit field.
2019-11-08 16:03:23 +08:00
2019-11-08 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (operand_type_set, operand_type_and,
operand_type_and_not, operand_type_or, operand_type_xor): Handle
"class" field specially.
(anyimm): New.
(operand_type_check, operand_size_match,
operand_type_register_match, pi, md_assemble, is_short_form,
process_suffix, check_byte_reg, check_long_reg, check_qword_reg,
check_word_reg, process_operands, build_modrm_byte): Use "class"
instead of "reg" field.
(optimize_imm): Likewise. Reduce redundancy. Adjust calculation
of "allowed".
[gas][aarch64] Add the v8.6 Data Gathering Hint mnemonic [10/X] Hi, This patch is part of a series that adds support for Armv8.6-A to binutils. In this last patch, the new Data Gathering Hint mnemonic is introduced. Committed on behalf of Mihail Ionescu. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * testsuite/gas/aarch64/dgh.s: New test. * testsuite/gas/aarch64/dgh.d: New test. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions. (aarch64_opcode_table): Add data gathering hint mnemonic. * opcodes/aarch64-dis-2.c: Account for new instruction. Is it ok for trunk? Regards, Mihail
2019-11-08 01:22:45 +08:00
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
* testsuite/gas/aarch64/dgh.s: New test.
* testsuite/gas/aarch64/dgh.d: New test.
[Patch][binutils][arm] Armv8.6-A Matrix Multiply extension [9/10] Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch introduces the Matrix Multiply (Int8, F32, F64) extensions to the arm backend. The following Matrix Multiply instructions are added: vummla, vsmmla, vusmmla, vusdot, vsudot[1]. [1]https://developer.arm.com/docs/ddi0597/latest/simd-and-floating-point-instructions-alphabetic-order Committed on behalf of Mihail Ionescu. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * config/tc-arm.c (arm_ext_i8mm): New feature set. (do_vusdot): New. (do_vsudot): New. (do_vsmmla): New. (do_vummla): New. (insns): Add vsmmla, vummla, vusmmla, vusdot, vsudot mnemonics. (armv86a_ext_table): Add i8mm extension. (arm_extensions): Move bf16 extension to context sensitive table. (armv82a_ext_table, armv84a_ext_table, armv85a_ext_table): Move bf16 extension to context sensitive table. (armv86a_ext_table): Add i8mm extension. * doc/c-arm.texi: Document i8mm extension. * testsuite/gas/arm/i8mm.s: New test. * testsuite/gas/arm/i8mm.d: New test. * testsuite/gas/arm/bfloat17-cmdline-bad-3.d: Update test. include/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * opcode/arm.h (ARM_EXT2_I8MM): New feature macro. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions. Regression tested on arm-none-eabi. Is this ok for trunk? Regards, Mihail
2019-11-08 01:20:08 +08:00
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
* config/tc-arm.c (arm_ext_i8mm): New feature set.
(do_vusdot): New.
(do_vsudot): New.
(do_vsmmla): New.
(do_vummla): New.
(insns): Add vsmmla, vummla, vusmmla, vusdot, vsudot mnemonics.
(armv86a_ext_table): Add i8mm extension.
(arm_extensions): Move bf16 extension to context sensitive table.
(armv82a_ext_table, armv84a_ext_table, armv85a_ext_table):
Move bf16 extension to context sensitive table.
(armv86a_ext_table): Add i8mm extension.
* doc/c-arm.texi: Document i8mm extension.
* testsuite/gas/arm/i8mm.s: New test.
* testsuite/gas/arm/i8mm.d: New test.
* testsuite/gas/arm/bfloat17-cmdline-bad-3.d: Update test.
[binutils][aarch64] Matrix Multiply extension enablement [8/X] Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch introduces the Matrix Multiply (Int8, F32, F64) extensions to the aarch64 backend. The following instructions are added: {s/u}mmla, usmmla, {us/su}dot, fmmla, ld1rob, ld1roh, d1row, ld1rod, uzip{1/2}, trn{1/2}. Committed on behalf of Mihail Ionescu. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * config/tc-aarch64.c: Add new arch fetures to suppport the mm extension. (parse_operands): Add new operand. * testsuite/gas/aarch64/i8mm.s: New test. * testsuite/gas/aarch64/i8mm.d: New test. * testsuite/gas/aarch64/f32mm.s: New test. * testsuite/gas/aarch64/f32mm.d: New test. * testsuite/gas/aarch64/f64mm.s: New test. * testsuite/gas/aarch64/f64mm.d: New test. * testsuite/gas/aarch64/sve-movprfx-mm.s: New test. * testsuite/gas/aarch64/sve-movprfx-mm.d: New test. include/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_I8MM): New. (AARCH64_FEATURE_F32MM): New. (AARCH64_FEATURE_F64MM): New. (AARCH64_OPND_SVE_ADDR_RI_S4x32): New. (enum aarch64_insn_class): Add new instruction class "aarch64_misc" for instructions that do not require special handling. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve, aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm, aarch64_feature_f64mm): New feature sets. (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN, F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply instructions. (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set macros. (QL_MMLA64, OP_SVE_SBB): New qualifiers. (OP_SVE_QQQ): New qualifier. (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC, F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support the movprfx constraint. (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32. (aarch64_opcode_table): Define new instructions smmla, ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod uzip{1/2}, trn{1/2}. * aarch64-opc.c (operand_general_constraint_met_p): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32. (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32. * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode): Account for new instructions. * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new S4x32 operand. * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand. Regression tested on arm-none-eabi. Is it ok for trunk? Regards, Mihail
2019-11-08 01:10:01 +08:00
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
* config/tc-aarch64.c: Add new arch fetures to suppport the mm extension.
(parse_operands): Add new operand.
* testsuite/gas/aarch64/i8mm.s: New test.
* testsuite/gas/aarch64/i8mm.d: New test.
* testsuite/gas/aarch64/f32mm.s: New test.
* testsuite/gas/aarch64/f32mm.d: New test.
* testsuite/gas/aarch64/f64mm.s: New test.
* testsuite/gas/aarch64/f64mm.d: New test.
* testsuite/gas/aarch64/sve-movprfx-mm.s: New test.
* testsuite/gas/aarch64/sve-movprfx-mm.d: New test.
[Patch][binutils][aarch64] .bfloat16 directive for AArch64 [7/10] Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch implements the '.bfloat' directive for the AArch64 backend. The syntax for the directive is: .bfloat16 <0-n numbers> e.g. .bfloat16 12.0 .bfloat16 0.123, 1.0, NaN, 5 This is implemented by utilizing the ieee_atof_detail function in order to encode the slightly different bfloat16 format. Added testcases to verify the correct encoding for various bfloat16 values (NaN, Infinity (+ & -), normals, subnormals etc...). Cross compiled and tested on aarch64-none-elf and aarch64-none-linux-gnu with no issues. Committed on behalf of Mihail Ionescu. gas/ChangeLog: 2019-10-29 Mihail Ionescu <mihail.ionescu@arm.com> 2019-10-29 Barnaby Wilks <barnaby.wilks@arm.com> * config/tc-aarch64.c (md_atof): Add encoding for the bfloat16 format. * testsuite/gas/aarch64/bfloat16-directive-le.d: New test. * testsuite/gas/aarch64/bfloat16-directive-be.d: New test. * testsuite/gas/aarch64/bfloat16-directive.s: New test. Is it ok for trunk? Regards, Mihail
2019-11-08 01:07:32 +08:00
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2019-11-07 Barnaby Wilks <barnaby.wilks@arm.com>
* config/tc-aarch64.c (md_atof): Add encoding for the bfloat16 format.
* testsuite/gas/aarch64/bfloat16-directive-le.d: New test.
* testsuite/gas/aarch64/bfloat16-directive-be.d: New test.
* testsuite/gas/aarch64/bfloat16-directive.s: New test.
[Patch][binutils][arm] .bfloat16 directive for Arm [6/X] Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch implements the '.bfloat16' directive for the Arm backend. The syntax for the directive is: .bfloat16 <0-n numbers> e.g. .bfloat16 12.0 .bfloat16 0.123, 1.0, NaN, 5 This is implemented by utilizing the ieee_atof_detail function (included in the previous patch) in order to encode the slightly different bfloat16 format. Added testcases to verify the correct encoding for various bfloat16 values (NaN, Infinity (+ & -), normals, subnormals etc...). Cross compiled and tested on arm-none-eabi and arm-none-linux-gnueabihf with no issues. Committed on behalf of Mihail Ionescu. gas/ChangeLog: 2019-10-21 Mihail Ionescu <mihail.ionescu@arm.com> 2019-10-21 Barnaby Wilks <barnaby.wilks@arm.com> * config/tc-arm.c (md_atof): Add encoding for bfloat16 * testsuite/gas/arm/bfloat16-directive-le.d: New test. * testsuite/gas/arm/bfloat16-directive-be.d: New test. * testsuite/gas/arm/bfloat16-directive.s: New test. Is it ok for trunk? Regards, Mihail
2019-11-08 01:03:54 +08:00
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2019-11-07 Barnaby Wilks <barnaby.wilks@arm.com>
* config/tc-arm.c (md_atof): Add encoding for bfloat16
* testsuite/gas/arm/bfloat16-directive-le.d: New test.
* testsuite/gas/arm/bfloat16-directive-be.d: New test.
* testsuite/gas/arm/bfloat16-directive.s: New test.
[Patch][binutils] Generic support for parsing numbers in bfloat16 format [5/X] Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions). This patch contains some general refactoring of the atof_ieee function, exposing a function that allows a higher level of control over the format of IEEE-like floating point numbers. This has been done in order to be able to add a directive for assembling floating point literals in the bfloat16 format in the following patches. Committed on behalf of Mihail Ionescu. Tested on arm-none-eabi, arm-none-linux-gnueabihf, aarch64-none-elf and aarch64-none-linux-gnuwith no issues. gas/ChangeLog: 2019-10-21 Mihail Ionescu <mihail.ionescu@arm.com> 2019-10-21 Barnaby Wilks <barnaby.wilks@arm.com> * as.h (atof_ieee_detail): Add prototype for atof_ieee_detail function. (atof_ieee): Move some code into the atof_ieee_detail function. (atof_ieee_detail): Add function that provides a higher level of control over generating IEEE-like numbers. Is it ok for trunk? Regards, Mihail
2019-11-08 01:01:04 +08:00
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2019-11-07 Barnaby Wilks <barnaby.wilks@arm.com>
* as.h (atof_ieee_detail): Add prototype for atof_ieee_detail function.
(atof_ieee): Move some code into the atof_ieee_detail function.
(atof_ieee_detail): Add function that provides a higher level of
control over generating IEEE-like numbers.
[binutils][arm] BFloat16 enablement [4/X] Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch introduces BFloat16 instructions to the arm backend. The following BFloat16 instructions are added: vdot, vfma{l/t}, vmmla, vfmal{t/b}, vcvt, vcvt{t/b}. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-arm.c (arm_archs): Add armv8.6-a option. (cpu_arch_ver): Add TAG_CPU_ARCH_V8 tag for Armv8.6-a. * doc/c-arm.texi (-march): New armv8.6-a arch. * config/tc-arm.c (arm_ext_bf16): New feature set. (enum neon_el_type): Add NT_bfloat value. (B_MNEM_vfmat, B_MNEM_vfmab): New bfloat16 encoder helpers. (BAD_BF16): New message. (parse_neon_type): Add bf16 type specifier. (enum neon_type_mask): Add N_BF16 type. (type_chk_of_el_type): Account for NT_bfloat. (el_type_of_type_chk): Account for N_BF16. (neon_three_args): Split out from neon_three_same. (neon_three_same): Part split out into neon_three_args. (CVT_FLAVOUR_VAR): Add bf16_f32 cvt flavour. (do_neon_cvt_1): Account for vcvt.bf16.f32. (do_bfloat_vmla): New. (do_mve_vfma): New function to deal with the mnemonic clash between the BF16 vfmat and the MVE vfma in a VPT block with a 't'rue condition. (do_neon_cvttb_1): Account for vcvt{t,b}.bf16.f32. (do_vdot): New (do_vmmla): New (insns): Add vdot and vmmla mnemonics. (arm_extensions): Add "bf16" extension. * doc/c-arm.texi: Document "bf16" extension. * testsuite/gas/arm/attr-march-armv8_6-a.d: New test. * testsuite/gas/arm/bfloat16-bad.d: New test. * testsuite/gas/arm/bfloat16-bad.l: New test. * testsuite/gas/arm/bfloat16-bad.s: New test. * testsuite/gas/arm/bfloat16-cmdline-bad-2.d: New test. * testsuite/gas/arm/bfloat16-cmdline-bad-3.d: New test. * testsuite/gas/arm/bfloat16-cmdline-bad.d: New test. * testsuite/gas/arm/bfloat16-neon.s: New test. * testsuite/gas/arm/bfloat16-non-neon.s: New test. * testsuite/gas/arm/bfloat16-thumb-bad.d: New test. * testsuite/gas/arm/bfloat16-thumb-bad.l: New test. * testsuite/gas/arm/bfloat16-thumb.d: New test. * testsuite/gas/arm/bfloat16-vfp.d: New test. * testsuite/gas/arm/bfloat16.d: New test. * testsuite/gas/arm/bfloat16.s: New test. include/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/arm.h (ARM_EXT2_V8_6A, ARM_AEXT2_V8_6A, ARM_ARCH_V8_6A): New. * opcode/arm.h (ARM_EXT2_BF16): New feature macro. (ARM_AEXT2_V8_6A): Include above macro in definition. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with Armv8.6-A. (coprocessor_opcodes): Add bfloat16 vcvt{t,b}. (neon_opcodes): Add bfloat SIMD instructions. (print_insn_coprocessor): Add new control character %b to print condition code without checking cp_num. (print_insn_neon): Account for BFloat16 instructions that have no special top-byte handling. Regression tested on arm-none-eabi. Is it ok for trunk? Regards, Mihail
2019-11-08 00:56:12 +08:00
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-arm.c (arm_archs): Add armv8.6-a option.
(cpu_arch_ver): Add TAG_CPU_ARCH_V8 tag for Armv8.6-a.
* doc/c-arm.texi (-march): New armv8.6-a arch.
* config/tc-arm.c (arm_ext_bf16): New feature set.
(enum neon_el_type): Add NT_bfloat value.
(B_MNEM_vfmat, B_MNEM_vfmab): New bfloat16 encoder
helpers.
(BAD_BF16): New message.
(parse_neon_type): Add bf16 type specifier.
(enum neon_type_mask): Add N_BF16 type.
(type_chk_of_el_type): Account for NT_bfloat.
(el_type_of_type_chk): Account for N_BF16.
(neon_three_args): Split out from neon_three_same.
(neon_three_same): Part split out into neon_three_args.
(CVT_FLAVOUR_VAR): Add bf16_f32 cvt flavour.
(do_neon_cvt_1): Account for vcvt.bf16.f32.
(do_bfloat_vmla): New.
(do_mve_vfma): New function to deal with the mnemonic clash between the BF16
vfmat and the MVE vfma in a VPT block with a 't'rue condition.
(do_neon_cvttb_1): Account for vcvt{t,b}.bf16.f32.
(do_vdot): New
(do_vmmla): New
(insns): Add vdot and vmmla mnemonics.
(arm_extensions): Add "bf16" extension.
* doc/c-arm.texi: Document "bf16" extension.
* testsuite/gas/arm/attr-march-armv8_6-a.d: New test.
* testsuite/gas/arm/bfloat16-bad.d: New test.
* testsuite/gas/arm/bfloat16-bad.l: New test.
* testsuite/gas/arm/bfloat16-bad.s: New test.
* testsuite/gas/arm/bfloat16-cmdline-bad-2.d: New test.
* testsuite/gas/arm/bfloat16-cmdline-bad-3.d: New test.
* testsuite/gas/arm/bfloat16-cmdline-bad.d: New test.
* testsuite/gas/arm/bfloat16-neon.s: New test.
* testsuite/gas/arm/bfloat16-non-neon.s: New test.
* testsuite/gas/arm/bfloat16-thumb-bad.d: New test.
* testsuite/gas/arm/bfloat16-thumb-bad.l: New test.
* testsuite/gas/arm/bfloat16-thumb.d: New test.
* testsuite/gas/arm/bfloat16-vfp.d: New test.
* testsuite/gas/arm/bfloat16.d: New test.
* testsuite/gas/arm/bfloat16.s: New test.
[binutils][aarch64] Bfloat16 enablement [2/X] Hi, This patch is part of a series that adds support for Armv8.6-A (Matrix Multiply and BFloat16 extensions) to binutils. This patch introduces the following BFloat16 instructions to the aarch64 backend: bfdot, bfmmla, bfcvt, bfcvtnt, bfmlal[t/b], bfcvtn2. Committed on behalf of Mihail Ionescu. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (vectype_to_qualifier): Special case the S_2H operand qualifier. * doc/c-aarch64.texi: Document bf16 and bf16mmla4 extensions. * testsuite/gas/aarch64/bfloat16.d: New test. * testsuite/gas/aarch64/bfloat16.s: New test. * testsuite/gas/aarch64/illegal-bfloat16.d: New test. * testsuite/gas/aarch64/illegal-bfloat16.l: New test. * testsuite/gas/aarch64/illegal-bfloat16.s: New test. * testsuite/gas/aarch64/sve-bfloat-movprfx.s: New test. * testsuite/gas/aarch64/sve-bfloat-movprfx.d: New test. include/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_BFLOAT16): New feature macros. (AARCH64_ARCH_V8_6): Include BFloat16 feature macros. (enum aarch64_opnd_qualifier): Introduce new operand qualifier AARCH64_OPND_QLF_S_2H. (enum aarch64_insn_class): Introduce new class "bfloat16". (BFLOAT16_SVE_INSNC): New feature set for bfloat16 instructions to support the movprfx constraint. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H in reglane special case. * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode): Account for new instructions. * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H in reglane special case. * aarch64-opc.c (struct operand_qualifier_data): Add data for new AARCH64_OPND_QLF_S_2H qualifier. * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2, QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers. (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve, aarch64_feature_bfloat16_bfmmla4): New feature sets. (BFLOAT_SVE, BFLOAT): New feature set macros. (BFLOAT_SVE_INSN, BFLOAT_BFMMLA4_INSN, BFLOAT_INSN): New macros to define BFloat16 instructions. (aarch64_opcode_table): Define new instructions bfdot, bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t] bfcvtn2, bfcvt. Regression tested on aarch64-elf. Is it ok for trunk? Regards, Mihail
2019-11-08 00:38:59 +08:00
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (vectype_to_qualifier): Special case the
S_2H operand qualifier.
* doc/c-aarch64.texi: Document bf16 extension.
* testsuite/gas/aarch64/bfloat16.d: New test.
* testsuite/gas/aarch64/bfloat16.s: New test.
* testsuite/gas/aarch64/illegal-bfloat16.d: New test.
* testsuite/gas/aarch64/illegal-bfloat16.l: New test.
* testsuite/gas/aarch64/illegal-bfloat16.s: New test.
* testsuite/gas/aarch64/sve-bfloat-movprfx.s: New test.
* testsuite/gas/aarch64/sve-bfloat-movprfx.d: New test.
[gas][aarch64] Armv8.6-a option [1/X] Hi, This patch is part of a series that adds support for Armv8.6-A to binutils. This first patch adds the Armv8.6-A flag to binutils. No instructions are behind it at the moment. Commited on behalf of Mihail Ionescu. gas/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (armv8.6-a): New arch. * doc/c-aarch64.texi (armv8.6-a): Document new arch. include/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_V8_6): New. (AARCH64_ARCH_V8_6): New. opcodes/ChangeLog: 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com> 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-tbl.h (ARMV8_6): New macro. Is it ok for trunk? Regards, Mihail
2019-11-08 00:18:51 +08:00
2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (armv8.6-a): New arch.
* doc/c-aarch64.texi (armv8.6-a): Document new arch.
x86: support further AMD Zen2 instructions Both RDPRU and MCOMMIT have been publicly documented meanwhile: https://www.amd.com/system/files/TechDocs/24594.pdf.
2019-11-07 16:29:14 +08:00
2019-11-07 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (cpu_arch): Add .rdpru and .mcommit entries.
* doc/c-i386.texi: Mention rdpru and mcommit.
* testsuite/gas/i386/arch-13.s,
testsuite/gas/i386/x86-64-arch-3.s: Add mcommit and rdpru cases.
* testsuite/gas/i386/arch-13.d,
testsuite/gas/i386/x86-64-arch-3.d: Extend -march=. Adjust
expectations.
* testsuite/gas/i386/arch-13-znver1.d: Extend -march=. Redirect
expectations to arch-13.d.
* testsuite/gas/i386/arch-13-znver2.d: Redirect expectations to
arch-13.d.
testsuite/gas/i386/x86-64-arch-3-znver1.d: Extend -march=.
x86: adjust register names printed for MONITOR/MWAIT As the comments (here: almost, in the opcode table: fully) correctly state - all register operands except MONITOR's address one are fixed at 32 bit size. Don't print 64-bit registers there. Also adjust x86-64-suffix.d's name such that it wouldn't be identical to x86-64-rep-suffix.d's, but instead resemble that of its sibling x86-64-suffix-intel.d.
2019-11-07 16:28:20 +08:00
2019-11-07 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/x86-64-arch-3.s: Add monitorx/mwaitx cases
with canonical operand sizes.
* testsuite/gas/i386/x86-64-sse3.s: Add monitor/mwait cases with
canonical operand sizes.
* testsuite/gas/i386/x86-64-arch-3-znver1.d,
testsuite/gas/i386/x86-64-arch-3-znver2.d: Redirect expectations
to x86-64-arch-3.d.
* testsuite/gas/i386/ilp32/x86-64-sse-noavx.d: Redirect
expectations to parent dir's x86-64-sse-noavx.d.
* testsuite/gas/i386/ilp32/x86-64-sse3.d: Redirect expectations
to to parent dir's x86-64-sse3.d.
* testsuite/gas/i386/x86-64-arch-3.d,
testsuite/gas/i386/x86-64-mwaitx-bdver4.d,
testsuite/gas/i386/x86-64-sse-noavx.d,
testsuite/gas/i386/x86-64-sse3.d,
testsuite/gas/i386/x86-64-suffix.d: Adjust expectations.
x86: re-arrange process_operands() Alter the sequence of conditions evaluated, without affecting the overall result. This is going to help subsequent changes (and as a nice side effect also slightly reduces overall indentation depth). While doing this take the liberty of simplifying the calculation of the operand index of the register operand in ShortForm handling.
2019-11-04 22:48:38 +08:00
2019-11-04 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (process_operands): Handle ShortForm insns
later, splitting out their segment register sub-form.
i386; Add .code16gcc fldenv tests * testsuite/gas/i386/general.s: Add .code16gcc fldenv tests. * testsuite/gas/i386/general.l: Updated.
2019-11-01 01:42:04 +08:00
2019-10-31 H.J. Lu <hongjiu.lu@intel.com>
* testsuite/gas/i386/general.s: Add .code16gcc fldenv tests.
* testsuite/gas/i386/general.l: Updated.
Add support for context sensitive '.arch_extension' to the ARM assembler. If the extension is not found in the context sensitive table, the legacy tables are still checked as a fallback. This is particularly useful for Armv8.1-M as it enables the use of '.arch_extension' with the 'mve' and 'mve.fp' extensions which are not part of the legacy table. * config/tc-arm.c (selected_ctx_ext_table) New static variable. (arm_parse_arch): Set context sensitive extension table based on the chosen base architecture. (s_arm_arch_extension): Change to lookup extensions in the new context sensitive tables. * gas/testsuite/gas/arm/mve-ext.s: New. * gas/testsuite/gas/arm/mve-ext.d: New. * gas/testsuite/gas/arm/mvefp-ext.s: New. * gas/testsuite/gas/arm/mvefp-ext.d: New.
2019-10-31 19:22:58 +08:00
2019-10-31 Mihail Ionescu <mihail.ionescu@arm.com>
* config/tc-arm.c (selected_ctx_ext_table) New static variable.
(arm_parse_arch): Set context sensitive extension table based on the
chosen base architecture.
(s_arm_arch_extension): Change to lookup extensions in the new context
sensitive tables.
* gas/testsuite/gas/arm/mve-ext.s: New.
* gas/testsuite/gas/arm/mve-ext.d: New.
* gas/testsuite/gas/arm/mvefp-ext.s: New.
* gas/testsuite/gas/arm/mvefp-ext.d: New.
Modify the ARNM assembler to accept the omission of the immediate argument for the writeback form of the LDRAA and LDRAB mnemonics This is a shorthand for the immediate argument being 0, as described here: https://developer.arm.com/docs/ddi0596/latest/base-instructions-alphabetic-order/ldraa-ldrab-load-register-with-pointer-authentication This is because the instructions still have a use with an immediate argument of 0, unlike loads without the PAC functionality. Currently, the mnemonics are LDRAA Xt, [Xn, #<simm10>]! LDRAB Xt, [Xn, #<simm10>]! After this patch they become LDRAA Xt, [Xn {, #<simm10>}]! LDRAB Xt, [Xn {, #<simm10>}]! gas * config/tc-aarch64.c (parse_address_main): Accept the omission of the immediate argument for ldraa and ldrab as a shorthand for the immediate being 0. * testsuite/gas/aarch64/ldraa-ldrab-no-offset.d: New test. * testsuite/gas/aarch64/ldraa-ldrab-no-offset.s: New test. * testsuite/gas/aarch64/illegal-ldraa.s: Modified to accept the writeback form with no offset. * testsuite/gas/aarch64/illegal-ldraa.s: Removed missing offset error. opcodes * aarch64-opc.c (print_immediate_offset_address): Don't print the immediate for the writeback form of ldraa/ldrab if it is 0. * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10. * aarch64-opc-2.c: Regenerated.
2019-10-30 21:23:35 +08:00
2019-10-30 Delia Burduv <Delia.Burduv@arm.com>
* config/tc-aarch64.c (parse_address_main): Accept the omission of
the immediate argument for ldraa and ldrab as a shorthand for the
immediate being 0.
* testsuite/gas/aarch64/ldraa-ldrab-no-offset.d: New test.
* testsuite/gas/aarch64/ldraa-ldrab-no-offset.s: New test.
* testsuite/gas/aarch64/illegal-ldraa.s: Modified to accept the
writeback form with no offset.
* testsuite/gas/aarch64/illegal-ldraa.s: Removed missing offset
error.
x86: add tests to cover defaulting of operand sizes for ambiguous insns Prior to changing the logic in the assembler install tests to make sure the present defaulting of operand sizes won't get broken. There are a few anomalies pointed out by this: - arithmetic insns (add, sub, etc) allow defaulting when their immediate fits in (signed) 8 bits, but they fail to assemble with larger values, - mov, other than arithmetic insns, doesn't allow any defaulting, - movsx/movzx default to byte sources (in AT&T mode), and their special casing needs to be adjusted first - bt and friends allow defaulting, while shl and friends don't, - ambiguous AVX and AVX512 insns don't allow defaulting. This should ultimately all become consistent (perhaps with the exception some of the SIMD insns); respective tests will be added to the test cases here as the issues get addressed.
2019-10-30 16:09:13 +08:00
2019-10-30 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/noreg16.d, testsuite/gas/i386/noreg16.s,
testsuite/gas/i386/noreg32.d, testsuite/gas/i386/noreg32.s,
testsuite/gas/i386/noreg64.d, testsuite/gas/i386/noreg64.s: New.
* testsuite/gas/i386/i386.exp: Run new tests.
x86: drop stray W The flag is used to indicate opcodes which can be switched between byte and word/dword/qword forms (in a "canonical" way). Obviously it's quite odd then to see it on insns not allowing for byte operands in the first place. As a result the opcode bytes need to be adjusted accordingly, which includes comparisons done in optimize_encoding(). To make re-introduction of such issues less likely have i386-gen diagnose it (in a generally non-fatal way for now).
2019-10-30 16:05:46 +08:00
2019-10-30 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (optimize_encoding): Adjust opcodes compared
against. Adjust replacement opcode and clear .w.
Re: Optimise away eh_frame advance_loc 0 If we happen to get the fixed and variable parts of the advance_loc in different frags, bad things happen when subtracting one from a fr_fix of zero. PR 25125 * dw2gencfi.c (output_cfi_insn): Don't allow DW_CFA_advance_loc4 to be placed in a different frag to the rs_cfa.
2019-10-29 09:05:05 +08:00
2019-10-29 Alan Modra <amodra@gmail.com>
PR 25125
* dw2gencfi.c (output_cfi_insn): Don't allow DW_CFA_advance_loc4
to be placed in a different frag to the rs_cfa.
Add some missing casts to suppress implicit cast warnings PR gas/25121 * config/tc-hppa.c (tc_gen_reloc): Cast some enums to int. (md_assemble): Likewise.
2019-10-27 04:48:59 +08:00
2019-10-26 John David Anglin <danglin@gcc.gnu.org>
PR gas/25121
* config/tc-hppa.c (tc_gen_reloc): Cast some enums to int.
(md_assemble): Likewise.
Optimise away eh_frame advance_loc 0 These can be generated when multiple cfi directives are emitted for an instruction and the insn frag is closed off between directives, as happens when listings are enabled. No doubt the advance_loc of zero could be avoided by backtracking over frags in dw2gencfi.c before calling cfi_add_advance_loc, but that seems like more work than cleaning up afterwards as this patch does. Noticed when looking at the testcase in PR25125. PR 25125 * dw2gencfi.c (output_cfi_insn): Don't output DW_CFA_advance_loc+0. * ehopt.c (eh_frame_estimate_size_before_relax): Return -1 for an advance_loc of zero. (eh_frame_relax_frag): Translate fr_subtype of 7 to size -1. (eh_frame_convert_frag): Handle fr_subtype of 7. Abort on unexpected fr_subtype.
2019-10-26 16:08:26 +08:00
2019-10-26 Alan Modra <amodra@gmail.com>
PR 25125
* dw2gencfi.c (output_cfi_insn): Don't output DW_CFA_advance_loc+0.
* ehopt.c (eh_frame_estimate_size_before_relax): Return -1 for
an advance_loc of zero.
(eh_frame_relax_frag): Translate fr_subtype of 7 to size -1.
(eh_frame_convert_frag): Handle fr_subtype of 7. Abort on
unexpected fr_subtype.
PR25125, relaxation chooses wrong branch size The patch I made for PR12049 didn't test for a "negative" branch properly. "if (target < address)" ought to have been "if (target < address + fragP->fr_fix)". Rather than making that change, this patch adds fragP->fr_fix into address earlier. The patch also avoids running into a bad interaction with the m68k md_prepare_relax_scan by returning zero growth immediately, since the adjusted target expression would result in a zero "aim". PR gas/25125 PR gas/12049 * write.c (relax_frag): Correct calculation of delta for positive branches where "stretch" would make the branch negative. Return zero immediately in that case. Correct TC_PCREL_ADJUST comment.
2019-10-25 17:16:24 +08:00
2019-10-25 Alan Modra <amodra@gmail.com>
PR gas/25125
PR gas/12049
* write.c (relax_frag): Correct calculation of delta for
positive branches where "stretch" would make the branch
negative. Return zero immediately in that case. Correct
TC_PCREL_ADJUST comment.
qsort: tc-xtensa.c tidy Not much to see here, just reduce the number of calls to S_GET_VALUE and symbol_symbolS in the comparison functions. * config/tc-xtensa.c (xg_order_trampoline_chain_entry): Don't call S_GET_VALUE multiple times for a symbol. Rearrange code so it is obvious what is the primary sort key. (xg_order_trampoline_chain): Similarly.
2019-10-15 20:34:14 +08:00
2019-10-16 Alan Modra <amodra@gmail.com>
* config/tc-xtensa.c (xg_order_trampoline_chain_entry): Don't
call S_GET_VALUE multiple times for a symbol. Rearrange code
so it is obvious what is the primary sort key.
(xg_order_trampoline_chain): Similarly.
remove more xmalloc in bfd Also fixes m68hc1x printf arguments which would have bombed when compiling on a 32-bit host with --enable-64-bit-bfd. bfd/ PR 24955 * elf32-arm.c (set_cmse_veneer_addr_from_implib): Use bfd_malloc rather than xmalloc. * elf32-m68hc1x.c (reloc_warning): New function. (elf32_m68hc11_relocate_section): Use it here. Cast bfd_vma values corresponding to %lx in format strings. * elf32-nds32.c (nds32_insertion_sort): Use a stack temporary. gas/ * config/tc-nds32.c (nds32_set_section_relocs): Use relocs and n parameters rather than equivalent sec->orelocation and sec->reloc_count. Don't sort for n <= 1. Tidy.
2019-10-15 13:27:35 +08:00
2019-10-15 Alan Modra <amodra@gmail.com>
* config/tc-nds32.c (nds32_set_section_relocs): Use relocs and n
parameters rather than equivalent sec->orelocation and
sec->reloc_count. Don't sort for n <= 1. Tidy.
Fix the disassembly of the LDS and STS instructions of the AVR architecture. PR 25041 opcodes * avr-dis.c (avr_operand): Fix construction of address for lds/sts instructions. gas * testsuite/gas/avr/pr25041.s: New test. * testsuite/gas/avr/pr25041.d: New test driver.
2019-10-09 20:48:06 +08:00
2019-10-09 Nick Clifton <nickc@redhat.com>
PR 25041
* testsuite/gas/avr/pr25041.s: New test.
* testsuite/gas/avr/pr25041.d: New test driver.
Add support for new functionality in the msp430 backend of GCC. This functionality will generate a new GNU object attribute for the "data region" has been added. This object attribute is used mark whether the compiler has generated code assuming that data could be in the upper or lower memory regions. Code which assumes data is always in the lower memory region is incompatible with code which uses the full memory range for data. The patch also adds a new assembler directive ".mspabi_attribute" to handle the existing MSPABI object attributes. GCC will now emit both .gnu_attribute and .mspabi_attribute directives to indicate what options the source file was compiled with. The assembler will now check the values set in these directives against the options that the it has been invoked with. If there is a discrepancy, the assembler will exit with an error. bfd * elf32-msp430.c (elf32_msp430_merge_mspabi_attributes): Rename to.. (elf32_msp430_merge_msp430_attributes): Add support for merging the GNU object attribute for data region. binutils* readelf.c (display_msp430_gnu_attribute): New. (process_arch_specific): Use msp430 specific handler for GNU attributes. gas * config/tc-msp430.c (md_parse_option): Set lower_data_region_only to FALSE if the data region is set to "upper", "either" or "none". (msp430_object_attribute): New. (md_pseudo_table): Handle .mspabi_attribute and .gnu_attribute. (msp430_md_end): Replace hard-coded attribute values with enums. Handle data region object attribute. * doc/as.texi: Document MSP430 Data Region object attribute. * doc/c-msp430.texi: Document the .mspabi_attribute directive. * testsuite/gas/msp430/attr-430-small-bad.d: New test. * testsuite/gas/msp430/attr-430-small-bad.l: New test. * testsuite/gas/msp430/attr-430-small-good.d: New test. * testsuite/gas/msp430/attr-430-small.s: New test. * testsuite/gas/msp430/attr-430x-large-any-bad.d: New test. * testsuite/gas/msp430/attr-430x-large-any-bad.l: New test. * testsuite/gas/msp430/attr-430x-large-any-good.d: New test. * testsuite/gas/msp430/attr-430x-large-any.s: New test. * testsuite/gas/msp430/attr-430x-large-lower-bad.d: New test. * testsuite/gas/msp430/attr-430x-large-lower-bad.l: New test. * testsuite/gas/msp430/attr-430x-large-lower-good.d: New test. * testsuite/gas/msp430/attr-430x-large-lower.s: New test. * testsuite/gas/msp430/msp430.exp: Run new tests. include * elf/msp430.h: Add enums for MSPABI and GNU object attribute tag names and values. ld * testsuite/ld-msp430-elf/attr-gnu-main.s: New test. * testsuite/ld-msp430-elf/attr-gnu-obj.s: New test. * testsuite/ld-msp430-elf/attr-gnu-region-lower-upper.d: New test. * testsuite/ld-msp430-elf/attr-gnu-region-lower.d: New test. * testsuite/ld-msp430-elf/attr-gnu-region-upper.d: New test. * testsuite/ld-msp430-elf/msp430-elf.exp: Run new tests.
2019-10-07 23:34:31 +08:00
2019-10-07 Jozef Lawrynowicz <jozef.l@mittosystems.com>
* config/tc-msp430.c (md_parse_option): Set lower_data_region_only
to FALSE if the data region is set to "upper", "either" or "none".
(msp430_object_attribute): New.
(md_pseudo_table): Handle .mspabi_attribute and .gnu_attribute.
(msp430_md_end): Replace hard-coded attribute values with enums.
Handle data region object attribute.
* doc/as.texi: Document MSP430 Data Region object attribute.
* doc/c-msp430.texi: Document the .mspabi_attribute directive.
* testsuite/gas/msp430/attr-430-small-bad.d: New test.
* testsuite/gas/msp430/attr-430-small-bad.l: New test.
* testsuite/gas/msp430/attr-430-small-good.d: New test.
* testsuite/gas/msp430/attr-430-small.s: New test.
* testsuite/gas/msp430/attr-430x-large-any-bad.d: New test.
* testsuite/gas/msp430/attr-430x-large-any-bad.l: New test.
* testsuite/gas/msp430/attr-430x-large-any-good.d: New test.
* testsuite/gas/msp430/attr-430x-large-any.s: New test.
* testsuite/gas/msp430/attr-430x-large-lower-bad.d: New test.
* testsuite/gas/msp430/attr-430x-large-lower-bad.l: New test.
* testsuite/gas/msp430/attr-430x-large-lower-good.d: New test.
* testsuite/gas/msp430/attr-430x-large-lower.s: New test.
* testsuite/gas/msp430/msp430.exp: Run new tests.
add missing ChangeLog entry for d241b91073
2019-10-07 14:40:03 +08:00
2019-10-07 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (check_string): Make reported operand number
depend on Intel syntax.
* testsuite/gas/i386/intel-cmps.s,
testsuite/gas/i386/intel-cmps32.d,
testsuite/gas/i386/intel-cmps64.d: New.
* testsuite/gas/i386/i386.exp: Run new tests.
* testsuite/gas/i386/intel-movs.s: Extend.
* testsuite/gas/i386/intel-movs32.d,
testsuite/gas/i386/intel-movs64.d: Adjust expectations.
* testsuite/gas/i386/string-bad.l: Tighten expectations.
Arm: Fix out of range conditional branch (PR/24991) The fix for PR12848 introduced an off by one error in the mask, this corrected the negative overflows but not the positive overflows. As a result the conditional branch instructions accepted a too wide positive immediate which resulted in it corrupting the instruction during encoding. The relocation I believe has been incorrectly named, to be consistent with the other relocations it should have been named BRANCH21 which is why the masks for it are confusing. I've replaced the masks with a function out_of_range_p which should make it harder to make such mistakes. The mask for BL/BLX on Armv6t+ is also wrong, the extended range is 25-bits and so the mask should be checking for 24-bits for positive overflow. gas/ChangeLog: PR gas/24991 * config/tc-arm.c (out_of_range_p): New. (md_apply_fix): Use it in BFD_RELOC_THUMB_PCREL_BRANCH9, BFD_RELOC_THUMB_PCREL_BRANCH12, BFD_RELOC_THUMB_PCREL_BRANCH20, BFD_RELOC_THUMB_PCREL_BRANCH23, BFD_RELOC_THUMB_PCREL_BRANCH25 * testsuite/gas/arm/pr24991.d: New test. * testsuite/gas/arm/pr24991.l: New test. * testsuite/gas/arm/pr24991.s: New test.
2019-09-24 21:46:17 +08:00
2019-09-24 Tamar Christina <tamar.christina@arm.com>
PR gas/24991
* config/tc-arm.c (out_of_range_p): New.
(md_apply_fix): Use it in BFD_RELOC_THUMB_PCREL_BRANCH9,
BFD_RELOC_THUMB_PCREL_BRANCH12, BFD_RELOC_THUMB_PCREL_BRANCH20,
BFD_RELOC_THUMB_PCREL_BRANCH23, BFD_RELOC_THUMB_PCREL_BRANCH25
* testsuite/gas/arm/pr24991.d: New test.
* testsuite/gas/arm/pr24991.l: New test.
* testsuite/gas/arm/pr24991.s: New test.
ecoff bfd.h tidy bfd/ * bfd-in.h: Move ecoff function declarations.. * ecoff-bfd.h: ..to here, new file. * ecoff.c: Include ecoff-bfd.h. * ecofflink.c: Likewise. * elf64-alpha.c: Likewise. * elfxx-mips.c: Likewise. * bfd-in2.h: Regenerate. gas/ * config/obj-ecoff.c: Include ecoff-bfd.h. * config/obj-elf.c: Likewise.
2019-09-23 08:43:26 +08:00
2019-09-23 Alan Modra <amodra@gmail.com>
* config/obj-ecoff.c: Include ecoff-bfd.h.
* config/obj-elf.c: Likewise.
arm bfd.h tidy bfd/ * bfd-in.h: Move arm declaraions.. * cpu-arm.h: ..to here, new file.. * coff-arm.h: ..and here, new file.. * elf32-arm.h: ..and here, new file. * cpu-arm.c: Include cpu-arm.h. * coff-arm.c: Include cpu-arm.h and coff-arm.h. * elf32-arm.c: Include cpu-arm.h and elf32-arm.h. * pe-arm.c: Move function rename defines later. * pe-arm-wince.c: Likewise and include sysdep.h and bfd.h early. * bfd-in2.h: Regenerate. gas/ * config/tc-arm.c: Include cpu-arm.h. ld/ * emultempl/armelf.em: Include elf32-arm.h. * emultempl/pe.em: Move func defines later and include coff-arm.h.
2019-09-23 08:36:45 +08:00
2019-09-23 Alan Modra <amodra@gmail.com>
* config/tc-arm.c: Include cpu-arm.h.
tc-i386.c gcc10 warning fix .../gas/config/tc-i386.c: In function ‘md_parse_option’: .../gas/config/tc-i386.c:11441:9: error: implicit conversion from ‘enum <anonymous>’ to ‘enum <anonymous>’ [-Werror=enum-conversion] 11441 | vexwig = evexw0; | ^ .../gas/config/tc-i386.c:11443:9: error: implicit conversion from ‘enum <anonymous>’ to ‘enum <anonymous>’ [-Werror=enum-conversion] 11443 | vexwig = evexw1; | ^ * config/tc-i386.c (md_parse_option): Fix warning on vexwig assignment.
2019-09-21 09:29:50 +08:00
2019-09-21 Alan Modra <amodra@gmail.com>
* config/tc-i386.c (md_parse_option): Fix warning on vexwig assignment.
bfd macro conversion to inline functions, section This one exposed a bug in tic6x gas, found with inline function parameter type checking. struct bfd_section and struct bfd_symbol both have a flags field, so bfd_is_com_section (symbol) compiled OK when bfd_is_com_section was a macro but didn't special case common symbols. bfd/ * bfd-in.h (bfd_section_name, bfd_section_size, bfd_section_vma), (bfd_section_lma, bfd_section_alignment, bfd_section_flags), (bfd_section_userdata, bfd_is_com_section, discarded_section), (bfd_get_section_limit_octets, bfd_get_section_limit): Delete macros. * bfd.c (bfd_get_section_limit_octets, bfd_get_section_limit), (bfd_section_list_remove, bfd_section_list_append), (bfd_section_list_prepend, bfd_section_list_insert_after), (bfd_section_list_insert_before, bfd_section_removed_from_list): New inline functions. * section.c (bfd_is_und_section, bfd_is_abs_section), (bfd_is_ind_section, bfd_is_const_section, bfd_section_list_remove), (bfd_section_list_append, bfd_section_list_prepend), (bfd_section_list_insert_after, bfd_section_list_insert_before), (bfd_section_removed_from_list): Delete macros. (bfd_section_name, bfd_section_size, bfd_section_vma), (bfd_section_lma, bfd_section_alignment, bfd_section_flags), (bfd_section_userdata, bfd_is_com_section, bfd_is_und_section), (bfd_is_abs_section, bfd_is_ind_section, bfd_is_const_section), (discarded_section): New inline functions. * bfd-in2.h: Regenerate. gas/ * config/tc-tic6x.c (tc_gen_reloc): Correct common symbol check. ld/ * emultempl/xtensaelf.em (xtensa_get_section_deps): Comment. Use bfd_section_userdata. (xtensa_set_section_deps): Use bfd_set_section_userdata. * ldlang.c (lang_output_section_get): Use bfd_section_userdata. (sort_def_symbol): Likewise, and bfd_set_section_userdata. (init_os): Use bfd_set_section_userdata. (print_all_symbols): Use bfd_section_userdata. * ldlang.h (get_userdata): Delete.
2019-09-17 07:29:25 +08:00
2019-09-20 Alan Modra <amodra@gmail.com>
* config/tc-tic6x.c (tc_gen_reloc): Correct common symbol check.
x86-64: fix handling of PUSH/POP of segment register Commit 21df382b91 ("x86: fold SReg{2,3}") went too far: Folding 64-bit PUSH/POP templates into non-64-bit ones isn't correct, due to the different operand widths, and hence suffixes permitted. Restore the separate templates. Add tests of PUSH/POP with q suffix and %fs/%gs operands to the testsuite. While doing so also add PUSHF/POPF ones _without_ suffix.
2019-09-20 16:18:15 +08:00
2018-09-20 Jan Beulich <jbeulich@suse.com>
PR gas/25012
* config/tc-i386.c (process_operands): Adjust handling of
PUSH/POP of segment registers.
* testsuite/gas/i386/x86-64-opcode.s: Add PUSHq/POPq case with
%fs/%gs operands. Add PUSHF/POPF case without suffix.
* testsuite/gas/i386/x86-64-opcode.d: Adjust expectations.
[gas][news] NEWS (2.33) note new SVE2 and TME instructions for AArch64 These NEWS entries had been missed when the instructions were added. gas/ChangeLog: 2019-09-19 Matthew Malcomson <matthew.malcomson@arm.com> * NEWS: Add SVE2 and TME entries.
2019-09-19 21:34:14 +08:00
2019-09-19 Matthew Malcomson <matthew.malcomson@arm.com>
* NEWS: Add SVE2 and TME entries.
bfd_section_* macros This large patch removes the unnecessary bfd parameter from various bfd section macros and functions. The bfd is hardly ever used and if needed for the bfd_set_section_* or bfd_rename_section functions can be found via section->owner except for the com, und, abs, and ind std_section special sections. Those sections shouldn't be modified anyway. The patch also removes various bfd_get_section_<field> macros, replacing their use with bfd_section_<field>, and adds bfd_set_section_lma. I've also fixed a minor bug in gas where compressed section renaming was done directly rather than calling bfd_rename_section. This would have broken bfd_get_section_by_name and similar functions, but that hardly mattered at such a late stage in gas processing. bfd/ * bfd-in.h (bfd_get_section_name, bfd_get_section_vma), (bfd_get_section_lma, bfd_get_section_alignment), (bfd_get_section_size, bfd_get_section_flags), (bfd_get_section_userdata): Delete. (bfd_section_name, bfd_section_size, bfd_section_vma), (bfd_section_lma, bfd_section_alignment): Lose bfd parameter. (bfd_section_flags, bfd_section_userdata): New. (bfd_is_com_section): Rename parameter. * section.c (bfd_set_section_userdata, bfd_set_section_vma), (bfd_set_section_alignment, bfd_set_section_flags, bfd_rename_section), (bfd_set_section_size): Delete bfd parameter, rename section parameter. (bfd_set_section_lma): New. * bfd-in2.h: Regenerate. * mach-o.c (bfd_mach_o_init_section_from_mach_o): Delete bfd param, update callers. * aoutx.h, * bfd.c, * coff-alpha.c, * coff-arm.c, * coff-mips.c, * coff64-rs6000.c, * coffcode.h, * coffgen.c, * cofflink.c, * compress.c, * ecoff.c, * elf-eh-frame.c, * elf-hppa.h, * elf-ifunc.c, * elf-m10200.c, * elf-m10300.c, * elf-properties.c, * elf-s390-common.c, * elf-vxworks.c, * elf.c, * elf32-arc.c, * elf32-arm.c, * elf32-avr.c, * elf32-bfin.c, * elf32-cr16.c, * elf32-cr16c.c, * elf32-cris.c, * elf32-crx.c, * elf32-csky.c, * elf32-d10v.c, * elf32-epiphany.c, * elf32-fr30.c, * elf32-frv.c, * elf32-ft32.c, * elf32-h8300.c, * elf32-hppa.c, * elf32-i386.c, * elf32-ip2k.c, * elf32-iq2000.c, * elf32-lm32.c, * elf32-m32c.c, * elf32-m32r.c, * elf32-m68hc1x.c, * elf32-m68k.c, * elf32-mcore.c, * elf32-mep.c, * elf32-metag.c, * elf32-microblaze.c, * elf32-moxie.c, * elf32-msp430.c, * elf32-mt.c, * elf32-nds32.c, * elf32-nios2.c, * elf32-or1k.c, * elf32-ppc.c, * elf32-pru.c, * elf32-rl78.c, * elf32-rx.c, * elf32-s390.c, * elf32-score.c, * elf32-score7.c, * elf32-sh.c, * elf32-spu.c, * elf32-tic6x.c, * elf32-tilepro.c, * elf32-v850.c, * elf32-vax.c, * elf32-visium.c, * elf32-xstormy16.c, * elf32-xtensa.c, * elf64-alpha.c, * elf64-bpf.c, * elf64-hppa.c, * elf64-ia64-vms.c, * elf64-mmix.c, * elf64-ppc.c, * elf64-s390.c, * elf64-sparc.c, * elf64-x86-64.c, * elflink.c, * elfnn-aarch64.c, * elfnn-ia64.c, * elfnn-riscv.c, * elfxx-aarch64.c, * elfxx-mips.c, * elfxx-sparc.c, * elfxx-tilegx.c, * elfxx-x86.c, * i386msdos.c, * linker.c, * mach-o.c, * mmo.c, * opncls.c, * pdp11.c, * pei-x86_64.c, * peicode.h, * reloc.c, * section.c, * syms.c, * vms-alpha.c, * xcofflink.c: Update throughout for bfd section macro and function changes. binutils/ * addr2line.c, * bucomm.c, * coffgrok.c, * dlltool.c, * nm.c, * objcopy.c, * objdump.c, * od-elf32_avr.c, * od-macho.c, * od-xcoff.c, * prdbg.c, * rdcoff.c, * rddbg.c, * rescoff.c, * resres.c, * size.c, * srconv.c, * strings.c, * windmc.c: Update throughout for bfd section macro and function changes. gas/ * as.c, * as.h, * dw2gencfi.c, * dwarf2dbg.c, * ecoff.c, * read.c, * stabs.c, * subsegs.c, * subsegs.h, * write.c, * config/obj-coff-seh.c, * config/obj-coff.c, * config/obj-ecoff.c, * config/obj-elf.c, * config/obj-macho.c, * config/obj-som.c, * config/tc-aarch64.c, * config/tc-alpha.c, * config/tc-arc.c, * config/tc-arm.c, * config/tc-avr.c, * config/tc-bfin.c, * config/tc-bpf.c, * config/tc-d10v.c, * config/tc-d30v.c, * config/tc-epiphany.c, * config/tc-fr30.c, * config/tc-frv.c, * config/tc-h8300.c, * config/tc-hppa.c, * config/tc-i386.c, * config/tc-ia64.c, * config/tc-ip2k.c, * config/tc-iq2000.c, * config/tc-lm32.c, * config/tc-m32c.c, * config/tc-m32r.c, * config/tc-m68hc11.c, * config/tc-mep.c, * config/tc-microblaze.c, * config/tc-mips.c, * config/tc-mmix.c, * config/tc-mn10200.c, * config/tc-mn10300.c, * config/tc-msp430.c, * config/tc-mt.c, * config/tc-nds32.c, * config/tc-or1k.c, * config/tc-ppc.c, * config/tc-pru.c, * config/tc-rl78.c, * config/tc-rx.c, * config/tc-s12z.c, * config/tc-s390.c, * config/tc-score.c, * config/tc-score7.c, * config/tc-sh.c, * config/tc-sparc.c, * config/tc-spu.c, * config/tc-tic4x.c, * config/tc-tic54x.c, * config/tc-tic6x.c, * config/tc-tilegx.c, * config/tc-tilepro.c, * config/tc-v850.c, * config/tc-visium.c, * config/tc-wasm32.c, * config/tc-xc16x.c, * config/tc-xgate.c, * config/tc-xstormy16.c, * config/tc-xtensa.c, * config/tc-z8k.c: Update throughout for bfd section macro and function changes. * write.c (compress_debug): Use bfd_rename_section. gdb/ * aarch64-linux-tdep.c, * arm-tdep.c, * auto-load.c, * coff-pe-read.c, * coffread.c, * corelow.c, * dbxread.c, * dicos-tdep.c, * dwarf2-frame.c, * dwarf2read.c, * elfread.c, * exec.c, * fbsd-tdep.c, * gcore.c, * gdb_bfd.c, * gdb_bfd.h, * hppa-tdep.c, * i386-cygwin-tdep.c, * i386-fbsd-tdep.c, * i386-linux-tdep.c, * jit.c, * linux-tdep.c, * machoread.c, * maint.c, * mdebugread.c, * minidebug.c, * mips-linux-tdep.c, * mips-sde-tdep.c, * mips-tdep.c, * mipsread.c, * nto-tdep.c, * objfiles.c, * objfiles.h, * osabi.c, * ppc-linux-tdep.c, * ppc64-tdep.c, * record-btrace.c, * record-full.c, * remote.c, * rs6000-aix-tdep.c, * rs6000-tdep.c, * s390-linux-tdep.c, * s390-tdep.c, * solib-aix.c, * solib-dsbt.c, * solib-frv.c, * solib-spu.c, * solib-svr4.c, * solib-target.c, * spu-linux-nat.c, * spu-tdep.c, * symfile-mem.c, * symfile.c, * symmisc.c, * symtab.c, * target.c, * windows-nat.c, * xcoffread.c, * cli/cli-dump.c, * compile/compile-object-load.c, * mi/mi-interp.c: Update throughout for bfd section macro and function changes. * gcore (gcore_create_callback): Use bfd_set_section_lma. * spu-tdep.c (spu_overlay_new_objfile): Likewise. gprof/ * corefile.c, * symtab.c: Update throughout for bfd section macro and function changes. ld/ * ldcref.c, * ldctor.c, * ldelf.c, * ldlang.c, * pe-dll.c, * emultempl/aarch64elf.em, * emultempl/aix.em, * emultempl/armcoff.em, * emultempl/armelf.em, * emultempl/cr16elf.em, * emultempl/cskyelf.em, * emultempl/m68hc1xelf.em, * emultempl/m68kelf.em, * emultempl/mipself.em, * emultempl/mmix-elfnmmo.em, * emultempl/mmo.em, * emultempl/msp430.em, * emultempl/nios2elf.em, * emultempl/pe.em, * emultempl/pep.em, * emultempl/ppc64elf.em, * emultempl/xtensaelf.em: Update throughout for bfd section macro and function changes. libctf/ * ctf-open-bfd.c: Update throughout for bfd section macro changes. opcodes/ * arc-ext.c: Update throughout for bfd section macro changes. sim/ * common/sim-load.c, * common/sim-utils.c, * cris/sim-if.c, * erc32/func.c, * lm32/sim-if.c, * m32c/load.c, * m32c/trace.c, * m68hc11/interp.c, * ppc/hw_htab.c, * ppc/hw_init.c, * rl78/load.c, * rl78/trace.c, * rx/gdb-if.c, * rx/load.c, * rx/trace.c: Update throughout for bfd section macro changes.
2019-09-16 18:55:17 +08:00
2019-09-18 Alan Modra <amodra@gmail.com>
* as.c, * as.h, * dw2gencfi.c, * dwarf2dbg.c, * ecoff.c,
* read.c, * stabs.c, * subsegs.c, * subsegs.h, * write.c,
* config/obj-coff-seh.c, * config/obj-coff.c, * config/obj-ecoff.c,
* config/obj-elf.c, * config/obj-macho.c, * config/obj-som.c,
* config/tc-aarch64.c, * config/tc-alpha.c, * config/tc-arc.c,
* config/tc-arm.c, * config/tc-avr.c, * config/tc-bfin.c,
* config/tc-bpf.c, * config/tc-d10v.c, * config/tc-d30v.c,
* config/tc-epiphany.c, * config/tc-fr30.c, * config/tc-frv.c,
* config/tc-h8300.c, * config/tc-hppa.c, * config/tc-i386.c,
* config/tc-ia64.c, * config/tc-ip2k.c, * config/tc-iq2000.c,
* config/tc-lm32.c, * config/tc-m32c.c, * config/tc-m32r.c,
* config/tc-m68hc11.c, * config/tc-mep.c, * config/tc-microblaze.c,
* config/tc-mips.c, * config/tc-mmix.c, * config/tc-mn10200.c,
* config/tc-mn10300.c, * config/tc-msp430.c, * config/tc-mt.c,
* config/tc-nds32.c, * config/tc-or1k.c, * config/tc-ppc.c,
* config/tc-pru.c, * config/tc-rl78.c, * config/tc-rx.c,
* config/tc-s12z.c, * config/tc-s390.c, * config/tc-score.c,
* config/tc-score7.c, * config/tc-sh.c, * config/tc-sparc.c,
* config/tc-spu.c, * config/tc-tic4x.c, * config/tc-tic54x.c,
* config/tc-tic6x.c, * config/tc-tilegx.c, * config/tc-tilepro.c,
* config/tc-v850.c, * config/tc-visium.c, * config/tc-wasm32.c,
* config/tc-xc16x.c, * config/tc-xgate.c, * config/tc-xstormy16.c,
* config/tc-xtensa.c, * config/tc-z8k.c: Update throughout for
bfd section macro and function changes.
* write.c (compress_debug): Use bfd_rename_section.
bfd_asymbol_* macros The main point of this patch is to give bfd_get_section a better name, bfd_asymbol_section. bfd/ * bfd-in.h (bfd_asymbol_section): Rename from bfd_get_section. (bfd_get_output_section): Delete. (bfd_asymbol_base): Delete. (bfd_asymbol_section, bfd_asymbol_value, bfd_asymbol_name), (bfd_asymbol_bfd, bfd_asymbol_flavour): Tidy. (bfd_set_asymbol_name): New macro. * bfd-in2.h: Regenerate. * aout-cris.c: Update throughout to use bfd_asymbol_section. * aoutx.h: Likewise. * cofflink.c: Likewise. * dwarf2.c: Likewise. * ecoff.c: Likewise. * elf.c: Likewise. * elf32-arm.c: Likewise. * elf32-mips.c: Likewise. * elf32-score.c: Likewise. * elf32-score7.c: Likewise. * elfn32-mips.c: Likewise. * elfnn-aarch64.c: Likewise. * elfxx-mips.c: Likewise. * linker.c: Likewise. * pdp11.c: Likewise. * elf64-mmix.c (mmix_elf_reloc): Expand bfd_get_output_section. binutils/ * nm.c: Update bfd_get_section to bfd_asymbol_section throughout. * objcopy.c: Likewise. * objdump.c: Likewise. * rdcoff.c: Likewise. * objcopy.c (create_new_symbol): Use bfd_set_asymbol_name. (filter_symbols): Likewise. gas/ * symbols.c (S_IS_LOCAL): Update bfd_get_section to bfd_asymbol_section. gdb/ * arm-tdep.c (arm_record_special_symbol): Update bfd_get_section to bfd_asymbol_section. ld/ * ldcref.c (check_reloc_refs): Update bfd_get_section to bfd_asymbol_section.
2019-09-18 14:55:19 +08:00
2019-09-18 Alan Modra <amodra@gmail.com>
* symbols.c (S_IS_LOCAL): Update bfd_get_section to
bfd_asymbol_section.
Re-generate many configure and Makefile.in files I get some spurious changes when running autoconf/automake for various projects in the tree. This is likely because they were generated using distro-patched tools last time. I ran `autoreconf -f` in the various automake projects of the binutils-gdb tree, and this is the result. The tools I am using have been compiled from source, from the upstream release. bfd/ChangeLog: * Makefile.in: Re-generate. * configure: Re-generate. * doc/Makefile.in: Re-generate. binutils/ChangeLog: * Makefile.in: Re-generate. * configure: Re-generate. * doc/Makefile.in: Re-generate. gas/ChangeLog: * Makefile.in: Re-generate. * configure: Re-generate. * doc/Makefile.in: Re-generate. gold/ChangeLog: * testsuite/Makefile.in: Re-generate. gprof/ChangeLog: * Makefile.in: Re-generate. * configure: Re-generate. ld/ChangeLog: * Makefile.in: Re-generate. * configure: Re-generate. opcodes/ChangeLog: * Makefile.in: Re-generate. * configure: Re-generate.
2019-09-18 21:07:44 +08:00
2019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
* Makefile.in: Re-generate.
* configure: Re-generate.
* doc/Makefile.in: Re-generate.
RISC-V: Gate opcode tables by enum rather than string. Generalize opcode arch dependencies so that we can support the overlapping B extension Zb* subsets. 2019-09-17 Maxim Blinov <maxim.blinov@embecosm.com> gas/ * config/tc-riscv.c (riscv_multi_subset_supports): Handle insn_class enum rather than subset char string. (riscv_ip): Update call to riscv_multi_subset_supports. include/ * opcode/riscv.h (riscv_insn_class): New enum. * opcode/riscv.h (struct riscv_opcode): Change subset field to insn_class field. opcodes/ * riscv-opc.c (riscv_opcodes): Change subset field to insn_class field for all instructions. (riscv_insn_types): Likewise.
2019-09-18 08:59:08 +08:00
2019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
* config/tc-riscv.c (riscv_multi_subset_supports): Handle
insn_class enum rather than subset char string.
(riscv_ip): Update call to riscv_multi_subset_supports.
Update version to 2.33.50 and regenerate configure scripts.
2019-09-16 18:01:00 +08:00
2019-09-16 Phil Blundell <pb@pbcl.net>
* Makefile.in, configure, doc/Makefile.in: Regenerated.
Enhance the disassembler so that it will reliably determine whether a reloc applies to the middle of the next insn. PR 24907 binutils* objdump.c (null_print): New function. (disassemble_bytes): Delete previous_octets local and replace with a test of the max_reloc_offset_into_insn field of the bfd_arch_info structure. If a reloc is a potential match for the next insn, then perform a dummy disassembly in order to calculate its real length. bfd * archures.c (bfd_arch_info_type): Add max_reloc_offset_into_insn field. (bfd_default_arch_struct): Initialise the new field. * bfd-in2.h: Regenerate. * cpu-aarch64.c: Initialise the new field. * cpu-alpha.c: Likewise. * cpu-arc.c: Likewise. * cpu-arm.c: Likewise. * cpu-avr.c: Likewise. * cpu-bfin.c: Likewise. * cpu-bpf.c: Likewise. * cpu-cr16.c: Likewise. * cpu-cr16c.c: Likewise. * cpu-cris.c: Likewise. * cpu-crx.c: Likewise. * cpu-csky.c: Likewise. * cpu-d10v.c: Likewise. * cpu-d30v.c: Likewise. * cpu-dlx.c: Likewise. * cpu-epiphany.c: Likewise. * cpu-fr30.c: Likewise. * cpu-frv.c: Likewise. * cpu-ft32.c: Likewise. * cpu-h8300.c: Likewise. * cpu-hppa.c: Likewise. * cpu-i386.c: Likewise. * cpu-ia64.c: Likewise. * cpu-iamcu.c: Likewise. * cpu-ip2k.c: Likewise. * cpu-iq2000.c: Likewise. * cpu-k1om.c: Likewise. * cpu-l1om.c: Likewise. * cpu-lm32.c: Likewise. * cpu-m10200.c: Likewise. * cpu-m10300.c: Likewise. * cpu-m32c.c: Likewise. * cpu-m32r.c: Likewise. * cpu-m68hc11.c: Likewise. * cpu-m68hc12.c: Likewise. * cpu-m68k.c: Likewise. * cpu-m9s12x.c: Likewise. * cpu-m9s12xg.c: Likewise. * cpu-mcore.c: Likewise. * cpu-mep.c: Likewise. * cpu-metag.c: Likewise. * cpu-microblaze.c: Likewise. * cpu-mips.c: Likewise. * cpu-mmix.c: Likewise. * cpu-moxie.c: Likewise. * cpu-msp430.c: Likewise. * cpu-mt.c: Likewise. * cpu-nds32.c: Likewise. * cpu-nfp.c: Likewise. * cpu-nios2.c: Likewise. * cpu-ns32k.c: Likewise. * cpu-or1k.c: Likewise. * cpu-pdp11.c: Likewise. * cpu-pj.c: Likewise. * cpu-plugin.c: Likewise. * cpu-powerpc.c: Likewise. * cpu-pru.c: Likewise. * cpu-riscv.c: Likewise. * cpu-rl78.c: Likewise. * cpu-rs6000.c: Likewise. * cpu-rx.c: Likewise. * cpu-s12z.c: Likewise. * cpu-s390.c: Likewise. * cpu-score.c: Likewise. * cpu-sh.c: Likewise. * cpu-sparc.c: Likewise. * cpu-spu.c: Likewise. * cpu-tic30.c: Likewise. * cpu-tic4x.c: Likewise. * cpu-tic54x.c: Likewise. * cpu-tic6x.c: Likewise. * cpu-tic80.c: Likewise. * cpu-tilegx.c: Likewise. * cpu-tilepro.c: Likewise. * cpu-v850.c: Likewise. * cpu-v850_rh850.c: Likewise. * cpu-vax.c: Likewise. * cpu-visium.c: Likewise. * cpu-wasm32.c: Likewise. * cpu-xc16x.c: Likewise. * cpu-xgate.c: Likewise. * cpu-xstormy16.c: Likewise. * cpu-xtensa.c: Likewise. * cpu-z80.c: Likewise. * cpu-z8k.c: Likewise. gas * testsuite/gas/arm/pr24907.s: New test. * testsuite/gas/arm/pr24907.d: Expected disassembly.
2019-09-10 22:20:58 +08:00
2019-09-10 Nick Clifton <nickc@redhat.com>
PR 24907
* testsuite/gas/arm/pr24907.s: New test.
* testsuite/gas/arm/pr24907.d: Expected disassembly.
Add markers for 2.33 branch to NEWS and ChangeLog files.
2019-09-09 17:27:03 +08:00
2019-09-09 Phil Blundell <pb@pbcl.net>
binutils 2.33 branch created.
PowerPC warning on symbol+offset@got * config/tc-ppc.c (ppc_elf_suffix): Display the relocation operator on GOT reloc warnings/errors.
2019-09-05 14:20:35 +08:00
2019-09-05 Alan Modra <amodra@gmail.com>
* config/tc-ppc.c (ppc_elf_suffix): Display the relocation
operator on GOT reloc warnings/errors.
Add support for the MVE VMOV instruction to the ARM assembler. This instruction copies the value of one vector register to another vector register. The patch also modifies the decoding of VORR instruction which is effecting decoding of VMOV instruction. gas * config/tc-arm.c (parse_neon_mov): Add check to accept vector register to both the arguments in VMOV instruction. * testsuite/gas/arm/mve-vmov-1.d: Modify. * testsuite/gas/arm/mve-vmov-1.s: Likewise. * testsuite/gas/arm/mve-vorr.d: Likewise. opcodes * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC. (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC. (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
2019-08-27 19:08:21 +08:00
2019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config/tc-arm.c (parse_neon_mov): Add check to accept vector
register to both the arguments in VMOV instruction.
* testsuite/gas/arm/mve-vmov-1.d: Modify.
* testsuite/gas/arm/mve-vmov-1.s: Likewise.
* testsuite/gas/arm/mve-vorr.d: Likewise.
Updated Swedish translation for the gas sub-directory. 2019-08-23 Nick Clifton <nickc@redhat.com> * po/sv.po: Updated Swedish translation.
2019-08-23 17:46:46 +08:00
2019-08-23 Nick Clifton <nickc@redhat.com>
* po/sv.po: Updated Swedish translation.
Arm: Add support for missing CPUs This patch adds support for following CPUs: Cortex-M35P, Cortex-A77, Cortex-A76AE. Related specifications can be found at https://developer.arm.com/ip-products/processors. gas/ChangeLog: * config/tc-arm.c: New entries for Cortex-M35P, Cortex-A77, and Cortex-A76AE. * doc/c-arm.texi: Document new processors. * testsuite/gas/arm/cpu-cortex-a76ae.d: New test. * testsuite/gas/arm/cpu-cortex-a77.d: New test. * testsuite/gas/arm/cpu-cortex-m35p.d: New test. bfd/ChangeLog: * cpu-arm.c: New entries for Cortex-M35P, Cortex-A77, Cortex-A76AE.
2019-08-22 22:21:32 +08:00
2019-08-22 Dennis Zhang <dennis.zhang@arm.com>
* config/tc-arm.c: New entries for Cortex-M35P, Cortex-A77,
and Cortex-A76AE.
* doc/c-arm.texi: Document new processors.
* testsuite/gas/arm/cpu-cortex-a76ae.d: New test.
* testsuite/gas/arm/cpu-cortex-a77.d: New test.
* testsuite/gas/arm/cpu-cortex-m35p.d: New test.
Fix the assembler's floating point number parser so that it can correctly handle numbers encoded as a leading decimal point, followed by zeroes, followed by a non-zero sequence. * atof-generic.c (atof_generic): Do not ignore leading zeros if they appear after a decimal point. * testsuite/gas/all/float.s: Extend test to include a number with a leading decimal point followed by several zeroes. * testsuite/gas/i386/fp.s: Likewise. * testsuite/gas/i386/fp.d: Update expected output.
2019-08-22 19:54:06 +08:00
2019-08-22 Bosco García <jbgg.gnu@gmail.com>
Nick Clifton <nickc@redhat.com>
* atof-generic.c (atof_generic): Do not ignore leading zeros if
they appear after a decimal point.
* testsuite/gas/all/float.s: Extend test to include a number with
a leading decimal point followed by several zeroes.
* testsuite/gas/i386/fp.s: Likewise.
* testsuite/gas/i386/fp.d: Update expected output.
Implement a float16 directive for assembling 16 bit IEEE 754 floating point numbers for the AArch64 assembler. The syntax of the directive is: .float16 <0-n decimal numbers> e.g. .float16 0.5 .float16 10.2, NaN, 452.09 The floats will always be encoded using the binary16 format as described in the IEEE 754-2008 standard. There is no need to support Arm's alternative half-precision format since AArch64 only supports the IEEE format. gas * config/tc-aarch64.c: Add float16 directive and add "Hh" to acceptable float characters. * doc/c-aarch64.texi: Documentation for float16 directive. * testsuite/gas/aarch64/float16-be.d: New test. * testsuite/gas/aarch64/float16-le.d: New test. * testsuite/gas/aarch64/float16.s: New test. * NEWS: Add NEWS entry.
2019-08-22 18:13:23 +08:00
2019-08-22 Barnaby Wilks <barnaby.wilks@arm.com>
* config/tc-aarch64.c: Add float16 directive and add "Hh" to
acceptable float characters.
* doc/c-aarch64.texi: Documentation for float16 directive.
* testsuite/gas/aarch64/float16-be.d: New test.
* testsuite/gas/aarch64/float16-le.d: New test.
* testsuite/gas/aarch64/float16.s: New test.
* NEWS: Add NEWS entry.
[AArch64][gas] Update MTE system register encodings The MTE specification adjusted the encoding of the TFSRE0_EL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12 system registers. This patch brings binutils up to date. The references for the encodings are at: https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/tfsre0_el1 (also contains TFSR_EL12 description) https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/tfsr_el1 https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/tfsr_el2 https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/tfsr_el3 Tested check-gas for aarch64-none-elf. opcodes/ * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1, tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12. (aarch64_sys_reg_supported_p): Update checks for the above. gas/ * testsuite/gas/aarch64/sysreg-4.d: Update expected disassembly for tfsre0_el1, tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12 system registers.
2019-08-22 17:20:01 +08:00
2019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* testsuite/gas/aarch64/sysreg-4.d: Update expected disassembly for
tfsre0_el1, tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12 system registers.
Adds support for following CPUs to the ARM and Aarch64 assemblers: Cortex-A77, Cortex-A76AE, Cortex-A34, Cortex-A65, and Cortex-A65AE. Related specifications can be found at https://developer.arm.com/ip-products/processors. gas * NEWS: Mention the Arm and AArch64 new processors. * config/tc-aarch64.c: New entries for Cortex-A34, Cortex-A65, Cortex-A77, cortex-A65AE, and Cortex-A76AE. * doc/c-aarch64.texi: Document new CPUs. * testsuite/gas/aarch64/cpu-cortex-a34.d: New test. * testsuite/gas/aarch64/cpu-cortex-a65.d: New test. * testsuite/gas/aarch64/cpu-cortex-a65ae.d: New test. * testsuite/gas/aarch64/cpu-cortex-a76ae.d: New test. * testsuite/gas/aarch64/cpu-cortex-a77.d: New test. * testsuite/gas/aarch64/nop-asm.s: New test. bfd * cpu-aarch64.c: New entries for Cortex-A34, Cortex-A65, Cortex-A77, cortex-A65AE, and Cortex-A76AE.
2019-08-21 00:13:29 +08:00
2019-08-20 Dennis Zhang <dennis.zhang@arm.com>
* NEWS: Mention the Arm and AArch64 new processors.
* config/tc-aarch64.c: New entries for Cortex-A34, Cortex-A65,
Cortex-A77, cortex-A65AE, and Cortex-A76AE.
* doc/c-aarch64.texi: Document new CPUs.
* testsuite/gas/aarch64/cpu-cortex-a34.d: New test.
* testsuite/gas/aarch64/cpu-cortex-a65.d: New test.
* testsuite/gas/aarch64/cpu-cortex-a65ae.d: New test.
* testsuite/gas/aarch64/cpu-cortex-a76ae.d: New test.
* testsuite/gas/aarch64/cpu-cortex-a77.d: New test.
* testsuite/gas/aarch64/nop-asm.s: New test.
MIPS/gas: Fix misaligned address errors to disregard ISA mode bit gas/ * config/tc-mips.c (fix_bad_misaligned_address): New function. (fix_validate_branch): Call fix_bad_misaligned address_to calculate the target address. (md_apply_fix): Likewise. (md_convert_frag): Update misaligned address calculation to disregard ISA mode bit.
2019-08-13 13:32:20 +08:00
2019-08-19 Faraz Shahbazker <fshahbazker@wavecomp.com>
* config/tc-mips.c (fix_bad_misaligned_address): New function.
(fix_validate_branch): Call fix_bad_misaligned address_to
calculate the target address.
(md_apply_fix): Likewise.
(md_convert_frag): Update misaligned address calculation to
disregard ISA mode bit.
MIPS/gas: Retain ISA mode bit for labels with .insn annotation gas/ * config/tc-mips.c (mips_move_labels): Retain ISA mode bit when moving labels in text segments. (mips_align): Indicate text mode when aligning labels in text segments. * gas/testsuite/gas/mips/insn-isa-mode.d: New test. * gas/testsuite/gas/mips/insn-isa-mode.s: New test source. * gas/testsuite/gas/mips/mips.exp: Run the new test.
2019-08-06 07:38:46 +08:00
2019-08-19 Faraz Shahbazker <fshahbazker@wavecomp.com>
* config/tc-mips.c (mips_move_labels): Retain ISA mode bit
when moving labels in text segments.
(mips_align): Indicate text mode when aligning labels in
text segments.
* gas/testsuite/gas/mips/insn-isa-mode.d: New test.
* gas/testsuite/gas/mips/insn-isa-mode.s: New test source.
* gas/testsuite/gas/mips/mips.exp: Run the new test.
Float16: Fix test failures for non ELF targets The tests were failing due to md_atof trying to do word-wise endian switching on the float16 (for little-endian targets sometimes multi word values have their word order changed). However since a float16 is only 1 word wide, it would end up writing incorrect data, as you cannot switch the word order of just one word. * config/tc-arm.c (md_atof): Add precision check. Formatting.
2019-08-16 00:21:59 +08:00
2019-08-19 Barnaby Wilks <Barnaby.Wilks@arm.com>
* config/tc-arm.c (md_atof): Add precision check. Formatting.
Updatesd Swdish translation for the gas sub-directory. * po/sv.po: Updated Swedish translation.
2019-08-15 19:41:24 +08:00
2019-08-15 Nick Clifton <nickc@redhat.com>
* po/sv.po: Updated Swedish translation.
Modify the ARM encoding and decoding of SQRSHRL and UQRSHLL MVE instructions. This is a change to the first published specifications [1][a] but since there is no hardware out there that uses the old instructions we do not want to support the old variant. This changes are done based on the latest published specifications [1][b]. [1] https://developer.arm.com/architectures/cpu-architecture/m-profile/docs/ddi0553/latest/armv81-m-architecture-reference-manual [a] version bf [b] version bh gas * config/tc-arm.c (enum operand_parse_code): Add the entry OP_I48_I64. (po_imm1_or_imm2_or_fail): Marco to check the immediate is either of 48 or 64. (parse_operands): Add case OP_I48_I64. (do_mve_scalar_shift1): Add function to encode the MVE shift instructions with 4 arguments. * testsuite/gas/arm/mve-shift-bad.l: Modify. * testsuite/gas/arm/mve-shift-bad.s: Likewise. * testsuite/gas/arm/mve-shift.d: Likewise. * testsuite/gas/arm/mve-shift.s: Likewise. opcodes * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for cases MVE_SQRSHRL and MVE_UQRSHLL. (print_insn_mve): Add case for specifier 'k' to check specific bit of the instruction.
2019-08-13 00:17:18 +08:00
2019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config/tc-arm.c (enum operand_parse_code): Add the entry OP_I48_I64.
(po_imm1_or_imm2_or_fail): Marco to check the immediate is either of
48 or 64.
(parse_operands): Add case OP_I48_I64.
(do_mve_scalar_shift1): Add function to encode the MVE shift
instructions with 4 arguments.
* testsuite/gas/arm/mve-shift-bad.l: Modify.
* testsuite/gas/arm/mve-shift-bad.s: Likewise.
* testsuite/gas/arm/mve-shift.d: Likewise.
* testsuite/gas/arm/mve-shift.s: Likewise.
Add generic and ARM specific support for half-precision IEEE 754 floating point numbers to the assembler. Half precision floating point numbers will be encoded using the IEEE 754 half precision floating point format - 16 bits in total, 1 for sign, 5 for exponent and 10 bits of mantissa. This patch implements the float16 directive for both the IEEE 754 format and the Arm alternative format for the Arm backend. The syntax of the directive is: .float16 <0-n decimal numbers> e.g. .float16 12.0 .float16 0.23, 433.1, 0.06 The Arm alternative format is almost identical to the IEEE 754 format, except that it doesn't encode for NaNs or Infinity (instead an exponent of 0x1F represents a normalized number in the range 65536 to 131008). The alternative format is documented in the reference manual: https://static.docs.arm.com/ddi0487/db/DDI0487D_b_armv8_arm.pdf?_ga=2.72318806.49764181.1561632697-999473562.1560847439 Which format is used is controlled by the .float16_format <format> directive, where if <format> = ieee, then use the IEEE 754 half-precision format else if <format> = alternative, then use the Arm alternative format Or the format can be set on the command line via the -mfp16-format option that has a similar syntax. -mfp16-format=<ieee|alternative>. This also fixes the format and it cannot be changed by any directives. Once the format has been set (either by the command line option or a directive) it cannot be changed, and any attempts to change it (i.e. with the float16_format directive) will result in a warning and the line being ignored. For ELF targets the appropriate EABI attribute will be written out at the end of assembling if the format has been explicitly specified. If no format has been explicitly specified then no EABI attributes will be written. If the format is not explicitly specified then any float16 directives are encoding using the IEEE 754-2008 format by default until the format is fixed or changed with the float16_format directive. gas * config/tc-arm.c (enum fp_16bit_format): Add enum to represent the 2 float16 encodings. (md_atof): Set precision for float16 type. (arm_is_largest_exponent_ok): Check for whether to encode with the IEEE or alternative format. (set_fp16_format): Parse a float16_format directive. (arm_parse_fp16_opt): Parse the fp16-format command line option. (aeabi_set_public_attributes): For ELF encode the FP16 format EABI attribute. * config/tc-arm.h (TC_LARGEST_EXPONENT_IS_NORMAL): Macro that expands to arm_is_largest_exponent_ok. (arm_is_largest_exponent_ok): Add prototype for arm_is_largest_exponent_ok function. * doc/c-arm.texi: Add documentation for .float16, .float16_format and -mfp16-format= * testsuite/gas/arm/float16-bad.d: New test. * testsuite/gas/arm/float16-bad.l: New test. * testsuite/gas/arm/float16-bad.s: New test. * testsuite/gas/arm/float16-be.d: New test. * testsuite/gas/arm/float16-format-bad.d: New test. * testsuite/gas/arm/float16-format-bad.l: New test. * testsuite/gas/arm/float16-format-bad.s: New test. * testsuite/gas/arm/float16-format-opt-bad.d: New test. * testsuite/gas/arm/float16-format-opt-bad.l: New test. * testsuite/gas/arm/float16-le.d: New test. * testsuite/gas/arm/float16.s: New test. * testsuite/gas/arm/float16-eabi-alternative-format.d: New test. * testsuite/gas/arm/float16-eabi-ieee-format.d: New test. * testsuite/gas/arm/float16-eabi-no-format.d: New test. * testsuite/gas/arm/float16-eabi.s: New test. * config/atof-ieee.c (H_PRECISION): Macro for precision of float16 type. (atof_ieee): Set precision and exponent bits for encoding float16 types. (gen_to_words): NaN and Infinity encoding for float16. (ieee_md_atof): Set precision for encoding float16 type.
2019-08-12 18:08:36 +08:00
2019-08-12 Barnaby Wilks <barnaby.wilks@arm.com>
* config/tc-arm.c (enum fp_16bit_format): Add enum to represent the 2 float16 encodings.
(md_atof): Set precision for float16 type.
(arm_is_largest_exponent_ok): Check for whether to encode with the IEEE or alternative
format.
(set_fp16_format): Parse a float16_format directive.
(arm_parse_fp16_opt): Parse the fp16-format command line option.
(aeabi_set_public_attributes): For ELF encode the FP16 format EABI attribute.
* config/tc-arm.h (TC_LARGEST_EXPONENT_IS_NORMAL): Macro that expands to
arm_is_largest_exponent_ok.
(arm_is_largest_exponent_ok): Add prototype for arm_is_largest_exponent_ok function.
* doc/c-arm.texi: Add documentation for .float16, .float16_format and -mfp16-format=
* testsuite/gas/arm/float16-bad.d: New test.
* testsuite/gas/arm/float16-bad.l: New test.
* testsuite/gas/arm/float16-bad.s: New test.
* testsuite/gas/arm/float16-be.d: New test.
* testsuite/gas/arm/float16-format-bad.d: New test.
* testsuite/gas/arm/float16-format-bad.l: New test.
* testsuite/gas/arm/float16-format-bad.s: New test.
* testsuite/gas/arm/float16-format-opt-bad.d: New test.
* testsuite/gas/arm/float16-format-opt-bad.l: New test.
* testsuite/gas/arm/float16-le.d: New test.
* testsuite/gas/arm/float16.s: New test.
* testsuite/gas/arm/float16-eabi-alternative-format.d: New test.
* testsuite/gas/arm/float16-eabi-ieee-format.d: New test.
* testsuite/gas/arm/float16-eabi-no-format.d: New test.
* testsuite/gas/arm/float16-eabi.s: New test.
2019-08-12 Barnaby Wilks <barnaby.wilks@arm.com>
* config/atof-ieee.c (H_PRECISION): Macro for precision of float16
type.
(atof_ieee): Set precision and exponent bits for encoding float16
types.
(gen_to_words): NaN and Infinity encoding for float16.
(ieee_md_atof): Set precision for encoding float16 type.
PR24851, gas/testsuite/gas/epiphany/badrelax.s failure with MALLOC_PERTURB_=1 PR 24851 * config/tc-epiphany.c (md_estimate_size_before_relax): Clear extra opcode bytes when changing from a 2-byte to a 4-byte insn.
2019-08-12 09:45:19 +08:00
2019-08-12 Alan Modra <amodra@gmail.com>
PR 24851
* config/tc-epiphany.c (md_estimate_size_before_relax): Clear
extra opcode bytes when changing from a 2-byte to a 4-byte insn.
x86-64: generalize SIMD test expectations In order to be able to add/remove insns to/from the middle of these tests, generalize the patterns for the symbol reference comments of RIP- relative operands.
2019-08-09 15:57:57 +08:00
2019-08-09 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/ilp32/x86-64-simd-intel.d,
testsuite/gas/i386/ilp32/x86-64-simd-suffix.d,
testsuite/gas/i386/ilp32/x86-64-simd.d: Redirect to parent dir
output expectations.
* testsuite/gas/i386/x86-64-simd-intel.d,
testsuite/gas/i386/x86-64-simd-suffix.d,
testsuite/gas/i386/x86-64-simd.d: Don't hard-code hex addresses
and symbol-relative offsets.
Change the output of readelf's note display so that the "Data size" column header is left justified. PR 24887 binutils* readelf.c (process_notes_at): Left justify the "Data size" column heading. * testsuite/binutils-all/i386/empty.d: Adjust for new output format. * testsuite/binutils-all/i386/ibt.d: Likewise. * testsuite/binutils-all/i386/pr21231a.d: Likewise. * testsuite/binutils-all/i386/pr21231b.d: Likewise. * testsuite/binutils-all/i386/shstk.d: Likewise. * testsuite/binutils-all/note-2-32.d: Likewise. * testsuite/binutils-all/note-2-64.d: Likewise. * testsuite/binutils-all/x86-64/empty-x32.d: Likewise. * testsuite/binutils-all/x86-64/empty.d: Likewise. * testsuite/binutils-all/x86-64/ibt-x32.d: Likewise. * testsuite/binutils-all/x86-64/ibt.d: Likewise. * testsuite/binutils-all/x86-64/pr21231a.d: Likewise. * testsuite/binutils-all/x86-64/pr21231b.d: Likewise. * testsuite/binutils-all/x86-64/pr23494a-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494a.d: Likewise. * testsuite/binutils-all/x86-64/pr23494c-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494c.d: Likewise. * testsuite/binutils-all/x86-64/pr23494d-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494d.d: Likewise. * testsuite/binutils-all/x86-64/pr23494e-x32.d: Likewise. * testsuite/binutils-all/x86-64/pr23494e.d: Likewise. * testsuite/binutils-all/x86-64/shstk-x32.d: Likewise. * testsuite/binutils-all/x86-64/shstk.d: Likewise. ld * testsuite/ld-aarch64/bti-plt-2.d: Adjust for new output format from readelf. * testsuite/ld-aarch64/bti-plt-4.d: Likewise. * testsuite/ld-aarch64/bti-plt-6.d: Likewise. * testsuite/ld-aarch64/bti-plt-7.d: Likewise. * testsuite/ld-aarch64/bti-warn.d: Likewise. * testsuite/ld-aarch64/property-bti-pac1.d: Likewise. * testsuite/ld-aarch64/property-bti-pac2.d: Likewise. * testsuite/ld-aarch64/property-bti-pac3.d: Likewise. * testsuite/ld-elf/x86-feature-1a.rd: Likewise. * testsuite/ld-elf/x86-feature-1b.rd: Likewise. * testsuite/ld-elf/x86-feature-1c.rd: Likewise. * testsuite/ld-elf/x86-feature-1d.rd: Likewise. * testsuite/ld-elf/x86-feature-1e.rd: Likewise. * testsuite/ld-i386/ibt-plt-2d.d: Likewise. * testsuite/ld-i386/ibt-plt-3d.d: Likewise. * testsuite/ld-i386/pr23372a.d: Likewise. * testsuite/ld-i386/pr23372c.d: Likewise. * testsuite/ld-i386/pr23486a.d: Likewise. * testsuite/ld-i386/pr23486b.d: Likewise. * testsuite/ld-i386/pr23486c.d: Likewise. * testsuite/ld-i386/pr23486d.d: Likewise. * testsuite/ld-i386/pr24322a.d: Likewise. * testsuite/ld-i386/pr24322b.d: Likewise. * testsuite/ld-i386/property-x86-3.d: Likewise. * testsuite/ld-i386/property-x86-4a.d: Likewise. * testsuite/ld-i386/property-x86-5.d: Likewise. * testsuite/ld-i386/property-x86-cet1.d: Likewise. * testsuite/ld-i386/property-x86-cet2a.d: Likewise. * testsuite/ld-i386/property-x86-cet5a.d: Likewise. * testsuite/ld-i386/property-x86-cet5b.d: Likewise. * testsuite/ld-i386/property-x86-ibt1a.d: Likewise. * testsuite/ld-i386/property-x86-ibt1b.d: Likewise. * testsuite/ld-i386/property-x86-ibt2.d: Likewise. * testsuite/ld-i386/property-x86-ibt3a.d: Likewise. * testsuite/ld-i386/property-x86-ibt3b.d: Likewise. * testsuite/ld-i386/property-x86-ibt4.d: Likewise. * testsuite/ld-i386/property-x86-ibt5.d: Likewise. * testsuite/ld-i386/property-x86-shstk1a.d: Likewise. * testsuite/ld-i386/property-x86-shstk1b.d: Likewise. * testsuite/ld-i386/property-x86-shstk2.d: Likewise. * testsuite/ld-i386/property-x86-shstk3a.d: Likewise. * testsuite/ld-i386/property-x86-shstk3b.d: Likewise. * testsuite/ld-i386/property-x86-shstk4.d: Likewise. * testsuite/ld-i386/property-x86-shstk5.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2d-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2d.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3d-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3d.d: Likewise. * testsuite/ld-x86-64/pr23372a-x32.d: Likewise. * testsuite/ld-x86-64/pr23372a.d: Likewise. * testsuite/ld-x86-64/pr23372c-x32.d: Likewise. * testsuite/ld-x86-64/pr23372c.d: Likewise. * testsuite/ld-x86-64/pr23486a-x32.d: Likewise. * testsuite/ld-x86-64/pr23486a.d: Likewise. * testsuite/ld-x86-64/pr23486b-x32.d: Likewise. * testsuite/ld-x86-64/pr23486b.d: Likewise. * testsuite/ld-x86-64/pr23486c-x32.d: Likewise. * testsuite/ld-x86-64/pr23486c.d: Likewise. * testsuite/ld-x86-64/pr23486d-x32.d: Likewise. * testsuite/ld-x86-64/pr23486d.d: Likewise. * testsuite/ld-x86-64/pr24322a-x32.d: Likewise. * testsuite/ld-x86-64/pr24322a.d: Likewise. * testsuite/ld-x86-64/pr24322b-x32.d: Likewise. * testsuite/ld-x86-64/pr24322b.d: Likewise. * testsuite/ld-x86-64/pr24458a-x32.d: Likewise. * testsuite/ld-x86-64/pr24458a.d: Likewise. * testsuite/ld-x86-64/pr24458b-x32.d: Likewise. * testsuite/ld-x86-64/pr24458b.d: Likewise. * testsuite/ld-x86-64/pr24458c-x32.d: Likewise. * testsuite/ld-x86-64/pr24458c.d: Likewise. * testsuite/ld-x86-64/property-1.r: Likewise. * testsuite/ld-x86-64/property-1a.r: Likewise. * testsuite/ld-x86-64/property-2.r: Likewise. * testsuite/ld-x86-64/property-2a.r: Likewise. * testsuite/ld-x86-64/property-3.r: Likewise. * testsuite/ld-x86-64/property-3a.r: Likewise. * testsuite/ld-x86-64/property-4.r: Likewise. * testsuite/ld-x86-64/property-4a.r: Likewise. * testsuite/ld-x86-64/property-5.r: Likewise. * testsuite/ld-x86-64/property-5a.r: Likewise. * testsuite/ld-x86-64/property-6.r: Likewise. * testsuite/ld-x86-64/property-7.r: Likewise. * testsuite/ld-x86-64/property-7a.r: Likewise. * testsuite/ld-x86-64/property-x86-3-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-3.d: Likewise. * testsuite/ld-x86-64/property-x86-4a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-4a.d: Likewise. * testsuite/ld-x86-64/property-x86-5-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-5.d: Likewise. * testsuite/ld-x86-64/property-x86-cet1-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-cet1.d: Likewise. * testsuite/ld-x86-64/property-x86-cet2a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-cet2a.d: Likewise. * testsuite/ld-x86-64/property-x86-cet5a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-cet5a.d: Likewise. * testsuite/ld-x86-64/property-x86-cet5b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-cet5b.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt1a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt1a.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt1b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt1b.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt2-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt2.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3a.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt3b.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt4-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt4.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt5-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-ibt5.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk1a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk1a.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk1b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk1b.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk2-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk2.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3a-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3a.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3b-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk3b.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk4-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk4.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk5-x32.d: Likewise. * testsuite/ld-x86-64/property-x86-shstk5.d: Likewise. gas * testsuite/gas/i386/property-1.d: Adjust for new output format from readelf. * testsuite/gas/i386/property-2.d: Likewise. * testsuite/gas/i386/x86-64-property-1.d: Likewise. * testsuite/gas/i386/x86-64-property-2.d: Likewise.
2019-08-09 00:04:31 +08:00
2019-08-08 Nick Clifton <nickc@redhat.com>
PR 24887
* testsuite/gas/i386/property-1.d: Adjust for new output format
from readelf.
* testsuite/gas/i386/property-2.d: Likewise.
* testsuite/gas/i386/x86-64-property-1.d: Likewise.
* testsuite/gas/i386/x86-64-property-2.d: Likewise.
Move the h8300 assembler's MOVFPE and MOVTPE tests to the correct location. * gas/testsuite/gas/h8300/h8300.exp: Fix movfpe and movtpe tests. * gas/testsuite/gas/h8300/misc.s: Likewise. * gas/testsuite/gas/h8300/misch.s: Likewise. * gas/testsuite/gas/h8300/miscs.s: Likewise.
2019-08-08 20:43:13 +08:00
2019-08-08 Yoshinori Sato <ysato@users.sourceforge.jp>
Update the handling of shift rotate and load/store multiple instructions in the H8300 assembler. incldue * opcode/h8300.h (EXPAND_UNOP_EXTENDED_B): Add MODEL. (EXPAND_UNOP_EXTENDED_W): Likewise. (EXPAND_UNOP_EXTENDED_L): Likewise. (struct h8_opcode h8_opcodes): Likewise. (struct h8_opcode h8_opcodes): tas / ldm / stm supported H8S or later.
2019-08-08 20:59:17 +08:00
* testsuite/gas/h8300/h8300.exp: Fix movfpe and movtpe tests.
* testsuite/gas/h8300/misc.s: Likewise.
* testsuite/gas/h8300/misch.s: Likewise.
* testsuite/gas/h8300/miscs.s: Likewise.
Move the h8300 assembler's MOVFPE and MOVTPE tests to the correct location. * gas/testsuite/gas/h8300/h8300.exp: Fix movfpe and movtpe tests. * gas/testsuite/gas/h8300/misc.s: Likewise. * gas/testsuite/gas/h8300/misch.s: Likewise. * gas/testsuite/gas/h8300/miscs.s: Likewise.
2019-08-08 20:43:13 +08:00
Removes support in the ARM assembler for the unsigned variants of the VQ(R)DMLAH and VQ(R)DMLASH MVE instructions. Previously GAS would accept .u32, .u16 and .u8 suffixes to the VQ(R)DMLAH and VQ(R)DMLASH instructions, however the Armv8.1-M Mainline specification states that these functions only have signed variations (.s32, .s16 and .s8 suffixes). This is documented here: https://static.docs.arm.com/ddi0553/bh/DDI0553B_h_armv8m_arm.pdf?_ga=2.143079093.1892401233.1563295591-999473562.1560847439#page=1183 gas * config/tc-arm.c (do_mve_vqdmlah): Use N_S_32 macro. (do_neon_qrdmlah): Use N_S_32 macro. * testsuite/gas/arm/mve-vqdmlah-bad.d: New test. * testsuite/gas/arm/mve-vqdmlah-bad.l: New test. * testsuite/gas/arm/mve-vqdmlah-bad.s: New test. * testsuite/gas/arm/mve-vqdmlah.d: Remove unsigned instruction tests. * testsuite/gas/arm/mve-vqdmlah.s: Remove unsigned instruction tests. * testsuite/gas/arm/mve-vqdmlash-bad.d: New test. * testsuite/gas/arm/mve-vqdmlash-bad.l: New test. * testsuite/gas/arm/mve-vqdmlash-bad.s: New test. * testsuite/gas/arm/mve-vqdmlash.d: Remove unsigned instruction tests. * testsuite/gas/arm/mve-vqdmlash.s: Remove unsigned instruction tests. opcodes * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH instructions.
2019-08-05 19:43:38 +08:00
2019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
* config/tc-arm.c (do_mve_vqdmlah): Use N_S_32 macro.
(do_neon_qrdmlah): Use N_S_32 macro.
* testsuite/gas/arm/mve-vqdmlah-bad.d: New test.
* testsuite/gas/arm/mve-vqdmlah-bad.l: New test.
* testsuite/gas/arm/mve-vqdmlah-bad.s: New test.
* testsuite/gas/arm/mve-vqdmlah.d: Remove unsigned instruction tests.
* testsuite/gas/arm/mve-vqdmlah.s: Remove unsigned instruction tests.
* testsuite/gas/arm/mve-vqdmlash-bad.d: New test.
* testsuite/gas/arm/mve-vqdmlash-bad.l: New test.
* testsuite/gas/arm/mve-vqdmlash-bad.s: New test.
* testsuite/gas/arm/mve-vqdmlash.d: Remove unsigned instruction tests.
* testsuite/gas/arm/mve-vqdmlash.s: Remove unsigned instruction tests.
RISC-V: Fix minor issues with FP csr instructions. Mel Chen <mel.chen@sifive.com> gas/ * testsuite/gas/riscv/alias-csr.s: Add testcase for CSR-access alias instructions. * testsuite/gas/riscv/no-aliases-csr.d: Run testcase alias-csr.s with -Mno-aliases. * testsuite/gas/riscv/alias-csr.d: Run testcase alias-csr.s. * testsuite/gas/riscv/priv-reg.d: Update. opcodes/ * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm, fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions. * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr, fscsr.
2019-07-31 05:42:16 +08:00
2019-07-30 Mel Chen <mel.chen@sifive.com>
* testsuite/gas/riscv/alias-csr.s: Add testcase for CSR-access
alias instructions.
* testsuite/gas/riscv/no-aliases-csr.d: Run testcase alias-csr.s with
-Mno-aliases.
* testsuite/gas/riscv/alias-csr.d: Run testcase alias-csr.s.
* testsuite/gas/riscv/priv-reg.d: Update.
Update the Swedish translation for the gas sub-directory.
2019-07-24 22:21:24 +08:00
2019-07-24 Nick Clifton <nickc@redhat.com>
* po/sv.po: Updated Swedish translation.
[ARC] Update disassembler opcode selection New instruction are added, and some of them are overlapping. Update disassembler to correctly recognize them. Introduce nps400 option. opcodes/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes, and MPY class instructions. (parse_option): Add nps400 option. (print_arc_disassembler_options): Add nps400 info. gas/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/nps400-6.d: Update test.
2019-07-24 21:52:23 +08:00
2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/nps400-6.d: Update test.
Complain about mbind, ifunc, and unique in final_write It's not as good as complaining in gas/config/obj-elf.c since you lose any reference to the source file. bfd/ * elf-bfd.h (struct elf_backend_data): Return bfd_boolean from elf_backend_final_write_processing, don't pass linker arg. (_bfd_elf_final_write_processing): Update prototype. * elf.c (_bfd_elf_write_object_contents): Adjust call. (_bfd_elf_final_write_processing): Return error on incompatible OSABI and has_gnu_osabi. Remove linker arg. * elf-nacl.h (nacl_final_write_processing): Update prototype. * elf-vxworks.h (elf_vxworks_final_write_processing): Likewise. * elfxx-mips.h (_bfd_mips_final_write_processing): Likewise. (_bfd_mips_elf_final_write_processing): Likewise. * elf-hppa.h (elf_hppa_final_write_processing): Return status and remove linker arg. * elf-m10300.c (_bfd_mn10300_elf_final_write_processing): Likewise. * elf-nacl.c (nacl_final_write_processing): Likewise. * elf-vxworks.c (elf_vxworks_final_write_processing): Likewise. * elf32-arc.c (arc_elf_final_write_processing): Likewise. * elf32-arm.c (arm_final_write_processing): Likewise. (elf32_arm_final_write_processing): Likewise. (elf32_arm_nacl_final_write_processing): Likewise. (elf32_arm_vxworks_final_write_processing): Likewise. * elf32-avr.c (bfd_elf_avr_final_write_processing): Likewise. * elf32-bfin.c (elf32_bfin_final_write_processing): Likewise. * elf32-cr16.c (_bfd_cr16_elf_final_write_processing): Likewise. * elf32-cris.c (cris_elf_final_write_processing): Likewise. * elf32-h8300.c (elf32_h8_final_write_processing): Likewise. * elf32-lm32.c (lm32_elf_final_write_processing): Likewise. * elf32-m32r.c (m32r_elf_final_write_processing): Likewise. * elf32-m68k.c (elf_m68k_final_write_processing): Likewise. * elf32-mips.c (mips_vxworks_final_write_processing): Likewise. * elf32-msp430.c (bfd_elf_msp430_final_write_processing): Likewise. * elf32-nds32.c (nds32_elf_final_write_processing): Likewise. * elf32-or1k.c (or1k_elf_final_write_processing): Likewise. * elf32-pj.c (pj_elf_final_write_processing): Likewise. * elf32-ppc.c (ppc_final_write_processing): Likewise. (ppc_elf_final_write_processing): Likewise. (ppc_elf_vxworks_final_write_processing): Likewise. * elf32-sparc.c (sparc_final_write_processing): Likewise. (elf32_sparc_final_write_processing): Likewise. (elf32_sparc_vxworks_final_write_processing): Likewise. * elf32-v850.c (v850_elf_final_write_processing): Likewise. * elf32-xc16x.c (elf32_xc16x_final_write_processing): Likewise. * elf32-xtensa.c (elf_xtensa_final_write_processing): Likewise. * elf64-ia64-vms.c (elf64_vms_final_write_processing): Likewise. * elfnn-ia64.c (elfNN_ia64_final_write_processing): Likewise. * elfxx-mips.c (_bfd_mips_final_write_processing): Likewise. (_bfd_mips_elf_final_write_processing): Likewise. gas/ * config/obj-elf.c (obj_elf_section, obj_elf_type): Set has_gnu_osabi. * testsuite/gas/elf/section12a.d: Update xfails. * testsuite/gas/elf/section12b.d: Likewise.
2019-07-24 08:13:30 +08:00
2019-07-24 Alan Modra <amodra@gmail.com>
* config/obj-elf.c (obj_elf_section, obj_elf_type): Set has_gnu_osabi.
* testsuite/gas/elf/section12a.d: Update xfails.
* testsuite/gas/elf/section12b.d: Likewise.
Define ELF_OSABI for visium and update expected results for gas mbind tests. bfd/ * elf32-visium.c (visium_elf_post_process_headers): Don't set EI_OSABI header byte here. (ELF_OSABI): Define. gas/ * testsuite/gas/elf/section12a.d: xfail visium and cloudabi. * testsuite/gas/elf/section12b.d: Likewise. * testsuite/gas/elf/section13.d: Likewise.
2019-07-24 09:21:56 +08:00
2019-07-24 Alan Modra <amodra@gmail.com>
* testsuite/gas/elf/section12a.d: xfail visium and cloudabi.
* testsuite/gas/elf/section12b.d: Likewise.
* testsuite/gas/elf/section13.d: Likewise.
[AArch64] Add support for GMID_EL1 register for +memtag We're missing support for the GMID_EL1 system register from the Memory Tagging Extension in binutils. This is specified at: https://developer.arm.com/docs/ddi0595/latest/aarch64-system-registers/gmid_el1 This simple patch adds the support for this read-only register. Tested make check on gas.
2019-07-23 22:54:54 +08:00
2019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* testsuite/gas/aarch64/sysreg-4.s: Test gmid_el1 read.
* testsuite/gas/aarch64/sysreg-4.d: Update expected output.
* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
SHF_GNU_MBIND requires ELFOSABI_GNU When SHF_GNU_MBIND was added in the SHF_LOOS to SHF_HIOS range, it should have required ELFOSABI_GNU since these flags are already in use by other OSes. HPUX SHF_HP_TLS in fact has the same value. That means no place in binutils should test SHF_GNU_MBIND without first checking OSABI, and SHF_GNU_MBIND should not be set without also setting OSABI. At least, that's the ideal, but the patch accepts SHF_GNU_MBIND on ELFOSABI_NONE object files since gas didn't always set OSABI. However, to reinforce the fact that SHF_GNU_MBIND isn't proper without a non-zero OSABI, readelf will display the flag as LOOS+0 if OSABI isn't set. The clash with SHF_HP_TLS means that hppa64-linux either has that flag on .tbss sections or supports GNU_MBIND, not both. (hppa64-linux users, if there are any, may have noticed that GNU ld since 2017 mysteriously aligned their .tbss sections to a 4k boundary. That was one consequence of SHF_HP_TLS being blindly interpreted as SHF_GNU_MBIND.) Since it seems that binutils, gdb, gcc, glibc, and the linux kernel don't care about SHF_HP_TLS I took that flag out of .tbss for hppa64-linux. bfd/ * elf-bfd.h (enum elf_gnu_osabi): Add elf_gnu_osabi_mbind. * elf.c (_bfd_elf_make_section_from_shdr): Set elf_gnu_osabi_mbind. (get_program_header_size): Formatting. Only test SH_GNU_MBIND when elf_gnu_osabi_mbind is set. (_bfd_elf_map_sections_to_segments): Likewise. (_bfd_elf_init_private_section_data): Likewise. (_bfd_elf_final_write_processing): Update comment. * elf64-hppa.c (elf64_hppa_special_sections): Move .tbss entry. (elf_backend_special_sections): Define without .tbss for linux. binutils/ * readelf.c (get_parisc_segment_type): Split off hpux entries.. (get_ia64_segment_type): ..and these.. (get_hpux_segment_type): ..to here. (get_segment_type): Condition GNU_MBIND on osabi. Use get_hpux_segment_type. (get_symbol_binding): Do not print UNIQUE for ELFOSABI_NONE. (get_symbol_type): Do not print IFUNC for ELFOSABI_NONE. gas/ * config/obj-elf.c (obj_elf_change_section): Don't emit a fatal error for non-SHF_ALLOC SHF_GNU_MBIND here. (obj_elf_parse_section_letters): Return SHF_GNU_MBIND in new gnu_attr param. (obj_elf_section): Adjust obj_elf_parse_section_letters call. Formatting. Set SHF_GNU_MBIND and elf_osabi from gnu_attr. Emit normal error for non-SHF_ALLOC SHF_GNU_MBIND and wrong osabi. (obj_elf_type): Set elf_osabi for ifunc. * testsuite/gas/elf/section12a.d: xfail msp430 and hpux. * testsuite/gas/elf/section12b.d: Likewise. * testsuite/gas/elf/section13.d: Likewise. * testsuite/gas/elf/section13.l: Adjust expected error. ld/ * emultempl/elf32.em (gld${EMULATION_NAME}_place_orphan): Condition SHF_GNU_MBIND on osabi. Set output elf_gnu_osabi_mbind.
2019-07-23 16:24:42 +08:00
2019-07-23 Alan Modra <amodra@gmail.com>
* config/obj-elf.c (obj_elf_change_section): Don't emit a fatal
error for non-SHF_ALLOC SHF_GNU_MBIND here.
(obj_elf_parse_section_letters): Return SHF_GNU_MBIND in new
gnu_attr param.
(obj_elf_section): Adjust obj_elf_parse_section_letters call.
Formatting. Set SHF_GNU_MBIND and elf_osabi from gnu_attr.
Emit normal error for non-SHF_ALLOC SHF_GNU_MBIND and wrong osabi.
(obj_elf_type): Set elf_osabi for ifunc.
* testsuite/gas/elf/section12a.d: xfail msp430 and hpux.
* testsuite/gas/elf/section12b.d: Likewise.
* testsuite/gas/elf/section13.d: Likewise.
* testsuite/gas/elf/section13.l: Adjust expected error.
gas "mbind sections" test Doesn't fail on rx-elf * testsuite/gas/elf/section12a.d: Don't skip for rx.
2019-07-23 16:13:28 +08:00
2019-07-23 Alan Modra <amodra@gmail.com>
* testsuite/gas/elf/section12a.d: Don't skip for rx.
This patch addresses the change in the June Armv8.1-M Mainline specification, that marks certain MVE instructions as no longer UNPREDICTABLE when a source operand is the same as a destination operand for a 32-bit element size. The instructions that this change apply to are: VQDMLADH, VQRDMLADH, VQDMLSDH, VQRDMLSDH The updated documentation is here: https://static.docs.arm.com/ddi0553/bh/DDI0553B_h_armv8m_arm.pdf Fixed this by removing the check for this warning from GAS as well as opcodes. Added testcases to test that the warning is not generated for the instructions that have a 32-bit element size and the same source and destination operand. Also fixed tests that would previously check for this warning. gas * config/tc-arm.c (do_mve_vqdmladh): Remove check for UNPREDICTABLE. * testsuite/gas/arm/mve-vqdmladh-bad.l: Remove tests. * testsuite/gas/arm/mve-vqdmladh-bad.s: Remove tests. * testsuite/gas/arm/mve-vqdmladh.d: New tests. * testsuite/gas/arm/mve-vqdmladh.s: New tests. * testsuite/gas/arm/mve-vqdmlsdh-bad.l: Remove tests. * testsuite/gas/arm/mve-vqdmlsdh-bad.s: Remove tests. * testsuite/gas/arm/mve-vqdmlsdh.d: New tests. * testsuite/gas/arm/mve-vqdmlsdh.s: New tests. opcodes * arm-dis.c (is_mve_unpredictable): Stop marking some MVE instructions as UNPREDICTABLE.
2019-07-22 20:18:27 +08:00
2019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
* config/tc-arm.c (do_mve_vqdmladh): Remove check for UNPREDICTABLE.
* testsuite/gas/arm/mve-vqdmladh-bad.l: Remove tests.
* testsuite/gas/arm/mve-vqdmladh-bad.s: Remove tests.
* testsuite/gas/arm/mve-vqdmladh.d: New tests.
* testsuite/gas/arm/mve-vqdmladh.s: New tests.
* testsuite/gas/arm/mve-vqdmlsdh-bad.l: Remove tests.
* testsuite/gas/arm/mve-vqdmlsdh-bad.s: Remove tests.
* testsuite/gas/arm/mve-vqdmlsdh.d: New tests.
* testsuite/gas/arm/mve-vqdmlsdh.s: New tests.
x86: Pass -O0 to assembler in noextreg.d * testsuite/gas/i386/noextreg.d: Pass -O0 to assembler.
2019-07-20 02:07:59 +08:00
2019-07-19 H.J. Lu <hongjiu.lu@intel.com>
* testsuite/gas/i386/noextreg.d: Pass -O0 to assembler.
cpu,opcodes,gas: use %r0 and %r6 instead of %a and %ctf in eBPF disassembler This patch changes the eBPF CPU description to prefer the register names %r0 and %r6 instead of %a and %ctx when disassembling. This matches better with the current practice, vs. cBPF. It also updates the GAS tests in order to reflect this change. Tested in a x86_64 host. cpu/ChangeLog: 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf.cpu (h-gpr): when disassembling, use %r0 and %r6 instead of %a and %ctx. opcodes/ChangeLog: 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-desc.c: Regenerated. gas/ChangeLog: 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/bpf/alu.d: Use %r6 instead of %ctx. * testsuite/gas/bpf/lddw-be.d: Likewise. * testsuite/gas/bpf/lddw.d: Likewise. * testsuite/gas/bpf/alu-be.d: Likewise. * testsuite/gas/bpf/alu32.d: Likewise.
2019-07-19 21:35:43 +08:00
2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/bpf/alu.d: Use %r6 instead of %ctx.
* testsuite/gas/bpf/lddw-be.d: Likewise.
* testsuite/gas/bpf/lddw.d: Likewise.
* testsuite/gas/bpf/alu-be.d: Likewise.
* testsuite/gas/bpf/alu32.d: Likewise.
gas: make .lcomm to accept an optional aligmnet in eBPF targets Tested in a x86_64 host. gas/ChangeLog: 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.c (pe_lcomm_internal): Adapted from tc-i386.c. (pe_lcomm): Likewise. (md_pseudo_table): Use pe_lcomm to implement .lcomm.
2019-07-19 21:35:02 +08:00
2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-bpf.c (pe_lcomm_internal): Adapted from tc-i386.c.
(pe_lcomm): Likewise.
(md_pseudo_table): Use pe_lcomm to implement .lcomm.
[AArch64] Rename +bitperm to +sve2-bitperm After some discussion, we've decided to rename the +bitperm feature flag to +sve2-bitperm, so that it's consistent with the other SVE2 feature flags. The associated internal macros already used "SVE2_BITPERM", so only the feature flag itself needs to change. 2019-07-19 Richard Sandiford <richard.sandiford@arm.com> gas/ * doc/c-aarch64.texi: Remame the +bitperm extension to +sve2-bitperm. * config/tc-aarch64.c (aarch64_features): Likewise. * testsuite/gas/aarch64/illegal-sve2-aes.d: Update accordingly. * testsuite/gas/aarch64/illegal-sve2-sha3.d: Likewise. * testsuite/gas/aarch64/illegal-sve2-sm4.d: Likewise. * testsuite/gas/aarch64/illegal-sve2.d: Likewise. * testsuite/gas/aarch64/sve2.d: Likewise.
2019-07-19 19:18:02 +08:00
2019-07-19 Richard Sandiford <richard.sandiford@arm.com>
* doc/c-aarch64.texi: Remame the +bitperm extension to +sve2-bitperm.
* config/tc-aarch64.c (aarch64_features): Likewise.
* testsuite/gas/aarch64/illegal-sve2-aes.d: Update accordingly.
* testsuite/gas/aarch64/illegal-sve2-sha3.d: Likewise.
* testsuite/gas/aarch64/illegal-sve2-sm4.d: Likewise.
* testsuite/gas/aarch64/illegal-sve2.d: Likewise.
* testsuite/gas/aarch64/sve2.d: Likewise.
[PowerPC64] pc-relative TLS relocations This patch supports using pcrel instructions in TLS code sequences. A number of new relocations are needed, gas operand modifiers to generate those relocations, and new TLS optimisation. For optimisation it turns out that the new pcrel GD and LD sequences can be distinguished from the non-pcrel GD and LD sequences by there being different relocations on the new sequence. The final "add ra,rb,13" on IE sequences similarly needs a new relocation, or as I chose, a modification of R_PPC64_TLS. On pcrel IE code, the R_PPC64_TLS points one byte into the "add" instruction rather than being on the instruction boundary. GD: pla 3,z@got@tlsgd@pcrel # R_PPC64_GOT_TLSGD34 bl __tls_get_addr@notoc(z@tlsgd) # R_PPC64_TLSGD and R_PPC64_REL24_NOTOC edited to IE pld 3,z@got@tprel@pcrel add 3,3,13 edited to LE paddi 3,13,z@tprel nop LD: pla 3,z@got@tlsld@pcrel # R_PPC64_GOT_TLSLD34 bl __tls_get_addr@notoc(z@tlsld) # R_PPC64_TLSLD and R_PPC64_REL24_NOTOC .. paddi 9,3,z2@dtprel pld 10,z3@got@dtprel@pcrel add 10,10,3 edited to LE paddi 3,13,0x1000 nop IE: pld 9,z@got@tprel@pcrel # R_PPC64_GOT_TPREL34 add 3,9,z@tls@pcrel # R_PPC64_TLS at insn+1 ldx 4,9,z@tls@pcrel lwax 5,9,z@tls@pcrel stdx 5,9,z@tls@pcrel edited to LE paddi 9,13,z@tprel nop ld 4,0(9) lwa 5,0(9) std 5,0(9) LE: paddi 10,13,z@tprel include/ * elf/ppc64.h (R_PPC64_TPREL34, R_PPC64_DTPREL34), (R_PPC64_GOT_TLSGD34, R_PPC64_GOT_TLSLD34), (R_PPC64_GOT_TPREL34, R_PPC64_GOT_DTPREL34): Define. (IS_PPC64_TLS_RELOC): Include new tls relocs. bfd/ * reloc.c (BFD_RELOC_PPC64_TPREL34, BFD_RELOC_PPC64_DTPREL34), (BFD_RELOC_PPC64_GOT_TLSGD34, BFD_RELOC_PPC64_GOT_TLSLD34), (BFD_RELOC_PPC64_GOT_TPREL34, BFD_RELOC_PPC64_GOT_DTPREL34), (BFD_RELOC_PPC64_TLS_PCREL): New pcrel tls relocs. * elf64-ppc.c (ppc64_elf_howto_raw): Add howtos for pcrel tls relocs. (ppc64_elf_reloc_type_lookup): Translate pcrel tls relocs. (must_be_dyn_reloc, dec_dynrel_count): Add R_PPC64_TPREL64. (ppc64_elf_check_relocs): Support pcrel tls relocs. (ppc64_elf_tls_optimize, ppc64_elf_relocate_section): Likewise. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. gas/ * config/tc-ppc.c (ppc_elf_suffix): Map "tls@pcrel", "got@tlsgd@pcrel", "got@tlsld@pcrel", "got@tprel@pcrel", and "got@dtprel@pcrel". (fixup_size, md_assemble): Handle pcrel tls relocs. (ppc_force_relocation, ppc_fix_adjustable): Likewise. (md_apply_fix, tc_gen_reloc): Likewise. ld/ * testsuite/ld-powerpc/tlsgd.d, * testsuite/ld-powerpc/tlsgd.s, * testsuite/ld-powerpc/tlsie.d, * testsuite/ld-powerpc/tlsie.s, * testsuite/ld-powerpc/tlsld.d, * testsuite/ld-powerpc/tlsld.s: New tests. * testsuite/ld-powerpc/powerpc.exp: Run them.
2019-07-19 14:06:58 +08:00
2019-07-19 Alan Modra <amodra@gmail.com>
* config/tc-ppc.c (ppc_elf_suffix): Map "tls@pcrel", "got@tlsgd@pcrel",
"got@tlsld@pcrel", "got@tprel@pcrel", and "got@dtprel@pcrel".
(fixup_size, md_assemble): Handle pcrel tls relocs.
(ppc_force_relocation, ppc_fix_adjustable): Likewise.
(md_apply_fix, tc_gen_reloc): Likewise.
gas: .lcomm gets an alignment argument in eBPF gas/ChangeLog: 2019-07-17 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.c: Make .lcomm to get a third argument with the alignment.
2019-07-18 05:18:41 +08:00
2019-07-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-bpf.c: Make .lcomm to get a third argument with the
alignment.
gas: support .half, .word and .dword directives in eBPF This little patch adds support to the eBPF port of GAS for a few data directives. The names for the directives have been chosen to be coherent with the suffixes used in eBPF instructions: b, h, w and dw for 8, 16, 32 and 64-bit values respectively. Documentation and tests included. Tested in a x86_64 host. gas/ChangeLog: 2019-07-17 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.c (md_pseudo_table): .half, .word and .dword. * testsuite/gas/bpf/data.s: New file. * testsuite/gas/bpf/data.d: Likewise. * testsuite/gas/bpf/data-be.d: Likewise. * testsuite/gas/bpf/bpf.exp: Run data and data-be. * doc/c-bpf.texi (BPF Directives): New section.
2019-07-18 04:57:23 +08:00
2019-07-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-bpf.c (md_pseudo_table): .half, .word and .dword.
gas: .lcomm gets an alignment argument in eBPF gas/ChangeLog: 2019-07-17 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.c: Make .lcomm to get a third argument with the alignment.
2019-07-18 05:18:41 +08:00
gas: support .half, .word and .dword directives in eBPF This little patch adds support to the eBPF port of GAS for a few data directives. The names for the directives have been chosen to be coherent with the suffixes used in eBPF instructions: b, h, w and dw for 8, 16, 32 and 64-bit values respectively. Documentation and tests included. Tested in a x86_64 host. gas/ChangeLog: 2019-07-17 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.c (md_pseudo_table): .half, .word and .dword. * testsuite/gas/bpf/data.s: New file. * testsuite/gas/bpf/data.d: Likewise. * testsuite/gas/bpf/data-be.d: Likewise. * testsuite/gas/bpf/bpf.exp: Run data and data-be. * doc/c-bpf.texi (BPF Directives): New section.
2019-07-18 04:57:23 +08:00
* testsuite/gas/bpf/data.s: New file.
* testsuite/gas/bpf/data.d: Likewise.
* testsuite/gas/bpf/data-be.d: Likewise.
* testsuite/gas/bpf/bpf.exp: Run data and data-be.
* doc/c-bpf.texi (BPF Directives): New section.
x86: replace "anymem" checks where possible Once operand parsing has completed, the simpler check of Operand_Mem can be used in places where i.types[] got passed to operand_type_check(). Note that this has shown a couple of omissions of adjusting i.flags[] when playing with i.op[] / i.types[] / i.tm.operand_types[]. Not all of them get added here, just all of the ones needed in process_operands().
2019-07-17 15:16:31 +08:00
2019-07-17 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (check_hle, md_assemble, check_VecOperands,
match_template, check_string, build_modrm_byte): Replace
operand_type_check(..., anymem) by Operand_Mem ones.
(process_operands): Also copy i.flags[] when copying other
operand properties.
x86: make RegMem an opcode modifier ... instead of an operand type bit: It's an insn property, not an operand one. There's just one actual change to be made to the templates: Most are now required to have the (unswapped) destination go into ModR/M.rm, so VMOVD template needs its opcode adjusted accordingly and its operands swapped. {,V}MOVS{S,D}, otoh, are left alone in this regard, as otherwise generated code would differ from what we've been producing so far (which I don't think is wanted). Take the opportunity and add a missing IgnoreSize to pextrb (leading to an error in 16-bit mode), and take the liberty to once again drop stray IgnoreSize attributes from lines changed and neighboring related ones.
2019-07-16 15:31:36 +08:00
2019-07-16 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (match_template): Adjust regmem reference.
Adjust comment and update regmem when swapping operands.
(build_modrm_byte): Drop clearing of regmem and stale part of
comment. Correct comment. Adjust regmem reference.
x86: fold SReg{2,3} They're the only exception to there generally being no mix of register kinds possible in an insn operand template, and there being two bits per operand for their representation is also quite wasteful, considering the low number of uses. Fold both bits and deal with the little bit of fallout. Also take the liberty and drop dead code trying to set REX_B: No segment register has RegRex set on it. Additionally I was quite surprised that PUSH/POP with the permitted segment registers is not covered by the test cases. Add the missing pieces.
2019-07-16 15:30:29 +08:00
2019-07-16 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (type_names): Replace SReg entries.
(pi, check_byte_reg, build_modrm_byte, i386_att_operand,
parse_real_register): Switch to using sreg field.
(process_operands): Likewise. Extend handling of PUSH/POP of
segment registers. Drop dead setting of REX_B.
* config/tc-i386-intel.c (i386_intel_simplify_register,
i386_intel_operand): Switch to using sreg field.
* testsuite/gas/i386/x86-64-opcode.s: Add PUSH/POP of %fs/%gs.
* testsuite/gas/i386/x86-64-opcode.d: Adjust expectations.
* testsuite/gas/i386/ilp32/x86-64-opcode.d: Use parent dir
expectations.
cpu,opcodes,gas: fix explicit arguments to eBPF ldabs instructions This patch fixes the eBPF CPU description in order to reflect the right explicit arguments passed to the ldabs{b,h,w,dw} instructions, updates the corresponding GAS tests, and updates the BPF section of the GAS manual. cpu/ChangeLog: 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf.cpu (dlabs): New pmacro. (dlind): Likewise. opcodes/ChangeLog: 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-desc.c: Regenerate. * bpf-opc.c: Likewise. * bpf-opc.h: Likewise. gas/ChangeLog: 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/bpf/mem.s: ldabs instructions do not take a `src' register as an argument. * testsuite/gas/bpf/mem.d: Updated accordingly. * testsuite/gas/bpf/mem-be.d: Likewise. * doc/c-bpf.texi (BPF Opcodes): Update to reflect the correct explicit arguments to ldabs and ldind instructions.
2019-07-15 22:00:28 +08:00
2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/bpf/mem.s: ldabs instructions do not take a `src'
register as an argument.
* testsuite/gas/bpf/mem.d: Updated accordingly.
* testsuite/gas/bpf/mem-be.d: Likewise.
* doc/c-bpf.texi (BPF Opcodes): Update to reflect the correct
explicit arguments to ldabs and ldind instructions.
cpu,opcodes,gas: fix arguments to ldabs and ldind eBPF instructions The eBPF non-generic load instructions ldind{b,h,w,dw} and ldabs{b,h,w,dw} do not take an explicit destination register as an argument. Instead, they put the loaded value in %r0, implicitly. This patch fixes the CPU BPF description to not expect a 'dst' argument in these arguments, regenerates the corresponding files in opcodes, and updates the impacted GAS tests. Tested in a x86-64 host. cpu/ChangeLog: 2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf.cpu (dlsi): ldabs and ldind instructions do not take an explicit 'dst' argument. opcodes/ChangeLog: 2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-desc.c: Regenerate. * bpf-opc.c: Likewise. gas/ChangeLog: 2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/bpf/mem.s: Do not use explicit arguments for ldabs and ldind instructions. * testsuite/gas/bpf/mem.d: Updated accordingly. * testsuite/gas/bpf/mem-be.d: Likewise.
2019-07-14 20:45:31 +08:00
2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/bpf/mem.s: Do not use explicit arguments for
ldabs and ldind instructions.
* testsuite/gas/bpf/mem.d: Updated accordingly.
* testsuite/gas/bpf/mem-be.d: Likewise.
Re: gas/ELF: don't accumulate .type settings git commit f2d4ba38f5 caused many failures for mips-sgi-irix targets, and added a new test that failed for aarch64, nds32, and rl78. The mips failures are due to BSF_OBJECT being set in many cases for symbols by the mips .global/.globl directive. This patch removes that code and instead sets BSF_OBJECT in a target frob_symbol function, also moving the mips hacks in elf_frob_symbol to the new function. Note that common symbols are handled fine in elf.c:swap_out_syms without needing to set BSF_OBJECT, so that old code can disappear. * config/obj-elf.c (elf_frob_symbol): Remove mips hacks. * config/tc-mips.h (tc_frob_symbol): Define. (mips_frob_symbol): Declare. * config/tc-mips.c (s_mips_globl): Don't set BSF_OBJECT for irix. (mips_frob_symbol): Fudge symbols for irix here. * testsuite/gas/elf/type-2.e: Allow random target symbols.
2019-07-09 10:57:55 +08:00
2019-07-09 Alan Modra <amodra@gmail.com>
* config/obj-elf.c (elf_frob_symbol): Remove mips hacks.
* config/tc-mips.h (tc_frob_symbol): Define.
(mips_frob_symbol): Declare.
* config/tc-mips.c (s_mips_globl): Don't set BSF_OBJECT for irix.
(mips_frob_symbol): Fudge symbols for irix here.
* testsuite/gas/elf/type-2.e: Allow random target symbols.
Kito's 5-part patch set to improve .insn support. From Kito Cheng <kito.cheng@sifive.com> gas/ChangeLog * doc/c-riscv.texi (Instruction Formats): Add r4 type. * testsuite/gas/riscv/insn.d: Add testcase for r4 type. * testsuite/gas/riscv/insn.s: Ditto. * doc/c-riscv.texi (Instruction Formats): Add b and j type. * testsuite/gas/riscv/insn.d: Add test case for b and j type. * testsuite/gas/riscv/insn.s: Ditto. * testsuite/gas/riscv/insn.s: Correct instruction type for load and store. * testsuite/gas/riscv/insn.d: Using regular expression to match address. * doc/c-riscv.texi (Instruction Formats): Fix encoding table for SB type and fix typo. opcode/ChangeLog * riscv-opc.c (riscv_insn_types): Add r4 type. * riscv-opc.c (riscv_insn_types): Add b and j type. * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect format for sb type and correct s type.
2019-07-05 15:19:11 +08:00
2019-07-05 Kito Cheng <kito.cheng@sifive.com>
* doc/c-riscv.texi (Instruction Formats): Add r4 type.
* testsuite/gas/riscv/insn.d: Add testcase for r4 type.
* testsuite/gas/riscv/insn.s: Ditto.
* doc/c-riscv.texi (Instruction Formats): Add b and j type.
* testsuite/gas/riscv/insn.d: Add test case for b and j type.
* testsuite/gas/riscv/insn.s: Ditto.
* testsuite/gas/riscv/insn.s: Correct instruction type for load
and store.
* testsuite/gas/riscv/insn.d: Using regular expression to match
address.
* doc/c-riscv.texi (Instruction Formats): Fix encoding table for SB
type and fix typo.
x86: correct "-Q" option handling For another patch I wanted to use a sufficiently benign option (simply to be able to specify one, which certain test case invocations require), and I stumbled across -Q in the --help output. Before realizing that this is x86-specific anyway, I've tried and and ran into a mysterious testsuite failure, until I further realized that other than the help text suggests the option requires an argument. Correct the help text, and make the implementation actually match what the comment there has been describing (and what the help text now says).
2019-07-04 16:36:41 +08:00
2019-07-04 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (md_parse_option): Don't blindly accept all
-Q options.
(md_show_usage): Correctly name the ignored -Q option flavors.
gas/ELF: don't accumulate .type settings Recently a patch was submitted for a Xen Project test harness binary to override the compiler specified @object to @func (see [1]). In a reply I suggested we shouldn't make ourselves dependent on currently unspecified behavior of gas here: It accumulates all requests, and then bfd/elf.c:swap_out_syms(), in an apparently ad hoc manner, prioritizes certain flags over others. Make the behavior predictable: Generally the last .type is what counts. Exceptions are directives which set multiple bits (TLS, IFUNC, and UNIQUE): Subsequent directives requesting just the more generic bit (i.e. FUNC following IFUNC) won't clear the more specific one. Warn about incompatible changes, except from/to STT_NOTYPE. Also add a new target hook, which hppa wants to use right away afaict. In the course of adding the warning I ran into two ld testsuite failures. I can only assume that it was a copy-and-paste mistake that lead to the same symbol having its type set twice. [1] https://lists.xenproject.org/archives/html/xen-devel/2019-05/msg01980.html
2019-07-04 16:35:47 +08:00
2019-07-04 Jan Beulich <jbeulich@suse.com>
* config/obj-elf.c (obj_elf_type): Check for conflicts between
old and new types.
* config/tc-hppa.h (md_elf_symbol_type_change): New.
* doc/as.texi: Mention warning behavior for the ELF flavor of
.type.
* testsuite/gas/elf/type-2.e, testsuite/gas/elf/type-2.l,
testsuite/gas/elf/type-2.s: New.
* testsuite/gas/elf/elf.exp: Run new test.
Fix assembler tests to work with toolchains that have been configured with --enable-generate-build-notes.
2019-07-03 22:26:32 +08:00
2019-07-03 Nick Clifton <nickc@redhat.com>
* testsuite/gas/aarch64/codealign.d: Update to work with a
toolchain configured to generate build notes.
* testsuite/gas/aarch64/codealign_1.d: Likewise.
* testsuite/gas/aarch64/dwarf.d: Likewise.
* testsuite/gas/aarch64/mapmisc.d: Likewise.
* testsuite/gas/aarch64/mapping.d: Likewise.
* testsuite/gas/aarch64/mapping2.d: Likewise.
* testsuite/gas/aarch64/mapping3.d: Likewise.
* testsuite/gas/aarch64/mapping4.d: Likewise.
* testsuite/gas/aarch64/mapping_5.d: Likewise.
* testsuite/gas/aarch64/mapping_6.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_1.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_10.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_11.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_12.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_13.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_14.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_15.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_16.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_17.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_18.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_19.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_2.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_20.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_21.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_22.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_23.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_24.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_25.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_26.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_27.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_3.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_4.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_5.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_6.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_7.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_8.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_9.d: Likewise.
* testsuite/gas/aarch64/symbol-variant_pcs-1.d: Likewise.
* testsuite/gas/aarch64/symbol-variant_pcs-2.d: Likewise.
* testsuite/gas/aarch64/symbol-variant_pcs-3.d: Likewise.
* testsuite/gas/all/assign.d: Likewise.
* testsuite/gas/all/none.d: Likewise.
* testsuite/gas/all/weakref1.d: Likewise.
* testsuite/gas/arm/got_prel.d: Likewise.
* testsuite/gas/arm/local_function.d: Likewise.
* testsuite/gas/arm/mapdir.d: Likewise.
* testsuite/gas/arm/mapmisc.d: Likewise.
* testsuite/gas/arm/mapping2.d: Likewise.
* testsuite/gas/arm/mapping3.d: Likewise.
* testsuite/gas/arm/mapping4.d: Likewise.
* testsuite/gas/arm/mapsecs.d: Likewise.
* testsuite/gas/arm/mapshort-eabi.d: Likewise.
* testsuite/gas/arm/thumbrel.d: Likewise.
* testsuite/gas/arm/unwind.d: Likewise.
* testsuite/gas/cfi/cfi-label.d: Likewise.
* testsuite/gas/elf/elf.exp: Likewise.
* testsuite/gas/i386/bss.d: Likewise.
* testsuite/gas/i386/ifunc-3.d: Likewise.
* testsuite/gas/i386/ilp32/mixed-mode-reloc64.d: Likewise.
* testsuite/gas/i386/ilp32/quad.d: Likewise.
* testsuite/gas/i386/ilp32/reloc64.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-size-1.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-size-3.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-size-5.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-unwind.d: Likewise.
* testsuite/gas/i386/mixed-mode-reloc32.d: Likewise.
* testsuite/gas/i386/mixed-mode-reloc64.d: Likewise.
* testsuite/gas/i386/nop-6.d: Likewise.
* testsuite/gas/i386/property-1.d: Likewise.
* testsuite/gas/i386/property-2.d: Likewise.
* testsuite/gas/i386/relax.d: Likewise.
* testsuite/gas/i386/reloc64.d: Likewise.
* testsuite/gas/i386/size-1.d: Likewise.
* testsuite/gas/i386/size-3.d: Likewise.
* testsuite/gas/i386/x86-64-nop-6.d: Likewise.
* testsuite/gas/i386/x86-64-property-1.d: Likewise.
* testsuite/gas/i386/x86-64-property-2.d: Likewise.
* testsuite/gas/i386/x86-64-size-1.d: Likewise.
* testsuite/gas/i386/x86-64-size-3.d: Likewise.
* testsuite/gas/i386/x86-64-size-5.d: Likewise.
* testsuite/gas/i386/x86-64-unwind.d: Likewise.
* testsuite/gas/macros/irp.d: Likewise.
* testsuite/gas/macros/repeat.d: Likewise.
* testsuite/gas/macros/rept.d: Likewise.
* testsuite/gas/macros/test2.d: Likewise.
* testsuite/gas/macros/test3.d: Likewise.
* testsuite/gas/macros/vararg.d: Likewise.
* testsuite/gas/ppc/astest2.d: Likewise.
* testsuite/gas/ppc/astest2_64.d: Likewise.
* testsuite/gas/ppc/astest64.d: Likewise.
* testsuite/gas/ppc/power4.d: Likewise.
* testsuite/gas/ppc/test1elf64.d: Likewise.
This patch fixes a bug in the AArch64 assembler where an incorrect structural load/store by element instruction would generate the wrong error message. For example, when provided with the (incorrect) instruction st4 {v0.16b-v3.16b}[4],[x0] currently assembler provides the following error message "Error: comma expected between operands at operand 2 -- `st4 {v0.16b-v3.16b}[4],[x0]'". This was due to the assembler consuming the {v0.16b-v3.16b} as the first operand leaving [4],[x0] as what it believed to be the second operand. The actual error is that the first operand should be of element type and not vector type (as provided). The new diagnostic for this error is "Error: expected element type rather than vector type at operand 1 -- `st4 {v0.16b-v3.16b}[4],[x0]'. Added testcases to check for the correct diagnostic message as well as checking that variations of the structural load/store by element instruction also generate the error when they have the same problem. * config/tc-aarch64.c (parse_operands): Add error check. * testsuite/gas/aarch64/diagnostic.l: New test. * testsuite/gas/aarch64/diagnostic.s: New test. * testsuite/gas/aarch64/illegal.l: New tests. * testsuite/gas/aarch64/illegal.s: New tests.
2019-07-02 21:09:52 +08:00
2019-07-02 Barnaby Wilks <barnaby.wilks@arm.com>
* config/tc-aarch64.c (parse_operands): Add error check.
* testsuite/gas/aarch64/diagnostic.l: New test.
* testsuite/gas/aarch64/diagnostic.s: New test.
* testsuite/gas/aarch64/illegal.l: New tests.
* testsuite/gas/aarch64/illegal.s: New tests.
[AArch64] Allow MOVPRFX to be used with FMOV The entry for the FMOV alias of FCPY was missing C_SCAN_MOVPRFX. (The entry for FCPY itself was OK.) This was the only /m-predicated instruction I could see that was missing the flag. 2019-07-02 Richard Sandiford <richard.sandiford@arm.com> opcodes/ * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the SVE FMOV alias of FCPY. gas/ * testsuite/gas/aarch64/sve-movprfx_27.s, * testsuite/gas/aarch64/sve-movprfx_27.d: New test.
2019-07-02 17:52:16 +08:00
2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
* testsuite/gas/aarch64/sve-movprfx_27.s,
* testsuite/gas/aarch64/sve-movprfx_27.d: New test.
[AArch64] Add missing C_MAX_ELEM flags for SVE conversions SVE FCVTZS, FCVTZU, SCVTF and UCVTF need the same treatment as FCVT: the register size used in a predicated MOVPRFX must be the wider of the destination and source sizes. Since I was adding a (supposedly) complete set of tests for converts, it seemed more consistent to add a complete set of tests for shifts as well, even though there's no bug to fix there. 2019-07-02 Richard Sandiford <richard.sandiford@arm.com> opcodes/ * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries. gas/ * testsuite/gas/aarch64/sve-movprfx_26.s: Also test FCVTZS, FCVTZU, SCVTF, UCVTF, LSR and ASR. * testsuite/gas/aarch64/sve-movprfx_26.d: Update accordingly. * testsuite/gas/aarch64/sve-movprfx_26.l: Likewise.
2019-07-02 17:51:09 +08:00
2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
* testsuite/gas/aarch64/sve-movprfx_26.s: Also test FCVTZS, FCVTZU,
SCVTF, UCVTF, LSR and ASR.
* testsuite/gas/aarch64/sve-movprfx_26.d: Update accordingly.
* testsuite/gas/aarch64/sve-movprfx_26.l: Likewise.
[AArch64] Fix bogus MOVPRFX warning for GPR form of CPY One of the MOVPRFX tests has: output register of preceding `movprfx' used as input at operand 3 -- `cpy z1.d,p1/m,x1' But X1 and Z1 are not the same register, so the instruction is actually OK. 2019-07-02 Richard Sandiford <richard.sandiford@arm.com> opcodes/ * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the registers in an instruction prefixed by MOVPRFX. gas/ * testsuite/gas/aarch64/sve-movprfx_25.s: Allow CPY Z1.D.P1/M,X1 to be prefixed by MOVPRFX. * testsuite/gas/aarch64/sve-movprfx_25.d: Update accordingly. * testsuite/gas/aarch64/sve-movprfx_25.l: Likewise.
2019-07-02 17:51:05 +08:00
2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
* testsuite/gas/aarch64/sve-movprfx_25.s: Allow CPY Z1.D.P1/M,X1
to be prefixed by MOVPRFX.
* testsuite/gas/aarch64/sve-movprfx_25.d: Update accordingly.
* testsuite/gas/aarch64/sve-movprfx_25.l: Likewise.
Fix bug when generating REL type relocs for assembler generated build notes. PR 24748 * write.c (create_note_reloc): Add desc2_offset parameter. Change name of offset parameter to note_offset. Only use desc2_offset when placing addend into REL reloc's address space. (maybe_generate_build_notes): Update parameters passed to create_note_reloc.
2019-07-01 23:19:14 +08:00
2019-07-01 Nick Clifton <nickc@redhat.com>
PR 24748
* write.c (create_note_reloc): Add desc2_offset parameter. Change
name of offset parameter to note_offset. Only use desc2_offset
when placing addend into REL reloc's address space.
(maybe_generate_build_notes): Update parameters passed to
create_note_reloc.
[gas][aarch64][SVE2] Fix pmull{t,b} requirement on SVE2-AES I had mistakenly given all variants of the new SVE2 instructions pmull{t,b} a dependency on the feature +sve2-aes. Only the variant specifying .Q -> .D sizes should have that restriction. This patch fixes that mistake and updates the testsuite to have extra tests (matching the given set of tests per line in aarch64-tbl.h that the rest of the SVE2 tests follow). We also add a line in the documentation of the command line to clarify how to enable `pmull{t,b}` of this larger size. This is needed because all other instructions gated under the `sve2-aes` architecture extension are marked in the instruction documentation by an `HaveSVE2AES` check while pmull{t,b} is gated under the `HaveSVE2PMULL128` check. Regtested targeting aarch64-linux. gas/ChangeLog: 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com> * testsuite/gas/aarch64/illegal-sve2-aes.d: Update tests. * testsuite/gas/aarch64/illegal-sve2.l: Update tests. * doc/c-aarch64.texi: Add special note of pmull{t,b} instructions under the sve2-aes architecture extension. * testsuite/gas/aarch64/illegal-sve2.s: Add small size pmull{t,b} instructions. * testsuite/gas/aarch64/sve2.d: Add small size pmull{t,b} disassembly. * testsuite/gas/aarch64/sve2.s: Add small size pmull{t,b} instructions. include/ChangeLog: 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_insn_class): sve_size_013 renamed to sve_size_13. opcodes/ChangeLog: 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new sve_size_13 icode to account for variant behaviour of pmull{t,b}. * aarch64-dis-2.c: Regenerate. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new sve_size_13 icode to account for variant behaviour of pmull{t,b}. * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier. (OP_SVE_VVV_Q_D): Add new qualifier. (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier. (struct aarch64_opcode): Split pmull{t,b} into those requiring AES and those not.
2019-07-01 22:17:22 +08:00
2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
* testsuite/gas/aarch64/illegal-sve2-aes.d: Update tests.
* testsuite/gas/aarch64/illegal-sve2.l: Update tests.
* doc/c-aarch64.texi: Add special note of pmull{t,b}
instructions under the sve2-aes architecture extension.
* testsuite/gas/aarch64/illegal-sve2.s: Add small size
pmull{t,b} instructions.
* testsuite/gas/aarch64/sve2.d: Add small size pmull{t,b}
disassembly.
* testsuite/gas/aarch64/sve2.s: Add small size pmull{t,b}
instructions.
Document the .value directive supported by the x86 and x86_64 assemblers. PR 24738 * doc/c-i386.texi (i386-Directives): Add a description of the Value directive.
2019-07-01 19:39:09 +08:00
2019-07-01 Nick Clifton <nickc@redhat.com>
PR 24738
* doc/c-i386.texi (i386-Directives): Add a description of the
Value directive.
Correct a typo in the description of the Align and P2align directives. PR 24737 * doc/as.texi (Align): Add missing word to description of pseudo-op. (P2align): Likewise.
2019-07-01 19:24:46 +08:00
2019-07-01 Nick Clifton <nickc@redhat.com>
PR 24737
* doc/as.texi (Align): Add missing word to description of
pseudo-op.
(P2align): Likewise.
Fix spelling error in assembler documentation.
2019-07-01 17:20:43 +08:00
2019-06-28 Nick Clifton <nickc@redhat.com>
PR 24735
* doc/as.texi (Zero): Fix spelling typo.
x86: drop Vec_Imm4 It is pretty wasteful to have a per-operand flag which is used in exactly 4 cases. It can be relatively easily replaced, and by doing so I've actually found some dead code to remove at the same time (there's no case of ImmExt set at the same time as Vec_Imm4).
2019-07-01 14:38:50 +08:00
2019-07-01 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (vec_imm4): Delete.
(VEX_check_operands): Replace Vec_Imm4 check by CpuXOP with five
operands one. Clear Imm<N> by different means.
(build_modrm_byte): Adjust comment. Remove dead code. Add and
adjust assertions.
x86: limit ImmExt abuse In quite a few cases ImmExt gets used when there's not really any immediate, but rather a degenerate ModR/M byte. ENCL{S,U} show how this case is supposed to be dealt with. Eliminate most abuses, leaving in place (for now) only ones where process_immext() is involved.
2019-07-01 14:37:40 +08:00
2019-07-01 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (output_insn): Adjust recognition of xFENCE
insns. Move PadLock special case of prefix emission to 3-byte
long base opcode handling.
(i386_index_check): Check for CpuPadLock instead of ImmExt.
x86: optimize AND/OR with twice the same register It seems to be not uncommon for people to use AND or OR in this form for just setting the status flags. TEST, which doesn't write to any register other than EFLAGS, ought to be preferred. Make the change only for -O2 and above though, at least for now.
2019-07-01 14:35:08 +08:00
2019-07-01 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (optimize_encoding): Handle AND / OR with
both operands being the same register.
* doc/c-i386.texi: Update -O2 documentation.
* testsuite/gas/i386/optimize-2.s,
testsuite/gas/i386/x86-64-optimize-3.s: Add cases of AND / OR
with both operands being the same register.
* testsuite/gas/i386/optimize-2.d,
testsuite/gas/i386/x86-64-optimize-3.d: Adjust expectations.
* testsuite/gas/i386/optimize-2b.d,
testsuite/gas/i386/x86-64-optimize-3b.d: New.
* testsuite/gas/i386/i386.exp: Run new test.
x86-64: optimize certain commutative VEX-encoded insns When they're in the 0F opcode space, swapping their source operands may allow switching from 3-byte to 2-byte VEX prefix encoding. Note that NaN behavior precludes us doing so for many packed and scalar floating point insns; such an optimization would need to be done by the compiler instead in this case, when it knows that NaN-s have undefined behavior anyway. While for explicitly specified AVX/AVX2 insns the optimization (for now at least) gets done only for -O2 and -Os, it is utilized by default in SSE2AVX mode, as there we're re-writing the programmer's specified insns anyway. Rather than introducing a new attribute flag, the change re-uses one which so far was meaningful only for EVEX-encoded insns.
2019-07-01 14:33:56 +08:00
2019-07-01 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (commutative): New.
(build_vex_prefix): Handle commutative case.
(optimize_encoding): Set commutative flag when appropriate.
* doc/c-i386.texi: Update -O2 documentation.
* testsuite/gas/i386/ilp32/x86-64-sse2avx.d: Re-use parent dir
output.
* testsuite/gas/i386/x86-64-sse2avx.s: Add tests with high
numbered source operands.
* testsuite/gas/i386/x86-64-optimize-2.d,
testsuite/gas/i386/x86-64-optimize-2b.d,
testsuite/gas/i386/x86-64-optimize-3.d,
testsuite/gas/i386/x86-64-optimize-5.d,
testsuite/gas/i386/x86-64-optimize-6.d,
testsuite/gas/i386/x86-64-sse2avx.d: Adjust expectations.
* testsuite/gas/i386/x86-64-avx-swap-2.d,
testsuite/gas/i386/x86-64-avx-swap-2.s: New.
* testsuite/gas/i386/i386.exp: Run new test.
x86: StaticRounding implies SAE This implication allows to simplify some conditionals, thus slightly improving performance. This change also paves the way for re-using StaticRounding for non-EVEX insns.
2019-07-01 14:31:50 +08:00
2019-07-01 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (is_evex_encoding): Don't check for SAE.
(check_VecOperands): Simplify static rounding / SAE checking.
x86: optimize EVEX packed integer logical instructions As long as there's no write mask as well as no broadcast, and as long as the scaled Disp8 wouldn't result in a shorter EVEX encoding, encode VPAND{D,Q}, VPANDN{D,Q}, VPOR{D,Q}, and VPXOR{D,Q} acting on only the lower 16 XMM/YMM registers using their VEX equivalents with -O1. Also take the opportunity and avoid looping twice over all operands when dealing with memory-with-displacement ones.
2019-07-01 14:31:14 +08:00
2019-07-01 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (optimize_encoding): Make j unsigned. Handle
vpand{d,q}, vpandn{d,q}, vpor{d,q}, and vpxor{d,q}. Also check/
clear broadcast. Eliminate a loop.
* doc/c-i386.texi: Update -O1 documentation.
* testsuite/gas/i386/optimize-1.s,
testsuite/gas/i386/optimize-2.s,
testsuite/gas/i386/optimize-3.s,
testsuite/gas/i386/optimize-5.s,
testsuite/gas/i386/x86-64-optimize-2.s,
testsuite/gas/i386/x86-64-optimize-3.s,
testsuite/gas/i386/x86-64-optimize-4.s,
testsuite/gas/i386/x86-64-optimize-6.s: Add vpand{d,q},
vpandn{d,q}, vpor{d,q}, and vpxor{d,q} cases.
testsuite/gas/i386/optimize-1.d,
testsuite/gas/i386/optimize-1a.d,
testsuite/gas/i386/optimize-2.d,
testsuite/gas/i386/optimize-3.d,
testsuite/gas/i386/optimize-4.d,
testsuite/gas/i386/optimize-5.d,
testsuite/gas/i386/x86-64-optimize-2.d,
testsuite/gas/i386/x86-64-optimize-2a.d,
testsuite/gas/i386/x86-64-optimize-2b.d,
testsuite/gas/i386/x86-64-optimize-3.d,
testsuite/gas/i386/x86-64-optimize-4.d,
testsuite/gas/i386/x86-64-optimize-5.d,
testsuite/gas/i386/x86-64-optimize-6.d: Adjust expectations.
x86: add missing pseudo ops for VPCLMULQDQ ISA extension While the ISA extensions doc suggests them to be made available just like the SDM does for the PCLMULQDQ ISA extension, these weren't added when supposrt for the new extension was introduced. Also make sure the 64-bit non-AVX512 test actually tests VEX encodings, not EVEX ones.
2019-07-01 14:28:58 +08:00
2019-07-01 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/avx512f_vpclmulqdq.s,
testsuite/gas/i386/avx512vl_vpclmulqdq.s,
testsuite/gas/i386/vpclmulqdq.s,
testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.s,
testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.s: Add pseudo ops.
* testsuite/gas/i386/x86-64-vpclmulqdq.s: Likewise. Don't use
high 16 [xy]mm registers.
* testsuite/gas/i386/avx512f_vpclmulqdq.d,
testsuite/gas/i386/avx512f_vpclmulqdq-intel.d,
testsuite/gas/i386/avx512vl_vpclmulqdq.d,
testsuite/gas/i386/avx512vl_vpclmulqdq-intel.d,
testsuite/gas/i386/vpclmulqdq.d,
testsuite/gas/i386/vpclmulqdq-intel.d,
testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.d,
testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-intel.d,
testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.d,
testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-intel.d,
testsuite/gas/i386/x86-64-vpclmulqdq.d,
testsuite/gas/i386/x86-64-vpclmulqdq-intel.d: Adjust
expectations.
x86: use encoding_length() also elsewhere
2019-07-01 14:25:33 +08:00
2019-07-01 Jan Beulich <jbeulich@suse.com>
* tc-i386.c (output_disp, output_imm): Use encoding_length.
x86: warn about insns exceeding the 15-byte limit Such insns will cause #UD when an attempt to execute them is made. See also http://www.sandpile.org/x86/opc_enc.htm.
2019-07-01 14:24:57 +08:00
2019-07-01 Jan Beulich <jbeulich@suse.com>
* tc-i386.c (encoding_length): New.
(output_insn): Use it.
* testsuite/gas/i386/oversized16.l,
testsuite/gas/i386/oversized16.s,
testsuite/gas/i386/oversized64.l,
testsuite/gas/i386/oversized64.s: New.
* testsuite/gas/i386/i386.exp: Run new tests.
i386: Check vector length for scatter/gather prefetch instructions Since not all vector lengths are supported by scatter/gather prefetch instructions, decode them only with supported vector lengths. gas/ PR binutils/24719 * testsuite/gas/i386/disassem.s: Add test for vgatherpf0dps with invalid vector length. * testsuite/gas/i386/x86-64-disassem.s: Likewise. * testsuite/gas/i386/disassem.d: Updated. * testsuite/gas/i386/x86-64-disassem.d: Likewise. opcodes/ PR binutils/24719 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and EVEX_LEN_0F38C7_R_6_P_2_W_1. * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and PREFIX_EVEX_0F38C6_REG_6 entries. * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and EVEX_W_0F38C7_R_6_P_2 entries. * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
2019-06-28 04:39:19 +08:00
2019-06-27 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/24719
* testsuite/gas/i386/disassem.s: Add test for vgatherpf0dps
with invalid vector length.
* testsuite/gas/i386/x86-64-disassem.s: Likewise.
* testsuite/gas/i386/disassem.d: Updated.
* testsuite/gas/i386/x86-64-disassem.d: Likewise.
This fixes a bug in the ARm assembler where an immediate operand larger than 4 bits (0xF) could be passed to the SMC (Secure Monitor Call) instruction. For example, this code is invalid: smc #0x6951 The code would previously check for and encode for up to 16 bit immediate values, however this immediate should instead be only a 4 bit value (as documented herehttps://static.docs.arm.com/ddi0406/c/DDI0406C_C_arm_architecture_reference_manual.pdf ). Fixed this by adding range checks in the relevant areas and also removing code that would encode more than the first 4 bits of the immediate (code that is now redundant, as any immediate operand larger than 0xF would error now anyway). gas * config/tc-arm.c (do_smc): Add range check for immediate operand. (do_t_smc): Add range check for immediate operand. Remove obsolete immediate encoding. (md_apply_fix): Fix range check. Remove obsolete immediate encoding. * testsuite/gas/arm/arch6zk.d: Fix test. * testsuite/gas/arm/arch6zk.s: Fix test. * testsuite/gas/arm/smc-bad.d: New test. * testsuite/gas/arm/smc-bad.l: New test. * testsuite/gas/arm/smc-bad.s: New test. * testsuite/gas/arm/thumb32.d: Fix test. * testsuite/gas/arm/thumb32.s: Fix test.
2019-06-27 21:06:02 +08:00
2019-06-27 Barnaby Wilk s<barnaby.wilks@arm.com>
* config/tc-arm.c (do_smc): Add range check for immediate operand.
(do_t_smc): Add range check for immediate operand. Remove
obsolete immediate encoding.
(md_apply_fix): Fix range check. Remove obsolete immediate encoding.
* testsuite/gas/arm/arch6zk.d: Fix test.
* testsuite/gas/arm/arch6zk.s: Fix test.
* testsuite/gas/arm/smc-bad.d: New test.
* testsuite/gas/arm/smc-bad.l: New test.
* testsuite/gas/arm/smc-bad.s: New test.
* testsuite/gas/arm/thumb32.d: Fix test.
* testsuite/gas/arm/thumb32.s: Fix test.
x86: allow VEX et al encodings in 16-bit (protected) mode These encodings aren't valid in real and VM86 modes, but they are very well usable in 16-bit protected mode. A few adjustments in the disassembler tables are needed where Ev or Gv were wrongly used. Additionally an adjustment is needed to avoid printing "addr32" when that's already recognizable by the use of %eiz. Furthermore the Iq operand template was wrong for XOP:0Ah encoding insns: They're having a uniform 32-bit immediate. Drop Iq and introduce Id instead. Clone a few existing test cases to exercise assembler and disassembler.
2019-06-27 14:49:40 +08:00
2019-06-27 Jan Beulich <jbeulich@suse.com>
config/tc-i386.c (md_assemble): Check for protected mode
incapable processor before encoding VEX and alike insns.
* testsuite/gas/i386/inval-16.s: For 80186 architecture.
* testsuite/gas/i386/inval-16.l: Adjust expectations.
* testsuite/gas/i386/avx-16bit.d,
testsuite/gas/i386/avx-16bit.s,
testsuite/gas/i386/avx512f-16bit.d,
testsuite/gas/i386/avx512f-16bit.s,
testsuite/gas/i386/bmi-16bit.d,
testsuite/gas/i386/bmi-16bit.s,
testsuite/gas/i386/bmi2-16bit.d,
testsuite/gas/i386/bmi2-16bit.s,
testsuite/gas/i386/lwp-16bit.d,
testsuite/gas/i386/lwp-16bit.s: New
testsuite/gas/i386/i386.exp: Run new tests.
Fix a few non-dash safe xstormy16 shell scripts. Noticed by a customer while looking at a tangentially related problem. The gas testsuite for xstormy16 has two scripts that have a typo on the first line, they are missing the !. They also use shell syntax that doesn't work on a system where /bin/sh is dash. So I fixed the typo, changed the shell to bash, and made them executable, so that they now work when run directly even if /bin/sh is dash. gas/ * testsuite/gas/xstormy16/allinsn.sh: Change first line to #!/bin/bash and make it executable. * testsuite/gas/xstormy16/gcc.sh: Likewise.
2019-06-27 09:12:55 +08:00
2019-06-26 Jim Wilson <jimw@sifive.com>
* testsuite/gas/xstormy16/allinsn.sh: Change first line to
#!/bin/bash and make it executable.
* testsuite/gas/xstormy16/gcc.sh: Likewise.
i386: Document memory size reference in assembler * doc/c-i386.texi: Document x/y/z instruction sufffixes in AT&T syntax and xmmword/ymmword/zmmword/fword/tbyte/oword ptr in Intel syntax.
2019-06-27 06:12:58 +08:00
2019-06-26 Lili Cui <lili.cui@intel.com>
* doc/c-i386.texi: Document x/y/z instruction sufffixes in AT&T
syntax and xmmword/ymmword/zmmword/fword/tbyte/oword ptr in
Intel syntax.
MIPS/gas: Fix order of instructions in LI macro expansion When MTHC1 instruction is paired with MTC1 to write a value to a 64-bit FPR, the MTC1 must be executed first, because the semantic definition of MTC1 is not aware that software will be using an MTHC1 to complete the operation, and sets the upper half of the 64-bit FPR to an UNPREDICTABLE value[1]. Fix the order of MTHC1 and MTC1 instructions in LI macro expansion. Modify the expansions to exploit moves from $zero directly by-passing the use of $AT, where ever possible. [1] "MIPS Architecture for Programmers Volume II-A: The MIPS32 Instruction Set Manual", Wave Computing, Inc., Document Number: MD00086, Revision 5.04, December 11, 2013, Section 3.2 "Alphabetical List of Instructions", pp. 217. gas/ * config/tc-mips.c (macro) <M_LI>: Re-order MTHC1 with respect to MTC1 and use $0 for either part where possible. * testsuite/gas/mips/li-d.s: Add test cases for non-zero words in double precision constants. * testsuite/gas/mips/li-d.d: Update reference output. * testsuite/gas/mips/micromips@isa-override-1.d: Likewise. * testsuite/gas/mips/mips32r2@isa-override-1.d: Likewise. * testsuite/gas/mips/mips64r2@isa-override-1.d: Likewise.
2019-06-20 06:55:04 +08:00
2019-06-25 Faraz Shahbazker <fshahbazker@wavecomp.com>
* config/tc-mips.c (macro) <M_LI>: Re-order MTHC1 with
respect to MTC1 and use $0 for either part where possible.
* testsuite/gas/mips/li-d.s: Add test cases for non-zero
words in double precision constants.
* testsuite/gas/mips/li-d.d: Update reference output.
* testsuite/gas/mips/micromips@isa-override-1.d: Likewise.
* testsuite/gas/mips/mips32r2@isa-override-1.d: Likewise.
* testsuite/gas/mips/mips64r2@isa-override-1.d: Likewise.
x86: correct / adjust debug printing For quite some time we've been using combinations of bits for specifying various registers in operands and templates. I think it was Alan who had indicated that likely the debug printing would need adjustment as a result. Here we go. Accumulator handling for GPRs gets changed to match that for FPU regs. For this to work, OPERAND_TYPE_ACC{32,64} get repurposed, with their original uses replaced by direct checks of the two bits of interest, which is cheaper than operand_type_equal() invocations. For SIMD registers nothing similar appears to be needed, as respective operands get stripped from the (copy of the) template before pt() is reached. The type change on pi() is to silence a compiler diagnostic. Arguably its other parameter could also be const-qualified.
2019-06-25 15:41:33 +08:00
2019-06-25 Jan Beulich <jbeulich@suse.com>
* tc-i386.c (acc32, acc64): Delete.
(pi): Make first parameter pinter-to-const.
(type_names): Remove Acc. Add acc8, acc16, acc32, and acc64.
(pt): Use operand_type_equal().
(match_template): Replace use of acc32.
(process_suffix): Replace use of acc64.
x86: document certain command line options as "dangerous" Errata BT36, BT41, and BT230 mean that gas may, when using one ofthese options, produce code that causes #UD on (at least) SandyBridge systems.
2019-06-25 15:40:44 +08:00
2019-06-25 Jan Beulich <jbeulich@suse.com>
* doc/c-i386.texi: Mark -mavxscalar= and -mvexwig as dangrous to
use.
x86: don't open code is_any_vex_encoding()
2019-06-25 15:27:49 +08:00
2019-06-25 Jan Beulich <jbeulich@suse.com>
* tc-i386.c (process_suffix): Use is_any_vex_encoding().
x86: fix (dis)assembly of certain SSE2 insns in 16-bit mode MOVNTI was wrongly assembled with a 66h prefix. Add IgnoreSize to address this. It and the scalar to/from integer conversion insns also were also wrongly using Ev / Gv, leading to 16-bit register names being printed when 32-bit ones were meant. Clone the 32-bit SSE2 test to cover both assembler and disassembler.
2019-06-25 15:25:26 +08:00
2019-06-25 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/sse2-16bit.d,
testsuite/gas/i386/sse2-16bit.s: New.
testsuite/gas/i386/i386.exp: Run new test.
x86-64: also optimize ANDQ with immediate fitting in 7 bits The same reasoning applies here as did/does for immediates fitting in 31 bits.
2019-06-25 15:23:48 +08:00
2019-06-25 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (optimize_encoding): Also handle ANDQ with
immediatie fitting in 7 bits.
* testsuite/gas/i386/x86-64-optimize-1.s: Add ANDQ cases with
7- and 8-bit immediates.
* testsuite/gas/i386/x86-64-optimize-1.d: Adjust expectations.
x86: add CVT{,T}PS2PI cases to xmmwords test I've (not so) recently noticed this further pair which should be tested here.
2019-06-25 15:22:38 +08:00
2019-06-25 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/xmmword.s: Add cvtps2pi and cvttps2pi
tests.
* testsuite/gas/i386/xmmword.l: Adjust expectations.
Fix logical expression in last commit * config/tc-ppc.c (ppc_handle_align): Add parentheses.
2019-06-25 15:26:16 +08:00
2019-06-25 Alan Modra <amodra@gmail.com>
* config/tc-ppc.c (ppc_handle_align): Add parentheses.
PowerPC nops This patch corrects ppc rs_align_code handling to choose the alignment nops based on the machine in force at the alignment directive rather than the machine at the end of file. * config/tc-ppc.h (ppc_nop_select): Declare. (NOP_OPCODE): Define. * config/tc-ppc.c (ppc_elf_end, ppc_xcoff_end): Zero ppc_cpu. (ppc_nop_encoding_for_rs_align_code): New enum. (ppc_nop_select): New function. (ppc_handle_align): Don't use ppc_cpu here. Get nop type from frag. * testsuite/gas/ppc/groupnop.d, * testsuite/gas/ppc/groupnop.s: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2019-06-25 08:42:58 +08:00
2019-06-25 Alan Modra <amodra@gmail.com>
* config/tc-ppc.h (ppc_nop_select): Declare.
(NOP_OPCODE): Define.
* config/tc-ppc.c (ppc_elf_end, ppc_xcoff_end): Zero ppc_cpu.
(ppc_nop_encoding_for_rs_align_code): New enum.
(ppc_nop_select): New function.
(ppc_handle_align): Don't use ppc_cpu here. Get nop type from frag.
* testsuite/gas/ppc/groupnop.d,
* testsuite/gas/ppc/groupnop.s: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
i386: Check vector length for EVEX broadcast instructions Since not all vector lengths are supported by EVEX broadcast instructions, decode them only with supported vector lengths. gas/ PR binutils/24700 * testsuite/gas/i386/disassem.s: Add test for vbroadcasti32x8 with invalid vector length. * testsuite/gas/i386/x86-64-disassem.s: Likewise. * testsuite/gas/i386/disassem.d: Updated. * testsuite/gas/i386/x86-64-disassem.d: Likewise. opcodes/ PR binutils/24700 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and EVEX_W_0F385B_P_2. (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0, EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and EVEX_LEN_0F385B_P_2_W_1. * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum. (EVEX_LEN_0F3819_P_2_W_1): Likewise. (EVEX_LEN_0F381A_P_2_W_0): Likewise. (EVEX_LEN_0F381A_P_2_W_1): Likewise. (EVEX_LEN_0F381B_P_2_W_0): Likewise. (EVEX_LEN_0F381B_P_2_W_1): Likewise. (EVEX_LEN_0F385A_P_2_W_0): Likewise. (EVEX_LEN_0F385A_P_2_W_1): Likewise. (EVEX_LEN_0F385B_P_2_W_0): Likewise. (EVEX_LEN_0F385B_P_2_W_1): Likewise.
2019-06-20 01:01:27 +08:00
2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/24700
* testsuite/gas/i386/disassem.s: Add test for vbroadcasti32x8
with invalid vector length.
* testsuite/gas/i386/x86-64-disassem.s: Likewise.
* testsuite/gas/i386/disassem.d: Updated.
* testsuite/gas/i386/x86-64-disassem.d: Likewise.
i386: Check vector length for vshufXXX/vinsertXXX/vextractXXX Since not all vector lengths are supported by vshufXXX, vinsertXXX and vextractXXX, decode them only with supported vector lengths. gas/ PR binutils/24691 * testsuite/gas/i386/disassem.s: Add test for vshuff32x4 with invalid vector length. * testsuite/gas/i386/x86-64-disassem.s: Likewise. * testsuite/gas/i386/disassem.d: Updated. * testsuite/gas/i386/x86-64-disassem.d: Likewise. opcodes/ PR binutils/24691 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2. (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and EVEX_LEN_0F3A43_P_2_W_1. * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum. (EVEX_LEN_0F3A23_P_2_W_1): Likewise. (EVEX_LEN_0F3A38_P_2_W_0): Likewise. (EVEX_LEN_0F3A38_P_2_W_1): Likewise. (EVEX_LEN_0F3A39_P_2_W_0): Likewise. (EVEX_LEN_0F3A39_P_2_W_1): Likewise. (EVEX_LEN_0F3A3A_P_2_W_0): Likewise. (EVEX_LEN_0F3A3A_P_2_W_1): Likewise. (EVEX_LEN_0F3A3B_P_2_W_0): Likewise. (EVEX_LEN_0F3A3B_P_2_W_1): Likewise. (EVEX_LEN_0F3A43_P_2_W_0): Likewise. (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
2019-06-18 01:20:04 +08:00
2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/24691
* testsuite/gas/i386/disassem.s: Add test for vshuff32x4 with
invalid vector length.
* testsuite/gas/i386/x86-64-disassem.s: Likewise.
* testsuite/gas/i386/disassem.d: Updated.
* testsuite/gas/i386/x86-64-disassem.d: Likewise.
Regenerate with approved autotools version bfd/ * Makefile.in: Regenerate. * configure: Regenerate. binutils/ * Makefile.in: Regenerate. * aclocal.m4: Regenerate. * doc/Makefile.in: Regenerate. gas/ * Makefile.in: Regenerate. * configure: Regenerate. * doc/Makefile.in: Regenerate. ld/ * Makefile.in: Regenerate. * configure: Regenerate. libctf/ * configure: Regenerate.
2019-06-14 09:00:35 +08:00
2019-06-14 Alan Modra <amodra@gmail.com>
* Makefile.in: Regenerate.
* configure: Regenerate.
* doc/Makefile.in: Regenerate.
Add missing ChangeLog entries
2019-06-13 04:51:01 +08:00
2019-06-12 Peter Bergner <bergner@linux.ibm.com>
* testsuite/gas/ppc/power9.d: Delete ldmx tests.
* testsuite/gas/ppc/power9.s: Likewise.
gas: Add .enqcmd and noenqcmd directives 2019-06-06 Lili Cui <lili.cui@intel.com> * config/tc-i386.c (cpu_arch): Add .enqcmd. (cpu_noarch): Add noenqcmd. * doc/c-i386.texi: Document noenqcmd.
2019-06-06 22:57:52 +08:00
2019-06-06 Lili Cui <lili.cui@intel.com>
* config/tc-i386.c (cpu_arch): Add .enqcmd.
(cpu_noarch): Add noenqcmd.
* doc/c-i386.texi: Document noenqcmd.
i386: Check vector length for EVEX vextractfXX and vinsertfXX Since not all vector lengths are supported by EVEX vextractfXX and vinsertfXX, decode them only with supported vector lengths. gas/ PR binutils/24633 * testsuite/gas/i386/disassem.s: Add tests for invalid vector lengths for EVEX vextractfXX and vinsertfXX. * testsuite/gas/i386/x86-64-disassem.s: Likewise. * testsuite/gas/i386/disassem.d: Updated. * testsuite/gas/i386/x86-64-disassem.d: Likewise. opcodes/ PR binutils/24633 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2. (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0, EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0, EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0, EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0, EVEX_LEN_0F3A1B_P_2_W_1. * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum. (EVEX_LEN_0F3A18_P_2_W_1): Likewise. (EVEX_LEN_0F3A19_P_2_W_0): Likewise. (EVEX_LEN_0F3A19_P_2_W_1): Likewise. (EVEX_LEN_0F3A1A_P_2_W_0): Likewise. (EVEX_LEN_0F3A1A_P_2_W_1): Likewise. (EVEX_LEN_0F3A1B_P_2_W_0): Likewise. (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
2019-06-06 01:27:08 +08:00
2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/24633
* testsuite/gas/i386/disassem.s: Add tests for invalid vector
lengths for EVEX vextractfXX and vinsertfXX.
* testsuite/gas/i386/x86-64-disassem.s: Likewise.
* testsuite/gas/i386/disassem.d: Updated.
* testsuite/gas/i386/x86-64-disassem.d: Likewise.
i386: Check for reserved VEX.vvvv and EVEX.vvvv If VEX.vvvv and EVEX.vvvv are reserved, they must be all 1s, which are all 0s in inverted form. Add check for unused VEX.vvvv and EVEX.vvvv when disassembling VEX and EVEX instructions. gas/ PR binutils/24626 * testsuite/gas/i386/disassem.s: Add tests for reserved VEX.vvvv and EVEX.vvvv. * testsuite/gas/i386/x86-64-disassem.s: Likewise. * testsuite/gas/i386/disassem.d: Updated. * testsuite/gas/i386/x86-64-disassem.d: Likewise. opcodes/ PR binutils/24626 * i386-dis.c (print_insn): Check for unused VEX.vvvv and EVEX.vvvv when disassembling VEX and EVEX instructions. (OP_VEX): Set vex.register_specifier to 0 after readding vex.register_specifier. (OP_Vex_2src_1): Likewise. (OP_Vex_2src_2): Likewise. (OP_LWP_E): Likewise. (OP_EX_Vex): Don't check vex.register_specifier. (OP_XMM_Vex): Likewise.
2019-06-05 03:45:20 +08:00
2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/24626
* testsuite/gas/i386/disassem.s: Add tests for reserved VEX.vvvv
and EVEX.vvvv.
* testsuite/gas/i386/x86-64-disassem.s: Likewise.
* testsuite/gas/i386/disassem.d: Updated.
* testsuite/gas/i386/x86-64-disassem.d: Likewise.
Enable Intel AVX512_VP2INTERSECT insn This patch enables support for VP2INTERSECT in binutils. Please refer to https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf for VP2INTERSECT details. Make check-gas is ok. gas/ 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (cpu_arch): Add .avx512_vp2intersect. (cpu_noarch): Likewise. * doc/c-i386.texi: Document avx512_vp2intersect. * testsuite/gas/i386/i386.exp: Run vp2intersect tests. * testsuite/gas/i386/vp2intersect-intel.d: New test. * testsuite/gas/i386/vp2intersect.d: Likewise. * testsuite/gas/i386/vp2intersect.s: Likewise. * testsuite/gas/i386/vp2intersect-inval-bcast.l: Likewise. * testsuite/gas/i386/vp2intersect-inval-bcast.s: Likewise. * testsuite/gas/i386/x86-64-vp2intersect-intel.d: Likewise. * testsuite/gas/i386/x86-64-vp2intersect.d: Likewise. * testsuite/gas/i386/x86-64-vp2intersect.s: Likewise. * testsuite/gas/i386/x86-64-vp2intersect-inval-bcast.l: Likewise. * testsuite/gas/i386/x86-64-vp2intersect-inval-bcast.s: Likewise. opcodes/ 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3. * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT instructions. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS, CPU_ANY_AVX512_VP2INTERSECT_FLAGS. (cpu_flags): Add CpuAVX512_VP2INTERSECT. * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT. (i386_cpu_flags): Add cpuavx512_vp2intersect. * i386-opc.tbl: Add AVX512_VP2INTERSECT insns. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2019-06-04 23:58:21 +08:00
2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
Lili Cui <lili.cui@intel.com>
* config/tc-i386.c (cpu_arch): Add .avx512_vp2intersect.
(cpu_noarch): Likewise.
* doc/c-i386.texi: Document avx512_vp2intersect.
* testsuite/gas/i386/i386.exp: Run vp2intersect tests.
* testsuite/gas/i386/vp2intersect-intel.d: New test.
* testsuite/gas/i386/vp2intersect.d: Likewise.
* testsuite/gas/i386/vp2intersect.s: Likewise.
* testsuite/gas/i386/vp2intersect-inval-bcast.l: Likewise.
* testsuite/gas/i386/vp2intersect-inval-bcast.s: Likewise.
* testsuite/gas/i386/x86-64-vp2intersect-intel.d: Likewise.
* testsuite/gas/i386/x86-64-vp2intersect.d: Likewise.
* testsuite/gas/i386/x86-64-vp2intersect.s: Likewise.
* testsuite/gas/i386/x86-64-vp2intersect-inval-bcast.l: Likewise.
* testsuite/gas/i386/x86-64-vp2intersect-inval-bcast.s: Likewise.
Add support for Intel ENQCMD[S] instructions This patch enables support for ENQCMD[S] in binutils. Please refer to https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf for ENQCMD[S] details. Make check-gas is ok. gas/ChangeLog: 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com> Lili Cui <lili.cui@intel.com> * doc/c-i386.texi: Document enqcmd. * testsuite/gas/i386/enqcmd-intel.d: New file. * testsuite/gas/i386/enqcmd-inval.l: Likewise. * testsuite/gas/i386/enqcmd-inval.s: Likewise. * testsuite/gas/i386/enqcmd.d: Likewise. * testsuite/gas/i386/enqcmd.s: Likewise. * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise. * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise. * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise. * testsuite/gas/i386/x86-64-enqcmd.d: Likewise. * testsuite/gas/i386/x86-64-enqcmd.s: Likewise. * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval, enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval, and x86-64-enqcmd. opcodes/ChangeLog: 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (enum): Add MOD_0F38F8_PREFIX_1 and MOD_0F38F8_PREFIX_3. (prefix_table): New instructions (see prefix above). (mod_table): New instructions (see prefix above). * i386-gen.c (cpu_flag_init): Add entries for enqcmd. (cpu_flags): Add a bitfield for enqmcd. * i386-init.h: Regenerated. * i386-opc.h (enum): Add CpuENQCMD. (i386_cpu_flags): Add a bitfield for cpuenqcmd. * i386-opc.tbl: Add enqcmd and enqcmds instructions. * i386-init.h: Regenerated. * i386-tbl.h: Regenerated.
2019-06-04 23:50:10 +08:00
2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
Lili Cui <lili.cui@intel.com>
gas: Correct ChangeLog for commit 5d79adc4b22b0abd
2019-06-06 22:55:40 +08:00
* doc/c-i386.texi: Document enqcmd.
* testsuite/gas/i386/enqcmd-intel.d: New file.
* testsuite/gas/i386/enqcmd-inval.l: Likewise.
* testsuite/gas/i386/enqcmd-inval.s: Likewise.
* testsuite/gas/i386/enqcmd.d: Likewise.
* testsuite/gas/i386/enqcmd.s: Likewise.
* testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
* testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
* testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
* testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
* testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
* testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
and x86-64-enqcmd.
Add support for Intel ENQCMD[S] instructions This patch enables support for ENQCMD[S] in binutils. Please refer to https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf for ENQCMD[S] details. Make check-gas is ok. gas/ChangeLog: 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com> Lili Cui <lili.cui@intel.com> * doc/c-i386.texi: Document enqcmd. * testsuite/gas/i386/enqcmd-intel.d: New file. * testsuite/gas/i386/enqcmd-inval.l: Likewise. * testsuite/gas/i386/enqcmd-inval.s: Likewise. * testsuite/gas/i386/enqcmd.d: Likewise. * testsuite/gas/i386/enqcmd.s: Likewise. * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise. * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise. * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise. * testsuite/gas/i386/x86-64-enqcmd.d: Likewise. * testsuite/gas/i386/x86-64-enqcmd.s: Likewise. * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval, enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval, and x86-64-enqcmd. opcodes/ChangeLog: 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (enum): Add MOD_0F38F8_PREFIX_1 and MOD_0F38F8_PREFIX_3. (prefix_table): New instructions (see prefix above). (mod_table): New instructions (see prefix above). * i386-gen.c (cpu_flag_init): Add entries for enqcmd. (cpu_flags): Add a bitfield for enqmcd. * i386-init.h: Regenerated. * i386-opc.h (enum): Add CpuENQCMD. (i386_cpu_flags): Add a bitfield for cpuenqcmd. * i386-opc.tbl: Add enqcmd and enqcmds instructions. * i386-init.h: Regenerated. * i386-tbl.h: Regenerated.
2019-06-04 23:50:10 +08:00
RISC-V: Fix lui argument parsing. This fixes a bug reported on the riscv.org sw-dev mailing list. This rejects "lui x1,symbol", as a symbol should only be accepted here when used inside %hi(). Without the fix, this gets assembled as "lui x1,0" with no relocation which is clearly wrong. gas/ * config/tc-riscv.c (riscv_ip) <'u'>: Move O_constant check inside if statement. Delete O_symbol and O_constant check after if statement. * testsuite/gas/riscv/auipc-parsing.s: Test lui with missing %hi. * testsuite/gas/riscv/auipc-parsing.l: Update.
2019-05-31 06:23:10 +08:00
2019-05-30 Jim Wilson <jimw@sifive.com>
* config/tc-riscv.c (riscv_ip) <'u'>: Move O_constant check inside if
statement. Delete O_symbol and O_constant check after if statement.
* testsuite/gas/riscv/auipc-parsing.s: Test lui with missing %hi.
* testsuite/gas/riscv/auipc-parsing.l: Update.
x86: Add CheckRegSize to AVX512_BF16 instructions with Disp8ShiftVL For AVX512 instructions with Disp8ShiftVL and Broadcast, we may need to add CheckRegSize to check if broadcast matches the destination register size. gas/ PR gas/24625 * testsuite/gas/i386/inval-avx512f.s: Add tests for AVX512_BF16 instructions with invalid broadcast. * testsuite/gas/i386/x86-64-inval-avx512f.s: Likewise. * testsuite/gas/i386/inval-avx512f.l: Updated. * testsuite/gas/i386/x86-64-inval-avx512f.l: Likewise. opcodes/ PR gas/24625 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with Disp8ShiftVL. * i386-tbl.h: Regenerated.
2019-05-29 01:05:28 +08:00
2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
PR gas/24625
* testsuite/gas/i386/inval-avx512f.s: Add tests for AVX512_BF16
instructions with invalid broadcast.
* testsuite/gas/i386/x86-64-inval-avx512f.s: Likewise.
* testsuite/gas/i386/inval-avx512f.l: Updated.
* testsuite/gas/i386/x86-64-inval-avx512f.l: Likewise.
Fix failure on powerpc 32-bit only targets Targets that lack ppc64 support were failing the new prefix-reloc test. This patch adds some test infrastructure to deal with that, and changes the powerpc gas usage info so that "-a64" is omitted when unsupported. I've been meaning to break up the usage message for a long time; While doing so causes translators some work now, it should make it easier next time a new powerpc option is added. * config/tc-ppc.c (is_ppc64_target): New function. (md_show_usage): Split up usage message. Don't show -a64 when unsupported. testsuite/gas/ppc/ppc.exp (supports_ppc64): New. (prefix-reloc): Only run for ppc64.
2019-05-27 10:07:51 +08:00
2019-05-27 Alan Modra <amodra@gmail.com>
* config/tc-ppc.c (is_ppc64_target): New function.
(md_show_usage): Split up usage message. Don't show -a64 when
unsupported.
testsuite/gas/ppc/ppc.exp (supports_ppc64): New.
(prefix-reloc): Only run for ppc64.
aarch64: override default elf .set handling in gas Allow st_other values such as STO_AARCH64_VARIANT_PCS to be set for alias symbols independently. This is needed for ifunc symbols which are aliased to the resolver using .set and don't expect resolver attributes to override the ifunc symbol attributes. This means .variant_pcs must be added explicitly to aliases. gas/ChangeLog: * config/tc-aarch64.c (aarch64_elf_copy_symbol_attributes): Define. * config/tc-aarch64.h (aarch64_elf_copy_symbol_attributes): Declare. (OBJ_COPY_SYMBOL_ATTRIBUTES): Define. * testsuite/gas/aarch64/symbol-variant_pcs-3.d: New test. * testsuite/gas/aarch64/symbol-variant_pcs-3.s: New test.
2019-04-25 22:07:10 +08:00
2019-05-24 Szabolcs Nagy <szabolcs.nagy@arm.com>
* config/tc-aarch64.c (aarch64_elf_copy_symbol_attributes): Define.
* config/tc-aarch64.h (aarch64_elf_copy_symbol_attributes): Declare.
(OBJ_COPY_SYMBOL_ATTRIBUTES): Define.
* testsuite/gas/aarch64/symbol-variant_pcs-3.d: New test.
* testsuite/gas/aarch64/symbol-variant_pcs-3.s: New test.
aarch64: handle .variant_pcs directive in gas In ELF objects the specified symbol is marked with STO_AARCH64_VARIANT_PCS. gas/ChangeLog: * config/tc-aarch64.c (s_variant_pcs): New function. * doc/c-aarch64.texi: Document .variant_pcs. * testsuite/gas/aarch64/symbol-variant_pcs-1.d: New test. * testsuite/gas/aarch64/symbol-variant_pcs-1.s: New test. * testsuite/gas/aarch64/symbol-variant_pcs-2.d: New test. * testsuite/gas/aarch64/symbol-variant_pcs-2.s: New test.
2019-04-25 22:06:53 +08:00
2019-05-24 Szabolcs Nagy <szabolcs.nagy@arm.com>
* config/tc-aarch64.c (s_variant_pcs): New function.
* doc/c-aarch64.texi: Document .variant_pcs.
* testsuite/gas/aarch64/symbol-variant_pcs-1.d: New test.
* testsuite/gas/aarch64/symbol-variant_pcs-1.s: New test.
* testsuite/gas/aarch64/symbol-variant_pcs-2.d: New test.
* testsuite/gas/aarch64/symbol-variant_pcs-2.s: New test.
Regen POTFILES for bpf bfd/ * po/SRC-POTFILES.in: Regenerate. gas/ * po/POTFILES.in: Regenerate. ld/ * po/BLD-POTFILES.in: Regenerate. opcodes/ * po/POTFILES.in: Regenerate.
2019-05-24 21:39:56 +08:00
2019-05-24 Alan Modra <amodra@gmail.com>
* po/POTFILES.in: Regenerate.
PowerPC relocations for prefix insns include/ * elf/ppc64.h (R_PPC64_PLTSEQ_NOTOC, R_PPC64_PLTCALL_NOTOC), (R_PPC64_PCREL_OPT, R_PPC64_D34, R_PPC64_D34_LO, R_PPC64_D34_HI30), (R_PPC64_D34_HA30, R_PPC64_PCREL34, R_PPC64_GOT_PCREL34), (R_PPC64_PLT_PCREL34, R_PPC64_PLT_PCREL34_NOTOC), (R_PPC64_ADDR16_HIGHER34, R_PPC64_ADDR16_HIGHERA34), (R_PPC64_ADDR16_HIGHEST34, R_PPC64_ADDR16_HIGHESTA34), (R_PPC64_REL16_HIGHER34, R_PPC64_REL16_HIGHERA34), (R_PPC64_REL16_HIGHEST34, R_PPC64_REL16_HIGHESTA34), (R_PPC64_D28, R_PPC64_PCREL28): Define. bfd/ * reloc.c (BFD_RELOC_PPC64_D34, BFD_RELOC_PPC64_D34_LO), (BFD_RELOC_PPC64_D34_HI30, BFD_RELOC_PPC64_D34_HA30), (BFD_RELOC_PPC64_PCREL34, BFD_RELOC_PPC64_GOT_PCREL34), (BFD_RELOC_PPC64_PLT_PCREL34), (BFD_RELOC_PPC64_ADDR16_HIGHER34, BFD_RELOC_PPC64_ADDR16_HIGHERA34), (BFD_RELOC_PPC64_ADDR16_HIGHEST34, BFD_RELOC_PPC64_ADDR16_HIGHESTA34), (BFD_RELOC_PPC64_REL16_HIGHER34, BFD_RELOC_PPC64_REL16_HIGHERA34), (BFD_RELOC_PPC64_REL16_HIGHEST34, BFD_RELOC_PPC64_REL16_HIGHESTA34), (BFD_RELOC_PPC64_D28, BFD_RELOC_PPC64_PCREL28): New reloc enums. * elf64-ppc.c (PNOP): Define. (ppc64_elf_howto_raw): Add reloc howtos for new relocations. (ppc64_elf_reloc_type_lookup): Translate new bfd reloc numbers. (ppc64_elf_ha_reloc): Adjust addend for highera34 and highesta34 relocs. (ppc64_elf_prefix_reloc): New function. (struct ppc_link_hash_table): Add notoc_plt. (is_branch_reloc): Add R_PPC64_PLTCALL_NOTOC. (is_plt_seq_reloc): Add R_PPC64_PLT_PCREL34, R_PPC64_PLT_PCREL34_NOTOC, and R_PPC64_PLTSEQ_NOTOC. (ppc64_elf_check_relocs): Handle pcrel got and plt relocs. Set has_pltcall for section on seeing R_PPC64_PLTCALL_NOTOC. Handle possible need for dynamic relocs on non-pcrel powerxx relocs. (dec_dynrel_count): Handle non-pcrel powerxx relocs. (ppc64_elf_inline_plt): Handle R_PPC64_PLTCALL_NOTOC. (toc_adjusting_stub_needed): Likewise. (ppc64_elf_tls_optimize): Handle R_PPC64_PLTSEQ_NOTOC. (ppc64_elf_relocate_section): Handle new powerxx relocs. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. gas/ * config/tc-ppc.c (ppc_elf_suffix): Support @pcrel, @got@pcrel, @plt@pcrel, @higher34, @highera34, @highest34, and @highesta34. (fixup_size): Handle new powerxx relocs. (md_assemble): Warn for @pcrel on non-prefix insns. Accept @l, @h and @ha on prefix insns, and infer reloc without any @ suffix. Translate powerxx relocs to suit DQ and DS field instructions. Include operand tests as well as opcode test to translate BFD_RELOC_HI16_S to BFD_RELOC_PPC_16DX_HA. (ppc_fix_adjustable): Return false for pcrel GOT and PLT relocs. (md_apply_fix): Handle new powerxx relocs. * config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): Accept BFD_RELOC_PPC64_ADDR16_HIGHER34, BFD_RELOC_PPC64_ADDR16_HIGHERA34, BFD_RELOC_PPC64_ADDR16_HIGHEST34, BFD_RELOC_PPC64_ADDR16_HIGHESTA34, BFD_RELOC_PPC64_D34, and BFD_RELOC_PPC64_D28. * testsuite/gas/ppc/prefix-reloc.d, * testsuite/gas/ppc/prefix-reloc.s: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2018-08-29 12:52:34 +08:00
2019-05-24 Alan Modra <amodra@gmail.com>
* config/tc-ppc.c (ppc_elf_suffix): Support @pcrel, @got@pcrel,
@plt@pcrel, @higher34, @highera34, @highest34, and @highesta34.
(fixup_size): Handle new powerxx relocs.
(md_assemble): Warn for @pcrel on non-prefix insns.
Accept @l, @h and @ha on prefix insns, and infer reloc without
any @ suffix. Translate powerxx relocs to suit DQ and DS field
instructions. Include operand tests as well as opcode test to
translate BFD_RELOC_HI16_S to BFD_RELOC_PPC_16DX_HA.
(ppc_fix_adjustable): Return false for pcrel GOT and PLT relocs.
(md_apply_fix): Handle new powerxx relocs.
* config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): Accept
BFD_RELOC_PPC64_ADDR16_HIGHER34, BFD_RELOC_PPC64_ADDR16_HIGHERA34,
BFD_RELOC_PPC64_ADDR16_HIGHEST34, BFD_RELOC_PPC64_ADDR16_HIGHESTA34,
BFD_RELOC_PPC64_D34, and BFD_RELOC_PPC64_D28.
* testsuite/gas/ppc/prefix-reloc.d,
* testsuite/gas/ppc/prefix-reloc.s: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
PowerPC D-form prefixed loads and stores opcodes/ * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34), (insert_pcrel, extract_pcrel, extract_pcrel0): New functions. (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment. (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0, XTOP>): Define and add entries. (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define. (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw, pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd, plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq. gas/ * config/tc-ppc.c (ppc_insert_operand): Only sign extend fields that are 32-bits or smaller. * messages.c (as_internal_value_out_of_range): Do not truncate variables and use BFD_VMA_FMT to print them. * testsuite/gas/ppc/prefix-pcrel.s, * testsuite/gas/ppc/prefix-pcrel.d: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2018-07-28 11:21:43 +08:00
2019-05-24 Peter Bergner <bergner@linux.ibm.com>
Alan Modra <amodra@gmail.com>
* config/tc-ppc.c (ppc_insert_operand): Only sign extend fields that
are 32-bits or smaller.
* messages.c (as_internal_value_out_of_range): Do not truncate
variables and use BFD_VMA_FMT to print them.
* testsuite/gas/ppc/prefix-pcrel.s,
* testsuite/gas/ppc/prefix-pcrel.d: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
PowerPC add initial -mfuture instruction support This patch adds initial 64-bit insn assembler/disassembler support. The only instruction added is "pnop" along with the automatic aligning of prefix instruction so they do not cross 64-byte boundaries. include/ * dis-asm.h (WIDE_OUTPUT): Define. * opcode/ppc.h (prefix_opcodes, prefix_num_opcodes): Declare. (PPC_OPCODE_POWERXX, PPC_GET_PREFIX, PPC_GET_SUFFIX), (PPC_PREFIX_P, PPC_PREFIX_SEG): Define. opcodes/ * ppc-dis.c (ppc_opts): Add "future" entry. (PREFIX_OPCD_SEGS): Define. (prefix_opcd_indices): New array. (disassemble_init_powerpc): Initialize prefix_opcd_indices. (lookup_prefix): New function. (print_insn_powerpc): Handle 64-bit prefix instructions. * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK), (PMRR, POWERXX): Define. (prefix_opcodes): New instruction table. (prefix_num_opcodes): New constant. binutils/ * objdump.c (disassemble_bytes): Set WIDE_OUTPUT in flags. gas/ * config/tc-ppc.c (ppc_setup_opcodes): Handle prefix_opcodes. (struct insn_label_list): New. (insn_labels, free_insn_labels): New variables. (ppc_record_label, ppc_clear_labels, ppc_start_line_hook): New funcs. (ppc_frob_label, ppc_new_dot_label): Move functions earlier in file and call ppc_record_label. (md_assemble): Handle 64-bit prefix instructions. Align labels that are on the same line as a prefix instruction. * config/tc-ppc.h (tc_frob_label, ppc_frob_label): Move to later in the file. (md_start_line_hook): Define. (ppc_start_line_hook): Declare. * testsuite/gas/ppc/prefix-align.d, * testsuite/gas/ppc/prefix-align.s: New test. * testsuite/gas/ppc/ppc.exp: Run new test.
2018-05-16 05:48:14 +08:00
2019-05-24 Peter Bergner <bergner@linux.ibm.com>
Alan Modra <amodra@gmail.com>
* config/tc-ppc.c (ppc_setup_opcodes): Handle prefix_opcodes.
(struct insn_label_list): New.
(insn_labels, free_insn_labels): New variables.
(ppc_record_label, ppc_clear_labels, ppc_start_line_hook): New funcs.
(ppc_frob_label, ppc_new_dot_label): Move functions earlier in file
and call ppc_record_label.
(md_assemble): Handle 64-bit prefix instructions. Align labels
that are on the same line as a prefix instruction.
* config/tc-ppc.h (tc_frob_label, ppc_frob_label): Move to
later in the file.
(md_start_line_hook): Define.
(ppc_start_line_hook): Declare.
* testsuite/gas/ppc/prefix-align.d,
* testsuite/gas/ppc/prefix-align.s: New test.
* testsuite/gas/ppc/ppc.exp: Run new test.
gas: add support for eBPF This patch adds a port for the Linux kernel eBPF to the GNU assembler. A testsuite and documentation updates are included. gas/ChangeLog: 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com> * configure.ac: Handle bpf-*-* targets. * configure.tgt (generic_target): Likewise. * configure: Regenerate. * Makefile.am (TARGET_CPU_CFILES): Add tc-bpf.c. (TARGET_CPU_HFILES): Add tc-bpf.h. * Makefile.in: Regenerated. * config/tc-bpf.c: New file. * config/tc-bpf.h: Likewise. * doc/Makefile.am (CPU_DOCS): Add c-bpf.texi. * doc/Makefile.in: Regenerated. * doc/all.texi: set BPF. * doc/as.texi: Add eBPF contents. * doc/c-bpf.texi: New file. * testsuite/gas/bpf/alu.d: New file. * testsuite/gas/bpf/mem-be.d: Likewise. * testsuite/gas/bpf/mem.s: Likewise. * testsuite/gas/bpf/mem.d: Likewise. * testsuite/gas/bpf/lddw-be.d: Likewise. * testsuite/gas/bpf/lddw.s: Likewise. * testsuite/gas/bpf/lddw.d: Likewise. * testsuite/gas/bpf/jump-be.d: Likewise. * testsuite/gas/bpf/jump.s: Likewise. * testsuite/gas/bpf/jump.d: Likewise. * testsuite/gas/bpf/exit-be.d: Likewise. * testsuite/gas/bpf/exit.s: Likewise. * testsuite/gas/bpf/exit.d: Likewise. * testsuite/gas/bpf/call-be.d: Likewise. * testsuite/gas/bpf/call.s: Likewise. * testsuite/gas/bpf/call.d: Likewise. * testsuite/gas/bpf/bpf.exp: Likewise. * testsuite/gas/bpf/atomic-be.d: Likewise. * testsuite/gas/bpf/atomic.s: Likewise. * testsuite/gas/bpf/atomic.d: Likewise. * testsuite/gas/bpf/alu-be.d: Likewise. * testsuite/gas/bpf/alu32-be.d: Likewise. * testsuite/gas/bpf/alu32.s: Likewise. * testsuite/gas/bpf/alu32.d: Likewise. * testsuite/gas/bpf/alu.s: Likewise. * testsuite/gas/all/gas.exp: Introduce a nop_type for eBPF. * testsuite/gas/all/org-1.s: Support nop_type 6. * testsuite/gas/all/org-1.l: Updated to reflect changes in org-1.s.
2019-05-24 01:05:12 +08:00
2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
* configure.ac: Handle bpf-*-* targets.
* configure.tgt (generic_target): Likewise.
* configure: Regenerate.
* Makefile.am (TARGET_CPU_CFILES): Add tc-bpf.c.
(TARGET_CPU_HFILES): Add tc-bpf.h.
* Makefile.in: Regenerated.
* config/tc-bpf.c: New file.
* config/tc-bpf.h: Likewise.
* doc/Makefile.am (CPU_DOCS): Add c-bpf.texi.
* doc/Makefile.in: Regenerated.
* doc/all.texi: set BPF.
* doc/as.texi: Add eBPF contents.
* doc/c-bpf.texi: New file.
* testsuite/gas/bpf/alu.d: New file.
* testsuite/gas/bpf/mem-be.d: Likewise.
* testsuite/gas/bpf/mem.s: Likewise.
* testsuite/gas/bpf/mem.d: Likewise.
* testsuite/gas/bpf/lddw-be.d: Likewise.
* testsuite/gas/bpf/lddw.s: Likewise.
* testsuite/gas/bpf/lddw.d: Likewise.
* testsuite/gas/bpf/jump-be.d: Likewise.
* testsuite/gas/bpf/jump.s: Likewise.
* testsuite/gas/bpf/jump.d: Likewise.
* testsuite/gas/bpf/exit-be.d: Likewise.
* testsuite/gas/bpf/exit.s: Likewise.
* testsuite/gas/bpf/exit.d: Likewise.
* testsuite/gas/bpf/call-be.d: Likewise.
* testsuite/gas/bpf/call.s: Likewise.
* testsuite/gas/bpf/call.d: Likewise.
* testsuite/gas/bpf/bpf.exp: Likewise.
* testsuite/gas/bpf/atomic-be.d: Likewise.
* testsuite/gas/bpf/atomic.s: Likewise.
* testsuite/gas/bpf/atomic.d: Likewise.
* testsuite/gas/bpf/alu-be.d: Likewise.
* testsuite/gas/bpf/alu32-be.d: Likewise.
* testsuite/gas/bpf/alu32.s: Likewise.
* testsuite/gas/bpf/alu32.d: Likewise.
* testsuite/gas/bpf/alu.s: Likewise.
* testsuite/gas/all/gas.exp: Introduce a nop_type for eBPF.
* testsuite/gas/all/org-1.s: Support nop_type 6.
* testsuite/gas/all/org-1.l: Updated to reflect changes in
org-1.s.
S12Z: GAS: New option --mdollar-hex. This option (also implied by --traditional) causes '$' to introduce literal hexadecimal constants, rather than the modern convention '0x'. gas/ * config/tc-s12z.c (s12z_strtol): New function. (md_show_usage): Update. (md_parse_option): new case OPTION_DOLLAR_HEX. (s12z_init_after_args): (<global>): Use s12z_strtol instead of strtol. * doc/c-s12z.texi (S12Z Options): Document new option -mdollar-hex. * testsuite/gas/s12z/dollar-hex.d: New file. * testsuite/gas/s12z/dollar-hex.s: New file. * testsuite/gas/s12z/s12z.exp: Add them.
2019-05-22 13:16:14 +08:00
2019-05-22 John Darrington <john@darrington.wattle.id.au>
* config/tc-s12z.c (s12z_strtol): New function. (md_show_usage): Update.
(md_parse_option): new case OPTION_DOLLAR_HEX. (s12z_init_after_args):
(<global>): Use s12z_strtol instead of strtol.
* doc/c-s12z.texi (S12Z Options): Document new option -mdollar-hex.
* testsuite/gas/s12z/dollar-hex.d: New file.
* testsuite/gas/s12z/dollar-hex.s: New file.
* testsuite/gas/s12z/s12z.exp: Add them.
[binutils, ARM] <spec_reg> changes for VMRS and VMSR instructions This patch makes changes to the <spec_reg> operand for VMRS and VMSR instructions as per the Armv8.1-M Mainline. New <spec_reg> options to support are: 0b0010: FPSCR_nzcvqc, access to FPSCR condition and saturation flags. 0b1100: VPR, privileged only access to the VPR register. 0b1101: P0, access to VPR.P0 predicate fields 0b1110: FPCXT_NS, enables saving and restoring of Non-secure floating point context. 0b1111: FPCXT_S, enables saving and restoring of Secure floating point context *** gas/ChangeLog *** 2019-05-21 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (parse_operands): Update case OP_RVC to parse p0 and P0. (do_vmrs): Add checks for valid operands with respect to cpu and fpu options. (do_vmsr): Likewise. (reg_names): New reg_names for FPSCR_nzcvqc, VPR, FPCXT_NS and FPCXT_S. * testsuite/gas/arm/armv8_1-m-spec-reg.d: New. * testsuite/gas/arm/armv8_1-m-spec-reg.s: New. * testsuite/gas/arm/armv8_1-m-spec-reg-bad1.d: New. * testsuite/gas/arm/armv8_1-m-spec-reg-bad2.d: New. * testsuite/gas/arm/armv8_1-m-spec-reg-bad3.d: New. * testsuite/gas/arm/armv8_1-m-spec-reg-bad1.l: New. * testsuite/gas/arm/armv8_1-m-spec-reg-bad2.l: New. * testsuite/gas/arm/armv8_1-m-spec-reg-bad3.l: New. * testsuite/gas/arm/vfp1xD.d: Updated to allow new valid values. * testsuite/gas/arm/vfp1xD_t2.d: Likewise. *** opcodes/ChangeLog *** 2019-05-21 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (coprocessor_opcodes): New instructions for VMRS and VMSR with the new operands.
2019-05-22 01:20:48 +08:00
2019-05-21 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (parse_operands): Update case OP_RVC to
parse p0 and P0.
(do_vmrs): Add checks for valid operands with respect to
cpu and fpu options.
(do_vmsr): Likewise.
(reg_names): New reg_names for FPSCR_nzcvqc, VPR, FPCXT_NS
and FPCXT_S.
* testsuite/gas/arm/armv8_1-m-spec-reg.d: New.
* testsuite/gas/arm/armv8_1-m-spec-reg.s: New.
* testsuite/gas/arm/armv8_1-m-spec-reg-bad1.d: New.
* testsuite/gas/arm/armv8_1-m-spec-reg-bad2.d: New.
* testsuite/gas/arm/armv8_1-m-spec-reg-bad3.d: New.
* testsuite/gas/arm/armv8_1-m-spec-reg-bad1.l: New.
* testsuite/gas/arm/armv8_1-m-spec-reg-bad2.l: New.
* testsuite/gas/arm/armv8_1-m-spec-reg-bad3.l: New.
* testsuite/gas/arm/vfp1xD.d: Updated to allow new valid values.
* testsuite/gas/arm/vfp1xD_t2.d: Likewise.
[binutils, Arm] Add support for conditional instructions in Armv8.1-M Mainline This patch adds the following instructions which are part of the Armv8.1-M Mainline: CINC CINV CNEG CSINC CSINV CSNEG CSET CSETM CSEL gas/ChangeLog: 2019-05-21 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (TOGGLE_BIT): New. (T16_32_TAB): New entries for cinc, cinv, cneg, csinc, csinv, csneg, cset, csetm and csel. (operand_parse_code): New OP_RR_ZR. (parse_operand): Handle case for OP_RR_ZR. (do_t_cond): New. (insns): New instructions for cinc, cinv, cneg, csinc, csinv, csneg, cset, csetm, csel. * testsuite/gas/arm/armv8_1-m-cond-bad.d: New test. * testsuite/gas/arm/armv8_1-m-cond-bad.l: New test. * testsuite/gas/arm/armv8_1-m-cond-bad.s: New test. * testsuite/gas/arm/armv8_1-m-cond.d: New test. * testsuite/gas/arm/armv8_1-m-cond.s: New test. opcodes/ChangeLog: 2019-05-21 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (enum mve_instructions): New enum for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv and cneg. (mve_opcodes): New instructions as above. (is_mve_encoding_conflict): Add cases for csinc, csinv, csneg and csel. (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
2019-05-22 01:15:13 +08:00
2019-05-21 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (TOGGLE_BIT): New.
(T16_32_TAB): New entries for cinc, cinv, cneg, csinc,
csinv, csneg, cset, csetm and csel.
(operand_parse_code): New OP_RR_ZR.
(parse_operand): Handle case for OP_RR_ZR.
(do_t_cond): New.
(insns): New instructions for cinc, cinv, cneg, csinc,
csinv, csneg, cset, csetm, csel.
* testsuite/gas/arm/armv8_1-m-cond-bad.d: New test.
* testsuite/gas/arm/armv8_1-m-cond-bad.l: New test.
* testsuite/gas/arm/armv8_1-m-cond-bad.s: New test.
* testsuite/gas/arm/armv8_1-m-cond.d: New test.
* testsuite/gas/arm/armv8_1-m-cond.s: New test.
[binutils, Arm] Add support for shift instructions in MVE This patch adds the following instructions which are part of Armv8.1-M MVE: ASRL (imm) ASRL (reg) LSLL (imm) LSLL (reg) LSRL SQRSHRL SRQSHR SQSHLL SQSHL SRSHRL SRSHR UQRSHLL UQRSHL UQSHLL UQSHL URSHLL URSHL *** gas/ChangeLog *** 2019-05-21 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (operand_parse_code): New entries for OP_RRnpcsp_I32 (register or integer operands). (do_mve_scalar_shift): New. (insns): New instructions for asrl, lsll, lsrl, sqrshrl, sqrshr, sqshl sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll, uqshl, urshrl and urshr. * testsuite/gas/arm/mve-shift.d: New. * testsuite/gas/arm/mve-shift.s: New. * testsuite/gas/arm/mve-shift-bad.d: New. * testsuite/gas/arm/mve-shift-bad.s: New. * testsuite/gas/arm/mve-shift-bad.l: New. *** opcodes/ChangeLog *** 2019-05-21 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (emun mve_instructions): Updated for new instructions. (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl, sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll, uqshl, urshrl and urshr. (is_mve_okay_in_it): Add new instructions to TRUE list. (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15. (print_insn_mve): Updated to accept new %j, %<bitfield>m and %<bitfield>n patterns.
2019-05-22 01:11:08 +08:00
2019-05-21 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (operand_parse_code): New entries for
OP_RRnpcsp_I32 (register or integer operands).
(do_mve_scalar_shift): New.
(insns): New instructions for asrl, lsll, lsrl, sqrshrl, sqrshr, sqshl
sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll, uqshl, urshrl and urshr.
* testsuite/gas/arm/mve-shift.d: New.
* testsuite/gas/arm/mve-shift.s: New.
* testsuite/gas/arm/mve-shift-bad.d: New.
* testsuite/gas/arm/mve-shift-bad.s: New.
* testsuite/gas/arm/mve-shift-bad.l: New.
MIPS/gas: Reject $0 as source register for DAUI instruction The MIPS64R6 TRM requires that the source register for DAUI not be r0. [1] "MIPS Architecture for Programmers Volume II-A: The MIPS64 Instruction Set Manual", Imagination Technologies Ltd., Document Number: MD00087, Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical List of Instructions", pp. 67-68. gas/ * testsuite/gas/mips/r6-branch-constraints.s: Rename to ... * testsuite/gas/mips/r6-reg-constraints.s: this and add test case for DAUI. * testsuite/gas/mips/r6-branch-constraints.l: Rename to ... * testsuite/gas/mips/r6-reg-constraints.l: this and add test for DAUI. * testsuite/gas/mips/mips.exp: Rename test from r6-branch-constraints to r6-reg-constraints. opcodes/ * mips-opc.c (mips_builtin_opcodes): Change source register constraint for DAUI.
2019-05-14 08:19:37 +08:00
2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
* testsuite/gas/mips/r6-branch-constraints.s: Rename to ...
* testsuite/gas/mips/r6-reg-constraints.s: this and add test
case for DAUI.
* testsuite/gas/mips/r6-branch-constraints.l: Rename to ...
* testsuite/gas/mips/r6-reg-constraints.l: this and add test
for DAUI.
* testsuite/gas/mips/mips.exp: Rename test from
r6-branch-constraints to r6-reg-constraints.
[GAS, Arm] PR24559: Fix pseudo load-operations for Armv8-M Baseline gas/ChangeLog: 2019-05-21 Andre Vieira <andre.simoesdiasvieira@arm.com> PR 24559 * config/tc-arm.c (move_or_literal_pool): Set size_req to 0 for MOVW replacement. * testsuite/gas/arm/load-pseudo.s: New test input. * testsuite/gas/arm/m0-load-pseudo.d: New test. * testsuite/gas/arm/m23-load-pseudo.d: New test. * testsuite/gas/arm/m33-load-pseudo.d: New test.
2019-05-21 21:51:43 +08:00
2019-05-21 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR 24559
* config/tc-arm.c (move_or_literal_pool): Set size_req to 0 for MOVW
replacement.
* testsuite/gas/arm/load-pseudo.s: New test input.
* testsuite/gas/arm/m0-load-pseudo.d: New test.
* testsuite/gas/arm/m23-load-pseudo.d: New test.
* testsuite/gas/arm/m33-load-pseudo.d: New test.
[binutils][Arm] Fix Branch Future relocation handling and testisms bfd/ChangeLog: 2019-05-21 Andre Vieira <andre.simoesdiasvieira@arm.com> PR/target 24460 * elf32-arm.c (get_value_helper): Remove. (elf32_arm_final_link_relocate): Fix branch future relocations. gas/ChangeLog: 2019-05-21 Andre Vieira <andre.simoesdiasvieira@arm.com> * testsuite/gas/arm/armv8_1-m-bf.d: Allow different branch target naming conventions. * testsuite/gas/arm/armv8_1-m-bfl.d: Likewise. * testsuite/gas/arm/armv8_1-m-bfcsel.d: Likewise. * testsuite/gas/arm/armv8_1-m-loloop.d: Likewise. * testsuite/gas/arm/armv8_1-m-bf-rel.d: Skip for vxworks. * testsuite/gas/arm/armv8_1-m-bf-rela.d: New test. * testsuite/gas/arm/armv8_1-m-bfl-rel.d: Skip for vxworks. * testsuite/gas/arm/armv8_1-m-bfl-rela.d: New test. ld/ChangeLog: 2019-05-21 Andre Vieira <andre.simoesdiasvieira@arm.com> * testsuite/ld-arm/arm-elf.exp: Add tests * testsuite/ld-arm/bfs-0.s: New test. * testsuite/ld-arm/bfs-1.s: New test. * testsuite/ld-arm/branch-futures.d: New test.
2019-05-21 21:49:03 +08:00
2019-05-21 Andre Vieira <andre.simoesdiasvieira@arm.com>
* testsuite/gas/arm/armv8_1-m-bf.d: Allow different branch target naming
conventions.
* testsuite/gas/arm/armv8_1-m-bfl.d: Likewise.
* testsuite/gas/arm/armv8_1-m-bfcsel.d: Likewise.
* testsuite/gas/arm/armv8_1-m-loloop.d: Likewise.
* testsuite/gas/arm/armv8_1-m-bf-rel.d: Skip for vxworks.
* testsuite/gas/arm/armv8_1-m-bf-rela.d: New test.
* testsuite/gas/arm/armv8_1-m-bfl-rel.d: Skip for vxworks.
* testsuite/gas/arm/armv8_1-m-bfl-rela.d: New test.
GAS: Replace macro LITERAL_PREFIXDOLLAR_HEX with a runtime value. In an upcoming commit, I need to be able to set the prefix used to introduce hexadecimal literal constants using a command line flag. This is not currently possible, because the switch which determines this (LITERAL_PREFIXDOLLAR_HEX) is a macro set at build time. This change substitutes it for a variable to be set at start up. gas/ChangeLog: * expr.c (literal_prefix_dollar_hex): New variable. (operand)[case '$']: Use the new variable instead of the old macro. Also, move this instance of "case '$'" next to the other one, and enable it only in the complementary proprocessor case. * expr.h (literal_prefix_dollar_hex): Declare it. * config/tc-epiphany.c (md_begin): Assign literal_prefix_dollar_hex. * config/tc-ip2k.c: ditto * config/tc-mt.c: ditto * config/tc-epiphany.h (LITERAL_PREFIXDOLLAR_HEX): Remove macro definition. * config/tc-ip2k.h: ditto * config/tc-mt.h: ditto
2019-05-21 16:11:40 +08:00
2019-05-21 John Darrington <john@darrington.wattle.id.au>
* expr.c (literal_prefix_dollar_hex): New variable.
(operand)[case '$']: Use the new variable instead of the old macro.
Also, move this instance of "case '$'" next to the other one, and
enable it only in the complementary proprocessor case.
* expr.h (literal_prefix_dollar_hex): Declare it.
* config/tc-epiphany.c (md_begin): Assign literal_prefix_dollar_hex.
* config/tc-ip2k.c: ditto
* config/tc-mt.c: ditto
* config/tc-epiphany.h (LITERAL_PREFIXDOLLAR_HEX): Remove macro definition.
* config/tc-ip2k.h: ditto
* config/tc-mt.h: ditto
[MIPS] PR gas/14798: Limit IRIX5 specific default typing to IRIX targets On IRIX 5, every global symbol that is not explicitly labelled as being a function is assumed to be an object. There is no reason why IRIX behaviour should extend to all MIPS targets, so limit this to only IRIX targets. gas/ PR 14798 * config/tc-mips.c (s_mips_globl): Only treat symbols that are not explicitly labelled as BSF_OBJECTs for IRIX targets. * testsuite/gas/mips/pr14798.s: New test source. * testsuite/gas/mips/pr14798-irix.d: New test. * testsuite/gas/mips/pr14798.d: Likewise. * testsuite/gas/mips/mips.exp: Run the new tests. binutils/ PR 14798 * testsuite/binutils-all/readelf.ss-mips: Update reference output. * testsuite/binutils-all/readelf.ss-tmips: Likewise. ld/ PR 14798 * testsuite/ld-mips-elf/reloc-6a.s: Specify .text section for global code symbols. * testsuite/ld-mips-elf/reloc-6b.s: Likewise.
2019-05-07 00:09:02 +08:00
2019-05-20 Faraz Shahbazker <fshahbazker@wavecomp.com>
PR 14798
* config/tc-mips.c (s_mips_globl): Only treat symbols that are
not explicitly labelled as BSF_OBJECTs for IRIX targets.
* testsuite/gas/mips/pr14798.s: New test source.
* testsuite/gas/mips/pr14798-irix.d: New test.
* testsuite/gas/mips/pr14798.d: Likewise.
* testsuite/gas/mips/mips.exp: Run the new tests.
GAS (documentation): Remove trademark acknowledgements. GNU policy is not to include trademark acknowlegements in documentation [1] [1] https://www.gnu.org/prep/standards/html_node/Trademarks.html Committing as obvious. gas/ * doc/c-arm.texi (ARM Options): Remove "(r)" and "(tm)" * doc/c-bfin.texi (Blackfin Syntax): Remove "(r)"
2019-05-17 21:05:44 +08:00
2019-05-17 John Darrington <john@darrington.wattle.id.au>
* doc/c-arm.texi (ARM Options): Remove "(r)" and "(tm)"
* doc/c-bfin.texi (Blackfin Syntax): Remove "(r)"
[PATCH, GAS, Arm] Refactor check_simd_pred_availability gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (check_simd_pred_availability): Refactor. (do_neon_dyadic_i_su): Refactor use of check_simd_pred_availability. (do_neon_dyadic_i64_su): Likewise. (do_neon_shl): Likewise. (do_neon_qshl): Likewise. (do_neon_rshl): Likewise. (do_neon_logic): Likewise. (do_neon_dyadic_if_su): Likewise. (do_neon_addsub_if_i): Likewise. (do_neon_mac_maybe_scalar): Likewise. (do_neon_fmac): Likewise. (do_neon_mul): Likewise. (do_neon_qdmulh): Likewise. (do_neon_qrdmlah): Likewise. (do_neon_abs_neg): Likewise. (do_neon_sli): Likewise. (do_neon_sri): Likewise. (do_neon_qshlu_imm): Likewise. (do_neon_cvt_1): Likewise. (do_neon_cvttb_1): Likewise. (do_neon_mvn): Likewise. (do_neon_rev): Likewise. (do_neon_dup): Likewise. (do_neon_mov): Likewise. (do_neon_rshift_round_imm): Likewise. (do_neon_sat_abs_neg): Likewise. (do_neon_cls): Likewise. (do_neon_clz): Likewise. (do_vmaxnm): Likewise. (do_vrint_1): Likewise. (do_vcmla): Likewise. (do_vcadd): Likewise.
2019-05-16 23:10:22 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (check_simd_pred_availability): Refactor.
(do_neon_dyadic_i_su): Refactor use of check_simd_pred_availability.
(do_neon_dyadic_i64_su): Likewise.
(do_neon_shl): Likewise.
(do_neon_qshl): Likewise.
(do_neon_rshl): Likewise.
(do_neon_logic): Likewise.
(do_neon_dyadic_if_su): Likewise.
(do_neon_addsub_if_i): Likewise.
(do_neon_mac_maybe_scalar): Likewise.
(do_neon_fmac): Likewise.
(do_neon_mul): Likewise.
(do_neon_qdmulh): Likewise.
(do_neon_qrdmlah): Likewise.
(do_neon_abs_neg): Likewise.
(do_neon_sli): Likewise.
(do_neon_sri): Likewise.
(do_neon_qshlu_imm): Likewise.
(do_neon_cvt_1): Likewise.
(do_neon_cvttb_1): Likewise.
(do_neon_mvn): Likewise.
(do_neon_rev): Likewise.
(do_neon_dup): Likewise.
(do_neon_mov): Likewise.
(do_neon_rshift_round_imm): Likewise.
(do_neon_sat_abs_neg): Likewise.
(do_neon_cls): Likewise.
(do_neon_clz): Likewise.
(do_vmaxnm): Likewise.
(do_vrint_1): Likewise.
(do_vcmla): Likewise.
(do_vcadd): Likewise.
[PATCH, binutils, Arm] Add Armv8.1-M Mainline and MVE enablement to NEWS gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * NEWS: Mention Armv8.1-M Mainline and MVE. binutils/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * NEWS: Mention Armv8.1-M Mainline and MVE.
2019-05-16 23:08:36 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* NEWS: Mention Armv8.1-M Mainline and MVE.
[PATCH 57/57][Arm][GAS] MVE Tests gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * testsuite/gas/arm/mve-tailpredloop.d: New test. * testsuite/gas/arm/mve-tailpredloop.s: New test. * testsuite/gas/arm/mve-vabav.d: New test. * testsuite/gas/arm/mve-vabav.s: New test. * testsuite/gas/arm/mve-vabd.d: New test. * testsuite/gas/arm/mve-vabd.s: New test. * testsuite/gas/arm/mve-vabsneg.d: New test. * testsuite/gas/arm/mve-vabsneg.s: New test. * testsuite/gas/arm/mve-vadc.d: New test. * testsuite/gas/arm/mve-vadc.s: New test. * testsuite/gas/arm/mve-vaddlv.d: New test. * testsuite/gas/arm/mve-vaddlv.s: New test. * testsuite/gas/arm/mve-vaddsub.d: New test. * testsuite/gas/arm/mve-vaddsub.s: New test. * testsuite/gas/arm/mve-vaddv.d: New test. * testsuite/gas/arm/mve-vaddv.s: New test. * testsuite/gas/arm/mve-vand.d: New test. * testsuite/gas/arm/mve-vand.s: New test. * testsuite/gas/arm/mve-vbic.d: New test. * testsuite/gas/arm/mve-vbic.s: New test. * testsuite/gas/arm/mve-vbrsr.d: New test. * testsuite/gas/arm/mve-vbrsr.s: New test. * testsuite/gas/arm/mve-vcadd.d: New test. * testsuite/gas/arm/mve-vcadd.s: New test. * testsuite/gas/arm/mve-vcls.d: New test. * testsuite/gas/arm/mve-vcls.s: New test. * testsuite/gas/arm/mve-vclz.d: New test. * testsuite/gas/arm/mve-vclz.s: New test. * testsuite/gas/arm/mve-vcmla.d: New test. * testsuite/gas/arm/mve-vcmla.s: New test. * testsuite/gas/arm/mve-vcmp.d: New test. * testsuite/gas/arm/mve-vcmp.s: New test. * testsuite/gas/arm/mve-vcmul.d: New test. * testsuite/gas/arm/mve-vcmul.s: New test. * testsuite/gas/arm/mve-vcvt-1.d: New test. * testsuite/gas/arm/mve-vcvt-1.s: New test. * testsuite/gas/arm/mve-vcvt-2.d: New test. * testsuite/gas/arm/mve-vcvt-2.s: New test. * testsuite/gas/arm/mve-vcvt-3.d: New test. * testsuite/gas/arm/mve-vcvt-3.s: New test. * testsuite/gas/arm/mve-vcvt-4.d: New test. * testsuite/gas/arm/mve-vcvt-4.s: New test. * testsuite/gas/arm/mve-vddup.d: New test. * testsuite/gas/arm/mve-vddup.s: New test. * testsuite/gas/arm/mve-vdup.d: New test. * testsuite/gas/arm/mve-vdup.s: New test. * testsuite/gas/arm/mve-veor.d: New test. * testsuite/gas/arm/mve-veor.s: New test. * testsuite/gas/arm/mve-vfma-vfms.d: New test. * testsuite/gas/arm/mve-vfma-vfms.s: New test. * testsuite/gas/arm/mve-vfmas.d: New test. * testsuite/gas/arm/mve-vfmas.s: New test. * testsuite/gas/arm/mve-vhadd-vhsub-vrhadd.d: New test. * testsuite/gas/arm/mve-vhadd-vhsub-vrhadd.s: New test. * testsuite/gas/arm/mve-vhcadd.d: New test. * testsuite/gas/arm/mve-vhcadd.s: New test. * testsuite/gas/arm/mve-vmax-vmin.d: New test. * testsuite/gas/arm/mve-vmax-vmin.s: New test. * testsuite/gas/arm/mve-vmaxa-vmina.d: New test. * testsuite/gas/arm/mve-vmaxa-vmina.s: New test. * testsuite/gas/arm/mve-vmaxnm-vminnm.d: New test. * testsuite/gas/arm/mve-vmaxnm-vminnm.s: New test. * testsuite/gas/arm/mve-vmaxnma-vminnma.s: New test. * testsuite/gas/arm/mve-vmaxnmv-vminnmv.d: New test. * testsuite/gas/arm/mve-vmaxnmv-vminnmv.s: New test. * testsuite/gas/arm/mve-vmaxv-vminv.d: New test. * testsuite/gas/arm/mve-vmaxv-vminv.s: New test. * testsuite/gas/arm/mve-vmla.d: New test. * testsuite/gas/arm/mve-vmla.s: New test. * testsuite/gas/arm/mve-vmladav.d: New test. * testsuite/gas/arm/mve-vmladav.s: New test. * testsuite/gas/arm/mve-vmlaldav.d: New test. * testsuite/gas/arm/mve-vmlaldav.s: New test. * testsuite/gas/arm/mve-vmlalv.d: New test. * testsuite/gas/arm/mve-vmlalv.s: New test. * testsuite/gas/arm/mve-vmlas.d: New test. * testsuite/gas/arm/mve-vmlas.s: New test. * testsuite/gas/arm/mve-vmlav.d: New test. * testsuite/gas/arm/mve-vmlav.s: New test. * testsuite/gas/arm/mve-vmlsdav.d: New test. * testsuite/gas/arm/mve-vmlsdav.s: New test. * testsuite/gas/arm/mve-vmlsldav.d: New test. * testsuite/gas/arm/mve-vmlsldav.s: New test. * testsuite/gas/arm/mve-vmov-1.d: New test. * testsuite/gas/arm/mve-vmov-1.s: New test. * testsuite/gas/arm/mve-vmov-2.d: New test. * testsuite/gas/arm/mve-vmov-2.s: New test. * testsuite/gas/arm/mve-vmul.d: New test. * testsuite/gas/arm/mve-vmul.s: New test. * testsuite/gas/arm/mve-vmulh.d: New test. * testsuite/gas/arm/mve-vmulh.s: New test. * testsuite/gas/arm/mve-vmullbt.d: New test. * testsuite/gas/arm/mve-vmullbt.s: New test. * testsuite/gas/arm/mve-vmvn.d: New test. * testsuite/gas/arm/mve-vmvn.s: New test. * testsuite/gas/arm/mve-vorn.d: New test. * testsuite/gas/arm/mve-vorn.s: New test. * testsuite/gas/arm/mve-vorr.d: New test. * testsuite/gas/arm/mve-vorr.s: New test. * testsuite/gas/arm/mve-vpnot.d: New test. * testsuite/gas/arm/mve-vpnot.s: New test. * testsuite/gas/arm/mve-vpsel.d: New test. * testsuite/gas/arm/mve-vpsel.s: New test. * testsuite/gas/arm/mve-vpt.d: New test. * testsuite/gas/arm/mve-vpt.s: New test. * testsuite/gas/arm/mve-vqabsneg.s: New test. * testsuite/gas/arm/mve-vqaddsub.d: New test. * testsuite/gas/arm/mve-vqaddsub.s: New test. * testsuite/gas/arm/mve-vqdmladh.d: New test. * testsuite/gas/arm/mve-vqdmladh.s: New test. * testsuite/gas/arm/mve-vqdmlah.d: New test. * testsuite/gas/arm/mve-vqdmlah.s: New test. * testsuite/gas/arm/mve-vqdmlash.d: New test. * testsuite/gas/arm/mve-vqdmlash.s: New test. * testsuite/gas/arm/mve-vqdmlsdh.d: New test. * testsuite/gas/arm/mve-vqdmlsdh.s: New test. * testsuite/gas/arm/mve-vqdmulh.d: New test. * testsuite/gas/arm/mve-vqdmulh.s: New test. * testsuite/gas/arm/mve-vqdmull.d: New test. * testsuite/gas/arm/mve-vqdmull.s: New test. * testsuite/gas/arm/mve-vqmovn.d: New test. * testsuite/gas/arm/mve-vqmovn.s: New test. * testsuite/gas/arm/mve-vqrshl.d: New test. * testsuite/gas/arm/mve-vqrshl.s: New test. * testsuite/gas/arm/mve-vqrshrn.d: New test. * testsuite/gas/arm/mve-vqrshrn.s: New test. * testsuite/gas/arm/mve-vqshl.d: New test. * testsuite/gas/arm/mve-vqshl.s: New test. * testsuite/gas/arm/mve-vrev.d: New test. * testsuite/gas/arm/mve-vrev.s: New test. * testsuite/gas/arm/mve-vrint.d: New test. * testsuite/gas/arm/mve-vrint.s: New test. * testsuite/gas/arm/mve-vrmlaldavh.d: New test. * testsuite/gas/arm/mve-vrmlaldavh.s: New test. * testsuite/gas/arm/mve-vrshl.d: New test. * testsuite/gas/arm/mve-vrshl.s: New test. * testsuite/gas/arm/mve-vsbc.d: New test. * testsuite/gas/arm/mve-vsbc.s: New test. * testsuite/gas/arm/mve-vshl.d: New test. * testsuite/gas/arm/mve-vshl.s: New test. * testsuite/gas/arm/mve-vshlc.d: New test. * testsuite/gas/arm/mve-vshlc.s: New test. * testsuite/gas/arm/mve-vshll.d: New test. * testsuite/gas/arm/mve-vshll.s: New test. * testsuite/gas/arm/mve-vshr.d: New test. * testsuite/gas/arm/mve-vshr.s: New test. * testsuite/gas/arm/mve-vshrn.d: New test. * testsuite/gas/arm/mve-vshrn.s: New test. * testsuite/gas/arm/mve-vsli.d: New test. * testsuite/gas/arm/mve-vsli.s: New test. * testsuite/gas/arm/mve-vsri.d: New test. * testsuite/gas/arm/mve-vsri.s: New test. * testsuite/gas/arm/mve-vstld.d: New test. * testsuite/gas/arm/mve-vstld.s: New test. * testsuite/gas/arm/mve-vstrldr-1.d: New test. * testsuite/gas/arm/mve-vstrldr-1.s: New test. * testsuite/gas/arm/mve-vstrldr-2.d: New test. * testsuite/gas/arm/mve-vstrldr-2.s: New test. * testsuite/gas/arm/mve-vstrldr-3.d: New test. * testsuite/gas/arm/mve-vstrldr-3.s: New test.
2019-05-16 23:06:29 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* testsuite/gas/arm/mve-tailpredloop.d: New test.
* testsuite/gas/arm/mve-tailpredloop.s: New test.
* testsuite/gas/arm/mve-vabav.d: New test.
* testsuite/gas/arm/mve-vabav.s: New test.
* testsuite/gas/arm/mve-vabd.d: New test.
* testsuite/gas/arm/mve-vabd.s: New test.
* testsuite/gas/arm/mve-vabsneg.d: New test.
* testsuite/gas/arm/mve-vabsneg.s: New test.
* testsuite/gas/arm/mve-vadc.d: New test.
* testsuite/gas/arm/mve-vadc.s: New test.
* testsuite/gas/arm/mve-vaddlv.d: New test.
* testsuite/gas/arm/mve-vaddlv.s: New test.
* testsuite/gas/arm/mve-vaddsub.d: New test.
* testsuite/gas/arm/mve-vaddsub.s: New test.
* testsuite/gas/arm/mve-vaddv.d: New test.
* testsuite/gas/arm/mve-vaddv.s: New test.
* testsuite/gas/arm/mve-vand.d: New test.
* testsuite/gas/arm/mve-vand.s: New test.
* testsuite/gas/arm/mve-vbic.d: New test.
* testsuite/gas/arm/mve-vbic.s: New test.
* testsuite/gas/arm/mve-vbrsr.d: New test.
* testsuite/gas/arm/mve-vbrsr.s: New test.
* testsuite/gas/arm/mve-vcadd.d: New test.
* testsuite/gas/arm/mve-vcadd.s: New test.
* testsuite/gas/arm/mve-vcls.d: New test.
* testsuite/gas/arm/mve-vcls.s: New test.
* testsuite/gas/arm/mve-vclz.d: New test.
* testsuite/gas/arm/mve-vclz.s: New test.
* testsuite/gas/arm/mve-vcmla.d: New test.
* testsuite/gas/arm/mve-vcmla.s: New test.
* testsuite/gas/arm/mve-vcmp.d: New test.
* testsuite/gas/arm/mve-vcmp.s: New test.
* testsuite/gas/arm/mve-vcmul.d: New test.
* testsuite/gas/arm/mve-vcmul.s: New test.
* testsuite/gas/arm/mve-vcvt-1.d: New test.
* testsuite/gas/arm/mve-vcvt-1.s: New test.
* testsuite/gas/arm/mve-vcvt-2.d: New test.
* testsuite/gas/arm/mve-vcvt-2.s: New test.
* testsuite/gas/arm/mve-vcvt-3.d: New test.
* testsuite/gas/arm/mve-vcvt-3.s: New test.
* testsuite/gas/arm/mve-vcvt-4.d: New test.
* testsuite/gas/arm/mve-vcvt-4.s: New test.
* testsuite/gas/arm/mve-vddup.d: New test.
* testsuite/gas/arm/mve-vddup.s: New test.
* testsuite/gas/arm/mve-vdup.d: New test.
* testsuite/gas/arm/mve-vdup.s: New test.
* testsuite/gas/arm/mve-veor.d: New test.
* testsuite/gas/arm/mve-veor.s: New test.
* testsuite/gas/arm/mve-vfma-vfms.d: New test.
* testsuite/gas/arm/mve-vfma-vfms.s: New test.
* testsuite/gas/arm/mve-vfmas.d: New test.
* testsuite/gas/arm/mve-vfmas.s: New test.
* testsuite/gas/arm/mve-vhadd-vhsub-vrhadd.d: New test.
* testsuite/gas/arm/mve-vhadd-vhsub-vrhadd.s: New test.
* testsuite/gas/arm/mve-vhcadd.d: New test.
* testsuite/gas/arm/mve-vhcadd.s: New test.
* testsuite/gas/arm/mve-vmax-vmin.d: New test.
* testsuite/gas/arm/mve-vmax-vmin.s: New test.
* testsuite/gas/arm/mve-vmaxa-vmina.d: New test.
* testsuite/gas/arm/mve-vmaxa-vmina.s: New test.
* testsuite/gas/arm/mve-vmaxnm-vminnm.d: New test.
* testsuite/gas/arm/mve-vmaxnm-vminnm.s: New test.
* testsuite/gas/arm/mve-vmaxnma-vminnma.s: New test.
* testsuite/gas/arm/mve-vmaxnmv-vminnmv.d: New test.
* testsuite/gas/arm/mve-vmaxnmv-vminnmv.s: New test.
* testsuite/gas/arm/mve-vmaxv-vminv.d: New test.
* testsuite/gas/arm/mve-vmaxv-vminv.s: New test.
* testsuite/gas/arm/mve-vmla.d: New test.
* testsuite/gas/arm/mve-vmla.s: New test.
* testsuite/gas/arm/mve-vmladav.d: New test.
* testsuite/gas/arm/mve-vmladav.s: New test.
* testsuite/gas/arm/mve-vmlaldav.d: New test.
* testsuite/gas/arm/mve-vmlaldav.s: New test.
* testsuite/gas/arm/mve-vmlalv.d: New test.
* testsuite/gas/arm/mve-vmlalv.s: New test.
* testsuite/gas/arm/mve-vmlas.d: New test.
* testsuite/gas/arm/mve-vmlas.s: New test.
* testsuite/gas/arm/mve-vmlav.d: New test.
* testsuite/gas/arm/mve-vmlav.s: New test.
* testsuite/gas/arm/mve-vmlsdav.d: New test.
* testsuite/gas/arm/mve-vmlsdav.s: New test.
* testsuite/gas/arm/mve-vmlsldav.d: New test.
* testsuite/gas/arm/mve-vmlsldav.s: New test.
* testsuite/gas/arm/mve-vmov-1.d: New test.
* testsuite/gas/arm/mve-vmov-1.s: New test.
* testsuite/gas/arm/mve-vmov-2.d: New test.
* testsuite/gas/arm/mve-vmov-2.s: New test.
* testsuite/gas/arm/mve-vmul.d: New test.
* testsuite/gas/arm/mve-vmul.s: New test.
* testsuite/gas/arm/mve-vmulh.d: New test.
* testsuite/gas/arm/mve-vmulh.s: New test.
* testsuite/gas/arm/mve-vmullbt.d: New test.
* testsuite/gas/arm/mve-vmullbt.s: New test.
* testsuite/gas/arm/mve-vmvn.d: New test.
* testsuite/gas/arm/mve-vmvn.s: New test.
* testsuite/gas/arm/mve-vorn.d: New test.
* testsuite/gas/arm/mve-vorn.s: New test.
* testsuite/gas/arm/mve-vorr.d: New test.
* testsuite/gas/arm/mve-vorr.s: New test.
* testsuite/gas/arm/mve-vpnot.d: New test.
* testsuite/gas/arm/mve-vpnot.s: New test.
* testsuite/gas/arm/mve-vpsel.d: New test.
* testsuite/gas/arm/mve-vpsel.s: New test.
* testsuite/gas/arm/mve-vpt.d: New test.
* testsuite/gas/arm/mve-vpt.s: New test.
* testsuite/gas/arm/mve-vqabsneg.s: New test.
* testsuite/gas/arm/mve-vqaddsub.d: New test.
* testsuite/gas/arm/mve-vqaddsub.s: New test.
* testsuite/gas/arm/mve-vqdmladh.d: New test.
* testsuite/gas/arm/mve-vqdmladh.s: New test.
* testsuite/gas/arm/mve-vqdmlah.d: New test.
* testsuite/gas/arm/mve-vqdmlah.s: New test.
* testsuite/gas/arm/mve-vqdmlash.d: New test.
* testsuite/gas/arm/mve-vqdmlash.s: New test.
* testsuite/gas/arm/mve-vqdmlsdh.d: New test.
* testsuite/gas/arm/mve-vqdmlsdh.s: New test.
* testsuite/gas/arm/mve-vqdmulh.d: New test.
* testsuite/gas/arm/mve-vqdmulh.s: New test.
* testsuite/gas/arm/mve-vqdmull.d: New test.
* testsuite/gas/arm/mve-vqdmull.s: New test.
* testsuite/gas/arm/mve-vqmovn.d: New test.
* testsuite/gas/arm/mve-vqmovn.s: New test.
* testsuite/gas/arm/mve-vqrshl.d: New test.
* testsuite/gas/arm/mve-vqrshl.s: New test.
* testsuite/gas/arm/mve-vqrshrn.d: New test.
* testsuite/gas/arm/mve-vqrshrn.s: New test.
* testsuite/gas/arm/mve-vqshl.d: New test.
* testsuite/gas/arm/mve-vqshl.s: New test.
* testsuite/gas/arm/mve-vrev.d: New test.
* testsuite/gas/arm/mve-vrev.s: New test.
* testsuite/gas/arm/mve-vrint.d: New test.
* testsuite/gas/arm/mve-vrint.s: New test.
* testsuite/gas/arm/mve-vrmlaldavh.d: New test.
* testsuite/gas/arm/mve-vrmlaldavh.s: New test.
* testsuite/gas/arm/mve-vrshl.d: New test.
* testsuite/gas/arm/mve-vrshl.s: New test.
* testsuite/gas/arm/mve-vsbc.d: New test.
* testsuite/gas/arm/mve-vsbc.s: New test.
* testsuite/gas/arm/mve-vshl.d: New test.
* testsuite/gas/arm/mve-vshl.s: New test.
* testsuite/gas/arm/mve-vshlc.d: New test.
* testsuite/gas/arm/mve-vshlc.s: New test.
* testsuite/gas/arm/mve-vshll.d: New test.
* testsuite/gas/arm/mve-vshll.s: New test.
* testsuite/gas/arm/mve-vshr.d: New test.
* testsuite/gas/arm/mve-vshr.s: New test.
* testsuite/gas/arm/mve-vshrn.d: New test.
* testsuite/gas/arm/mve-vshrn.s: New test.
* testsuite/gas/arm/mve-vsli.d: New test.
* testsuite/gas/arm/mve-vsli.s: New test.
* testsuite/gas/arm/mve-vsri.d: New test.
* testsuite/gas/arm/mve-vsri.s: New test.
* testsuite/gas/arm/mve-vstld.d: New test.
* testsuite/gas/arm/mve-vstld.s: New test.
* testsuite/gas/arm/mve-vstrldr-1.d: New test.
* testsuite/gas/arm/mve-vstrldr-1.s: New test.
* testsuite/gas/arm/mve-vstrldr-2.d: New test.
* testsuite/gas/arm/mve-vstrldr-2.s: New test.
* testsuite/gas/arm/mve-vstrldr-3.d: New test.
* testsuite/gas/arm/mve-vstrldr-3.s: New test.
[PATCH 36/57][Arm][GAS] Add support for MVE instructions: wlstp, dlstp, letp and lctp gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (T16_32_TAB): Add new instructions. (do_t_loloop): Changed to handle tail predication variants. (md_apply_fix): Likewise. (insns): Add entries for MVE mnemonics. * testsuite/gas/arm/mve-tailpredloop-bad.d: New test. * testsuite/gas/arm/mve-tailpredloop-bad.l: New test. * testsuite/gas/arm/mve-tailpredloop-bad.s: New test. * testsuite/gas/arm/mve-tailpredloop.d: New test.
2019-05-16 20:52:51 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (T16_32_TAB): Add new instructions.
(do_t_loloop): Changed to handle tail predication variants.
(md_apply_fix): Likewise.
(insns): Add entries for MVE mnemonics.
* testsuite/gas/arm/mve-tailpredloop-bad.d: New test.
* testsuite/gas/arm/mve-tailpredloop-bad.l: New test.
* testsuite/gas/arm/mve-tailpredloop-bad.s: New test.
* testsuite/gas/arm/mve-tailpredloop.d: New test.
[PATCH 35/57][Arm][GAS] Add support for MVE instructions: vshlc and vshll gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (do_mve_vshll): New encoding function. (do_mve_vshlc): Likewise. (insns): Add entries for MVE mnemonics. * testsuite/gas/arm/mve-vshlc-bad.d: New test. * testsuite/gas/arm/mve-vshlc-bad.l: New test. * testsuite/gas/arm/mve-vshlc-bad.s: New test. * testsuite/gas/arm/mve-vshll-bad.d: New test. * testsuite/gas/arm/mve-vshll-bad.l: New test. * testsuite/gas/arm/mve-vshll-bad.s: New test.
2019-05-16 20:44:14 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_mve_vshll): New encoding function.
(do_mve_vshlc): Likewise.
(insns): Add entries for MVE mnemonics.
* testsuite/gas/arm/mve-vshlc-bad.d: New test.
* testsuite/gas/arm/mve-vshlc-bad.l: New test.
* testsuite/gas/arm/mve-vshlc-bad.s: New test.
* testsuite/gas/arm/mve-vshll-bad.d: New test.
* testsuite/gas/arm/mve-vshll-bad.l: New test.
* testsuite/gas/arm/mve-vshll-bad.s: New test.
[PATCH 34/57][Arm][GAS] Add support for MVE instructions: vshl and vqshl gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (enum operand_parse_code): Add new operand. (parse_operands): Handle new operand. (do_neon_shl_imm): Accept MVE variants. (do_neon_shl): Likewise. (do_neon_qshl_imm): Likewise. (do_neon_qshl): Likewise. (do_neon_qshlu_imm): Likewise. (insns): Likewise. * testsuite/gas/arm/mve-vqshl-bad.d: New test. * testsuite/gas/arm/mve-vqshl-bad.l: New test. * testsuite/gas/arm/mve-vqshl-bad.s: New test. * testsuite/gas/arm/mve-vshl-bad.d: New test. * testsuite/gas/arm/mve-vshl-bad.l: New test. * testsuite/gas/arm/mve-vshl-bad.s: New test.
2019-05-16 19:17:44 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (enum operand_parse_code): Add new operand.
(parse_operands): Handle new operand.
(do_neon_shl_imm): Accept MVE variants.
(do_neon_shl): Likewise.
(do_neon_qshl_imm): Likewise.
(do_neon_qshl): Likewise.
(do_neon_qshlu_imm): Likewise.
(insns): Likewise.
* testsuite/gas/arm/mve-vqshl-bad.d: New test.
* testsuite/gas/arm/mve-vqshl-bad.l: New test.
* testsuite/gas/arm/mve-vqshl-bad.s: New test.
* testsuite/gas/arm/mve-vshl-bad.d: New test.
* testsuite/gas/arm/mve-vshl-bad.l: New test.
* testsuite/gas/arm/mve-vshl-bad.s: New test.
[PATCH 33/57][Arm][GAS] Add support for MVE instructions: vshr, vrshr, vsli, vsri, vrev16, vrev32 and vrev64 gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (do_neon_sli): Accept MVE variants. (do_neon_sri): Likewise. (do_neon_rev): Likewise. (do_neon_rshift_round_imm): Likewise. (insns): Likewise. * testsuite/gas/arm/mve-vrev-bad.d: New test. * testsuite/gas/arm/mve-vrev-bad.l: New test. * testsuite/gas/arm/mve-vrev-bad.s: New test. * testsuite/gas/arm/mve-vshr-bad.d: New test. * testsuite/gas/arm/mve-vshr-bad.l: New test. * testsuite/gas/arm/mve-vshr-bad.s: New test. * testsuite/gas/arm/mve-vsli-bad.d: New test. * testsuite/gas/arm/mve-vsli-bad.l: New test. * testsuite/gas/arm/mve-vsli-bad.s: New test. * testsuite/gas/arm/mve-vsri-bad.d: New test. * testsuite/gas/arm/mve-vsri-bad.l: New test. * testsuite/gas/arm/mve-vsri-bad.s: New test.
2019-05-16 19:08:38 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_neon_sli): Accept MVE variants.
(do_neon_sri): Likewise.
(do_neon_rev): Likewise.
(do_neon_rshift_round_imm): Likewise.
(insns): Likewise.
* testsuite/gas/arm/mve-vrev-bad.d: New test.
* testsuite/gas/arm/mve-vrev-bad.l: New test.
* testsuite/gas/arm/mve-vrev-bad.s: New test.
* testsuite/gas/arm/mve-vshr-bad.d: New test.
* testsuite/gas/arm/mve-vshr-bad.l: New test.
* testsuite/gas/arm/mve-vshr-bad.s: New test.
* testsuite/gas/arm/mve-vsli-bad.d: New test.
* testsuite/gas/arm/mve-vsli-bad.l: New test.
* testsuite/gas/arm/mve-vsli-bad.s: New test.
* testsuite/gas/arm/mve-vsri-bad.d: New test.
* testsuite/gas/arm/mve-vsri-bad.l: New test.
* testsuite/gas/arm/mve-vsri-bad.s: New test.
[PATCH 32/57][Arm][GAS] Add support for MVE instructions: vrintn, vrintx, vrinta, vrintz, vrintm and vrintp gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (do_vrint_1): Accept MVE variants. (insns): Change entries to accept MVE variants. * testsuite/gas/arm/mve-vrint-bad.d: New test. * testsuite/gas/arm/mve-vrint-bad.l: New test. * testsuite/gas/arm/mve-vrint-bad.s: New test.
2019-05-16 19:07:22 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_vrint_1): Accept MVE variants.
(insns): Change entries to accept MVE variants.
* testsuite/gas/arm/mve-vrint-bad.d: New test.
* testsuite/gas/arm/mve-vrint-bad.l: New test.
* testsuite/gas/arm/mve-vrint-bad.s: New test.
[PATCH 31/57][Arm][GAS] Add support for MVE instructions: vshrn[tb], vrshrn[tb], vqshrn[tb], vqshrun[tb], vqrshrn[tb] and vqrshrun[tb] gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (M_MNEM_vshrnt, M_MNEM_vshrnb, M_MNEM_vrshrnt, M_MNEM_vqshrnt, M_MNEM_vqshrnb, M_MNEM_vqshrunt, M_MNEM_vqshrunb, M_MNEM_vrshrnb, M_MNEM_vqrshrnt, M_MNEM_vqrshrnb, M_MNEM_vqrshrunt, M_MNEM_vqrshrunb): New instruction encodings. (do_mve_vshrn): New encoding function. (insns): Add entries for MVE mnemonics. * testsuite/gas/arm/mve-vqrshrn-bad.d: New test. * testsuite/gas/arm/mve-vqrshrn-bad.l: New test. * testsuite/gas/arm/mve-vqrshrn-bad.s: New test. * testsuite/gas/arm/mve-vshrn-bad.d: New test. * testsuite/gas/arm/mve-vshrn-bad.l: New test. * testsuite/gas/arm/mve-vshrn-bad.s: New test.
2019-05-16 19:05:34 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (M_MNEM_vshrnt, M_MNEM_vshrnb, M_MNEM_vrshrnt,
M_MNEM_vqshrnt, M_MNEM_vqshrnb, M_MNEM_vqshrunt, M_MNEM_vqshrunb,
M_MNEM_vrshrnb, M_MNEM_vqrshrnt, M_MNEM_vqrshrnb, M_MNEM_vqrshrunt,
M_MNEM_vqrshrunb): New instruction encodings.
(do_mve_vshrn): New encoding function.
(insns): Add entries for MVE mnemonics.
* testsuite/gas/arm/mve-vqrshrn-bad.d: New test.
* testsuite/gas/arm/mve-vqrshrn-bad.l: New test.
* testsuite/gas/arm/mve-vqrshrn-bad.s: New test.
* testsuite/gas/arm/mve-vshrn-bad.d: New test.
* testsuite/gas/arm/mve-vshrn-bad.l: New test.
* testsuite/gas/arm/mve-vshrn-bad.s: New test.
[PATCH 30/57][Arm][GAS] Add support for MVE instructions: vqmovnt, vqmovnb, vqmovunt, vqmovunb, vqrshl and vrshl gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (M_MNEM_vqmovnt, M_MNEM_vqmovnb, M_MNEM_vqmovunt, M_MNEM_vqmovunb): New instruction encodings. (do_mve_vqmovn): New encoding function. (do_neon_rshl): Change to accepte MVE variants. (insns): Change entries and add new for MVE mnemonics. * testsuite/gas/arm/mve-vqmovn-bad.d: New test. * testsuite/gas/arm/mve-vqmovn-bad.l: New test. * testsuite/gas/arm/mve-vqmovn-bad.s: New test. * testsuite/gas/arm/mve-vqrshl-bad.d: New test. * testsuite/gas/arm/mve-vqrshl-bad.l: New test. * testsuite/gas/arm/mve-vqrshl-bad.s: New test. * testsuite/gas/arm/mve-vrshl-bad.d: New test. * testsuite/gas/arm/mve-vrshl-bad.l: New test. * testsuite/gas/arm/mve-vrshl-bad.s: New test.
2019-05-16 19:04:35 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (M_MNEM_vqmovnt, M_MNEM_vqmovnb,
M_MNEM_vqmovunt, M_MNEM_vqmovunb): New instruction encodings.
(do_mve_vqmovn): New encoding function.
(do_neon_rshl): Change to accepte MVE variants.
(insns): Change entries and add new for MVE mnemonics.
* testsuite/gas/arm/mve-vqmovn-bad.d: New test.
* testsuite/gas/arm/mve-vqmovn-bad.l: New test.
* testsuite/gas/arm/mve-vqmovn-bad.s: New test.
* testsuite/gas/arm/mve-vqrshl-bad.d: New test.
* testsuite/gas/arm/mve-vqrshl-bad.l: New test.
* testsuite/gas/arm/mve-vqrshl-bad.s: New test.
* testsuite/gas/arm/mve-vrshl-bad.d: New test.
* testsuite/gas/arm/mve-vrshl-bad.l: New test.
* testsuite/gas/arm/mve-vrshl-bad.s: New test.
[PATCH 29/57][Arm][GAS] Add support for MVE instructions: vqdmullt and vqdmullb gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (enum operand_parse_code): Add new operand. (parse_operands): Handle new operand. (do_mve_vqdmull): New encoding function. (insns): Add entry for MVE mnemonics. * testsuite/gas/arm/mve-vqdmull-bad.d: New test. * testsuite/gas/arm/mve-vqdmull-bad.l: New test. * testsuite/gas/arm/mve-vqdmull-bad.s: New test.
2019-05-16 19:03:30 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (enum operand_parse_code): Add new operand.
(parse_operands): Handle new operand.
(do_mve_vqdmull): New encoding function.
(insns): Add entry for MVE mnemonics.
* testsuite/gas/arm/mve-vqdmull-bad.d: New test.
* testsuite/gas/arm/mve-vqdmull-bad.l: New test.
* testsuite/gas/arm/mve-vqdmull-bad.s: New test.
[PATCH 28/57][Arm][GAS] Add support for MVE instructions: vqdmlah, vqrdmlah, vqdmlash, vqrdmlash, vqdmulh and vqrdmulh gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (enum operand_parse_code): Add new operand. (parse_operands): Handle new operand. (mve_encode_qqr): Handle new instructions. (do_neon_qdmulh): Add support for MVE variants. (do_neon_qrdmlah): Likewise. (do_mve_vqdmlah): New encoding function. (insns): Change entries and add new entries for MVE mnemonics. * testsuite/gas/arm/mve-vqdmulh-bad.d: New test. * testsuite/gas/arm/mve-vqdmulh-bad.l: New test. * testsuite/gas/arm/mve-vqdmulh-bad.s: New test.
2019-05-16 19:00:54 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (enum operand_parse_code): Add new operand.
(parse_operands): Handle new operand.
(mve_encode_qqr): Handle new instructions.
(do_neon_qdmulh): Add support for MVE variants.
(do_neon_qrdmlah): Likewise.
(do_mve_vqdmlah): New encoding function.
(insns): Change entries and add new entries for MVE mnemonics.
* testsuite/gas/arm/mve-vqdmulh-bad.d: New test.
* testsuite/gas/arm/mve-vqdmulh-bad.l: New test.
* testsuite/gas/arm/mve-vqdmulh-bad.s: New test.
[PATCH 27/57][Arm][GAS] Add support for MVE instructions: vqdmladh, vqrdmladh, vqdmlsdh and vqrdmlsdh gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (do_mve_vqdmladh): New encoding function. (insns): Add entries for MVE mnemonics. * testsuite/gas/arm/mve-vqdmladh-bad.d: New test. * testsuite/gas/arm/mve-vqdmladh-bad.l: New test. * testsuite/gas/arm/mve-vqdmladh-bad.s: New test. * testsuite/gas/arm/mve-vqdmlsdh-bad.d: New test. * testsuite/gas/arm/mve-vqdmlsdh-bad.l: New test. * testsuite/gas/arm/mve-vqdmlsdh-bad.s: New test.
2019-05-16 18:59:36 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_mve_vqdmladh): New encoding function.
(insns): Add entries for MVE mnemonics.
* testsuite/gas/arm/mve-vqdmladh-bad.d: New test.
* testsuite/gas/arm/mve-vqdmladh-bad.l: New test.
* testsuite/gas/arm/mve-vqdmladh-bad.s: New test.
* testsuite/gas/arm/mve-vqdmlsdh-bad.d: New test.
* testsuite/gas/arm/mve-vqdmlsdh-bad.l: New test.
* testsuite/gas/arm/mve-vqdmlsdh-bad.s: New test.
[PATCH 26/57][Arm][GAS] Add support for MVE instructions: vpnot and vpsel gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (do_mve_vpsel): New encoding function. (do_mve_vpnot): Likewise. (insns): Add entries for MVE mnemonics. * testsuite/gas/arm/mve-vpnot-bad.d: New test. * testsuite/gas/arm/mve-vpnot-bad.l: New test. * testsuite/gas/arm/mve-vpnot-bad.s: New test. * testsuite/gas/arm/mve-vpsel-bad.d: New test. * testsuite/gas/arm/mve-vpsel-bad.l: New test. * testsuite/gas/arm/mve-vpsel-bad.s: New test.
2019-05-16 18:57:44 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_mve_vpsel): New encoding function.
(do_mve_vpnot): Likewise.
(insns): Add entries for MVE mnemonics.
* testsuite/gas/arm/mve-vpnot-bad.d: New test.
* testsuite/gas/arm/mve-vpnot-bad.l: New test.
* testsuite/gas/arm/mve-vpnot-bad.s: New test.
* testsuite/gas/arm/mve-vpsel-bad.d: New test.
* testsuite/gas/arm/mve-vpsel-bad.l: New test.
* testsuite/gas/arm/mve-vpsel-bad.s: New test.
[PATCH 25/57][Arm][GAS] Add support for MVE instruction: vmvn, vqabs and vqneg gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (do_neon_mvn): Change to accept MVE variants. (do_neon_sat_abs_neg): Likewise. (insns): Likewise. * testsuite/gas/arm/mve-vmvn-bad.d: New test. * testsuite/gas/arm/mve-vmvn-bad.l: New test. * testsuite/gas/arm/mve-vmvn-bad.s: New test. * testsuite/gas/arm/mve-vqabsneg-bad.d: New test. * testsuite/gas/arm/mve-vqabsneg-bad.l: New test. * testsuite/gas/arm/mve-vqabsneg-bad.s: New test.
2019-05-16 18:52:29 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_neon_mvn): Change to accept MVE variants.
(do_neon_sat_abs_neg): Likewise.
(insns): Likewise.
* testsuite/gas/arm/mve-vmvn-bad.d: New test.
* testsuite/gas/arm/mve-vmvn-bad.l: New test.
* testsuite/gas/arm/mve-vmvn-bad.s: New test.
* testsuite/gas/arm/mve-vqabsneg-bad.d: New test.
* testsuite/gas/arm/mve-vqabsneg-bad.l: New test.
* testsuite/gas/arm/mve-vqabsneg-bad.s: New test.
[PATCH 24/57][Arm][GAS] Add support for MVE instructions: vmlas, vmulh and vrmulh gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (do_mve_vmlas): New encoding function. (do_mve_vmulh): Likewise. (insns): Add entries for MVE mnemonics. * testsuite/gas/arm/mve-vmlas-bad.d: New test. * testsuite/gas/arm/mve-vmlas-bad.l: New test. * testsuite/gas/arm/mve-vmlas-bad.s: New test. * testsuite/gas/arm/mve-vmulh-bad.d: New test. * testsuite/gas/arm/mve-vmulh-bad.l: New test. * testsuite/gas/arm/mve-vmulh-bad.s: New test.
2019-05-16 18:49:02 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_mve_vmlas): New encoding function.
(do_mve_vmulh): Likewise.
(insns): Add entries for MVE mnemonics.
* testsuite/gas/arm/mve-vmlas-bad.d: New test.
* testsuite/gas/arm/mve-vmlas-bad.l: New test.
* testsuite/gas/arm/mve-vmlas-bad.s: New test.
* testsuite/gas/arm/mve-vmulh-bad.d: New test.
* testsuite/gas/arm/mve-vmulh-bad.l: New test.
* testsuite/gas/arm/mve-vmulh-bad.s: New test.
[PATCH 23/57][Arm][GAS] Add support for MVE instructions: vmla, vmul, vqadd and vqsub gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (enum operand_parse_code): New operand. (parse_operands): Handle new operand. (mve_encode_qqr): Handle new instructions. (do_neon_dyadic_i64_su): Accept MVE variants. (neon_dyadic_misc): Likewise. (do_neon_mac_maybe_scalar): Likewise. (do_neon_mul): Likewise. (insns): Change to accept MVE variants. * testsuite/gas/arm/mve-vmla-bad.d: New test. * testsuite/gas/arm/mve-vmla-bad.l: New test. * testsuite/gas/arm/mve-vmla-bad.s: New test. * testsuite/gas/arm/mve-vmul-bad-1.d: New test. * testsuite/gas/arm/mve-vmul-bad-1.l: New test. * testsuite/gas/arm/mve-vmul-bad-1.s: New test. * testsuite/gas/arm/mve-vmul-bad-2.d: New test. * testsuite/gas/arm/mve-vmul-bad-2.l: New test. * testsuite/gas/arm/mve-vmul-bad-2.s: New test. * testsuite/gas/arm/mve-vqaddsub-bad.d: New test. * testsuite/gas/arm/mve-vqaddsub-bad.l: New test. * testsuite/gas/arm/mve-vqaddsub-bad.s: New test.
2019-05-16 18:46:48 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (enum operand_parse_code): New operand.
(parse_operands): Handle new operand.
(mve_encode_qqr): Handle new instructions.
(do_neon_dyadic_i64_su): Accept MVE variants.
(neon_dyadic_misc): Likewise.
(do_neon_mac_maybe_scalar): Likewise.
(do_neon_mul): Likewise.
(insns): Change to accept MVE variants.
* testsuite/gas/arm/mve-vmla-bad.d: New test.
* testsuite/gas/arm/mve-vmla-bad.l: New test.
* testsuite/gas/arm/mve-vmla-bad.s: New test.
* testsuite/gas/arm/mve-vmul-bad-1.d: New test.
* testsuite/gas/arm/mve-vmul-bad-1.l: New test.
* testsuite/gas/arm/mve-vmul-bad-1.s: New test.
* testsuite/gas/arm/mve-vmul-bad-2.d: New test.
* testsuite/gas/arm/mve-vmul-bad-2.l: New test.
* testsuite/gas/arm/mve-vmul-bad-2.s: New test.
* testsuite/gas/arm/mve-vqaddsub-bad.d: New test.
* testsuite/gas/arm/mve-vqaddsub-bad.l: New test.
* testsuite/gas/arm/mve-vqaddsub-bad.s: New test.
[PATCH 22/57][Arm][GAS] Add support for MVE instructions: vmlaldav, vmlalv, vmlsldav, vrmlaldavh, vrmlalvh and vrmlsldavh gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (M_MNEM_vmlaldav, M_MNEM_vmlaldava, M_MNEM_vmlaldavx, M_MNEM_vmlaldavax, M_MNEM_vmlsldav, M_MNEM_vmlsldava, M_MNEM_vmlsldavx, M_MNEM_vmlsldavax, M_MNEM_vrmlaldavhx, M_MNEM_vrmlaldavhax, M_MNEM_vrmlsldavh, M_MNEM_vrmlsldavha, M_MNEM_vrmlsldavhx, M_MNEM_vrmlsldavhax): New instruction encodings. (NEON_SHAPE_DEF): New shape (mve_encode_rrqq): New encoding helper function. (do_mve_vmlaldav): New encoding function. (do_mve_vrmlaldavh): New encoding function. (insns): Add entries for MVE mnemonics. * testsuite/gas/arm/mve-vmlaldav-bad.d: New test. * testsuite/gas/arm/mve-vmlaldav-bad.l: New test. * testsuite/gas/arm/mve-vmlaldav-bad.s: New test. * testsuite/gas/arm/mve-vmlalv-bad.d: New test. * testsuite/gas/arm/mve-vmlalv-bad.l: New test. * testsuite/gas/arm/mve-vmlalv-bad.s: New test. * testsuite/gas/arm/mve-vmlsldav-bad.d: New test. * testsuite/gas/arm/mve-vmlsldav-bad.l: New test. * testsuite/gas/arm/mve-vmlsldav-bad.s: New test. * testsuite/gas/arm/mve-vrmlaldavh-bad.d: New test. * testsuite/gas/arm/mve-vrmlaldavh-bad.l: New test. * testsuite/gas/arm/mve-vrmlaldavh-bad.s: New test.
2019-05-16 18:45:46 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (M_MNEM_vmlaldav, M_MNEM_vmlaldava,
M_MNEM_vmlaldavx, M_MNEM_vmlaldavax, M_MNEM_vmlsldav,
M_MNEM_vmlsldava, M_MNEM_vmlsldavx, M_MNEM_vmlsldavax,
M_MNEM_vrmlaldavhx, M_MNEM_vrmlaldavhax, M_MNEM_vrmlsldavh,
M_MNEM_vrmlsldavha, M_MNEM_vrmlsldavhx, M_MNEM_vrmlsldavhax): New
instruction encodings.
(NEON_SHAPE_DEF): New shape
(mve_encode_rrqq): New encoding helper function.
(do_mve_vmlaldav): New encoding function.
(do_mve_vrmlaldavh): New encoding function.
(insns): Add entries for MVE mnemonics.
* testsuite/gas/arm/mve-vmlaldav-bad.d: New test.
* testsuite/gas/arm/mve-vmlaldav-bad.l: New test.
* testsuite/gas/arm/mve-vmlaldav-bad.s: New test.
* testsuite/gas/arm/mve-vmlalv-bad.d: New test.
* testsuite/gas/arm/mve-vmlalv-bad.l: New test.
* testsuite/gas/arm/mve-vmlalv-bad.s: New test.
* testsuite/gas/arm/mve-vmlsldav-bad.d: New test.
* testsuite/gas/arm/mve-vmlsldav-bad.l: New test.
* testsuite/gas/arm/mve-vmlsldav-bad.s: New test.
* testsuite/gas/arm/mve-vrmlaldavh-bad.d: New test.
* testsuite/gas/arm/mve-vrmlaldavh-bad.l: New test.
* testsuite/gas/arm/mve-vrmlaldavh-bad.s: New test.
[PATCH 21/57][Arm][GAS] Add support for MVE instructions: vmaxv, vmaxav, vminv and vminav gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (M_MNEM_vmaxv, M_MNEM_vmaxav, M_MNEM_vminv, M_MNEM_vminav): New instruction encodings. (do_mve_vmaxv): New encoding function. (insns): Add entries for new MVE mnemonics. * testsuite/gas/arm/mve-vmaxv-vminv-bad.d: New test. * testsuite/gas/arm/mve-vmaxv-vminv-bad.l: New test. * testsuite/gas/arm/mve-vmaxv-vminv-bad.s: New test.
2019-05-16 18:44:19 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (M_MNEM_vmaxv, M_MNEM_vmaxav, M_MNEM_vminv,
M_MNEM_vminav): New instruction encodings.
(do_mve_vmaxv): New encoding function.
(insns): Add entries for new MVE mnemonics.
* testsuite/gas/arm/mve-vmaxv-vminv-bad.d: New test.
* testsuite/gas/arm/mve-vmaxv-vminv-bad.l: New test.
* testsuite/gas/arm/mve-vmaxv-vminv-bad.s: New test.
[PATCH 20/57][Arm][GAS] Add support for MVE instructions: vmaxnmv, vmaxnmav, vminnmv and vminnmav gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (do_mve_vmaxnmv): New encoding function. (insns): Add entries for new mnemonics. * testsuite/gas/arm/mve-vmaxnmv-vminnmv-bad.d: New test. * testsuite/gas/arm/mve-vmaxnmv-vminnmv-bad.l: New test. * testsuite/gas/arm/mve-vmaxnmv-vminnmv-bad.s: New test.
2019-05-16 18:42:52 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_mve_vmaxnmv): New encoding function.
(insns): Add entries for new mnemonics.
* testsuite/gas/arm/mve-vmaxnmv-vminnmv-bad.d: New test.
* testsuite/gas/arm/mve-vmaxnmv-vminnmv-bad.l: New test.
* testsuite/gas/arm/mve-vmaxnmv-vminnmv-bad.s: New test.
[PATCH 19/57][Arm][GAS] Add support for MVE instructions: vmax[nm][a] and vmin[nm][a] gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (do_mve_vmaxa_vmina): New encoding function. (do_mve_vmaxnma_vminnma): Likewise. (do_neon_dyadic_if_su): Change to support MVE variants. (do_vmaxnm): Likewise. (insns): Change to accept MVE variants and add new. * testsuite/gas/arm/mve-vmax-vmin-bad.d: New test. * testsuite/gas/arm/mve-vmax-vmin-bad.l: New test. * testsuite/gas/arm/mve-vmax-vmin-bad.s: New test. * testsuite/gas/arm/mve-vmaxa-vmina-bad.d: New test. * testsuite/gas/arm/mve-vmaxa-vmina-bad.l: New test. * testsuite/gas/arm/mve-vmaxa-vmina-bad.s: New test. * testsuite/gas/arm/mve-vmaxnm-vminnm-bad.d: New test. * testsuite/gas/arm/mve-vmaxnm-vminnm-bad.l: New test. * testsuite/gas/arm/mve-vmaxnm-vminnm-bad.s: New test. * testsuite/gas/arm/mve-vmaxnma-vminnma-bad.d: New test. * testsuite/gas/arm/mve-vmaxnma-vminnma-bad.l: New test. * testsuite/gas/arm/mve-vmaxnma-vminnma-bad.s: New test.
2019-05-16 18:41:52 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_mve_vmaxa_vmina): New encoding function.
(do_mve_vmaxnma_vminnma): Likewise.
(do_neon_dyadic_if_su): Change to support MVE variants.
(do_vmaxnm): Likewise.
(insns): Change to accept MVE variants and add new.
* testsuite/gas/arm/mve-vmax-vmin-bad.d: New test.
* testsuite/gas/arm/mve-vmax-vmin-bad.l: New test.
* testsuite/gas/arm/mve-vmax-vmin-bad.s: New test.
* testsuite/gas/arm/mve-vmaxa-vmina-bad.d: New test.
* testsuite/gas/arm/mve-vmaxa-vmina-bad.l: New test.
* testsuite/gas/arm/mve-vmaxa-vmina-bad.s: New test.
* testsuite/gas/arm/mve-vmaxnm-vminnm-bad.d: New test.
* testsuite/gas/arm/mve-vmaxnm-vminnm-bad.l: New test.
* testsuite/gas/arm/mve-vmaxnm-vminnm-bad.s: New test.
* testsuite/gas/arm/mve-vmaxnma-vminnma-bad.d: New test.
* testsuite/gas/arm/mve-vmaxnma-vminnma-bad.l: New test.
* testsuite/gas/arm/mve-vmaxnma-vminnma-bad.s: New test.
[PATCH 18/57][Arm][GAS] Add support for MVE instructions: vhcadd, vhadd, vhsub and vrhadd gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (enum operand_parse_code): New operand. (parse_operands): Handle new operand. (mve_encode_qqr): Change to support new instructions. (enum vfp_or_neon_is_neon_bits): Moved. (vfp_or_neon_is_neon): Moved. (check_simd_pred_availability): Moved. (do_neon_dyadic_i_su): Changed to support MVE variants. (neon_dyadic_misc): Changed mve_encode_qqr call. (do_mve_vbrsr): Likewise. (do_mve_vhcadd): New encoding function. (insns): Change existing to accept MVE variants and add new. * testsuite/gas/arm/mve-vhadd-vhsub-vrhadd-bad.d: New test. * testsuite/gas/arm/mve-vhadd-vhsub-vrhadd-bad.l: New test. * testsuite/gas/arm/mve-vhadd-vhsub-vrhadd-bad.s: New test. * testsuite/gas/arm/mve-vhcadd-bad.d: New test. * testsuite/gas/arm/mve-vhcadd-bad.l: New test. * testsuite/gas/arm/mve-vhcadd-bad.s: New test.
2019-05-16 18:40:26 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (enum operand_parse_code): New operand.
(parse_operands): Handle new operand.
(mve_encode_qqr): Change to support new instructions.
(enum vfp_or_neon_is_neon_bits): Moved.
(vfp_or_neon_is_neon): Moved.
(check_simd_pred_availability): Moved.
(do_neon_dyadic_i_su): Changed to support MVE variants.
(neon_dyadic_misc): Changed mve_encode_qqr call.
(do_mve_vbrsr): Likewise.
(do_mve_vhcadd): New encoding function.
(insns): Change existing to accept MVE variants and add new.
* testsuite/gas/arm/mve-vhadd-vhsub-vrhadd-bad.d: New test.
* testsuite/gas/arm/mve-vhadd-vhsub-vrhadd-bad.l: New test.
* testsuite/gas/arm/mve-vhadd-vhsub-vrhadd-bad.s: New test.
* testsuite/gas/arm/mve-vhcadd-bad.d: New test.
* testsuite/gas/arm/mve-vhcadd-bad.l: New test.
* testsuite/gas/arm/mve-vhcadd-bad.s: New test.
[PATCH 17/57][Arm][GAS] Add support for MVE instructions: vfma and vfms gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (do_neon_fmac): Change to support MVE variants. (insns): Change to accept MVE variants. * testsuite/gas/arm/mve-vfma-vfms-bad.d: New test. * testsuite/gas/arm/mve-vfma-vfms-bad.l: New test. * testsuite/gas/arm/mve-vfma-vfms-bad.s: New test.
2019-05-16 18:39:24 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_neon_fmac): Change to support MVE variants.
(insns): Change to accept MVE variants.
* testsuite/gas/arm/mve-vfma-vfms-bad.d: New test.
* testsuite/gas/arm/mve-vfma-vfms-bad.l: New test.
* testsuite/gas/arm/mve-vfma-vfms-bad.s: New test.
[PATCH 16/57][Arm][GAS] Add support for MVE instructions: vdup, vddup, vdwdup, vidup and viwdup gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (M_MNEM_vddup, M_MNEM_vdwdup, M_MNEM_vidup, M_MNEM_viwdup): New instruction encodings. (NEON_SHAPE_DEF): New shapes. (do_mve_viddup): New encoding function. (do_neon_dup): Change to support new MVE variants. (insns): Change existing to accept MVE variants and add new. * testsuite/gas/arm/mve-vddup-bad.d: New test. * testsuite/gas/arm/mve-vddup-bad.l: New test. * testsuite/gas/arm/mve-vddup-bad.s: New test. * testsuite/gas/arm/mve-vdup-bad.d: New test. * testsuite/gas/arm/mve-vdup-bad.l: New test. * testsuite/gas/arm/mve-vdup-bad.s: New test. * testsuite/gas/arm/mve-vidup-bad.d: New test. * testsuite/gas/arm/mve-vidup-bad.l: New test. * testsuite/gas/arm/mve-vidup-bad.s: New test.
2019-05-16 01:36:48 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (M_MNEM_vddup, M_MNEM_vdwdup, M_MNEM_vidup,
M_MNEM_viwdup): New instruction encodings.
(NEON_SHAPE_DEF): New shapes.
(do_mve_viddup): New encoding function.
(do_neon_dup): Change to support new MVE variants.
(insns): Change existing to accept MVE variants and add new.
* testsuite/gas/arm/mve-vddup-bad.d: New test.
* testsuite/gas/arm/mve-vddup-bad.l: New test.
* testsuite/gas/arm/mve-vddup-bad.s: New test.
* testsuite/gas/arm/mve-vdup-bad.d: New test.
* testsuite/gas/arm/mve-vdup-bad.l: New test.
* testsuite/gas/arm/mve-vdup-bad.s: New test.
* testsuite/gas/arm/mve-vidup-bad.d: New test.
* testsuite/gas/arm/mve-vidup-bad.l: New test.
* testsuite/gas/arm/mve-vidup-bad.s: New test.
[PATCH 15/57][Arm][GAS] Add support for MVE instructions: vcls, vclz and vfmas gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (do_mve_vfmas): New encoding function. (do_neon_cls): Change to support MVE variants. (do_neon_clz): Change to support MVE variants. (insns): Change to support MVE variants and add new. * testsuite/gas/arm/mve-vcls-bad.d: New test. * testsuite/gas/arm/mve-vcls-bad.l: New test. * testsuite/gas/arm/mve-vcls-bad.s: New test. * testsuite/gas/arm/mve-vclz-bad.d: New test. * testsuite/gas/arm/mve-vclz-bad.l: New test. * testsuite/gas/arm/mve-vclz-bad.s: New test. * testsuite/gas/arm/mve-vfmas-bad.d: New test. * testsuite/gas/arm/mve-vfmas-bad.l: New test. * testsuite/gas/arm/mve-vfmas-bad.s: New test.
2019-05-16 01:31:38 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_mve_vfmas): New encoding function.
(do_neon_cls): Change to support MVE variants.
(do_neon_clz): Change to support MVE variants.
(insns): Change to support MVE variants and add new.
* testsuite/gas/arm/mve-vcls-bad.d: New test.
* testsuite/gas/arm/mve-vcls-bad.l: New test.
* testsuite/gas/arm/mve-vcls-bad.s: New test.
* testsuite/gas/arm/mve-vclz-bad.d: New test.
* testsuite/gas/arm/mve-vclz-bad.l: New test.
* testsuite/gas/arm/mve-vclz-bad.s: New test.
* testsuite/gas/arm/mve-vfmas-bad.d: New test.
* testsuite/gas/arm/mve-vfmas-bad.l: New test.
* testsuite/gas/arm/mve-vfmas-bad.s: New test.
[PATCH 14/57][Arm][GAS] Add support for MVE instructions: vcadd, vcmla and vcmul gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (enum operand_parse_code): New operands. (parse_operands): Handle new operands. (do_mve_vcmul): New encoding function. (do_vcmla): Change to support MVE variants. (do_vcadd): Change to support MVE variants. (insns): Change existing to support MVE variants and add new. * testsuite/gas/arm/mve-vcadd-bad-1.d: New test. * testsuite/gas/arm/mve-vcadd-bad-1.l: New test. * testsuite/gas/arm/mve-vcadd-bad-1.s: New test. * testsuite/gas/arm/mve-vcadd-bad-2.d: New test. * testsuite/gas/arm/mve-vcadd-bad-2.l: New test. * testsuite/gas/arm/mve-vcadd-bad-2.s: New test. * testsuite/gas/arm/mve-vcmla-bad-1.d: New test. * testsuite/gas/arm/mve-vcmla-bad-1.l: New test. * testsuite/gas/arm/mve-vcmla-bad-1.s: New test. * testsuite/gas/arm/mve-vcmla-bad-2.d: New test. * testsuite/gas/arm/mve-vcmla-bad-2.l: New test. * testsuite/gas/arm/mve-vcmla-bad-2.s: New test. * testsuite/gas/arm/mve-vcmul-bad-1.d: New test. * testsuite/gas/arm/mve-vcmul-bad-1.l: New test. * testsuite/gas/arm/mve-vcmul-bad-1.s: New test. * testsuite/gas/arm/mve-vcmul-bad-2.d: New test. * testsuite/gas/arm/mve-vcmul-bad-2.l: New test. * testsuite/gas/arm/mve-vcmul-bad-2.s: New test.
2019-05-16 01:21:32 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (enum operand_parse_code): New operands.
(parse_operands): Handle new operands.
(do_mve_vcmul): New encoding function.
(do_vcmla): Change to support MVE variants.
(do_vcadd): Change to support MVE variants.
(insns): Change existing to support MVE variants and add new.
* testsuite/gas/arm/mve-vcadd-bad-1.d: New test.
* testsuite/gas/arm/mve-vcadd-bad-1.l: New test.
* testsuite/gas/arm/mve-vcadd-bad-1.s: New test.
* testsuite/gas/arm/mve-vcadd-bad-2.d: New test.
* testsuite/gas/arm/mve-vcadd-bad-2.l: New test.
* testsuite/gas/arm/mve-vcadd-bad-2.s: New test.
* testsuite/gas/arm/mve-vcmla-bad-1.d: New test.
* testsuite/gas/arm/mve-vcmla-bad-1.l: New test.
* testsuite/gas/arm/mve-vcmla-bad-1.s: New test.
* testsuite/gas/arm/mve-vcmla-bad-2.d: New test.
* testsuite/gas/arm/mve-vcmla-bad-2.l: New test.
* testsuite/gas/arm/mve-vcmla-bad-2.s: New test.
* testsuite/gas/arm/mve-vcmul-bad-1.d: New test.
* testsuite/gas/arm/mve-vcmul-bad-1.l: New test.
* testsuite/gas/arm/mve-vcmul-bad-1.s: New test.
* testsuite/gas/arm/mve-vcmul-bad-2.d: New test.
* testsuite/gas/arm/mve-vcmul-bad-2.l: New test.
* testsuite/gas/arm/mve-vcmul-bad-2.s: New test.
[PATCH 13/57][Arm][GAS] Add support for MVE instructions: vand, vbic, vorr, vorn and veor gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (enum operand_parse_code): New operands. (parse_operands): Handle new operands. (enum vfp_or_neon_is_neon_bits): Moved (vfp_or_neon_is_neon): Moved (check_simd_pred_availability): Moved. (do_neon_logic): Change to accept MVE variants. (insns): Changed to accept MVE variants. * testsuite/gas/arm/mve-vand-bad.d: New test. * testsuite/gas/arm/mve-vand-bad.l: New test. * testsuite/gas/arm/mve-vand-bad.s: New test. * testsuite/gas/arm/mve-vbic-bad.d: New test. * testsuite/gas/arm/mve-vbic-bad.l: New test. * testsuite/gas/arm/mve-vbic-bad.s: New test. * testsuite/gas/arm/mve-veor-bad.d: New test. * testsuite/gas/arm/mve-veor-bad.l: New test. * testsuite/gas/arm/mve-veor-bad.s: New test. * testsuite/gas/arm/mve-vorn-bad.d: New test. * testsuite/gas/arm/mve-vorn-bad.l: New test. * testsuite/gas/arm/mve-vorn-bad.s: New test. * testsuite/gas/arm/mve-vorr-bad.d: New test. * testsuite/gas/arm/mve-vorr-bad.l: New test. * testsuite/gas/arm/mve-vorr-bad.s: New test.
2019-05-16 00:40:06 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (enum operand_parse_code): New operands.
(parse_operands): Handle new operands.
(enum vfp_or_neon_is_neon_bits): Moved
(vfp_or_neon_is_neon): Moved
(check_simd_pred_availability): Moved.
(do_neon_logic): Change to accept MVE variants.
(insns): Changed to accept MVE variants.
* testsuite/gas/arm/mve-vand-bad.d: New test.
* testsuite/gas/arm/mve-vand-bad.l: New test.
* testsuite/gas/arm/mve-vand-bad.s: New test.
* testsuite/gas/arm/mve-vbic-bad.d: New test.
* testsuite/gas/arm/mve-vbic-bad.l: New test.
* testsuite/gas/arm/mve-vbic-bad.s: New test.
* testsuite/gas/arm/mve-veor-bad.d: New test.
* testsuite/gas/arm/mve-veor-bad.l: New test.
* testsuite/gas/arm/mve-veor-bad.s: New test.
* testsuite/gas/arm/mve-vorn-bad.d: New test.
* testsuite/gas/arm/mve-vorn-bad.l: New test.
* testsuite/gas/arm/mve-vorn-bad.s: New test.
* testsuite/gas/arm/mve-vorr-bad.d: New test.
* testsuite/gas/arm/mve-vorr-bad.l: New test.
* testsuite/gas/arm/mve-vorr-bad.s: New test.
[PATCH 12/57][Arm][GAS] Add support for MVE instructions: vaddlv and vaddv gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (M_MNEM_vaddlv, M_MNEM_vaddlva, M_MNEM_vaddv, M_MNEM_vaddva): New instruction encodings. (mve_encode_rq): New encoding helper function. (do_mve_vaddlv): New encoding function. (do_mve_vaddv): New encoding function. * testsuite/gas/arm/mve-vaddlv-bad.d: New test. * testsuite/gas/arm/mve-vaddlv-bad.l: New test. * testsuite/gas/arm/mve-vaddlv-bad.s: New test. * testsuite/gas/arm/mve-vaddv-bad.d: New test. * testsuite/gas/arm/mve-vaddv-bad.l: New test. * testsuite/gas/arm/mve-vaddv-bad.s: New test.
2019-05-16 00:38:12 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (M_MNEM_vaddlv, M_MNEM_vaddlva, M_MNEM_vaddv,
M_MNEM_vaddva): New instruction encodings.
(mve_encode_rq): New encoding helper function.
(do_mve_vaddlv): New encoding function.
(do_mve_vaddv): New encoding function.
* testsuite/gas/arm/mve-vaddlv-bad.d: New test.
* testsuite/gas/arm/mve-vaddlv-bad.l: New test.
* testsuite/gas/arm/mve-vaddlv-bad.s: New test.
* testsuite/gas/arm/mve-vaddv-bad.d: New test.
* testsuite/gas/arm/mve-vaddv-bad.l: New test.
* testsuite/gas/arm/mve-vaddv-bad.s: New test.
[PATCH 11/57][Arm][GAS] Add support for MVE instructions: vadc, vsbc and vbrsr gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (M_MNEM_vadc, M_MNEM_vadci, M_MNEM_vbrsr): New instruction encodings. (do_mve_vadc): New encoding instruction. (do_mve_vbrsr): Likewise. (do_mve_vsbc): Likewise. * testsuite/gas/arm/mve-vadc-bad.d: New test. * testsuite/gas/arm/mve-vadc-bad.l: New test. * testsuite/gas/arm/mve-vadc-bad.s: New test. * testsuite/gas/arm/mve-vbrsr-bad.d: New test. * testsuite/gas/arm/mve-vbrsr-bad.l: New test. * testsuite/gas/arm/mve-vbrsr-bad.s: New test. * testsuite/gas/arm/mve-vsbc-bad.d: New test. * testsuite/gas/arm/mve-vsbc-bad.l: New test. * testsuite/gas/arm/mve-vsbc-bad.s: New test.
2019-05-16 00:37:07 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (M_MNEM_vadc, M_MNEM_vadci, M_MNEM_vbrsr):
New instruction encodings.
(do_mve_vadc): New encoding instruction.
(do_mve_vbrsr): Likewise.
(do_mve_vsbc): Likewise.
* testsuite/gas/arm/mve-vadc-bad.d: New test.
* testsuite/gas/arm/mve-vadc-bad.l: New test.
* testsuite/gas/arm/mve-vadc-bad.s: New test.
* testsuite/gas/arm/mve-vbrsr-bad.d: New test.
* testsuite/gas/arm/mve-vbrsr-bad.l: New test.
* testsuite/gas/arm/mve-vbrsr-bad.s: New test.
* testsuite/gas/arm/mve-vsbc-bad.d: New test.
* testsuite/gas/arm/mve-vsbc-bad.l: New test.
* testsuite/gas/arm/mve-vsbc-bad.s: New test.
[PATCH 10/57][Arm][GAS] Add support for MVE instructions: vcmp and vpt gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (MVE_BAD_QREG): New error message. (enum operand_parse_code): Define new operand. (parse_operands): Handle new operand. (do_mve_vpt): Change for VPT blocks. (NEON_SHAPE_DEF): New shape. (neon_logbits): Moved. (LOW4): Moved (HI1): Moved (mve_get_vcmp_vpt_cond): New function to translate vpt conditions. (do_mve_vcmp): New encoding function. (do_vfp_nsyn_cmp): Changed to support MVE variants. (insns): Change to support MVE variants of vcmp and add vpt. * testsuite/gas/arm/mve-vcmp-bad-1.d: New test. * testsuite/gas/arm/mve-vcmp-bad-1.l: New test. * testsuite/gas/arm/mve-vcmp-bad-1.s: New test. * testsuite/gas/arm/mve-vcmp-bad-2.d: New test. * testsuite/gas/arm/mve-vcmp-bad-2.l: New test. * testsuite/gas/arm/mve-vcmp-bad-2.s: New test. * testsuite/gas/arm/mve-vpt-bad-1.d: New test. * testsuite/gas/arm/mve-vpt-bad-1.l: New test. * testsuite/gas/arm/mve-vpt-bad-1.s: New test. * testsuite/gas/arm/mve-vpt-bad-2.d: New test. * testsuite/gas/arm/mve-vpt-bad-2.l: New test. * testsuite/gas/arm/mve-vpt-bad-2.s: New test.
2019-05-16 00:35:43 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (MVE_BAD_QREG): New error message.
(enum operand_parse_code): Define new operand.
(parse_operands): Handle new operand.
(do_mve_vpt): Change for VPT blocks.
(NEON_SHAPE_DEF): New shape.
(neon_logbits): Moved.
(LOW4): Moved
(HI1): Moved
(mve_get_vcmp_vpt_cond): New function to translate vpt conditions.
(do_mve_vcmp): New encoding function.
(do_vfp_nsyn_cmp): Changed to support MVE variants.
(insns): Change to support MVE variants of vcmp and add vpt.
* testsuite/gas/arm/mve-vcmp-bad-1.d: New test.
* testsuite/gas/arm/mve-vcmp-bad-1.l: New test.
* testsuite/gas/arm/mve-vcmp-bad-1.s: New test.
* testsuite/gas/arm/mve-vcmp-bad-2.d: New test.
* testsuite/gas/arm/mve-vcmp-bad-2.l: New test.
* testsuite/gas/arm/mve-vcmp-bad-2.s: New test.
* testsuite/gas/arm/mve-vpt-bad-1.d: New test.
* testsuite/gas/arm/mve-vpt-bad-1.l: New test.
* testsuite/gas/arm/mve-vpt-bad-1.s: New test.
* testsuite/gas/arm/mve-vpt-bad-2.d: New test.
* testsuite/gas/arm/mve-vpt-bad-2.l: New test.
* testsuite/gas/arm/mve-vpt-bad-2.s: New test.
[PATCH 9/57][Arm][GAS] Add support for MVE instructions: vmov gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (struct arm_it): Expand isscalar field to be able to distinguish between types of scalar. (parse_typed_reg_or_scalar): Change to accept MVE scalar variants. (parse_scalar): Likewise. (parse_neon_mov): Accept MVE variant. (po_scalar_or_goto): Make use reg_type. (parse_operands): Change uses of po_scalar_or_goto. (do_vfp_sp_monadic): Change to accept MVE variants. (do_vfp_reg_from_sp): Likewise. (do_vfp_sp_from_reg): Likewise. (do_vfp_dp_rd_rm): Likewise. (do_vfp_dp_rd_rn_rm): Likewise. (do_vfp_dp_rm_rd_rn): Likewise. (M_MNEM_vmovlt, M_MNEM_vmovlb, M_MNEM_vmovnt, M_MNEM_vmovnb): New instruction encodings. (NEON_SHAPE_DEF): New shape. (do_mve_mov): New encoding fuction. (do_mve_movn): Likewise. (do_mve_movl): Likewise. (do_neon_mov): Change to accept MVE variants. (mcCE): New MACRO. (insns): Accept new MVE variants and instructions. * testsuite/gas/arm/mve-vmov-bad-1.d: New test. * testsuite/gas/arm/mve-vmov-bad-1.l: New test. * testsuite/gas/arm/mve-vmov-bad-1.s: New test. * testsuite/gas/arm/mve-vmov-bad-2.d: New test. * testsuite/gas/arm/mve-vmov-bad-2.l: New test. * testsuite/gas/arm/mve-vmov-bad-2.s: New test.
2019-05-16 00:31:25 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (struct arm_it): Expand isscalar field to be able to
distinguish between types of scalar.
(parse_typed_reg_or_scalar): Change to accept MVE scalar variants.
(parse_scalar): Likewise.
(parse_neon_mov): Accept MVE variant.
(po_scalar_or_goto): Make use reg_type.
(parse_operands): Change uses of po_scalar_or_goto.
(do_vfp_sp_monadic): Change to accept MVE variants.
(do_vfp_reg_from_sp): Likewise.
(do_vfp_sp_from_reg): Likewise.
(do_vfp_dp_rd_rm): Likewise.
(do_vfp_dp_rd_rn_rm): Likewise.
(do_vfp_dp_rm_rd_rn): Likewise.
(M_MNEM_vmovlt, M_MNEM_vmovlb, M_MNEM_vmovnt, M_MNEM_vmovnb): New
instruction encodings.
(NEON_SHAPE_DEF): New shape.
(do_mve_mov): New encoding fuction.
(do_mve_movn): Likewise.
(do_mve_movl): Likewise.
(do_neon_mov): Change to accept MVE variants.
(mcCE): New MACRO.
(insns): Accept new MVE variants and instructions.
* testsuite/gas/arm/mve-vmov-bad-1.d: New test.
* testsuite/gas/arm/mve-vmov-bad-1.l: New test.
* testsuite/gas/arm/mve-vmov-bad-1.s: New test.
* testsuite/gas/arm/mve-vmov-bad-2.d: New test.
* testsuite/gas/arm/mve-vmov-bad-2.l: New test.
* testsuite/gas/arm/mve-vmov-bad-2.s: New test.
[PATCH 8/57][Arm][GAS] Add support for MVE instructions: vcvt gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (enum operand_parse_code): Add new operand. (parse_operands): Handle new operand. (do_neon_cvt_1): Handle MVE variants. (do_neon_cvttb_1): Likewise. (insns): Accept MVE variants. * testsuite/gas/arm/mve-vcvt-bad-1.d: New test. * testsuite/gas/arm/mve-vcvt-bad-1.l: New test. * testsuite/gas/arm/mve-vcvt-bad-1.s: New test. * testsuite/gas/arm/mve-vcvt-bad-2.d: New test. * testsuite/gas/arm/mve-vcvt-bad-2.l: New test. * testsuite/gas/arm/mve-vcvt-bad-2.s: New test. * testsuite/gas/arm/mve-vcvt-bad-3.d: New test. * testsuite/gas/arm/mve-vcvt-bad-3.l: New test. * testsuite/gas/arm/mve-vcvt-bad-3.s: New test. * testsuite/gas/arm/mve-vcvt-bad-4.d: New test. * testsuite/gas/arm/mve-vcvt-bad-4.l: New test. * testsuite/gas/arm/mve-vcvt-bad-4.s: New test. * testsuite/gas/arm/mve-vcvt-bad.d: New test. * testsuite/gas/arm/mve-vcvt-bad.l: New test. * testsuite/gas/arm/mve-vcvt-bad.s: New test.
2019-05-16 00:21:53 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (enum operand_parse_code): Add new operand.
(parse_operands): Handle new operand.
(do_neon_cvt_1): Handle MVE variants.
(do_neon_cvttb_1): Likewise.
(insns): Accept MVE variants.
* testsuite/gas/arm/mve-vcvt-bad-1.d: New test.
* testsuite/gas/arm/mve-vcvt-bad-1.l: New test.
* testsuite/gas/arm/mve-vcvt-bad-1.s: New test.
* testsuite/gas/arm/mve-vcvt-bad-2.d: New test.
* testsuite/gas/arm/mve-vcvt-bad-2.l: New test.
* testsuite/gas/arm/mve-vcvt-bad-2.s: New test.
* testsuite/gas/arm/mve-vcvt-bad-3.d: New test.
* testsuite/gas/arm/mve-vcvt-bad-3.l: New test.
* testsuite/gas/arm/mve-vcvt-bad-3.s: New test.
* testsuite/gas/arm/mve-vcvt-bad-4.d: New test.
* testsuite/gas/arm/mve-vcvt-bad-4.l: New test.
* testsuite/gas/arm/mve-vcvt-bad-4.s: New test.
* testsuite/gas/arm/mve-vcvt-bad.d: New test.
* testsuite/gas/arm/mve-vcvt-bad.l: New test.
* testsuite/gas/arm/mve-vcvt-bad.s: New test.
[PATCH 7/57][Arm][GAS] Add support for MVE instructions: vstr/vldr gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (struct arm_it): Make immisreg field larger to hold type of register. (enum shift_kind): Add SHIFT_UXTW shift kind. (enum parse_shift_mode): Add SHIFT_UXTW_IMMEDIATE shift mode. (parse_shift): Handle new shift type. (parse_address_main): Accept new addressing modes. (M_MNEM_vstrb, M_MNEM_vstrh, M_MNEM_vstrw, M_MNEM_vstrd, M_MNEM_vldrb, M_MNEM_vldrh, M_MNEM_vldrw, M_MNEM_vldrd): New instruction encodings. (do_mve_vstr_vldr_QI): New encoding functions. (do_mve_vstr_vldr_RQ): Likewise. (do_mve_vstr_vldr_RI): Likewise. (do_mve_vstr_vldr): Likewise. * testsuite/gas/arm/mve-vldr-bad-1.d: New test. * testsuite/gas/arm/mve-vldr-bad-1.l: New test. * testsuite/gas/arm/mve-vldr-bad-1.s: New test. * testsuite/gas/arm/mve-vldr-bad-2.d: New test. * testsuite/gas/arm/mve-vldr-bad-2.l: New test. * testsuite/gas/arm/mve-vldr-bad-2.s: New test. * testsuite/gas/arm/mve-vldr-bad-3.d: New test. * testsuite/gas/arm/mve-vldr-bad-3.l: New test. * testsuite/gas/arm/mve-vldr-bad-3.s: New test. * testsuite/gas/arm/mve-vstr-bad-1.d: New test. * testsuite/gas/arm/mve-vstr-bad-1.l: New test. * testsuite/gas/arm/mve-vstr-bad-1.s: New test. * testsuite/gas/arm/mve-vstr-bad-2.d: New test. * testsuite/gas/arm/mve-vstr-bad-2.l: New test. * testsuite/gas/arm/mve-vstr-bad-2.s: New test. * testsuite/gas/arm/mve-vstr-bad-3.d: New test. * testsuite/gas/arm/mve-vstr-bad-3.l: New test. * testsuite/gas/arm/mve-vstr-bad-3.s: New test.
2019-05-16 00:20:46 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (struct arm_it): Make immisreg field larger to hold
type of register.
(enum shift_kind): Add SHIFT_UXTW shift kind.
(enum parse_shift_mode): Add SHIFT_UXTW_IMMEDIATE shift mode.
(parse_shift): Handle new shift type.
(parse_address_main): Accept new addressing modes.
(M_MNEM_vstrb, M_MNEM_vstrh, M_MNEM_vstrw, M_MNEM_vstrd,
M_MNEM_vldrb, M_MNEM_vldrh, M_MNEM_vldrw, M_MNEM_vldrd): New
instruction encodings.
(do_mve_vstr_vldr_QI): New encoding functions.
(do_mve_vstr_vldr_RQ): Likewise.
(do_mve_vstr_vldr_RI): Likewise.
(do_mve_vstr_vldr): Likewise.
* testsuite/gas/arm/mve-vldr-bad-1.d: New test.
* testsuite/gas/arm/mve-vldr-bad-1.l: New test.
* testsuite/gas/arm/mve-vldr-bad-1.s: New test.
* testsuite/gas/arm/mve-vldr-bad-2.d: New test.
* testsuite/gas/arm/mve-vldr-bad-2.l: New test.
* testsuite/gas/arm/mve-vldr-bad-2.s: New test.
* testsuite/gas/arm/mve-vldr-bad-3.d: New test.
* testsuite/gas/arm/mve-vldr-bad-3.l: New test.
* testsuite/gas/arm/mve-vldr-bad-3.s: New test.
* testsuite/gas/arm/mve-vstr-bad-1.d: New test.
* testsuite/gas/arm/mve-vstr-bad-1.l: New test.
* testsuite/gas/arm/mve-vstr-bad-1.s: New test.
* testsuite/gas/arm/mve-vstr-bad-2.d: New test.
* testsuite/gas/arm/mve-vstr-bad-2.l: New test.
* testsuite/gas/arm/mve-vstr-bad-2.s: New test.
* testsuite/gas/arm/mve-vstr-bad-3.d: New test.
* testsuite/gas/arm/mve-vstr-bad-3.l: New test.
* testsuite/gas/arm/mve-vstr-bad-3.s: New test.
[PATCH 6/57][Arm][GAS] Add support for MVE instructions: vst/vld{2,4} gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (enum it_instruction_type): Add MVE_UNPREDICABLE_INSN. (BAD_EL_TYPE): New error message. (parse_neon_el_struct_list): Adapt to be able to accept MVE variant. (parse_address_main): Likewise. (group_reloc_type): Add GROUP_MVE. (enum operand_parse_code): Add new operands. (parse_operands): Handle new operands. (M_MNEM_vst20, M_MNEM_vst21, M_MNEM_vst40, M_MNEM_vst41, M_MNEM_vst42, M_MNEM_vst43, M_MNEM_vld20, M_MNEM_vld21, M_MNEM_vld40, M_MNEM_vld41, M_MNEM_vld42, M_MNEM_vld43): New encodings. (do_mve_vst_vld): New encoding function. (do_neon_ld_st_interleave): Use BAD_EL_TYPE. (it_fsm_pre_encode): Handle new it_instruction_type (handle_pred_state): Likewise. * testsuite/gas/arm/mve-vstld-bad.d: New test. * testsuite/gas/arm/mve-vstld-bad.l: New test. * testsuite/gas/arm/mve-vstld-bad.s: New test.
2019-05-16 00:05:58 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (enum it_instruction_type): Add MVE_UNPREDICABLE_INSN.
(BAD_EL_TYPE): New error message.
(parse_neon_el_struct_list): Adapt to be able to accept MVE variant.
(parse_address_main): Likewise.
(group_reloc_type): Add GROUP_MVE.
(enum operand_parse_code): Add new operands.
(parse_operands): Handle new operands.
(M_MNEM_vst20, M_MNEM_vst21, M_MNEM_vst40, M_MNEM_vst41, M_MNEM_vst42,
M_MNEM_vst43, M_MNEM_vld20, M_MNEM_vld21, M_MNEM_vld40, M_MNEM_vld41,
M_MNEM_vld42, M_MNEM_vld43): New encodings.
(do_mve_vst_vld): New encoding function.
(do_neon_ld_st_interleave): Use BAD_EL_TYPE.
(it_fsm_pre_encode): Handle new it_instruction_type
(handle_pred_state): Likewise.
* testsuite/gas/arm/mve-vstld-bad.d: New test.
* testsuite/gas/arm/mve-vstld-bad.l: New test.
* testsuite/gas/arm/mve-vstld-bad.s: New test.
[PATCH 5/57][Arm][GAS] Add support for MVE instructions: vmull{b,t} gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (BAD_MVE_AUTO): New error message. (BAD_MVE_SRCDEST): Likewise. (mark_feature_used): Diagnose MVE only instructions when in auto-detection mode or -march=all. (enum operand_parse_code): Define new operand. (parse_operands): Handle new operand. (M_MNEM_vmullt, M_MNEM_vmullb): New encodings. (mve_encode_qqq): New encoding helper function. (do_mve_vmull): New encoding function. (insns): Handle new instructions. * testsuite/gas/arm/mve-vmullbt-bad.d: New test. * testsuite/gas/arm/mve-vmullbt-bad.l: New test. * testsuite/gas/arm/mve-vmullbt-bad.s: New test.
2019-05-15 23:56:30 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (BAD_MVE_AUTO): New error message.
(BAD_MVE_SRCDEST): Likewise.
(mark_feature_used): Diagnose MVE only instructions when in
auto-detection mode or -march=all.
(enum operand_parse_code): Define new operand.
(parse_operands): Handle new operand.
(M_MNEM_vmullt, M_MNEM_vmullb): New encodings.
(mve_encode_qqq): New encoding helper function.
(do_mve_vmull): New encoding function.
(insns): Handle new instructions.
* testsuite/gas/arm/mve-vmullbt-bad.d: New test.
* testsuite/gas/arm/mve-vmullbt-bad.l: New test.
* testsuite/gas/arm/mve-vmullbt-bad.s: New test.
[PATCH 4/57][Arm][GAS] Add support for MVE instructions: vabav, vmladav and vmlsdav gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (struct asm_opcode): Make avalue a full int. (BAD_ODD, BAD_EVEN, BAD_SIMD_TYPE): New errors. (enum operand_parse_code): Handle new operands. (parse_operands): Likewise. (M_MNEM_vabav, M_MNEM_vmladav, M_MNEM_vmladava, M_MNEM_vmladavx, M_MNEM_vmladavax, M_MNEM_vmlsdav, M_MNEM_vmlsdava, M_MNEM_vmlsdavx, M_MNEM_vmlsdavax): Define new encodings. (NEON_SHAPE_DEF): Add new shape. (neon_check_type): Use BAD_SIMD_TYPE. (mve_encode_rqq): New encoding helper function. (do_mve_vabav, do_mve_vmladav): New encoding functions. (mCEF): New MACRO. * testsuite/gas/arm/mve-vabav-bad.d: New test. * testsuite/gas/arm/mve-vabav-bad.l: New test. * testsuite/gas/arm/mve-vabav-bad.s: New test. * testsuite/gas/arm/mve-vmladav-bad.d: New test. * testsuite/gas/arm/mve-vmladav-bad.l: New test. * testsuite/gas/arm/mve-vmladav-bad.s: New test. * testsuite/gas/arm/mve-vmlav-bad.d: New test. * testsuite/gas/arm/mve-vmlav-bad.l: New test. * testsuite/gas/arm/mve-vmlav-bad.s: New test. * testsuite/gas/arm/mve-vmlsdav-bad.d: New test. * testsuite/gas/arm/mve-vmlsdav-bad.l: New test. * testsuite/gas/arm/mve-vmlsdav-bad.s: New test.
2019-05-15 23:54:23 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (struct asm_opcode): Make avalue a full int.
(BAD_ODD, BAD_EVEN, BAD_SIMD_TYPE): New errors.
(enum operand_parse_code): Handle new operands.
(parse_operands): Likewise.
(M_MNEM_vabav, M_MNEM_vmladav, M_MNEM_vmladava, M_MNEM_vmladavx,
M_MNEM_vmladavax, M_MNEM_vmlsdav, M_MNEM_vmlsdava, M_MNEM_vmlsdavx,
M_MNEM_vmlsdavax): Define new encodings.
(NEON_SHAPE_DEF): Add new shape.
(neon_check_type): Use BAD_SIMD_TYPE.
(mve_encode_rqq): New encoding helper function.
(do_mve_vabav, do_mve_vmladav): New encoding functions.
(mCEF): New MACRO.
* testsuite/gas/arm/mve-vabav-bad.d: New test.
* testsuite/gas/arm/mve-vabav-bad.l: New test.
* testsuite/gas/arm/mve-vabav-bad.s: New test.
* testsuite/gas/arm/mve-vmladav-bad.d: New test.
* testsuite/gas/arm/mve-vmladav-bad.l: New test.
* testsuite/gas/arm/mve-vmladav-bad.s: New test.
* testsuite/gas/arm/mve-vmlav-bad.d: New test.
* testsuite/gas/arm/mve-vmlav-bad.l: New test.
* testsuite/gas/arm/mve-vmlav-bad.s: New test.
* testsuite/gas/arm/mve-vmlsdav-bad.d: New test.
* testsuite/gas/arm/mve-vmlsdav-bad.l: New test.
* testsuite/gas/arm/mve-vmlsdav-bad.s: New test.
[PATCH 3/57][Arm][GAS] Add support for MVE instructions: vabs and vneg gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (do_neon_abs_neg): Make it accept MVE variant. (insns): Change vabs and vneg entries to accept MVE variants. * testsuite/gas/arm/mve-vabsneg-bad-1.d: New test. * testsuite/gas/arm/mve-vabsneg-bad-1.l: New test. * testsuite/gas/arm/mve-vabsneg-bad-1.s: New test. * testsuite/gas/arm/mve-vabsneg-bad-2.d: New test. * testsuite/gas/arm/mve-vabsneg-bad-2.l: New test. * testsuite/gas/arm/mve-vabsneg-bad-2.s: New test.
2019-05-15 23:52:50 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_neon_abs_neg): Make it accept MVE variant.
(insns): Change vabs and vneg entries to accept MVE variants.
* testsuite/gas/arm/mve-vabsneg-bad-1.d: New test.
* testsuite/gas/arm/mve-vabsneg-bad-1.l: New test.
* testsuite/gas/arm/mve-vabsneg-bad-1.s: New test.
* testsuite/gas/arm/mve-vabsneg-bad-2.d: New test.
* testsuite/gas/arm/mve-vabsneg-bad-2.l: New test.
* testsuite/gas/arm/mve-vabsneg-bad-2.s: New test.
[PATCH 2/57][Arm][GAS] Add support for MVE instructions: vpst, vadd, vsub and vabd gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (enum it_instruction_type): Rename to... (enum pred_instruction_type): ... this. Include VPT types. (it_insn_type): Rename to ... (pred_insn_type): .. this. (arm_it): Change comment. (enum arm_reg_type): Add new value. (reg_expected_msgs): New entry. (asm_opcode): Add mayBeVecPred member. (BAD_SYNTAX, BAD_NOT_VPT, BAD_OUT_VPT, BAD_VPT_COND, MVE_NOT_IT, MVE_NOT_VPT, MVE_BAD_PC, MVE_BAD_SP): New diagnostic MACROS. (arm_vcond_hsh): New table for vector condition codes. (now_it): Rename to ... (now_pred): ... this. (now_it_compatible): Rename to ... (now_pred_compatible): ... this. (in_it_block): Rename to ... (in_pred_block): ... this. (handle_it_state): Rename to ... (handle_pred_state): ... this. And change it to accept VPT blocks. (set_it_insn_type): Rename to ... (set_pred_insn_type): ... this. (set_it_insn_type_nonvoid): Rename to ... (set_pred_insn_type_nonvoid): ... this. (set_it_insn_type_last): Rename to ... (set_pred_insn_type_last): ... this. (record_feature_use): Moved. (mark_feature_used): Likewise. (parse_typed_reg_or_scalar): Add new case for REG_TYPE_MQ. (emit_insn): Use renamed functions and variables. (enum operand_parse_code): Add new operands. (parse_operands): Handle new operands. (do_scalar_fp16_v82_encode): Change predication detection. (do_it): Use renamed functions and variables. (do_t_add_sub): Likewise. (do_t_arit3): Likewise. (do_t_arit3c): Likewise. (do_t_blx): Likewise. (do_t_branch): Likewise. (do_t_bkpt_hlt1): Likewise. (do_t_branch23): Likewise. (do_t_bx): Likewise. (do_t_bxj): Likewise. (do_t_cond): Likewise. (do_t_csdb): Likewise. (do_t_cps): Likewise. (do_t_cpsi): Likewise. (do_t_cbz): Likewise. (do_t_it): Likewise. (do_mve_vpt): New function to handle VPT blocks. (encode_thumb2_multi): Use renamed functions and variables. (do_t_ldst): Use renamed functions and variables. (do_t_mov_cmp): Likewise. (do_t_mvn_tst): Likewise. (do_t_mul): Likewise. (do_t_nop): Likewise. (do_t_neg): Likewise. (do_t_rsb): Likewise. (do_t_setend): Likewise. (do_t_shift): Likewise. (do_t_smc): Likewise. (do_t_tb): Likewise. (do_t_udf): Likewise. (do_t_loloop): Likewise. (do_neon_cvt_1): Likewise. (do_vfp_nsyn_cvt_fpv8): Likewise. (do_vsel): Likewise. (do_vmaxnm): Likewise. (do_vrint_1): Likewise. (do_crypto_2op_1): Likewise. (do_crypto_3op_1): Likewise. (do_crc32_1): Likewise. (it_fsm_pre_encode): Likewise. (it_fsm_post_encode): Likewise. (force_automatic_it_block_close): Likewise. (check_it_blocks_finished): Likewise. (check_pred_blocks_finished): Likewise. (arm_cleanup): Likewise. (now_it_add_mask): Rename to ... (now_pred_add_mask): ... this. And use new variables and functions. (NEON_ENC_TAB): Add entries for vabdl, vaddl and vsubl. (N_I_MVE, N_F_MVE, N_SU_MVE): New MACROs. (neon_check_type): Generalize error message. (mve_encode_qqr): New MVE generic encoding function. (neon_dyadic_misc): Change to accept MVE variants. (do_neon_dyadic_if_su): Likewise. (do_neon_addsub_if_i): Likewise. (do_neon_dyadic_long): Likewise. (vfp_or_neon_is_neon): Add extra checks. (check_simd_pred_availability): Helper function to check SIMD instruction availability with respect to predication. (enum opcode_tag): New suffix value. (opcode_lookup): Change to handle VPT blocks. (new_automatic_it_block): Rename to ... (close_automatic_it_block): ...this. (TxCE, TxC3, TxC3w, TUE, TUEc, TUF, CE, C3, ToC, ToU, toC, toU, CL, cCE, cCL, C3E, xCM_, UE, UF, NUF, nUF, NCE_tag, NCE, NCEF, nCE_tag, nCE, nCEF): Add default value for new field. (mCEF, mnCEF, mnCE, MNUF, mnUF, mToC, MNCE, MNCEF): New MACROs. (insns): Redefine vadd, vsub, cabd, vabdl, vaddl, vsubl to accept MVE variants. Add entries for vscclrm, and vpst. (md_begin): Add arm_vcond_hsh initialization. * config/tc-arm.h (enum it_state): Rename to... (enum pred_state): ...this. (struct current_it): Rename to... (struct current_pred): ...this. (enum pred_type): New enum. (struct arm_segment_info_type): Use current_pred. * testsuite/gas/arm/armv8_3-a-fp-bad.l: Update error message. * testsuite/gas/arm/armv8_3-a-simd-bad.l: Update error message. * testsuite/gas/arm/dotprod-illegal.l: Update error message. * testsuite/gas/arm/mve-vaddsubabd-bad-1.d: New test. * testsuite/gas/arm/mve-vaddsubabd-bad-1.l: New test. * testsuite/gas/arm/mve-vaddsubabd-bad-1.s: New test. * testsuite/gas/arm/mve-vaddsubabd-bad-2.d: New test. * testsuite/gas/arm/mve-vaddsubabd-bad-2.l: New test. * testsuite/gas/arm/mve-vaddsubabd-bad-2.s: New test. * testsuite/gas/arm/mve-vpst-bad.d: New test. * testsuite/gas/arm/mve-vpst-bad.l: New test. * testsuite/gas/arm/mve-vpst-bad.s: New test. * testsuite/gas/arm/neon-ldst-es-bad.l: Updated error message.
2019-05-15 23:50:58 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (enum it_instruction_type): Rename to...
(enum pred_instruction_type): ... this. Include VPT types.
(it_insn_type): Rename to ...
(pred_insn_type): .. this.
(arm_it): Change comment.
(enum arm_reg_type): Add new value.
(reg_expected_msgs): New entry.
(asm_opcode): Add mayBeVecPred member.
(BAD_SYNTAX, BAD_NOT_VPT, BAD_OUT_VPT, BAD_VPT_COND, MVE_NOT_IT,
MVE_NOT_VPT, MVE_BAD_PC, MVE_BAD_SP): New diagnostic MACROS.
(arm_vcond_hsh): New table for vector condition codes.
(now_it): Rename to ...
(now_pred): ... this.
(now_it_compatible): Rename to ...
(now_pred_compatible): ... this.
(in_it_block): Rename to ...
(in_pred_block): ... this.
(handle_it_state): Rename to ...
(handle_pred_state): ... this. And change it to accept VPT blocks.
(set_it_insn_type): Rename to ...
(set_pred_insn_type): ... this.
(set_it_insn_type_nonvoid): Rename to ...
(set_pred_insn_type_nonvoid): ... this.
(set_it_insn_type_last): Rename to ...
(set_pred_insn_type_last): ... this.
(record_feature_use): Moved.
(mark_feature_used): Likewise.
(parse_typed_reg_or_scalar): Add new case for REG_TYPE_MQ.
(emit_insn): Use renamed functions and variables.
(enum operand_parse_code): Add new operands.
(parse_operands): Handle new operands.
(do_scalar_fp16_v82_encode): Change predication detection.
(do_it): Use renamed functions and variables.
(do_t_add_sub): Likewise.
(do_t_arit3): Likewise.
(do_t_arit3c): Likewise.
(do_t_blx): Likewise.
(do_t_branch): Likewise.
(do_t_bkpt_hlt1): Likewise.
(do_t_branch23): Likewise.
(do_t_bx): Likewise.
(do_t_bxj): Likewise.
(do_t_cond): Likewise.
(do_t_csdb): Likewise.
(do_t_cps): Likewise.
(do_t_cpsi): Likewise.
(do_t_cbz): Likewise.
(do_t_it): Likewise.
(do_mve_vpt): New function to handle VPT blocks.
(encode_thumb2_multi): Use renamed functions and variables.
(do_t_ldst): Use renamed functions and variables.
(do_t_mov_cmp): Likewise.
(do_t_mvn_tst): Likewise.
(do_t_mul): Likewise.
(do_t_nop): Likewise.
(do_t_neg): Likewise.
(do_t_rsb): Likewise.
(do_t_setend): Likewise.
(do_t_shift): Likewise.
(do_t_smc): Likewise.
(do_t_tb): Likewise.
(do_t_udf): Likewise.
(do_t_loloop): Likewise.
(do_neon_cvt_1): Likewise.
(do_vfp_nsyn_cvt_fpv8): Likewise.
(do_vsel): Likewise.
(do_vmaxnm): Likewise.
(do_vrint_1): Likewise.
(do_crypto_2op_1): Likewise.
(do_crypto_3op_1): Likewise.
(do_crc32_1): Likewise.
(it_fsm_pre_encode): Likewise.
(it_fsm_post_encode): Likewise.
(force_automatic_it_block_close): Likewise.
(check_it_blocks_finished): Likewise.
(check_pred_blocks_finished): Likewise.
(arm_cleanup): Likewise.
(now_it_add_mask): Rename to ...
(now_pred_add_mask): ... this. And use new variables and functions.
(NEON_ENC_TAB): Add entries for vabdl, vaddl and vsubl.
(N_I_MVE, N_F_MVE, N_SU_MVE): New MACROs.
(neon_check_type): Generalize error message.
(mve_encode_qqr): New MVE generic encoding function.
(neon_dyadic_misc): Change to accept MVE variants.
(do_neon_dyadic_if_su): Likewise.
(do_neon_addsub_if_i): Likewise.
(do_neon_dyadic_long): Likewise.
(vfp_or_neon_is_neon): Add extra checks.
(check_simd_pred_availability): Helper function to check SIMD
instruction availability with respect to predication.
(enum opcode_tag): New suffix value.
(opcode_lookup): Change to handle VPT blocks.
(new_automatic_it_block): Rename to ...
(close_automatic_it_block): ...this.
(TxCE, TxC3, TxC3w, TUE, TUEc, TUF, CE, C3, ToC, ToU,
toC, toU, CL, cCE, cCL, C3E, xCM_, UE, UF, NUF, nUF,
NCE_tag, NCE, NCEF, nCE_tag, nCE, nCEF): Add default value for new
field.
(mCEF, mnCEF, mnCE, MNUF, mnUF, mToC, MNCE, MNCEF): New MACROs.
(insns): Redefine vadd, vsub, cabd, vabdl, vaddl, vsubl to accept MVE
variants. Add entries for vscclrm, and vpst.
(md_begin): Add arm_vcond_hsh initialization.
* config/tc-arm.h (enum it_state): Rename to...
(enum pred_state): ...this.
(struct current_it): Rename to...
(struct current_pred): ...this.
(enum pred_type): New enum.
(struct arm_segment_info_type): Use current_pred.
* testsuite/gas/arm/armv8_3-a-fp-bad.l: Update error message.
* testsuite/gas/arm/armv8_3-a-simd-bad.l: Update error message.
* testsuite/gas/arm/dotprod-illegal.l: Update error message.
* testsuite/gas/arm/mve-vaddsubabd-bad-1.d: New test.
* testsuite/gas/arm/mve-vaddsubabd-bad-1.l: New test.
* testsuite/gas/arm/mve-vaddsubabd-bad-1.s: New test.
* testsuite/gas/arm/mve-vaddsubabd-bad-2.d: New test.
* testsuite/gas/arm/mve-vaddsubabd-bad-2.l: New test.
* testsuite/gas/arm/mve-vaddsubabd-bad-2.s: New test.
* testsuite/gas/arm/mve-vpst-bad.d: New test.
* testsuite/gas/arm/mve-vpst-bad.l: New test.
* testsuite/gas/arm/mve-vpst-bad.s: New test.
* testsuite/gas/arm/neon-ldst-es-bad.l: Updated error message.
[PATCH 1/57][Arm][GAS]: Add support for +mve and +mve.fp bfd/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * elf32-arm.c (elf32_arm_merge_eabi_attributes): Add case for Tag_MVE_arch. binutils/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * readelf.c (arm_attr_tag_MVE_arch): New array for Tag_MVE_arch values. (arm_attr_public_tag arm_attr_public_tags): Add case for Tag_MVE_arch. elfcpp/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * arm.h (Tag_MVE_arch): Define new enum value. gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (mve_ext, mve_fp_ext): New features. (armv8_1m_main_ext_table): Add new extensions. (aeabi_set_public_attributes): Translate new features to new build attributes. (arm_convert_symbolic_attribute): Add Tag_MVE_arch. * doc/c-arm.texi: Document new extensions and new build attribute. include/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * elf/arm.h (Tag_MVE_arch): Define new enum value. * opcode/arm.h (FPU_MVE, FPU_MVE_FP): New MACROs for new features.
2019-05-15 23:44:57 +08:00
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (mve_ext, mve_fp_ext): New features.
(armv8_1m_main_ext_table): Add new extensions.
(aeabi_set_public_attributes): Translate new features to new build attributes.
(arm_convert_symbolic_attribute): Add Tag_MVE_arch.
* doc/c-arm.texi: Document new extensions and new build attribute.
S12Z: New option -mreg-prefix Add a new machine dependent option to set a prefix for register names. gas/ * config/tc-s12z.c (register_prefix): New variable. (md_show_usage, md_parse_option): parse the new option. (lex_reg_name): Scan the prefix if one is set. * doc/c-s12z.texi (S12Z-Opts): Document the new option. * testsuite/gas/s12z/reg-prefix.d: New file. * testsuite/gas/s12z/reg-prefix.s: New file. * testsuite/gas/s12z/s12z.exp: Add them.
2019-05-15 20:16:33 +08:00
2019-05-15 John Darrington <john@darrington.wattle.id.au>
* config/tc-s12z.c (register_prefix): New variable. (md_show_usage,
md_parse_option): parse the new option.
(lex_reg_name): Scan the prefix if one is set.
* doc/c-s12z.texi (S12Z-Opts): Document the new option.
* testsuite/gas/s12z/reg-prefix.d: New file.
* testsuite/gas/s12z/reg-prefix.s: New file.
* testsuite/gas/s12z/s12z.exp: Add them.
GAS (doc): Fix misaligned menu entry. gas/ * doc/as.texi (Machine Dependencies): Fix misaligned menu entry.
2019-05-15 20:15:02 +08:00
2019-05-14 John Darrington <john@darrington.wattle.id.au>
* doc/as.texi (Machine Dependencies): Fix misaligned menu entry.
C-SKY FAIL: jbt - csky Another failure seen with MALLOC_PERTURB_=1. * config/tc-csky.c (md_convert_frag): Initialise trailing padding for COND_JUMP_PIC.
2019-05-15 15:07:18 +08:00
2019-05-15 Alan Modra <amodra@gmail.com>
* config/tc-csky.c (md_convert_frag): Initialise trailing
padding for COND_JUMP_PIC.
.file file number checking This adds another test for file numbers given in .file directives, checking that the value can be represented as an unsigned int and that a memory allocation expression doesn't overflow. I removed a test added recently since an earlier test (num < 1) already covers the (num < 0) case. * dwarf2dbg.c: Whitespace fixes. (get_filenum): Don't strdup "file". Adjust error message. (dwarf2_directive_filename): Use an unsigned type for "num". Catch truncation of file number and overflow of get_filenum XRESIZEVEC multiplication. Delete dead code.
2019-05-15 09:54:09 +08:00
2019-05-15 Alan Modra <amodra@gmail.com>
* dwarf2dbg.c: Whitespace fixes.
(get_filenum): Don't strdup "file". Adjust error message.
(dwarf2_directive_filename): Use an unsigned type for "num".
Catch truncation of file number and overflow of get_filenum
XRESIZEVEC multiplication. Delete dead code.
tic54x_start_line_hook git commit 3076e59490 caused tic54x-coff +FAIL: c54x subsym assignment/use PR 24538 * config/tc-tic54x.c (tic54x_start_line_hook): Do skip end of line chars in setting endp.
2019-05-15 09:45:17 +08:00
2019-05-15 Alan Modra <amodra@gmail.com>
PR 24538
* config/tc-tic54x.c (tic54x_start_line_hook): Do skip end of line
chars in setting endp.
Fix illegal memory access triggered when attempting to assemble a bogus i386 source file. PR 24538 * config/tc-i386-intel.c (i386_intel_simplify_register): Reject illegal register numbers.
2019-05-14 19:42:02 +08:00
2019-05-14 Nick Clifton <nickc@redhat.com>
PR 24538
* config/tc-i386-intel.c (i386_intel_simplify_register): Reject
illegal register numbers.
A series of fixes to addres problems detected by compiling the assembler with address sanitization enabled. PR 24538 gas * macro.c (get_any_string): Increase size of buffer used to hold decimal value of expression result. * dw2gencfi.c (get_debugseg_name): Handle an empty name. * dwarf2dbg.c (get_filenum): Catch integer wraparound when extending allocate file array. (dwarf2_directive_filename): Add extra checks of the computed file number. * config/tc-arm.c (arm_tc_equal_in_insn): Insert copy of name into warning hash table. (s_arm_eabi_attribute): Check for obj_elf_vendor_attribute returning -1. * config/tc-i386.c (i386_output_nops): Catch an attempt to generate nops of negative lengths. * as.h (MAX_LITTLENUMS): Move definition to here from... * config/atof-ieee.c: ...here. * config/tc-aarch64.c: ...here. * config/tc-arc.c: ...here. * config/tc-arm.c: ...here. * config/tc-epiphany.c: ...here. * config/tc-i386.c: ...here. * config/tc-ia64.c: ...here. (And correct the value). * config/tc-m32c.c: ...here. * config/tc-m32r.c: ...here. * config/tc-metag.c: ...here. * config/tc-microblaze.c: ...here. * config/tc-nds32.c: ...here. * config/tc-or1k.c: ...here. * config/tc-score.c: ...here. * config/tc-score7.c: ...here. * config/tc-tic4x.c: ...here. * config/tc-tilegx.c: ...here. * config/tc-tilepro.c: ...here. * config/tc-visium.c: ...here. * config/tc-sh.c (md_assemble): Add check for an instruction with no opcodes. * config/tc-mips.c (mips_lookup_insn): Add check for very short instruction name. * config/tc-tic54x.c: Use unsigned chars to access is_end_of_line array. (tic54x_start_line_hook): Check for an empty line. (next_line_shows_parallel): Do not walk off the end of the string. (tic54x_macro_start): Check for too much macro nesting. (tic54x_start_label): Add label_start parameter. Use this parameter to check the first character of the label. * config/tc-tic54x.h (TC_START_LABEL_WITHOUT_COLON): Pass line_start variable to tic54x_start_label. PR 24538 opcodes * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the end of the table prematurely.
2019-05-10 23:57:31 +08:00
2019-05-10 Nick Clifton <nickc@redhat.com>
PR 24538
* macro.c (get_any_string): Increase size of buffer used to hold
decimal value of expression result.
* dw2gencfi.c (get_debugseg_name): Handle an empty name.
* dwarf2dbg.c (get_filenum): Catch integer wraparound when
extending allocate file array.
(dwarf2_directive_filename): Add extra checks of the computed file
number.
* config/tc-arm.c (arm_tc_equal_in_insn): Insert copy of name into
warning hash table.
(s_arm_eabi_attribute): Check for obj_elf_vendor_attribute
returning -1.
* config/tc-i386.c (i386_output_nops): Catch an attempt to
generate nops of negative lengths.
* as.h (MAX_LITTLENUMS): Move definition to here from...
* config/atof-ieee.c: ...here.
* config/tc-aarch64.c: ...here.
* config/tc-arc.c: ...here.
* config/tc-arm.c: ...here.
* config/tc-epiphany.c: ...here.
* config/tc-i386.c: ...here.
* config/tc-ia64.c: ...here. (And correct the value).
* config/tc-m32c.c: ...here.
* config/tc-m32r.c: ...here.
* config/tc-metag.c: ...here.
* config/tc-microblaze.c: ...here.
* config/tc-nds32.c: ...here.
* config/tc-or1k.c: ...here.
* config/tc-score.c: ...here.
* config/tc-score7.c: ...here.
* config/tc-tic4x.c: ...here.
* config/tc-tilegx.c: ...here.
* config/tc-tilepro.c: ...here.
* config/tc-visium.c: ...here.
* config/tc-sh.c (md_assemble): Add check for an instruction with
no opcodes.
* config/tc-mips.c (mips_lookup_insn): Add check for very short
instruction name.
* config/tc-tic54x.c: Use unsigned chars to access is_end_of_line
array.
(tic54x_start_line_hook): Check for an empty line.
(next_line_shows_parallel): Do not walk off the end of the string.
(tic54x_macro_start): Check for too much macro nesting.
(tic54x_start_label): Add label_start parameter. Use this
parameter to check the first character of the label.
* config/tc-tic54x.h (TC_START_LABEL_WITHOUT_COLON): Pass
line_start variable to tic54x_start_label.
Add macro expansions for ADD, SUB, DADD and DSUB for MIPS r6 Release 6 of the MIPS architecture does not have an ADDI instruction. ADD/SUB instructions with immediate operands can be expanded to load and immediate value and then perform the operation. gas/ * config/tc-mips.c (macro) <M_ADD_I, M_SUB_I, M_DADD_I, M_DSUB_I>: Add expansions for MIPS r6. * testsuite/gas/mips/add.s: Enable tests for R6. * testsuite/gas/mips/daddi.s: Annotate to test DADD for R6. * testsuite/gas/mips/mipsr6@add.d: Likewise. * gas/testsuite/gas/mips/mipsr6@dadd.d: New test. * gas/testsuite/gas/mips/mips.exp: Run the new test. opcodes/ * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB macros for R6.
2019-05-07 00:29:20 +08:00
2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
* config/tc-mips.c (macro) <M_ADD_I, M_SUB_I, M_DADD_I, M_DSUB_I>:
Add expansions for MIPS r6.
* testsuite/gas/mips/add.s: Enable tests for R6.
* testsuite/gas/mips/daddi.s: Annotate to test DADD for R6.
* testsuite/gas/mips/mipsr6@add.d: Likewise.
* gas/testsuite/gas/mips/mipsr6@dadd.d: New test.
* gas/testsuite/gas/mips/mips.exp: Run the new test.
[gas][testsuite] Don't specify arch in testsuite output My testcase matched against a file format of elf64-littleaarch64 in the objdump output. This was unnecessarily restrictive and causes testcase failures on aarch64_be. Here we remove that restriction. Committed as obvious. Testing done on aarch64_be-none-elf gas to see the failure goes away. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * testsuite/gas/aarch64/sve2.d: Remove file format restriction.
2019-05-09 21:52:45 +08:00
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* testsuite/gas/aarch64/sve2.d: Remove file format restriction.
[binutils][aarch64] Add SVE2 tests Add tests that SVE2 instructions are encoded as they should be, and tests that invalid instructions have their problems reported. Also check that each sve2 cryptographic extension is required to use the corresponding cryptographic instructions. Finally, test to ensure that sve2 instructions using mnemonics that exist in sve1 still need the sve2 feature to be used. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * testsuite/gas/aarch64/illegal-sve2-aes.d: New test. * testsuite/gas/aarch64/illegal-sve2-bitperm.d: New test. * testsuite/gas/aarch64/illegal-sve2-sha3.d: Test new instructions. * testsuite/gas/aarch64/illegal-sve2-sm4.d: Test new instructions. * testsuite/gas/aarch64/illegal-sve2-sve1ext.d: Test new instructions. * testsuite/gas/aarch64/illegal-sve2-sve1ext.l: Test new instructions. * testsuite/gas/aarch64/illegal-sve2.d: Test new instructions. * testsuite/gas/aarch64/illegal-sve2.l: Test new instructions. * testsuite/gas/aarch64/illegal-sve2.s: Test new instructions. * testsuite/gas/aarch64/sve1-extended-sve2.s: New test. * testsuite/gas/aarch64/sve2.d: Test new instructions. * testsuite/gas/aarch64/sve2.s: Test new instructions.
2019-05-09 17:29:29 +08:00
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* testsuite/gas/aarch64/illegal-sve2-aes.d: New test.
* testsuite/gas/aarch64/illegal-sve2-bitperm.d: New test.
* testsuite/gas/aarch64/illegal-sve2-sha3.d: Test new instructions.
* testsuite/gas/aarch64/illegal-sve2-sm4.d: Test new instructions.
* testsuite/gas/aarch64/illegal-sve2-sve1ext.d: Test new instructions.
* testsuite/gas/aarch64/illegal-sve2-sve1ext.l: Test new instructions.
* testsuite/gas/aarch64/illegal-sve2.d: Test new instructions.
* testsuite/gas/aarch64/illegal-sve2.l: Test new instructions.
* testsuite/gas/aarch64/illegal-sve2.s: Test new instructions.
* testsuite/gas/aarch64/sve1-extended-sve2.s: New test.
* testsuite/gas/aarch64/sve2.d: Test new instructions.
* testsuite/gas/aarch64/sve2.s: Test new instructions.
[binutils][aarch64] New SVE_SHLIMM_UNPRED_22 operand. New operand describes a shift-left immediate encoded in bits 22:20-19:18-16 where UInt(bits) - esize == shift. This operand is useful for instructions like sshllb. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (parse_operands): Handle new SVE_SHLIMM_UNPRED_22 operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New SVE_SHLIMM_UNPRED_22 operand. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_SHLIMM_UNPRED_22. (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22 operand.
2019-05-09 17:29:27 +08:00
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (parse_operands): Handle new SVE_SHLIMM_UNPRED_22
operand.
[binutils][aarch64] New SVE_Zm4_11_INDEX operand. This includes defining a new single bit field SVE_i2h at position 20. SVE_Zm4_11_INDEX handles indexed Zn registers where the index is encoded in bits 20:11 and the register is chosed from range z0-z15 in bits 19-16. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (parse_operands): Handle new SVE_Zm4_11_INDEX operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm4_11_INDEX operand. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_Zm4_11_INDEX. (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX. (fields): Handle SVE_i2h field. * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
2019-05-09 17:29:24 +08:00
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (parse_operands): Handle new SVE_Zm4_11_INDEX
operand.
[binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand. Include a new iclass to extract the variant from the most significant 3 bits of this operand. Instructions such as rshrnb include a constant shift amount as an operand, where the most significant three bits of this operand determine what size elements the instruction is operating on. The new SVE_SHRIMM_UNPRED_22 operand denotes this constant encoded in bits 22:20-19:18-16 while the new sve_shift_tsz_hsd iclass denotes that the SVE qualifier is encoded in bits 22:20-19. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (parse_operands): Handle new SVE_SHRIMM_UNPRED_22 operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New SVE_SHRIMM_UNPRED_22 operand. (enum aarch64_insn_class): Add sve_shift_tsz_hsd iclass. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-asm.c (aarch64_ins_sve_shrimm): (aarch64_encode_variant_using_iclass): Handle sve_shift_tsz_hsd iclass encode. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle sve_shift_tsz_hsd iclass decode. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_SHRIMM_UNPRED_22. (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22 operand.
2019-05-09 17:29:22 +08:00
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (parse_operands): Handle new SVE_SHRIMM_UNPRED_22
operand.
[binutils][aarch64] New SVE_ADDR_ZX operand. Add AARCH64_OPND_SVE_ADDR_ZX operand that allows a vector of addresses in a Zn register, offset by an Xm register. This is used with scatter/gather SVE2 instructions. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (REG_ZR): Macro specifying zero register. (parse_address_main): Account for new addressing mode [Zn.S, Xm]. (parse_operands): Handle new SVE_ADDR_ZX operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New SVE_ADDR_ZX operand. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_ADDR_ZX. (aarch64_print_operand): Add printing for SVE_ADDR_ZX. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
2019-05-09 17:29:18 +08:00
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (REG_ZR): Macro specifying zero register.
(parse_address_main): Account for new addressing mode [Zn.S, Xm].
(parse_operands): Handle new SVE_ADDR_ZX operand.
[binutils][aarch64] New SVE_Zm3_11_INDEX operand. Introduce new operand SVE_Zm3_11_INDEX that indicates a register between z0-z7 stored in bits 18-16 and an index stored in bits 20-19:11. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (parse_operands): Handle new SVE_Zm3_11_INDEX operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm3_11_INDEX operand. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_Zm3_11_INDEX. (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX. (fields): Handle SVE_i3l and SVE_i3h2 fields. * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2 fields. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
2019-05-09 17:29:17 +08:00
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (parse_operands): Handle new SVE_Zm3_11_INDEX
operand.
[binutils][aarch64] Introduce SVE_IMM_ROT3 operand. New operand AARCH64_OPND_SVE_IMM_ROT3 handles a single bit rotate operand encoded at bit position 10. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (parse_operands): Handle new SVE_IMM_ROT3 operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New SVE_IMM_ROT3 operand. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_IMM_ROT3. (aarch64_print_operand): Add printing for SVE_IMM_ROT3. (fields): Handle SVE_rot3 field. * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
2019-05-09 17:29:15 +08:00
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (parse_operands): Handle new SVE_IMM_ROT3 operand.
[binutils][aarch64] SVE2 feature extension flags. Include all feature flag macros. The "sve2" extension that enables the core sve2 instructions. This also enables the sve extension, since sve is a requirement of sve2. Extra optional sve2 features are the bitperm, sm4, aes, and sha3 extensions. These are all given extra feature flags, "bitperm", "sve2-sm4", "sve2-aes", and "sve2-sha3" respectively. The sm4, aes, and sha3 extensions are explicitly marked as sve2 extensions to distinguish them from the corresponding NEON extensions. Rather than continue extending the current feature flag numbers, I used some bits that have been skipped. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c: Add command line architecture feature flags "sve2", "sve2-sm4", "sve2-aes", "sve2-sha3", "bitperm". * doc/c-aarch64.texi: Document new architecture feature flags. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_SVE2 AARCH64_FEATURE_SVE2_AES, AARCH64_FEATURE_SVE2_BITPERM, AARCH64_FEATURE_SVE2_SM4, AARCH64_FEATURE_SVE2_SHA3): New feature macros. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-tbl.h (aarch64_feature_sve2, aarch64_feature_sve2aes, aarch64_feature_sve2sha3, aarch64_feature_sve2sm4, aarch64_feature_sve2bitperm): New feature sets. (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros for feature set addresses. (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN, SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
2019-05-09 17:29:12 +08:00
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c: Add command line architecture feature flags
"sve2", "sve2-sm4", "sve2-aes", "sve2-sha3", "bitperm".
* doc/c-aarch64.texi: Document new architecture feature flags.
gas/elf dwarf2 tests Make them work for tile, by using ".quad 0" as the simulated instruction and doubling size of aligns. The larger aligns tripped over riscv alignment handling, fixed by adding -mno-relax there. Also disable link-relax for avr, pru and xtensa, allowing these targets to pass these tests. With link-time relaxation enabled, these targets emit alignment relocations rather than aligning at assembly time. This means the assembler doesn't see a change in PC when it is expected over an alignment frag and thus view numbers are calculated incorrectly. * testsuite/gas/elf/dwarf2-1.s, * testsuite/gas/elf/dwarf2-2.s, * testsuite/gas/elf/dwarf2-5.s, * testsuite/gas/elf/dwarf2-7.s, * testsuite/gas/elf/dwarf2-8.s, * testsuite/gas/elf/dwarf2-9.s, * testsuite/gas/elf/dwarf2-10.s, * testsuite/gas/elf/dwarf2-11.s, * testsuite/gas/elf/dwarf2-12.s, * testsuite/gas/elf/dwarf2-13.s, * testsuite/gas/elf/dwarf2-14.s, * testsuite/gas/elf/dwarf2-15.s, * testsuite/gas/elf/dwarf2-16.s, * testsuite/gas/elf/dwarf2-17.s, * testsuite/gas/elf/dwarf2-18.s, * testsuite/gas/elf/dwarf2-19.s: Double size of align and simulated instructions. * testsuite/gas/elf/dwarf2-1.d, * testsuite/gas/elf/dwarf2-2.d, * testsuite/gas/elf/dwarf2-5.d, * testsuite/gas/elf/dwarf2-7.d, * testsuite/gas/elf/dwarf2-8.d, * testsuite/gas/elf/dwarf2-9.d, * testsuite/gas/elf/dwarf2-10.d, * testsuite/gas/elf/dwarf2-11.d, * testsuite/gas/elf/dwarf2-12.d, * testsuite/gas/elf/dwarf2-13.d, * testsuite/gas/elf/dwarf2-14.d, * testsuite/gas/elf/dwarf2-15.d, * testsuite/gas/elf/dwarf2-16.d, * testsuite/gas/elf/dwarf2-17.d, * testsuite/gas/elf/dwarf2-18.d, * testsuite/gas/elf/dwarf2-19.d: Use xfail rather than notarget. Remove avr, pru, tile, xtensa from xfails. Update expected output. * testsuite/gas/elf/elf.exp: Sort targets. (dump_opts): Pass {as -mno-relax} for riscv, {as -mno-link-relax} for avr and pru, and {as --no-link-relax} for xtensa to dwarf tests. * testsuite/gas/elf/section2.e-miwmmxt: Delete unused file.
2019-05-08 07:56:56 +08:00
2019-05-08 Alan Modra <amodra@gmail.com>
* testsuite/gas/elf/dwarf2-1.s,
* testsuite/gas/elf/dwarf2-2.s,
* testsuite/gas/elf/dwarf2-5.s,
* testsuite/gas/elf/dwarf2-7.s,
* testsuite/gas/elf/dwarf2-8.s,
* testsuite/gas/elf/dwarf2-9.s,
* testsuite/gas/elf/dwarf2-10.s,
* testsuite/gas/elf/dwarf2-11.s,
* testsuite/gas/elf/dwarf2-12.s,
* testsuite/gas/elf/dwarf2-13.s,
* testsuite/gas/elf/dwarf2-14.s,
* testsuite/gas/elf/dwarf2-15.s,
* testsuite/gas/elf/dwarf2-16.s,
* testsuite/gas/elf/dwarf2-17.s,
* testsuite/gas/elf/dwarf2-18.s,
* testsuite/gas/elf/dwarf2-19.s: Double size of align and simulated
instructions.
* testsuite/gas/elf/dwarf2-1.d,
* testsuite/gas/elf/dwarf2-2.d,
* testsuite/gas/elf/dwarf2-5.d,
* testsuite/gas/elf/dwarf2-7.d,
* testsuite/gas/elf/dwarf2-8.d,
* testsuite/gas/elf/dwarf2-9.d,
* testsuite/gas/elf/dwarf2-10.d,
* testsuite/gas/elf/dwarf2-11.d,
* testsuite/gas/elf/dwarf2-12.d,
* testsuite/gas/elf/dwarf2-13.d,
* testsuite/gas/elf/dwarf2-14.d,
* testsuite/gas/elf/dwarf2-15.d,
* testsuite/gas/elf/dwarf2-16.d,
* testsuite/gas/elf/dwarf2-17.d,
* testsuite/gas/elf/dwarf2-18.d,
* testsuite/gas/elf/dwarf2-19.d: Use xfail rather than notarget.
Remove avr, pru, tile, xtensa from xfails. Update expected output.
* testsuite/gas/elf/elf.exp: Sort targets.
(dump_opts): Pass {as -mno-relax} for riscv, {as -mno-link-relax}
for avr and pru, and {as --no-link-relax} for xtensa to dwarf tests.
* testsuite/gas/elf/section2.e-miwmmxt: Delete unused file.
xtensa ignores option --no-link-relax md_begin happens after md_parse_option. * config/tc-xtensa.c (opt_linkrelax): New variable. (md_parse_option): Set it here. (md_begin): Copy opt_linkrelax to linkrelax.
2019-05-08 07:56:36 +08:00
2019-05-08 Alan Modra <amodra@gmail.com>
* config/tc-xtensa.c (opt_linkrelax): New variable.
(md_parse_option): Set it here.
(md_begin): Copy opt_linkrelax to linkrelax.
xfail locview tests on mep that use complex relocs for view numbers Expressions that compute view numbers that aren't simplified early enough to a constant end up being selected for representation as complex relocations, enabled on mep-* targets. It would be possible to recognize such expressions, that can resolve to constants, but this problem was hit before, in preexisting tests, so xfail the new hits similarly. The new hits were caused by yesterday's patch to dwarf2dbg.c: views in the beginning of subsections are now computed later, based on the final views or previous subsections in the same section. for gas/ChangeLog * testsuite/gas/elf/dwarf2-18.d: Xfail mep-*. * testsuite/gas/elf/dwarf2-19.d: Likewise.
2019-05-08 03:34:19 +08:00
2019-05-07 Alexandre Oliva <aoliva@redhat.com>
* testsuite/gas/elf/dwarf2-18.d: Xfail mep-*.
* testsuite/gas/elf/dwarf2-19.d: Likewise.
Tidy use_complex_relocs_for Since I was looking at this I decided to fix the formatting, and used an old C switch statements trick to factor out common code. * symbols.c (use_complex_relocs_for): Formatting. Factor out X_add_symbol tests.
2019-05-06 19:53:45 +08:00
2019-05-07 Alan Modra <amodra@gmail.com>
* symbols.c (use_complex_relocs_for): Formatting. Factor out
X_add_symbol tests.
Add load-link, store-conditional paired EVA instructions Add paired load-link and store-conditional instructions to the EVA ASE for MIPS32R6[1]. These instructions are optional within the EVA ASE. Their presence is indicated by the XNP bit in the Config5 register. [1] "MIPS Architecture for Programmers Volume II-A: The MIPS32 Instruction Set Manual", Imagination Technologies Ltd., Document Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical List of Instructions", pp. 230-231, pp. 357-360. gas/ * config/tc-mips.c (mips_set_ase): Handle ASE_EVA_R6. (macro) <M_LLWPE_AB, M_SCWPE_AB>: New cases. (mips_after_parse_args): Translate EVA to EVA_R6. * testsuite/gas/mips/ase-errors-1.s: Add new instructions. * testsuite/gas/mips/eva.s: Likewise. * testsuite/gas/mips/ase-errors-1.l: Check errors for new instructions. * testsuite/gas/mips/mipsr6@eva.d: Check new test cases. include/ * opcode/mips.h (ASE_EVA_R6): New macro. (M_LLWPE_AB, M_SCWPE_AB): New enum values. opcodes/ * mips-dis.c (mips_calculate_combination_ases): Add ISA argument and set ASE_EVA_R6 appropriately. (set_default_mips_dis_options): Pass ISA to above. (parse_mips_dis_option): Likewise. * mips-opc.c (EVAR6): New macro. (mips_builtin_opcodes): Add llwpe, scwpe. Derived from patch authored by Andrew Bennett <andrew.bennett@imgtec.com>
2019-04-29 09:21:00 +08:00
2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
Faraz Shahbazker <fshahbazker@wavecomp.com>
* config/tc-mips.c (mips_set_ase): Handle ASE_EVA_R6.
(macro) <M_LLWPE_AB, M_SCWPE_AB>: New cases.
(mips_after_parse_args): Translate EVA to EVA_R6.
* testsuite/gas/mips/ase-errors-1.s: Add new instructions.
* testsuite/gas/mips/eva.s: Likewise.
* testsuite/gas/mips/ase-errors-1.l: Check errors for
new instructions.
* testsuite/gas/mips/mipsr6@eva.d: Check new test cases.
sym->sy_value is not valid for struct local_symbol Fixes this mep-elf error: gas/elf/dwarf2-19.s: Error: Unknown expression operator (enum 0) gas/elf/dwarf2-19.s: Error: cannot convert expression symbol .L2 to complex relocation * symbols.c (symbol_relc_make_sym): Do not access sym->sy_value directly.
2019-05-06 13:08:24 +08:00
2019-05-06 Alan Modra <amodra@gmail.com>
* symbols.c (symbol_relc_make_sym): Do not access sym->sy_value
directly.
PowerPC reloc symbols that shouldn't be adjusted GOT and PLT relocs shouldn't have their symbols replaced with a section symbol plus added. Nor should the HIGHA TLS relocations, which failed to be caught by the range test in ppc_fix_adjustable. bfd/ * reloc.c (BFD_RELOC_PPC64_TPREL16_HIGH, BFD_RELOC_PPC64_TPREL16_HIGHA), (BFD_RELOC_PPC64_DTPREL16_HIGH, BFD_RELOC_PPC64_DTPREL16_HIGHA): Sort before BFD_RELOC_PPC64_DTPREL16_HIGHESTA entry. gas/ * config/tc-ppc.c (ppc_fix_adjustable): Exclude all GOT and PLT relocs, and VLE sdarel relocs. * testsuite/gas/ppc/power4.d: Adjust.
2019-05-06 07:13:32 +08:00
2019-05-06 Alan Modra <amodra@gmail.com>
* config/tc-ppc.c (ppc_fix_adjustable): Exclude all GOT and PLT
relocs, and VLE sdarel relocs.
* testsuite/gas/ppc/power4.d: Adjust.
[LVu] base subseg head view on prev subseg's tail Location views at borders between subsegments/subsections in the same segment/section are computed as if each new subsegment/subsection started with a forced view reset to zero, but the line number program does not introduce resets that are not explicitly requested, so if a subsegment ends at the same address another starts, the line number program will have a continuity of views at the border address, whereas the initial view number label in the latter subsegment will be miscomputed as zero. This patch delays the assignment of view expressions at subsegment heads to the time of chaining the frags of subsegments into a single segment, so that they are set based on the view at the end of the previous subsegment in the same segment. The line number program created for the test program had an unnecessary DW_LNS_advance_pc at the end. This patch also arranges for us not to emit it. for gas/ChangeLog * dwarf2dbg.c (set_or_check_view): Skip heads when assigning views of prior locs. (dwarf2_gen_line_info_1): Skip heads. (size_inc_line_addr, emit_inc_line_addr): Drop DW_LNS_advance_pc for zero addr delta. (dwarf2_finish): Assign views for heads of segments. * testsuite/gas/elf/dwarf2-19.d: New. * testsuite/gas/elf/dwarf2-19.s: New. * testsuite/gas/elf/elf.exp: Test it.
2019-05-06 10:07:20 +08:00
2019-05-05 Alexandre Oliva <aoliva@redhat.com>
* dwarf2dbg.c (set_or_check_view): Skip heads when assigning
views of prior locs.
(dwarf2_gen_line_info_1): Skip heads.
(size_inc_line_addr, emit_inc_line_addr): Drop
DW_LNS_advance_pc for zero addr delta.
(dwarf2_finish): Assign views for heads of segments.
* testsuite/gas/elf/dwarf2-19.d: New.
* testsuite/gas/elf/dwarf2-19.s: New.
* testsuite/gas/elf/elf.exp: Test it.
m32c padding with nops m32c_md_end attempted to pad out a code section with nops, but this was just plain wrong in many ways: - The padding didn't happen at all if the last section emitted wasn't a code section. - The padding went to the wrong place if subsections were used, and the last subseg used wasn't the highest numbered subseg. - Padding wasn't added to all code sections. - If the last section was empty, it was padded to 4 bytes. - The padding didn't go to a 4-byte alignment boundary, instead it effectively made the last instruction 4 bytes in size. - The padding didn't take into account that code sections may have contents other than machine instructions. So, rip it out and handle nop padding properly, also fixing .align .balign/.p2align in the middle of code. gas/ * config/tc-m32c.c (insn_size): Delete static var. (md_begin): Don't set it. (m32c_md_end): Delete. (md_assemble): Add insn_size auto var. * config/tc-m32c.h (md_end): Don't define. (m32c_md_end): Delete. (NOP_OPCODE, HANDLE_ALIGN, MAX_MEM_FOR_RS_ALIGN_CODE): Define. * testsuite/gas/all/align.d: Remove m32c from notarget list. * testsuite/gas/all/incbin.d: Likewise. * testsuite/gas/elf/dwarf2-11.d: Likewise. * testsuite/gas/macros/semi.d: Likewise. * testsuite/gas/all/gas.exp (do_comment): Similarly. ld/ * testsuite/ld-scripts/fill.d: Don't xfail m32c * testsuite/ld-scripts/fill16.d: Likewise.
2019-05-04 14:33:47 +08:00
2019-05-04 Alan Modra <amodra@gmail.com>
* config/tc-m32c.c (insn_size): Delete static var.
(md_begin): Don't set it.
(m32c_md_end): Delete.
(md_assemble): Add insn_size auto var.
* config/tc-m32c.h (md_end): Don't define.
(m32c_md_end): Delete.
(NOP_OPCODE, HANDLE_ALIGN, MAX_MEM_FOR_RS_ALIGN_CODE): Define.
* testsuite/gas/all/align.d: Remove m32c from notarget list.
* testsuite/gas/all/incbin.d: Likewise.
* testsuite/gas/elf/dwarf2-11.d: Likewise.
* testsuite/gas/macros/semi.d: Likewise.
* testsuite/gas/all/gas.exp (do_comment): Similarly.
i386: Issue a warning to IRET without suffix for .code16gcc The .code16gcc directive to support 16-bit mode with 32-bit address. For IRET without a suffix, generate 16-bit IRET with a warning to return from an interrupt handler in 16-bit mode. PR gas/24485 * config/tc-i386.c (process_suffix): Issue a warning to IRET without a suffix for .code16gcc. * testsuite/gas/i386/jump16.s: Add tests for iretX. * testsuite/gas/i386/jump16.d: Updated. * testsuite/gas/i386/jump16.e: New file.
2019-05-03 01:46:55 +08:00
2019-05-02 H.J. Lu <hongjiu.lu@intel.com>
PR gas/24485
* config/tc-i386.c (process_suffix): Issue a warning to IRET
without a suffix for .code16gcc.
* testsuite/gas/i386/jump16.s: Add tests for iretX.
* testsuite/gas/i386/jump16.d: Updated.
* testsuite/gas/i386/jump16.e: New file.
[BINUTILS, AArch64] Enable Transactional Memory Extension This patch enables the new Transactional Memory Extension added recently as part of Arm's new architecture technologies. We introduce a new optional extension "tme" to enable this. The following instructions are part of the extension: * tstart <Xt> * ttest <Xt> * tcommit * tcancel #<imm> The ISA for the above can be found here: https://developer.arm.com/docs/ddi0602/latest/base-instructions-alphabetic-order *** gas/ChangeLog *** 2019-05-01 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (parse_operands): Add case for AARCH64_OPND_TME_UIMM16. (aarch64_features): Add "tme". * doc/c-aarch64.texi: Document the same. * testsuite/gas/aarch64/tme-invalid.d: New test. * testsuite/gas/aarch64/tme-invalid.l: New test. * testsuite/gas/aarch64/tme-invalid.s: New test. * testsuite/gas/aarch64/tme.d: New test. * testsuite/gas/aarch64/tme.s: New test. *** include/ChangeLog *** 2019-05-01 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_TME): New. (enum aarch64_opnd): Add AARCH64_OPND_TME_UIMM16. *** opcodes/ChangeLog *** 2019-05-01 Sudakshina Das <sudi.das@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Add case for AARCH64_OPND_TME_UIMM16. (aarch64_print_operand): Likewise. * aarch64-tbl.h (QL_IMM_NIL): New. (TME): New. (_TME_INSN): New. (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
2019-05-02 00:14:01 +08:00
2019-05-01 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_operands): Add case for
AARCH64_OPND_TME_UIMM16.
(aarch64_features): Add "tme".
* doc/c-aarch64.texi: Document the same.
* testsuite/gas/aarch64/tme-invalid.d: New test.
* testsuite/gas/aarch64/tme-invalid.l: New test.
* testsuite/gas/aarch64/tme-invalid.s: New test.
* testsuite/gas/aarch64/tme.d: New test.
* testsuite/gas/aarch64/tme.s: New test.
S12Z: Opcodes: Fix crash when trying to decode a truncated operation. opcodes/ * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails. gas/ * testsuite/gas/s12z/truncated.d: New file. * testsuite/gas/s12z/truncated.s: New file. * testsuite/gas/s12z/s12z.exp: Add new test.
2019-04-29 22:05:54 +08:00
2019-04-29 John Darrington <john@darrington.wattle.id.au>
.file file number checking This adds another test for file numbers given in .file directives, checking that the value can be represented as an unsigned int and that a memory allocation expression doesn't overflow. I removed a test added recently since an earlier test (num < 1) already covers the (num < 0) case. * dwarf2dbg.c: Whitespace fixes. (get_filenum): Don't strdup "file". Adjust error message. (dwarf2_directive_filename): Use an unsigned type for "num". Catch truncation of file number and overflow of get_filenum XRESIZEVEC multiplication. Delete dead code.
2019-05-15 09:54:09 +08:00
* testsuite/gas/s12z/truncated.d: New file.
S12Z: Opcodes: Fix crash when trying to decode a truncated operation. opcodes/ * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails. gas/ * testsuite/gas/s12z/truncated.d: New file. * testsuite/gas/s12z/truncated.s: New file. * testsuite/gas/s12z/s12z.exp: Add new test.
2019-04-29 22:05:54 +08:00
* testsuite/gas/s12z/truncated.s: New file.
* testsuite/gas/s12z/s12z.exp: Add new test.
[MIPS] Add load-link, store-conditional paired instructions Add several baseline MIPS32R6[1] and MIPS64R6[2] instructions that were omitted from the initial spec. These instructions are optional in implementations but not associated with any ASE or pseudo-ASE. Their presence is indicated by the XNP bit in the Config5 register. [1] "MIPS Architecture for Programmers Volume II-A: The MIPS32 Instruction Set Manual", Imagination Technologies Ltd., Document Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical List of Instructions", pp. 228-229, pp. 354-357. [2] "MIPS Architecture for Programmers Volume II-A: The MIPS64 Instruction Set Manual", Imagination Technologies Ltd., Document Number: MD00087, Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical List of Instructions", pp. 289-290 and pp. 458-460. gas/ * config/tc-mips.c (macro) <M_LLWP_AB, M_LLDP_AB, M_SCWP_AB, M_SCDP_AB>: New cases and expansions for paired instructions. * testsuite/gas/mips/llpscp-32.s: New test source. * testsuite/gas/mips/llpscp-64.s: Likewise. * testsuite/gas/mips/llpscp-32.d: New test. * testsuite/gas/mips/llpscp-64.d: Likewise. * testsuite/gas/mips/mips.exp: Run the new tests. * testsuite/gas/mips/r6.s: Add new instructions to test source. * testsuite/gas/mips/r6-64.s: Likewise. * testsuite/gas/mips/r6-64-n32.d: Check new instructions. * testsuite/gas/mips/r6-64-n64.d: Likewise. * testsuite/gas/mips/r6-n32.d: Likewise. * testsuite/gas/mips/r6-n64.d: Likwwise. * testsuite/gas/mips/r6.d: Likewise. include/ * opcode/mips.h (M_LLWP_AB, M_LLDP_AB): New enum values. (M_SCWP_AB, M_SCDP_AB): Likewise. opcodes/ * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
2019-04-23 06:12:09 +08:00
2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
Faraz Shahbazker <fshahbazker@wavecomp.com>
* config/tc-mips.c (macro) <M_LLWP_AB, M_LLDP_AB, M_SCWP_AB,
M_SCDP_AB>: New cases and expansions for paired instructions.
* testsuite/gas/mips/llpscp-32.s: New test source.
* testsuite/gas/mips/llpscp-64.s: Likewise.
* testsuite/gas/mips/llpscp-32.d: New test.
* testsuite/gas/mips/llpscp-64.d: Likewise.
* testsuite/gas/mips/mips.exp: Run the new tests.
* testsuite/gas/mips/r6.s: Add new instructions to test source.
* testsuite/gas/mips/r6-64.s: Likewise.
* testsuite/gas/mips/r6-64-n32.d: Check new instructions.
* testsuite/gas/mips/r6-64-n64.d: Likewise.
* testsuite/gas/mips/r6-n32.d: Likewise.
* testsuite/gas/mips/r6-n64.d: Likwwise.
* testsuite/gas/mips/r6.d: Likewise.
i386: Don't add 0x66 prefix to IRET for .code16gcc The .code16gcc directive supports 16bit mode with 32-bit address. Since IRET (opcode 0xcf) in 16bit mode returns from an interrupt in 16bit mode, we shouldn't add 0x66 prefix for IRET. PR gas/24485 * config/tc-i386.c (process_suffix): Don't add DATA_PREFIX_OPCODE to IRET for .code16gcc. * testsuite/gas/i386/jump16.s: Add IRET tests. * testsuite/gas/i386/jump16.d: Updated.
2019-04-27 01:19:53 +08:00
2019-04-26 H.J. Lu <hongjiu.lu@intel.com>
PR gas/24485
* config/tc-i386.c (process_suffix): Don't add DATA_PREFIX_OPCODE
to IRET for .code16gcc.
* testsuite/gas/i386/jump16.s: Add IRET tests.
* testsuite/gas/i386/jump16.d: Updated.
Speed up locview resolution with relaxable frags Targets such as xtensa incur a much higher overhead to resolve location view numbers than e.g. x86, because the expressions used to compute view numbers cannot be resolved soon enough. Each view number is computed by incrementing the previous view, if they are both at the same address, or by resetting it to zero otherwise. If PV is the previous view number, PL is its location, and NL is the location of the next view, its number is computed by evaluating NV = !(NL > PL) * (PV + 1). set_or_check_view uses resolve_expression to decide whether portions of this expression can be simplified to constants. The (NL > PL) subexpression is one that can often be resolved to a constant, breaking chains of view number computations at instructions of nonzero length, but not after alignment that might be unnecessary. Alas, when nearly every frag ends with a relaxable instruction, frag_offset_fixed_p will correctly fail to determine a known offset between two unresolved addresses in neighboring frags, so the unresolved symbolic operation will be constructed and used in the computation of most view numbers. This results in very deep expressions. As view numbers get referenced in location view lists, each operand in the list goes through symbol_clone_if_forward_ref, which recurses on every subexpression. If each view number were to be referenced, this would exhibit O(n^2) behavior, where n is the depth of the view number expressions, i.e., the length of view number sequences without an early resolution that cuts the expression short. This patch enables address compares used by view numbering to be resolved even when exact offsets are not known, using new logic to determine when the location either remained the same or changed for sure, even with the possibility of relaxation. This enables most view number expressions to be resolved with a small, reasonable depth. PR gas/24444 * frags.c (frag_gtoffset_p): New. * frags.h (frag_gtoffset_p): Declare it. * expr.c (resolve_expression): Use it.
2019-04-13 16:55:34 +08:00
2019-04-25 Alexandre Oliva <aoliva@redhat.com>
Alan Modra <amodra@gmail.com>
PR gas/24444
* frags.c (frag_gtoffset_p): New.
* frags.h (frag_gtoffset_p): Declare it.
* expr.c (resolve_expression): Use it.
resolve_symbol_value vs. .loc view resolution In most cases we don't want expression symbols, such as that created for an expression like "symbol + (1f - .)", resolved down to a constant. Instead we'd like to leave the expression as "symbol + constant" once the "1f - ." part has been resolved, and let the backend decide whether "symbol" can be reduced further. However, that doesn't work when trying to resolve .loc view symbols early. We get expression symbols left as an O_symbol expression pointing at an absolute symbol, and marked as sy_flags.sy_resolved. That wouldn't really be a problem, but when one of those expression symbols is used in further .loc view expressions, its value is taken as zero. This patch fixes the symbol value mistake, and stops creation of O_symbol expression symbols pointing to absolute symbols. Either of these fixes would cure the .loc view usage. PR 24444 * symbols.c (resolve_symbol_value): When handling symbols marked as sy_flags.resolved, return correct value for the case of expression symbols left as an O_symbol expression. Merge O_symbol code handling undefined and common symbols with code handling special cases of expression symbols. Use seg_left to test for undefined and common symbols. Don't leave an O_symbol expression when X_add_symbol resolves to the absolute_section. Init final_val later. * testsuite/gas/mmix/basep-7.d: Adjust expected output.
2019-04-24 09:56:51 +08:00
2019-04-24 Alan Modra <amodra@gmail.com>
PR 24444
* symbols.c (resolve_symbol_value): When handling symbols
marked as sy_flags.resolved, return correct value for the
case of expression symbols left as an O_symbol expression.
Merge O_symbol code handling undefined and common symbols with
code handling special cases of expression symbols. Use
seg_left to test for undefined and common symbols. Don't
leave an O_symbol expression when X_add_symbol resolves to
the absolute_section. Init final_val later.
* testsuite/gas/mmix/basep-7.d: Adjust expected output.
S12Z: Opcodes: Handle bit map operations with non-canonical operands. opcodes/ * s12z-opc.c (bm_decode): Handle the RESERVERD0 case. gas/ * testsuite/gas/s12z/bit-manip-invalid.d: Extend the test. * testsuite/gas/s12z/bit-manip-invalid.s: Extend the test.
2019-04-24 15:41:23 +08:00
2019-04-24 John Darrington <john@darrington.wattle.id.au>
* testsuite/gas/s12z/bit-manip-invalid.s: Extend test for BSET
and BCLR instructions with an invalid mode.
* testsuite/gas/s12z/bit-manip-invalid.d: ditto.
RX Assembler: Ensure that the internal limit on the number of relaxation iterations is not larger that the external limit. PR 24464 * config/tc-rx.h (md_relax_frag): Pass the max_iterations variable to the relaxation function. * config/tc-rx.c (rx_relax_frag): Add new parameter - the maximum number of iterations. Make sure that our internal iteration limit does not exceed this external iteration limit.
2019-04-19 17:39:47 +08:00
2019-04-19 Nick Clifton <nickc@redhat.com>
PR 24464
* config/tc-rx.h (md_relax_frag): Pass the max_iterations variable
to the relaxation function.
* config/tc-rx.c (rx_relax_frag): Add new parameter - the maximum
number of iterations. Make sure that our internal iteration limit
does not exceed this external iteration limit.
Improve warning message for $0 constraint on MIPSR6 branches gas/ * config/tc-mips.c (match_non_zero_reg_operand): Update warning message. * testsuite/gas/mips/r6-branch-constraints.l: Likewise.
2019-04-17 12:07:19 +08:00
2019-04-18 Matthew Fortune <matthew.fortune@mips.com>
* config/tc-mips.c (match_non_zero_reg_operand): Update
warning message.
* testsuite/gas/mips/r6-branch-constraints.l: Likewise.
MSP430 Assembler: Define symbols for functions to run through. gas * config/tc-msp430.c (msp430_make_init_symbols): Define __crt0_run_{preinit,init,fini}_array symbols if .{preinit,init,fini}_array sections exist. * testsuite/gas/msp430/fini-array.d: New test. * testsuite/gas/msp430/init-array.d: New test. * testsuite/gas/msp430/preinit-array.d: New test. * testsuite/gas/msp430/fini-array.s: New test source. * testsuite/gas/msp430/init-array.s: New test source. * testsuite/gas/msp430/preinit-array.s: New test source. * testsuite/gas/msp430/msp430.exp: Add new tests to driver.
2019-04-18 20:15:09 +08:00
2019-04-18 Jozef Lawrynowicz <jozef.l@mittosystems.com>
* config/tc-msp430.c (msp430_make_init_symbols): Define
__crt0_run_{preinit,init,fini}_array symbols if
.{preinit,init,fini}_array sections exist.
* testsuite/gas/msp430/fini-array.d: New test.
* testsuite/gas/msp430/init-array.d: New test.
* testsuite/gas/msp430/preinit-array.d: New test.
* testsuite/gas/msp430/fini-array.s: New test source.
* testsuite/gas/msp430/init-array.s: New test source.
* testsuite/gas/msp430/preinit-array.s: New test source.
* testsuite/gas/msp430/msp430.exp: Add new tests to driver.
MSP430 Assembler: Leave placement of .lower and .upper sections to generic linker code. * config/tc-msp430.c (msp430_make_init_symbols): Define __crt0_init_bss symbol when .lower.bss or .either.bss sections exist. Define __crt0_movedata when .lower.data or .either.data sections exist. * testsuite/gas/msp430/either-data-bss-sym.d: New test. * testsuite/gas/msp430/low-data-bss-sym.d: New test. * testsuite/gas/msp430/either-data-bss-sym.s: New test source. * testsuite/gas/msp430/low-data-bss-sym.s: New test source. * testsuite/gas/msp430/msp430.exp: Run new tests. Enable large code model when running -mdata-region={upper,either} tests.
2019-04-17 22:03:27 +08:00
2019-04-17 Jozef Lawrynowicz <jozef.l@mittosystems.com>
* config/tc-msp430.c (msp430_make_init_symbols): Define __crt0_init_bss
symbol when .lower.bss or .either.bss sections exist.
Define __crt0_movedata when .lower.data or .either.data sections exist.
* testsuite/gas/msp430/either-data-bss-sym.d: New test.
* testsuite/gas/msp430/low-data-bss-sym.d: New test.
* testsuite/gas/msp430/either-data-bss-sym.s: New test source.
* testsuite/gas/msp430/low-data-bss-sym.s: New test source.
* testsuite/gas/msp430/msp430.exp: Run new tests.
Enable large code model when running -mdata-region={upper,either}
tests.
MSP420 assembler: Add -m{u,U} options to enable/disable NOP warnings for unknown interrupt state changes gas * config/tc-msp430.c (options): New OPTION_UNKNOWN_INTR_NOPS, OPTION_NO_UNKNOWN_INTR_NOPS and do_unknown_interrupt_nops. (md_parse_option): Handle OPTION_UNKNOWN_INTR_NOPS and OPTION_NO_UNKNOWN_INTR_NOPS by setting do_unknown_interrupt_nops accordingly. (md_show_usage): Likewise. (md_shortopts): Add "mu" for OPTION_UNKNOWN_INTR_NOPS and "mU" for OPTION_NO_UNKNOWN_INTR_NOPS. (md_longopts): Likewise. (warn_eint_nop): Update comment. (warn_unsure_interrupt): Don't warn if prev_insn_is_nop or prev_insn_is_dint or we are assembling for 430 ISA. (msp430_operands): Only call warn_unsure_interrupt if do_unknown_interrupt_nops == TRUE. * testsuite/gas/msp430/nop-unknown-intr.s: New test source file. * testsuite/gas/msp430/nop-unknown-intr-430.d: New test. * testsuite/gas/msp430/nop-unknown-intr-430x.d: New test. * testsuite/gas/msp430/nop-unknown-intr-430x-ignore.d: New test. * testsuite/gas/msp430/nop-unknown-intr-430.l: Warning output for new test. * testsuite/gas/msp430/nop-unknown-intr-430x.l: Likewise. * testsuite/gas/msp430/msp430.exp: Add new tests to driver.
2019-04-17 22:01:28 +08:00
2019-04-17 Jozef Lawrynowicz <jozef.l@mittosystems.com>
* config/tc-msp430.c (options): New OPTION_UNKNOWN_INTR_NOPS,
OPTION_NO_UNKNOWN_INTR_NOPS and do_unknown_interrupt_nops.
(md_parse_option): Handle OPTION_UNKNOWN_INTR_NOPS and
OPTION_NO_UNKNOWN_INTR_NOPS by setting do_unknown_interrupt_nops
accordingly.
(md_show_usage): Likewise.
(md_shortopts): Add "mu" for OPTION_UNKNOWN_INTR_NOPS and
"mU" for OPTION_NO_UNKNOWN_INTR_NOPS.
(md_longopts): Likewise.
(warn_eint_nop): Update comment.
(warn_unsure_interrupt): Don't warn if prev_insn_is_nop or
prev_insn_is_dint or we are assembling for 430 ISA.
(msp430_operands): Only call warn_unsure_interrupt if
do_unknown_interrupt_nops == TRUE.
* testsuite/gas/msp430/nop-unknown-intr.s: New test source file.
* testsuite/gas/msp430/nop-unknown-intr-430.d: New test.
* testsuite/gas/msp430/nop-unknown-intr-430x.d: New test.
* testsuite/gas/msp430/nop-unknown-intr-430x-ignore.d: New test.
* testsuite/gas/msp430/nop-unknown-intr-430.l: Warning output for new
test.
* testsuite/gas/msp430/nop-unknown-intr-430x.l: Likewise.
* testsuite/gas/msp430/msp430.exp: Add new tests to driver.
xfail gas weakref1 test for nds32 Oops, I removed the wrong xfail from gas.exp in last commit, fix it here. * testsuite/gas/all/weakref1.d: xfail nds32.
2019-04-16 20:04:22 +08:00
2019-04-16 Alan Modra <amodra@gmail.com>
* testsuite/gas/all/weakref1.d: xfail nds32.
ns32k testsuite tidy Some of these tests were excluded for ns32k-netbsd, exclude for all ns32k instead. binutils/ * testsuite/binutils-all/copy-2.d: Don't run for ns32k-*-*. * testsuite/binutils-all/copy-3.d: Likewise. gas/ * testsuite/gas/all/gas.exp: Remove ns32k xfails. * testsuite/gas/all/weakref1u.d: Don't run for ns32k-*-*. ld/ * testsuite/ld-scripts/pr20302.d: Don't run for ns32k-*-*. * testsuite/ld-scripts/section-match-1.d: Likewise. * testsuite/ld-undefined/require-defined.exp: Likewise.
2019-04-16 16:38:11 +08:00
2019-04-16 Alan Modra <amodra@gmail.com>
* testsuite/gas/all/gas.exp: Remove ns32k xfails.
* testsuite/gas/all/weakref1u.d: Don't run for ns32k-*-*.
Move fixup fx_bit_fixP and fx_im_disp fields to TC_FIX_TYPE These are only used by dlx and ns32k. * write.h: Don't include bit_fix.h. (struct fix): Rearrange some fields. Delete fx_im_disp and fx_bit_fixP. Use bitfields for fx_size and fx_pcrel_adjust. * write.c (fix_new_internal): Don't init fx_im_disp and fx_bit_fixP. (fixup_segment): Don't exclude overflow checks on fx_bit_fixP. (print_fixup): Don't print im_disp. * config/tc-cris.c (md_apply_fix): Remove tests of fx_bit_fixP and fx_im_disp. * config/tc-dlx.c (md_apply_fix): Remove wrong debug code. Set fx_no_overflow when fx_bit_fixP. * config/tc-dlx.h: Include bit_fix.h. (TC_FIX_TYPE, tc_fix_data, TC_INIT_FIX_DATA): Define. * config/tc-ns32k.c (fix_new_ns32k, fix_new_ns32k_exp): Set fx_no_overflow when bit_fixP. * config/tc-ns32k.h (TC_FIX_TYPE): Add fx_bit_fixP and fx_im_disp. (fix_im_disp, fix_bit_fixP): Adjust to suit. (TC_INIT_FIX_DATA, TC_FIX_DATA_PRINT): Likewise.
2019-04-16 14:17:02 +08:00
2019-04-16 Alan Modra <amodra@gmail.com>
* write.h: Don't include bit_fix.h.
(struct fix): Rearrange some fields. Delete fx_im_disp and
fx_bit_fixP. Use bitfields for fx_size and fx_pcrel_adjust.
* write.c (fix_new_internal): Don't init fx_im_disp and fx_bit_fixP.
(fixup_segment): Don't exclude overflow checks on fx_bit_fixP.
(print_fixup): Don't print im_disp.
* config/tc-cris.c (md_apply_fix): Remove tests of fx_bit_fixP
and fx_im_disp.
* config/tc-dlx.c (md_apply_fix): Remove wrong debug code. Set
fx_no_overflow when fx_bit_fixP.
* config/tc-dlx.h: Include bit_fix.h.
(TC_FIX_TYPE, tc_fix_data, TC_INIT_FIX_DATA): Define.
* config/tc-ns32k.c (fix_new_ns32k, fix_new_ns32k_exp): Set
fx_no_overflow when bit_fixP.
* config/tc-ns32k.h (TC_FIX_TYPE): Add fx_bit_fixP and fx_im_disp.
(fix_im_disp, fix_bit_fixP): Adjust to suit.
(TC_INIT_FIX_DATA, TC_FIX_DATA_PRINT): Likewise.
Make fixup fx_where unsigned Another field that only stores unsigned values. * write.h (struct fix <fx_where>): Make unsigned. (fix_new, fix_at_start, fix_new_exp): Adjust prototypes. * write.c (fix_new, fix_new_exp, fix_at_start): Make "where" and "size" parameters unsigned long. (fix_new_internal): Likewise. Adjust error format string to suit. * config/tc-mips.c (md_convert_frag): Remove cast of fx_where. * config/tc-sparc.c (md_apply_fix): Likewise. * config/tc-score.c (s3_convert_frag): Adjust for unsigned fx_where. * config/tc-score7.c (s7_convert_frag): Likewise.
2019-04-16 09:40:44 +08:00
2019-04-16 Alan Modra <amodra@gmail.com>
* write.h (struct fix <fx_where>): Make unsigned.
(fix_new, fix_at_start, fix_new_exp): Adjust prototypes.
* write.c (fix_new, fix_new_exp, fix_at_start): Make "where" and
"size" parameters unsigned long.
(fix_new_internal): Likewise. Adjust error format string to suit.
* config/tc-mips.c (md_convert_frag): Remove cast of fx_where.
* config/tc-sparc.c (md_apply_fix): Likewise.
* config/tc-score.c (s3_convert_frag): Adjust for unsigned fx_where.
* config/tc-score7.c (s7_convert_frag): Likewise.
Make frag fr_fix unsigned The field only stores unsigned values, so let's make it unsigned to stop people worrying about the possibility of negative values. * frags.h (struct frag <fr_fix>): Use unsigned type. * frags.c (frag_new): Assert that current size exceeds old_frags_var_max_size. * ehopt.c (get_cie_info): Adjust for unsigned fr_fix. * listing.c (calc_hex): Likewise. * write.c (cvt_frag_to_fill, write_relocs): Likewise. * config/tc-arc.c (md_convert_frag): Likewise. * config/tc-avr.c (avr_patch_gccisr_frag): Likewise. * config/tc-mips.c (md_convert_frag): Likewise. * config/tc-rl78.c (md_convert_frag): Likewise. * config/tc-rx.c (md_convert_frag): Likewise. * config/tc-sparc.c (md_apply_fix): Likewise. * config/tc-xtensa.c (next_instrs_are_b_retw): Likewise. (unrelaxed_frag_min_insn_count, unrelaxed_frag_has_b_j): Likewise.
2019-04-15 20:21:44 +08:00
2019-04-16 Alan Modra <amodra@gmail.com>
* frags.h (struct frag <fr_fix>): Use unsigned type.
* frags.c (frag_new): Assert that current size exceeds
old_frags_var_max_size.
* ehopt.c (get_cie_info): Adjust for unsigned fr_fix.
* listing.c (calc_hex): Likewise.
* write.c (cvt_frag_to_fill, write_relocs): Likewise.
* config/tc-arc.c (md_convert_frag): Likewise.
* config/tc-avr.c (avr_patch_gccisr_frag): Likewise.
* config/tc-mips.c (md_convert_frag): Likewise.
* config/tc-rl78.c (md_convert_frag): Likewise.
* config/tc-rx.c (md_convert_frag): Likewise.
* config/tc-sparc.c (md_apply_fix): Likewise.
* config/tc-xtensa.c (next_instrs_are_b_retw): Likewise.
(unrelaxed_frag_min_insn_count, unrelaxed_frag_has_b_j): Likewise.
[binutils, ARM, 16/16] Add support to VLDR and VSTR of system registers GNU as' Arm backend assumes each mnemonic has a single entry in the instruction table but VLDR (system register) and VSTR (system register) are different instructions than VLDR and VSTR. It is thus necessary to add some form of demultiplexing in the parser. It starts by creating a new operand type OP_VLDR which indicate that the operand is either the existing OP_RVSD operand or a system register. The function parse_operands () then tries these two cases in order, calling the new parse_sys_vldr_vstr for the second case. Since the encoding function is specified in the instruction table entry, it also need to have some sort of demultiplexing. This is done in do_vldr_vstr which either calls the existing do_neon_ldr_str () or calls the new do_t_vldr_vstr_sysreg (). A new internal relocation is needed as well since the offset has a shorter range than in other Thumb coprocessor instructions. Disassembly also requires special care since VSTR (system register) reuse the STC encoding with the coprocessor number 15. Armv8.1-M Mainline ARM manual states that coprocessor 8, 14 and 15 are reserved for floating-point and MVE instructions a feature bit check is added if the coprocessor number is one of this value and we are trying to match a coprocessor instruction (eg. STC) to forbid the match. ChangeLog entries are as follows: *** bfd/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * reloc.c (BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM): New internal relocation. * bfd-in2.h: Regenerate. * libbfd.h: Likewise. *** gas/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/tc-arm.c (parse_sys_vldr_vstr): New function. (OP_VLDR): New enum operand_parse_code enumerator. (parse_operands): Add logic for OP_VLDR. (do_t_vldr_vstr_sysreg): New function. (do_vldr_vstr): Likewise. (insns): Guard VLDR and VSTR by arm_ext_v4t for Thumb mode. (md_apply_fix): Add bound check for VLDR and VSTR co-processor offset. Add masking logic for BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM relocation. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Add examples of bad uses of VLDR and VSTR. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Add error messages for above bad uses. * testsuite/gas/arm/archv8m_1m-cmse-main.s: Add examples of VLDR and VSTR valid uses. * testsuite/gas/arm/archv8m_1m-cmse-main.d: Add disassembly for the above examples. *** opcodes/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * arm-dis.c (coprocessor_opcodes): Document new %J and %K format specifier. Add entries for VLDR and VSTR of system registers. (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in coprocessor instructions on Armv8.1-M Mainline targets. Add handling of %J and %K format specifier.
2019-04-15 19:23:24 +08:00
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (parse_sys_vldr_vstr): New function.
(OP_VLDR): New enum operand_parse_code enumerator.
(parse_operands): Add logic for OP_VLDR.
(do_t_vldr_vstr_sysreg): New function.
(do_vldr_vstr): Likewise.
(insns): Guard VLDR and VSTR by arm_ext_v4t for Thumb mode.
(md_apply_fix): Add bound check for VLDR and VSTR co-processor offset.
Add masking logic for BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM relocation.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Add examples of bad
uses of VLDR and VSTR.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Add error messages for
above bad uses.
* testsuite/gas/arm/archv8m_1m-cmse-main.s: Add examples of VLDR and
VSTR valid uses.
* testsuite/gas/arm/archv8m_1m-cmse-main.d: Add disassembly for the
above examples.
[binutils, ARM, 15/16] Add support for VSCCLRM Like for CLRM, this patch aims to share as much logic with the similar looking VLDM/VSTM. This is achieved by adding 2 new enumerator values in enum reg_list_els for the single-precision and double-precision variants of VSCCLRM and extending parse_vfp_reg_list () to deal with these types. These behave like the existing REGLIST_VFP_S and REGLIST_VFP_D types with extra logic to expect VPR as the last element in the register list. The function is algo augmented with a new partial_match parameter to indicate if any register other than VPR had already been parsed in the register list so as to not try parsing the second variant if that's the case and return the right error message. The rest of the patch is the usual encoding function, new disassembler table entries and format specifier and parsing, encoding and disassembling tests. It is worth mentioning that the new entry in the disassembler table was added in the coprocessor-related table despite VSCCLRM always being available even in FPU-less configurations. The main reason for this is that VSCCLRM also match VLDMIA entry and must thus be tried first but coprocessor entries are tried before T32 entries. It also makes sense because it is in the same encoding space as coprocessor and VFP instructions and is thus the natural place for someone to look for this instruction. Note: Both variants of VSCCLRM support D16-D31 registers but Armv8.1-M Mainline overall does not. I have thus decided not to implement support for these registers in order to keep the code simpler. It can always be added later if needed. ChangeLog entries are as follows: *** gas/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/tc-arm.c (arm_typed_reg_parse): Fix typo in comment. (enum reg_list_els): New REGLIST_VFP_S_VPR and REGLIST_VFP_D_VPR enumerators. (parse_vfp_reg_list): Add new partial_match parameter. Set *partial_match to TRUE if at least one element in the register list has matched. Add support for REGLIST_VFP_S_VPR and REGLIST_VFP_D_VPR register lists which expect VPR as last element in the list. (s_arm_unwind_save_vfp_armv6): Adapt call to parse_vfp_reg_list to new prototype. (s_arm_unwind_save_vfp): Likewise. (enum operand_parse_code): New OP_VRSDVLST enumerator. (parse_operands): Adapt call to parse_vfp_reg_list to new prototype. Handle new OP_VRSDVLST case. (do_t_vscclrm): New function. (insns): New entry for VSCCLRM instruction. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Add invalid VSCCLRM instructions. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Add error expectations for above instructions. * testsuite/gas/arm/archv8m_1m-cmse-main.s: Add tests for VSCCLRM instruction. * testsuite/gas/arm/archv8m_1m-cmse-main.d: Add expected disassembly for above instructions. *** opcodes/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * arm-dis.c (coprocessor_opcodes): Document new %C format control code. Add new entries for VSCCLRM instruction. (print_insn_coprocessor): Handle new %C format control code.
2019-04-15 19:18:16 +08:00
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (arm_typed_reg_parse): Fix typo in comment.
(enum reg_list_els): New REGLIST_VFP_S_VPR and REGLIST_VFP_D_VPR
enumerators.
(parse_vfp_reg_list): Add new partial_match parameter. Set
*partial_match to TRUE if at least one element in the register list has
matched. Add support for REGLIST_VFP_S_VPR and REGLIST_VFP_D_VPR
register lists which expect VPR as last element in the list.
(s_arm_unwind_save_vfp_armv6): Adapt call to parse_vfp_reg_list to new
prototype.
(s_arm_unwind_save_vfp): Likewise.
(enum operand_parse_code): New OP_VRSDVLST enumerator.
(parse_operands): Adapt call to parse_vfp_reg_list to new prototype.
Handle new OP_VRSDVLST case.
(do_t_vscclrm): New function.
(insns): New entry for VSCCLRM instruction.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Add invalid VSCCLRM
instructions.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Add error expectations
for above instructions.
* testsuite/gas/arm/archv8m_1m-cmse-main.s: Add tests for VSCCLRM
instruction.
* testsuite/gas/arm/archv8m_1m-cmse-main.d: Add expected disassembly
for above instructions.
[binutils, ARM, 13/16] Add support for CLRM Given the similarity between LDM/STM and CLRM register lists, most of the changes in this patch aim at sharing code between those two sets of instruction. Sharing is achieved both in parsing and encoding of those instructions. In terms of parsing, parse_reg_list () is extended to take a type that describe what type of instruction is being parsed. The reg_list_els used for parse_vfp_reg_list () is reused for the type and that function is added an assert for the new REGLIST_CLRM and REGLIST_RN enumerators. parse_reg_list () is then taught to accept APSR and reject SP and PC when parsing for a CLRM instruction. At last, caller of parse_reg_list () is updated accordingly and logic is added for the new OP_CLRMLST operand. Encoding-wise, encode_thumb2_ldmstm () is reused to encode the variable bits of CLRM and is thus renamed encode_thumb2_multi (). A new do_io parameter is added to distinguish between LDM/STM and CLRM which guard all the LDM/STM specific code of the function. Finally objdump is told how to disassemble CLRM, again reusing the logic to print the LDM/STM register list (format specifier 'm'). Tests are also added in the form of negative tests to check parsing and encoding/disassembling tests. ChangeLog entries are as follows: *** gas/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/tc-arm.c (enum reg_list_els): Define earlier and add REGLIST_RN and REGLIST_CLRM enumerators. (parse_reg_list): Add etype parameter to distinguish between regular core register list and CLRM register list. Add logic to recognize CLRM register list. (parse_vfp_reg_list): Assert type is not for core register list. (s_arm_unwind_save_core): Update call to parse_reg_list to new prototype. (enum operand_parse_code): Declare OP_CLRMLST enumerator. (parse_operands): Update call to parse_reg_list to new prototype. Add logic for OP_CLRMLST. (encode_thumb2_ldmstm): Rename into ... (encode_thumb2_multi): This. Add do_io parameter. Add logic to encode CLRM and guard LDM/STM only code by do_io. (do_t_ldmstm): Adapt to use encode_thumb2_multi. (do_t_push_pop): Likewise. (do_t_clrm): New function. (insns): Define CLRM. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.d: New file. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Likewise. * testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Likewise. * testsuite/gas/arm/archv8m_1m-cmse-main.d: Likewise. * testsuite/gas/arm/archv8m_1m-cmse-main.s: Likewise. *** opcodes/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for CLRM. (print_insn_thumb32): Add logic to print %n CLRM register list.
2019-04-15 19:07:20 +08:00
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (enum reg_list_els): Define earlier and add
REGLIST_RN and REGLIST_CLRM enumerators.
(parse_reg_list): Add etype parameter to distinguish between regular
core register list and CLRM register list. Add logic to
recognize CLRM register list.
(parse_vfp_reg_list): Assert type is not for core register list.
(s_arm_unwind_save_core): Update call to parse_reg_list to new
prototype.
(enum operand_parse_code): Declare OP_CLRMLST enumerator.
(parse_operands): Update call to parse_reg_list to new prototype. Add
logic for OP_CLRMLST.
(encode_thumb2_ldmstm): Rename into ...
(encode_thumb2_multi): This. Add do_io parameter. Add logic to
encode CLRM and guard LDM/STM only code by do_io.
(do_t_ldmstm): Adapt to use encode_thumb2_multi.
(do_t_push_pop): Likewise.
(do_t_clrm): New function.
(insns): Define CLRM.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.d: New file.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Likewise.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Likewise.
* testsuite/gas/arm/archv8m_1m-cmse-main.d: Likewise.
* testsuite/gas/arm/archv8m_1m-cmse-main.s: Likewise.
[binutils, ARM, 12/16] Scalar Low Overhead loop instructions for Armv8.1-M Mainline s patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This patch adds support to the Scalar low overhead loop instructions: LE WLS DLS We also add a new assembler resolvable relocation bfd_reloc_code_real enum for the 12-bit branch offset used in these instructions. ChangeLog entries are as follows: *** bfd/ChnageLog *** 2019-04-12 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_ARM_THUMB_LOOP12): New. * bfd-in2.h: Regenerated. * libbfd.h: Regenerated. *** gas/ChangeLog *** 2019-04-12 Sudakshina Das <sudi.das@arm.com> Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (operand_parse_code): Add OP_LR and OP_oLR for the LR operand and optional LR operand. (parse_operands): Add switch cases for OP_LR and OP_oLR for both type checking and value checking. (encode_thumb32_addr_mode): New entries for DLS, WLS and LE. (v8_1_loop_reloc): New helper function for handling labels for the low overhead loop instructions. (do_t_loloop): New function to encode DLS, WLS and LE. (insns): New entries for WLS, DLS and LE. (md_pcrel_from_section): New switch case for BFD_RELOC_ARM_THUMB_LOOP12. (md_appdy_fix): Likewise. (tc_gen_reloc): Likewise. * testsuite/gas/arm/armv8_1-m-tloop.s: New. * testsuite/gas/arm/armv8_1-m-tloop.d: New. * testsuite/gas/arm/armv8_1-m-tloop-bad.s: New. * testsuite/gas/arm/armv8_1-m-tloop-bad.d: New. * testsuite/gas/arm/armv8_1-m-tloop-bad.l: New. *** opcodes/ChangeLog *** 2019-04-12 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %P and %Q patterns.
2019-04-15 18:58:47 +08:00
2019-04-15 Sudakshina Das <sudi.das@arm.com>
.file file number checking This adds another test for file numbers given in .file directives, checking that the value can be represented as an unsigned int and that a memory allocation expression doesn't overflow. I removed a test added recently since an earlier test (num < 1) already covers the (num < 0) case. * dwarf2dbg.c: Whitespace fixes. (get_filenum): Don't strdup "file". Adjust error message. (dwarf2_directive_filename): Use an unsigned type for "num". Catch truncation of file number and overflow of get_filenum XRESIZEVEC multiplication. Delete dead code.
2019-05-15 09:54:09 +08:00
Andre Vieira <andre.simoesdiasvieira@arm.com>
[binutils, ARM, 12/16] Scalar Low Overhead loop instructions for Armv8.1-M Mainline s patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This patch adds support to the Scalar low overhead loop instructions: LE WLS DLS We also add a new assembler resolvable relocation bfd_reloc_code_real enum for the 12-bit branch offset used in these instructions. ChangeLog entries are as follows: *** bfd/ChnageLog *** 2019-04-12 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_ARM_THUMB_LOOP12): New. * bfd-in2.h: Regenerated. * libbfd.h: Regenerated. *** gas/ChangeLog *** 2019-04-12 Sudakshina Das <sudi.das@arm.com> Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (operand_parse_code): Add OP_LR and OP_oLR for the LR operand and optional LR operand. (parse_operands): Add switch cases for OP_LR and OP_oLR for both type checking and value checking. (encode_thumb32_addr_mode): New entries for DLS, WLS and LE. (v8_1_loop_reloc): New helper function for handling labels for the low overhead loop instructions. (do_t_loloop): New function to encode DLS, WLS and LE. (insns): New entries for WLS, DLS and LE. (md_pcrel_from_section): New switch case for BFD_RELOC_ARM_THUMB_LOOP12. (md_appdy_fix): Likewise. (tc_gen_reloc): Likewise. * testsuite/gas/arm/armv8_1-m-tloop.s: New. * testsuite/gas/arm/armv8_1-m-tloop.d: New. * testsuite/gas/arm/armv8_1-m-tloop-bad.s: New. * testsuite/gas/arm/armv8_1-m-tloop-bad.d: New. * testsuite/gas/arm/armv8_1-m-tloop-bad.l: New. *** opcodes/ChangeLog *** 2019-04-12 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %P and %Q patterns.
2019-04-15 18:58:47 +08:00
* config/tc-arm.c (operand_parse_code): Add OP_LR and OP_oLR
for the LR operand and optional LR operand.
(parse_operands): Add switch cases for OP_LR and OP_oLR for
both type checking and value checking.
(encode_thumb32_addr_mode): New entries for DLS, WLS and LE.
(v8_1_loop_reloc): New helper function for handling labels
for the low overhead loop instructions.
(do_t_loloop): New function to encode DLS, WLS and LE.
(insns): New entries for WLS, DLS and LE.
(md_pcrel_from_section): New switch case
for BFD_RELOC_ARM_THUMB_LOOP12.
(md_appdy_fix): Likewise.
(tc_gen_reloc): Likewise.
* testsuite/gas/arm/armv8_1-m-tloop.s: New.
* testsuite/gas/arm/armv8_1-m-tloop.d: New.
* testsuite/gas/arm/armv8_1-m-tloop-bad.s: New.
* testsuite/gas/arm/armv8_1-m-tloop-bad.d: New.
* testsuite/gas/arm/armv8_1-m-tloop-bad.l: New.
[binutils, ARM, 11/16] New BFCSEL instruction for Armv8.1-M Mainline s patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This patch adds the BFCSEL instruction. It also adds a local relocation with a new bfd_reloc_code_real enum. ChangeLog entries are as follows: 2019-04-15 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_THUMB_PCREL_BFCSEL): New relocation. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (T16_32_TAB): New entriy for bfcsel. (do_t_v8_1_branch): New switch case for bfcsel. (toU): Define. (insns): New instruction for bfcsel. (md_pcrel_from_section): New switch case for BFD_RELOC_THUMB_PCREL_BFCSEL. (md_appdy_fix): Likewise (tc_gen_reloc): Likewise. * testsuite/gas/arm/armv8_1-m-bfcsel.d: New. * testsuite/gas/arm/armv8_1-m-bfcsel.s: New. *** ld/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * testsuite/ld-arm/bfcsel.s: New. * testsuite/ld-arm/bfcsel.d: New. * testsuite/ld-arm/arm-elf.exp: Add above test. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (thumb32_opcodes): New instruction bfcsel. (print_insn_thumb32): Edit the switch case for %Z.
2019-04-15 18:53:25 +08:00
2019-04-15 Sudakshina Das <sudi.das@arm.com>
.file file number checking This adds another test for file numbers given in .file directives, checking that the value can be represented as an unsigned int and that a memory allocation expression doesn't overflow. I removed a test added recently since an earlier test (num < 1) already covers the (num < 0) case. * dwarf2dbg.c: Whitespace fixes. (get_filenum): Don't strdup "file". Adjust error message. (dwarf2_directive_filename): Use an unsigned type for "num". Catch truncation of file number and overflow of get_filenum XRESIZEVEC multiplication. Delete dead code.
2019-05-15 09:54:09 +08:00
Andre Vieira <andre.simoesdiasvieira@arm.com>
[binutils, ARM, 11/16] New BFCSEL instruction for Armv8.1-M Mainline s patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This patch adds the BFCSEL instruction. It also adds a local relocation with a new bfd_reloc_code_real enum. ChangeLog entries are as follows: 2019-04-15 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_THUMB_PCREL_BFCSEL): New relocation. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (T16_32_TAB): New entriy for bfcsel. (do_t_v8_1_branch): New switch case for bfcsel. (toU): Define. (insns): New instruction for bfcsel. (md_pcrel_from_section): New switch case for BFD_RELOC_THUMB_PCREL_BFCSEL. (md_appdy_fix): Likewise (tc_gen_reloc): Likewise. * testsuite/gas/arm/armv8_1-m-bfcsel.d: New. * testsuite/gas/arm/armv8_1-m-bfcsel.s: New. *** ld/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * testsuite/ld-arm/bfcsel.s: New. * testsuite/ld-arm/bfcsel.d: New. * testsuite/ld-arm/arm-elf.exp: Add above test. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (thumb32_opcodes): New instruction bfcsel. (print_insn_thumb32): Edit the switch case for %Z.
2019-04-15 18:53:25 +08:00
* config/tc-arm.c (T16_32_TAB): New entriy for bfcsel.
(do_t_v8_1_branch): New switch case for bfcsel.
(toU): Define.
(insns): New instruction for bfcsel.
(md_pcrel_from_section): New switch case
for BFD_RELOC_THUMB_PCREL_BFCSEL.
(md_appdy_fix): Likewise
(tc_gen_reloc): Likewise.
* testsuite/gas/arm/armv8_1-m-bfcsel.d: New.
* testsuite/gas/arm/armv8_1-m-bfcsel.s: New.
[binutils, ARM, 10/16] BFCSEL infrastructure with new global reloc R_ARM_THM_BF12 This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This adds infrastructure for the BFCSEL instructions which is one of the first instructions in Arm that have more than one relocations in them. This adds a new relocation R_ARM_THM_BF12. The inconsistency between external R_ARM_THM_BF12 and internal BFD_RELOC_ARM_THUMB_BF13 is because internally we count the static bit-0 of the immediate and we don't externally. ChangeLog entries are as follows : ChangeLog entries are as follows : *** bfd/ChnageLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_ARM_THUMB_BF13): New. * bfd-in2.h: Regenerated. * libbfd.h: Regenerated. * elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF13. (elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF13 and R_ARM_THM_BF12 together. (elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF13. *** elfcpp/ChangeLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * arm.h (R_ARM_THM_BF12): New relocation code. *** gas/ChangeLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (md_pcrel_from_section): New switch case for BFD_RELOC_ARM_THUMB_BF13. (md_appdy_fix): Likewise. (tc_gen_reloc): Likewise. *** include/ChangeLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF12. *** opcodes/ChangeLog *** 2019-04-04 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
2019-04-15 18:46:54 +08:00
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (md_pcrel_from_section): New switch case for
BFD_RELOC_ARM_THUMB_BF13.
(md_appdy_fix): Likewise.
(tc_gen_reloc): Likewise.
[binutils, ARM, 9/16] New BFL instruction for Armv8.1-M Mainline This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This patch adds the BFL instruction. *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (T16_32_TAB): New entrie for bfl. (do_t_v8_1_branch): New switch case for bfl. (insns): New instruction for bfl. * testsuite/gas/arm/armv8_1-m-bfl.d: New. * testsuite/gas/arm/armv8_1-m-bfl.s: New. * testsuite/gas/arm/armv8_1-m-bfl-bad.s: New. * testsuite/gas/arm/armv8_1-m-bfl-bad.d: New. * testsuite/gas/arm/armv8_1-m-bfl-bad.l: New. * testsuite/gas/arm/armv8_1-m-bfl-rel.d: New. * testsuite/gas/arm/armv8_1-m-bfl-rel.s: New. *** ld/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * testsuite/ld-arm/bfl.s: New. * testsuite/ld-arm/bfl.d: New. * testsuite/ld-arm/arm-elf.exp: Add above test. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (thumb32_opcodes): New instruction bfl.
2019-04-15 18:42:10 +08:00
2019-04-15 Sudakshina Das <sudi.das@arm.com>
.file file number checking This adds another test for file numbers given in .file directives, checking that the value can be represented as an unsigned int and that a memory allocation expression doesn't overflow. I removed a test added recently since an earlier test (num < 1) already covers the (num < 0) case. * dwarf2dbg.c: Whitespace fixes. (get_filenum): Don't strdup "file". Adjust error message. (dwarf2_directive_filename): Use an unsigned type for "num". Catch truncation of file number and overflow of get_filenum XRESIZEVEC multiplication. Delete dead code.
2019-05-15 09:54:09 +08:00
Andre Vieira <andre.simoesdiasvieira@arm.com>
[binutils, ARM, 9/16] New BFL instruction for Armv8.1-M Mainline This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This patch adds the BFL instruction. *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (T16_32_TAB): New entrie for bfl. (do_t_v8_1_branch): New switch case for bfl. (insns): New instruction for bfl. * testsuite/gas/arm/armv8_1-m-bfl.d: New. * testsuite/gas/arm/armv8_1-m-bfl.s: New. * testsuite/gas/arm/armv8_1-m-bfl-bad.s: New. * testsuite/gas/arm/armv8_1-m-bfl-bad.d: New. * testsuite/gas/arm/armv8_1-m-bfl-bad.l: New. * testsuite/gas/arm/armv8_1-m-bfl-rel.d: New. * testsuite/gas/arm/armv8_1-m-bfl-rel.s: New. *** ld/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * testsuite/ld-arm/bfl.s: New. * testsuite/ld-arm/bfl.d: New. * testsuite/ld-arm/arm-elf.exp: Add above test. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (thumb32_opcodes): New instruction bfl.
2019-04-15 18:42:10 +08:00
* config/tc-arm.c (T16_32_TAB): New entrie for bfl.
(do_t_v8_1_branch): New switch case for bfl.
(insns): New instruction for bfl.
* testsuite/gas/arm/armv8_1-m-bfl.d: New.
* testsuite/gas/arm/armv8_1-m-bfl.s: New.
* testsuite/gas/arm/armv8_1-m-bfl-bad.s: New.
* testsuite/gas/arm/armv8_1-m-bfl-bad.d: New.
* testsuite/gas/arm/armv8_1-m-bfl-bad.l: New.
* testsuite/gas/arm/armv8_1-m-bfl-rel.d: New.
* testsuite/gas/arm/armv8_1-m-bfl-rel.s: New.
[binutils, ARM, 8/16] BFL infrastructure with new global reloc R_ARM_THM_BF18 This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This adds infrastructure for the BFL instructions which is one of the first instructions in Arm that have more than one relocations in them. This adds a new relocation R_ARM_THM_BF18. The inconsistency between external R_ARM_THM_BF18 and internal BFD_RELOC_ARM_THUMB_BF19 is because internally we count the static bit-0 of the immediate and we don't externally. ChangeLog entries are as follows : *** bfd/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_ARM_THUMB_BF19): New * libbfd.h: Regenerated. * bfd-in2.h: Regenerated. * bfd-elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF18. (elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF19 and R_ARM_THM_BF18 together. (elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF19. *** elfcpp/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm.h (R_ARM_THM_BF18): New relocation code. *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (md_pcrel_from_section): New switch case for BFD_RELOC_ARM_THUMB_BF19. (md_appdy_fix): Likewise. (tc_gen_reloc): Likewise. *** include/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF18. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
2019-04-15 18:37:51 +08:00
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (md_pcrel_from_section): New switch case for
BFD_RELOC_ARM_THUMB_BF19.
(md_appdy_fix): Likewise.
(tc_gen_reloc): Likewise.
[binutils, ARM, 7/16] New BFX and BFLX instruction for Armv8.1-M Mainline This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This patch adds the BFX and BFLX instructions. ChangeLog entries are as follows : *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (T16_32_TAB): New entries for bfx and bflx. (do_t_v8_1_branch): New switch cases for bfx and bflx. (insns): New instruction for bfx and bflx. * testsuite/gas/arm/armv8_1-m-bf-exchange.d: New. * testsuite/gas/arm/armv8_1-m-bf-exchange.s: New. * testsuite/gas/arm/armv8_1-m-bf-exchange-bad.s: New * testsuite/gas/arm/armv8_1-m-bf-exchange-bad.l: New * testsuite/gas/arm/armv8_1-m-bf-exchange-bad.d: New *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an Arm register with r13 and r15 unpredictable. (thumb32_opcodes): New instructions for bfx and bflx.
2019-04-15 18:29:14 +08:00
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (T16_32_TAB): New entries for bfx and bflx.
(do_t_v8_1_branch): New switch cases for bfx and bflx.
(insns): New instruction for bfx and bflx.
* testsuite/gas/arm/armv8_1-m-bf-exchange.d: New.
* testsuite/gas/arm/armv8_1-m-bf-exchange.s: New.
* testsuite/gas/arm/armv8_1-m-bf-exchange-bad.s: New
* testsuite/gas/arm/armv8_1-m-bf-exchange-bad.l: New
* testsuite/gas/arm/armv8_1-m-bf-exchange-bad.d: New
[binutils, ARM, 6/16] New BF instruction for Armv8.1-M Mainline This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This patch adds the BF instruction. ChangeLog entries are as follows: *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (T16_32_TAB): New entries for bf. (do_t_branch_future): New. (insns): New instruction for bf. * testsuite/gas/arm/armv8_1-m-bf.d: New. * testsuite/gas/arm/armv8_1-m-bf.s: New. * testsuite/gas/arm/armv8_1-m-bf-bad.s: New. * testsuite/gas/arm/armv8_1-m-bf-bad.l: New. * testsuite/gas/arm/armv8_1-m-bf-bad.d: New. * testsuite/gas/arm/armv8_1-m-bf-rel.d: New. * testsuite/gas/arm/armv8_1-m-bf-rel.s: New. *** ld/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * testsuite/ld-arm/bf.s: New. * testsuite/ld-arm/bf.d: New. * testsuite/ld-arm/arm-elf.exp: Add above test. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (thumb32_opcodes): New instructions for bf.
2019-04-15 18:25:12 +08:00
2019-04-15 Sudakshina Das <sudi.das@arm.com>
.file file number checking This adds another test for file numbers given in .file directives, checking that the value can be represented as an unsigned int and that a memory allocation expression doesn't overflow. I removed a test added recently since an earlier test (num < 1) already covers the (num < 0) case. * dwarf2dbg.c: Whitespace fixes. (get_filenum): Don't strdup "file". Adjust error message. (dwarf2_directive_filename): Use an unsigned type for "num". Catch truncation of file number and overflow of get_filenum XRESIZEVEC multiplication. Delete dead code.
2019-05-15 09:54:09 +08:00
Andre Vieira <andre.simoesdiasvieira@arm.com>
[binutils, ARM, 6/16] New BF instruction for Armv8.1-M Mainline This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This patch adds the BF instruction. ChangeLog entries are as follows: *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (T16_32_TAB): New entries for bf. (do_t_branch_future): New. (insns): New instruction for bf. * testsuite/gas/arm/armv8_1-m-bf.d: New. * testsuite/gas/arm/armv8_1-m-bf.s: New. * testsuite/gas/arm/armv8_1-m-bf-bad.s: New. * testsuite/gas/arm/armv8_1-m-bf-bad.l: New. * testsuite/gas/arm/armv8_1-m-bf-bad.d: New. * testsuite/gas/arm/armv8_1-m-bf-rel.d: New. * testsuite/gas/arm/armv8_1-m-bf-rel.s: New. *** ld/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * testsuite/ld-arm/bf.s: New. * testsuite/ld-arm/bf.d: New. * testsuite/ld-arm/arm-elf.exp: Add above test. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (thumb32_opcodes): New instructions for bf.
2019-04-15 18:25:12 +08:00
* config/tc-arm.c (T16_32_TAB): New entries for bf.
(do_t_branch_future): New.
(insns): New instruction for bf.
* testsuite/gas/arm/armv8_1-m-bf.d: New.
* testsuite/gas/arm/armv8_1-m-bf.s: New.
* testsuite/gas/arm/armv8_1-m-bf-bad.s: New.
* testsuite/gas/arm/armv8_1-m-bf-bad.l: New.
* testsuite/gas/arm/armv8_1-m-bf-bad.d: New.
* testsuite/gas/arm/armv8_1-m-bf-rel.d: New.
* testsuite/gas/arm/armv8_1-m-bf-rel.s: New.
[binutils, ARM, 5/16] BF insns infrastructure with new global reloc R_ARM_THM_BF16 This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This adds infrastructure for the BF instructions which is one of the first instructions in Arm that have more than one relocations in them. This is the third infrastructure patch that adds a new relocation R_ARM_THM_BF16. The inconsistency between external R_ARM_THM_BF16 and internal BFD_RELOC_ARM_THUMB_BF17 is because internally we count the static bit-0 of the immediate and we don't externally. ChangeLog entries are as follows : *** bfd/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_ARM_THUMB_BF17): New enum. * bfd-in2.h: Regenerated. * libbfd.h: Regenerated. * bfd-elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF16. (elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF17 and R_ARM_THM_BF16 together. (get_value_helper): New reloc helper. (elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF16. *** elfcpp/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm.h (R_ARM_THM_BF16): New relocation code. *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (md_pcrel_from_section): New switch case for BFD_RELOC_ARM_THUMB_BF17. (md_appdy_fix): Likewise. (tc_gen_reloc): Likewise. *** include/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF16. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
2019-04-15 18:18:57 +08:00
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (md_pcrel_from_section): New switch case for
BFD_RELOC_ARM_THUMB_BF17.
(md_appdy_fix): Likewise.
(tc_gen_reloc): Likewise.
[binutils, ARM, 4/16] BF insns infrastructure with array of relocs in struct arm_it This patch is part of a series of patches to add support for ARMv8.1-M Mainline instructions to binutils. This adds infrastructure for the Branch Future instructions (BF, BFX, BFL, BFLX, BFCSEL). These are the first instructions in ARM that have more than one relocations in them. Their external relocations can be found in the 'ELF for the Arm Architecture - ABI 2019Q1' document on developer.arm.com This is the second infrastructure patch that adds support to allow up to 3 relocations in an instruction. This is done by changing the reloc member of struct arm_it to an array instead (relocs[3]). All the previous occurrences of reloc can now to referring to relocs[0]. ChangeLog entries are as follows : *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (ARM_IT_MAX_RELOCS): New macro. (arm_it): Member reloc renamed relocs and updated to an array. Rest: Replace all occurrences of reloc to relocs[0].
2019-04-15 18:12:57 +08:00
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (ARM_IT_MAX_RELOCS): New macro.
(arm_it): Member reloc renamed relocs and updated to an array.
Rest: Replace all occurrences of reloc to relocs[0].
[binutils, ARM, 3/16] BF insns infrastructure with new bfd_reloc_code_real for fallback branch This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This adds infrastructure for the Branch Future instructions (BF, BFX, BFL, BFLX, BFCSEL). These are the first instructions in ARM that have more than one relocations in them. This is the first infrastructure patch that adds a new bfd_reloc_code_real enum for the fallback branch offset. This is common for all such instructions and needs to be resolvable by the assembler. ChangeLog entries are as follows : *** bfd/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * reloc.c (BFD_RELOC_THUMB_PCREL_BRANCH5): New enum. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. *** gas/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (md_pcrel_from_section): New switch case for BFD_RELOC_THUMB_PCREL_BRANCH5. (v8_1_branch_value_check): New function to check branch offsets. (md_appdy_fix): New switch case for BFD_RELOC_THUMB_PCREL_BRANCH5. (tc_gen_reloc): Likewise. *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
2019-04-15 18:06:30 +08:00
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (md_pcrel_from_section): New switch case
for BFD_RELOC_THUMB_PCREL_BRANCH5.
(v8_1_branch_value_check): New function to check branch
offsets.
(md_appdy_fix): New switch case for
BFD_RELOC_THUMB_PCREL_BRANCH5.
(tc_gen_reloc): Likewise.
[GAS, ARM, 2/16] Add CLI extension support for Armv8.1-M Mainline This patch implements the dsp, fp and fp.dp extensions for Armv8.1-M Mainline. This patch also removes the fp-armv8 check from the half-precision move instructions 'do_neon_movhf', as checking that the FP16 instructions extension feature bit is enabled 'ARM_EXT2_FP16_INST' is enough. gas/ChangeLog: 2019-04-15 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (do_neon_movhf): Remove fp-armv8 check. (armv8_1m_main_ext_table): New extension table. (arm_archs): Use the new extension table. * doc/c-arm.texi: Add missing arch and document new extensions. * testsuite/gas/arm/armv8.1-m.main-fp.d: New. * testsuite/gas/arm/armv8.1-m.main-fp-dp.d: New. * testsuite/gas/arm/armv8.1-m.main-hp.d: New.
2019-04-15 18:00:21 +08:00
2019-04-15 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_neon_movhf): Remove fp-armv8 check.
(armv8_1m_main_ext_table): New extension table.
(arm_archs): Use the new extension table.
* doc/c-arm.texi: Add missing arch and document new extensions.
* testsuite/gas/arm/armv8.1-m.main-fp.d: New.
* testsuite/gas/arm/armv8.1-m.main-fp-dp.d: New.
* testsuite/gas/arm/armv8.1-m.main-hp.d: New.
[binutils, ARM, 1/16] Add support for Armv8.1-M Mainline CLI The patch is straightforward, it does the following: - support the new Tag_CPU_arch build attribute value, ie.: + declare the new value + update all the asserts forcing logic to be reviewed for new architectures + create a corresponding bfd_mach_arm_8_1M_MAIN enumerator in bfd and add mapping from Tag_CPU_arch to it + teach readelf about new Tag_CPU_arch value - declare armv8.1-m.main as a supported architecture value - define Armv8.1-M Mainline in terms of feature bits available - tell objdump mapping from bfd_mach_arm_8_1M_MAIN enumerator to feature bits available - update architecture-specific logic in gas and bfd guarded by the asserts mentioned above. - tests for all the above ChangeLog entries are as follows: *** bfd/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * archures.c (bfd_mach_arm_8_1M_MAIN): Define. * bfd-in2.h: Regenerate. * cpu-arm.c (arch_info_struct): Add entry for Armv8.1-M Mainline. * elf32-arm.c (using_thumb_only): Return true for Armv8.1-M Mainline and update assert. (using_thumb2): Likewise. (using_thumb2_bl): Update assert. (arch_has_arm_nop): Likewise. (bfd_arm_get_mach_from_attributes): Add case for Armv8.1-M Mainline. (tag_cpu_arch_combine): Add logic for Armv8.1-M Mainline merging. *** binutils/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * readelf.c (arm_attr_tag_CPU_arch): Add entry for Armv8.1-M Mainline. *** gas/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/tc-arm.c (cpu_arch_ver): Add entry for Armv8.1-M Mainline Tag_CPU_arch build attribute value. Reindent. (get_aeabi_cpu_arch_from_fset): Update assert. (aeabi_set_public_attributes): Update assert for Tag_DIV_use logic. * testsuite/gas/arm/attr-march-armv8_1-m.main.d: New test. *** include/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * elf/arm.h (TAG_CPU_ARCH_V8_1M_MAIN): new macro. (MAX_TAG_CPU_ARCH): Set value to above macro. * opcode/arm.h (ARM_EXT2_V8_1M_MAIN): New macro. (ARM_AEXT_V8_1M_MAIN): Likewise. (ARM_AEXT2_V8_1M_MAIN): Likewise. (ARM_ARCH_V8_1M_MAIN): Likewise. *** ld/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * testsuite/ld-arm/attr-merge-13.attr: New test. * testsuite/ld-arm/attr-merge-13a.s: New test. * testsuite/ld-arm/attr-merge-13b.s: New test. *** opcodes/ChangeLog *** 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
2019-04-15 17:54:42 +08:00
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (cpu_arch_ver): Add entry for Armv8.1-M Mainline
Tag_CPU_arch build attribute value. Reindent.
(get_aeabi_cpu_arch_from_fset): Update assert.
(aeabi_set_public_attributes): Update assert for Tag_DIV_use logic.
* testsuite/gas/arm/attr-march-armv8_1-m.main.d: New test.
[MIPS] Add i6500 CPU and fix i6400 default ASEs gas/ * config/tc-mips.c (mips_cpu_info_table): Add i6500. Update default ASEs for i6400. * doc/c-mips.texi (-march): Document i6500. * testsuite/gas/mips/elf_mach_i6400.d: New test. * testsuite/gas/mips/elf_mach_i6500.d: New test. * testsuite/gas/mips/mips.exp: Run the new tests.
2019-04-10 04:40:00 +08:00
2019-04-09 Matthew Fortune <matthew.fortune@mips.com>
* config/tc-mips.c (mips_cpu_info_table): Add i6500. Update
default ASEs for i6400.
* doc/c-mips.texi (-march): Document i6500.
* testsuite/gas/mips/elf_mach_i6400.d: New test.
* testsuite/gas/mips/elf_mach_i6500.d: New test.
* testsuite/gas/mips/mips.exp: Run the new tests.
[MIPS] Apply ASE information for the selected processor GAS does not enable implicit ASEs for most MIPS processors. The rework of option handling done as part of .module implementation left the implicit ASE logic broken and default enabled ASEs for most processors did not get applied. This patch ensures the ASE information is carried forward to the point where it is required. gas/ * config/tc-mips.c (mips_set_options) <init_ase>: New field. (file_mips_opts, mips_opts) <init_ase>: Initialize new field. (file_mips_check_options): Propagate initial ASE settings. (mips_after_parse_args, parse_code_option): Track the initial ASE settings for a CPU. (s_mipsset): Restore the initial ASE settings when reverting to the default arch. * testsuite/gas/mips/elf_mach_p6600.d: New test. * testsuite/gas/mips/mips.exp: Run the new test.
2019-04-10 01:34:48 +08:00
2019-04-09 Matthew Fortune <matthew.fortune@mips.com>
* config/tc-mips.c (mips_set_options) <init_ase>: New field.
(file_mips_opts, mips_opts) <init_ase>: Initialize new field.
(file_mips_check_options): Propagate initial ASE settings.
(mips_after_parse_args, parse_code_option): Track the initial
ASE settings for a CPU.
(s_mipsset): Restore the initial ASE settings when reverting
to the default arch.
* testsuite/gas/mips/elf_mach_p6600.d: New test.
* testsuite/gas/mips/mips.exp: Run the new test.
GAS: S12Z: Remove definition of macro TC_M68K. gas/config: * tc-s12z.h: Remove inappropriate macro definition.
2019-04-13 00:39:01 +08:00
2019-04-12 John Darrington <john@darrington.wattle.id.au>
.file file number checking This adds another test for file numbers given in .file directives, checking that the value can be represented as an unsigned int and that a memory allocation expression doesn't overflow. I removed a test added recently since an earlier test (num < 1) already covers the (num < 0) case. * dwarf2dbg.c: Whitespace fixes. (get_filenum): Don't strdup "file". Adjust error message. (dwarf2_directive_filename): Use an unsigned type for "num". Catch truncation of file number and overflow of get_filenum XRESIZEVEC multiplication. Delete dead code.
2019-05-15 09:54:09 +08:00
GAS: S12Z: Remove definition of macro TC_M68K. gas/config: * tc-s12z.h: Remove inappropriate macro definition.
2019-04-13 00:39:01 +08:00
config/tc-s12z.h: Remove definition of macro TC_M68K
GAS: tc-s12z.c: int -> bfd_boolean Use bfd_boolean where appropriate.
2019-04-13 00:39:01 +08:00
2019-04-01 John Darrington <john@darrington.wattle.id.au>
.file file number checking This adds another test for file numbers given in .file directives, checking that the value can be represented as an unsigned int and that a memory allocation expression doesn't overflow. I removed a test added recently since an earlier test (num < 1) already covers the (num < 0) case. * dwarf2dbg.c: Whitespace fixes. (get_filenum): Don't strdup "file". Adjust error message. (dwarf2_directive_filename): Use an unsigned type for "num". Catch truncation of file number and overflow of get_filenum XRESIZEVEC multiplication. Delete dead code.
2019-05-15 09:54:09 +08:00
GAS: tc-s12z.c: int -> bfd_boolean Use bfd_boolean where appropriate.
2019-04-13 00:39:01 +08:00
config/tc-s12z.c: Use bfd_boolean where appropriate.
xtensa: gas: add relaxations tests gas/ 2019-04-11 Max Filippov <jcmvbkbc@gmail.com> * testsuite/gas/xtensa/loop-relax-2.d: New test definition. * testsuite/gas/xtensa/loop-relax.d: New test definition. * testsuite/gas/xtensa/loop-relax.s: New test source. * testsuite/gas/xtensa/text-section-literals-1a.d: New test definition. * testsuite/gas/xtensa/text-section-literals-2.d: New test definition. * testsuite/gas/xtensa/text-section-literals-2.s: New test source. * testsuite/gas/xtensa/text-section-literals-2a.d: New test definition. * testsuite/gas/xtensa/text-section-literals-3.d: New test definition. * testsuite/gas/xtensa/text-section-literals-3.s: New test source. * testsuite/gas/xtensa/text-section-literals-4.d: New test definition. * testsuite/gas/xtensa/text-section-literals-4.s: New test source. * testsuite/gas/xtensa/text-section-literals-4a.d: New test definition.
2019-04-05 08:06:57 +08:00
2019-04-11 Max Filippov <jcmvbkbc@gmail.com>
* testsuite/gas/xtensa/loop-relax-2.d: New test definition.
* testsuite/gas/xtensa/loop-relax.d: New test definition.
* testsuite/gas/xtensa/loop-relax.s: New test source.
* testsuite/gas/xtensa/text-section-literals-1a.d: New test
definition.
* testsuite/gas/xtensa/text-section-literals-2.d: New test
definition.
* testsuite/gas/xtensa/text-section-literals-2.s: New test
source.
* testsuite/gas/xtensa/text-section-literals-2a.d: New test
definition.
* testsuite/gas/xtensa/text-section-literals-3.d: New test
definition.
* testsuite/gas/xtensa/text-section-literals-3.s: New test
source.
* testsuite/gas/xtensa/text-section-literals-4.d: New test
definition.
* testsuite/gas/xtensa/text-section-literals-4.s: New test
source.
* testsuite/gas/xtensa/text-section-literals-4a.d: New test
definition.
xtensa: gas: convert tests to run_dump_tests gas/ 2019-04-11 Max Filippov <jcmvbkbc@gmail.com> * testsuite/gas/xtensa/all.exp: Remove all expect-based tests and all explicit run_dump_test / run_list_test invocations. Add run_dump_tests for all .d files in the test subdirectory. * testsuite/gas/xtensa/entry_align.d: New test definition. * testsuite/gas/xtensa/entry_align.l: New test output. * testsuite/gas/xtensa/entry_misalign.d: New test definition. * testsuite/gas/xtensa/entry_misalign2.d: New test definition. * testsuite/gas/xtensa/j_too_far.d: New test definition. * testsuite/gas/xtensa/j_too_far.l: New test output. * testsuite/gas/xtensa/loop_align.d: New test definition. * testsuite/gas/xtensa/loop_misalign.d: New test definition. * testsuite/gas/xtensa/trampoline-2.d: New test definition. * testsuite/gas/xtensa/trampoline-2.l: Remove empty output. * testsuite/gas/xtensa/xtensa-err.exp: Use positive logic.
2019-04-05 08:51:00 +08:00
2019-04-11 Max Filippov <jcmvbkbc@gmail.com>
* testsuite/gas/xtensa/all.exp: Remove all expect-based
tests and all explicit run_dump_test / run_list_test
invocations. Add run_dump_tests for all .d files in the
test subdirectory.
* testsuite/gas/xtensa/entry_align.d: New test definition.
* testsuite/gas/xtensa/entry_align.l: New test output.
* testsuite/gas/xtensa/entry_misalign.d: New test definition.
* testsuite/gas/xtensa/entry_misalign2.d: New test definition.
* testsuite/gas/xtensa/j_too_far.d: New test definition.
* testsuite/gas/xtensa/j_too_far.l: New test output.
* testsuite/gas/xtensa/loop_align.d: New test definition.
* testsuite/gas/xtensa/loop_misalign.d: New test definition.
* testsuite/gas/xtensa/trampoline-2.d: New test definition.
* testsuite/gas/xtensa/trampoline-2.l: Remove empty output.
* testsuite/gas/xtensa/xtensa-err.exp: Use positive logic.
xtensa: gas: clean up literal management code gas/ 2019-04-11 Max Filippov <jcmvbkbc@gmail.com> * config/tc-xtensa.c (xtensa_literal_pseudo): Drop code that has no effect. (get_literal_pool_location): Only search for the literal pool when auto litpools is used, otherwise take one recorded in the tc_segment_info_data. (xtensa_assign_litpool_addresses): New function. (xtensa_move_literals): Don't duplicate 'literal pool location required...' error message. Call xtensa_assign_litpool_addresses.
2019-04-10 16:18:01 +08:00
2019-04-11 Max Filippov <jcmvbkbc@gmail.com>
* config/tc-xtensa.c (xtensa_literal_pseudo): Drop code that has
no effect.
(get_literal_pool_location): Only search for the literal pool
when auto litpools is used, otherwise take one recorded in the
tc_segment_info_data.
(xtensa_assign_litpool_addresses): New function.
(xtensa_move_literals): Don't duplicate 'literal pool location
required...' error message. Call xtensa_assign_litpool_addresses.
xtensa: gas: put .literal_position at section start Provide literal position at the beginning of each section for literal space reserved by relaxations when text-section-literals or auto-litpools options are used. Remove code that adds fill frag to the literal section for every .literal_position directive to avoid creation of empty literal sections. Fix auto-litpools tests that got literal pool address changes. gas/ 2019-04-11 Max Filippov <jcmvbkbc@gmail.com> * config/tc-xtensa.c (xtensa_is_init_fini): Add declaration. (xtensa_mark_literal_pool_location): Don't add fill frag to literal section that records literal pool location. (md_begin): Call xtensa_mark_literal_pool_location when text section literals or auto litpools are used. (xtensa_elf_section_change_hook): Call xtensa_mark_literal_pool_location when text section literals or auto litpools are used, there's no literal pool location defined for the current section and it's not .init or .fini. * testsuite/gas/xtensa/auto-litpools-first1.d: Fix up addresses. * testsuite/gas/xtensa/auto-litpools-first2.d: Likewise. * testsuite/gas/xtensa/auto-litpools.d: Likewise.
2019-04-09 04:47:18 +08:00
2019-04-11 Max Filippov <jcmvbkbc@gmail.com>
* config/tc-xtensa.c (xtensa_is_init_fini): Add declaration.
(xtensa_mark_literal_pool_location): Don't add fill frag to literal
section that records literal pool location.
(md_begin): Call xtensa_mark_literal_pool_location when text
section literals or auto litpools are used.
(xtensa_elf_section_change_hook): Call
xtensa_mark_literal_pool_location when text section literals or
auto litpools are used, there's no literal pool location defined
for the current section and it's not .init or .fini.
* testsuite/gas/xtensa/auto-litpools-first1.d: Fix up addresses.
* testsuite/gas/xtensa/auto-litpools-first2.d: Likewise.
* testsuite/gas/xtensa/auto-litpools.d: Likewise.
[BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructions This patch updates the Store allocation tags instructions in Armv8.5-A Memory Tagging Extension. This is part of the changes that have been introduced recently in the 00bet10 release All of these instructions have an updated register operand (Xt -> <Xt|SP>) - STG <Xt|SP>, [<Xn|SP>, #<simm>] - STG <Xt|SP>, [<Xn|SP>, #<simm>]! - STG <Xt|SP>, [<Xn|SP>], #<simm> - STZG <Xt|SP>, [<Xn|SP>, #<simm>] - STZG <Xt|SP>, [<Xn|SP>, #<simm>]! - STZG <Xt|SP>, [<Xn|SP>], #<simm> - ST2G <Xt|SP>, [<Xn|SP>, #<simm>] - ST2G <Xt|SP>, [<Xn|SP>, #<simm>]! - ST2G <Xt|SP>, [<Xn|SP>], #<simm> - STZ2G <Xt|SP>, [<Xn|SP>, #<simm>] - STZ2G <Xt|SP>, [<Xn|SP>, #<simm>]! - STZ2G <Xt|SP>, [<Xn|SP>], #<simm> In order to accept <Rt|SP> a new operand type Rt_SP is introduced which has the same field as FLD_Rt but follows other semantics of Rn_SP. *** gas/ChangeLog *** 2019-04-11 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (process_omitted_operand): Add case for AARCH64_OPND_Rt_SP. (parse_operands): Likewise. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Update tests. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. *** include/ChangeLog *** 2019-04-11 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rt_SP. *** opcodes/ChangeLog *** 2019-04-11 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.c (aarch64_print_operand): Add case for AARCH64_OPND_Rt_SP. (verify_constraints): Likewise. * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier. (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions to accept Rt|SP as first operand. (AARCH64_OPERANDS): Add new Rt_SP. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
2019-04-11 17:19:37 +08:00
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (process_omitted_operand): Add case for
AARCH64_OPND_Rt_SP.
(parse_operands): Likewise.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Update tests.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
[BINUTILS, AArch64, 1/2] Add new LDGM/STGM instruction This patch adds the new LDGM/STGM instructions of the Armv8.5-A Memory Tagging Extension. This is part of the changes that have been introduced recently in the 00bet10 release The instructions are as follows: LDGM Xt, [<Xn|SP>] STGM Xt, [<Xn|SP>] *** gas/ChangeLog *** 2019-04-11 Sudakshina Das <sudi.das@arm.com> * testsuite/gas/aarch64/armv8_5-a-memtag.d: New tests for ldgm and stgm. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. *** opcodes/ChangeLog *** 2019-04-11 Sudakshina Das <sudi.das@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
2019-04-11 17:13:23 +08:00
2019-04-11 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/armv8_5-a-memtag.d: New tests for ldgm and stgm.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
Disable R_X86_64_PLT32 generation as branch marker on Solaris/x86 The fix H.J. implemented for PR gas/22791 in the thread starting at [PATCH] x86-64: Treat PC32 relocation with branch as PLT32 https://sourceware.org/ml/binutils/2018-02/msg00065.html is causing problems on Solaris/x86. The native linker is strongly preferred there, and there's no intention of implementing the linker optimization he plans there. Besides, the kernel runtime linker, otherwise has no need to deal with that reloc at all, and instead of adding (possibly even more) workarounds with no benefit, it seems appropriate to disable the R_X86_64_PLT32 generation as branch marker on Solaris/x86 in the first place. The patch itself is trivial, the only complication is adapting the testsuite. Since I've found no way to have conditional sections in the .d files, I've instead used the solution already found elsewhere of having separate .d files for the affected tests in an i386/solaris subdirectory and skipping the original ones. Tested on amd64-pc-solaris2.11 and x86_64-pc-linux-gnu without regressions. * config/tc-i386.c (need_plt32_p) [TE_SOLARIS]: Return FALSE. * testsuite/gas/i386/solaris/solaris.exp: New driver. * testsuite/gas/i386/solaris/reloc64.d, testsuite/gas/i386/solaris/x86-64-jump.d, testsuite/gas/i386/solaris/x86-64-mpx-branch-1.d, testsuite/gas/i386/solaris/x86-64-mpx-branch-2.d, testsuite/gas/i386/solaris/x86-64-nop-3.d, testsuite/gas/i386/solaris/x86-64-nop-4.d, testsuite/gas/i386/solaris/x86-64-nop-5.d, testsuite/gas/i386/solaris/x86-64-relax-2.d, testsuite/gas/i386/solaris/x86-64-relax-3.d: New tests. * testsuite/gas/i386/reloc64.d, testsuite/gas/i386/x86-64-jump.d, testsuite/gas/i386/x86-64-mpx-branch-1.d, testsuite/gas/i386/x86-64-mpx-branch-2.d, testsuite/gas/i386/x86-64-nop-3.d, testsuite/gas/i386/x86-64-nop-4.d, testsuite/gas/i386/x86-64-nop-5.d, testsuite/gas/i386/x86-64-relax-2.d, testsuite/gas/i386/x86-64-relax-3.d: Skip on *-*-solaris*.
2019-04-10 15:48:43 +08:00
2019-04-10 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* config/tc-i386.c (need_plt32_p) [TE_SOLARIS]: Return FALSE.
* testsuite/gas/i386/solaris/solaris.exp: New driver.
* testsuite/gas/i386/solaris/reloc64.d,
testsuite/gas/i386/solaris/x86-64-jump.d,
testsuite/gas/i386/solaris/x86-64-mpx-branch-1.d,
testsuite/gas/i386/solaris/x86-64-mpx-branch-2.d,
testsuite/gas/i386/solaris/x86-64-nop-3.d,
testsuite/gas/i386/solaris/x86-64-nop-4.d,
testsuite/gas/i386/solaris/x86-64-nop-5.d,
testsuite/gas/i386/solaris/x86-64-relax-2.d,
testsuite/gas/i386/solaris/x86-64-relax-3.d: New tests.
* testsuite/gas/i386/reloc64.d,
testsuite/gas/i386/x86-64-jump.d,
testsuite/gas/i386/x86-64-mpx-branch-1.d,
testsuite/gas/i386/x86-64-mpx-branch-2.d,
testsuite/gas/i386/x86-64-nop-3.d,
testsuite/gas/i386/x86-64-nop-4.d,
testsuite/gas/i386/x86-64-nop-5.d,
testsuite/gas/i386/x86-64-relax-2.d,
testsuite/gas/i386/x86-64-relax-3.d: Skip on *-*-solaris*.
te-cloudabi.h This patch is aimed a fixing large numbers of x86_64-cloudabi failures caused by gas selecting the wrong target name. * config/te-cloudabi.h: New file. * config/tc-aarch64.c (aarch64_after_parse_args): Use TE_CLOUDABI rather than TARGET_OS to select cloudabi. * config/tc-i386.h (ELF_TARGET_FORMAT64): Define for TE_CLOUDABI. * configure.tgt (*-*-cloudabi*): Set em=cloudabi.
2019-04-08 15:27:51 +08:00
2019-04-10 Alan Modra <amodra@gmail.com>
* config/te-cloudabi.h: New file.
* config/tc-aarch64.c (aarch64_after_parse_args): Use TE_CLOUDABI
rather than TARGET_OS to select cloudabi.
* config/tc-i386.h (ELF_TARGET_FORMAT64): Define for TE_CLOUDABI.
* configure.tgt (*-*-cloudabi*): Set em=cloudabi.
[MIPS] Add RDHWR with the SEL field for MIPS R6. In Release 6 of the MIPS architecture [1], instruction RDHWR supports a 3rd operand to serve as the 3-bit select field for the hardware register. [1] "MIPS Architecture for Programmers Volume II-A: The MIPS32 Instruction Set Manual", Imagination Technologies Ltd., Document Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical List of Instructions", pp. 332-334 opcodes/ * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel. gas/ * testsuite/gas/mips/mips.exp: Run hwr-names test. * testsuite/gas/mips/hwr-names.s: Add test cases for RDHWR with the SEL field. * testsuite/gas/mips/mipsr6@hwr-names.d: New file.
2019-04-09 17:30:26 +08:00
2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
* testsuite/gas/mips/mips.exp: Run hwr-names test.
* testsuite/gas/mips/hwr-names.s: Add test cases for RDHWR with
the SEL field.
* testsuite/gas/mips/mipsr6@hwr-names.d: New file.
x86: Define GNU_PROPERTY_X86_ISA_1_AVX512_BF16 Update assembler and readelf to support #define GNU_PROPERTY_X86_ISA_1_AVX512_BF16 (1U << 24) for AVX512_BF16. binutils/ * readelf.c (decode_x86_isa): Handle GNU_PROPERTY_X86_ISA_1_AVX512_BF16. * testsuite/binutils-all/i386/pr21231b.d: Updated. * testsuite/binutils-all/x86-64/pr21231b.d: Likewise. gas/ * config/tc-i386.c (output_insn): Support GNU_PROPERTY_X86_ISA_1_AVX512_BF16. * testsuite/gas/i386/property-2.s: Add AVX512_BF16 test. * testsuite/gas/i386/property-2.d: Updated. * testsuite/gas/i386/x86-64-property-2.d: Likewise. include/ * elf/common.h (GNU_PROPERTY_X86_ISA_1_AVX512_BF16): New.
2019-04-09 08:04:01 +08:00
2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (output_insn): Support
GNU_PROPERTY_X86_ISA_1_AVX512_BF16.
* testsuite/gas/i386/property-2.s: Add AVX512_BF16 test.
* testsuite/gas/i386/property-2.d: Updated.
* testsuite/gas/i386/x86-64-property-2.d: Likewise.
x86: Remove i386-*-kaos* and i386-*-chaos targets Remove i386-*-kaos* and i386-*-chaos targets since they are no longer supported by config.sub: $ .../config.sub i386-kaos Invalid configuration `i386-kaos': system `kaos' not recognized $ .../config.sub i386-chaos Invalid configuration `i386-chaos': system `chaos' not recognized $ bfd/ * config.bfd: Remove i[3-7]86-*-kaos* and i[3-7]86-*-chaos targets. gas/ * configure.tgt: Remove i386-*-kaos* and i386-*-chaos targets. * testsuite/gas/i386/i386.exp: Remove *-*-caos* and "*-*-kaos* check. ld/ * Makefile.am (ALL_EMULATION_SOURCES): Remove eelf_i386_chaos.c. (eelf_i386_chaos.c): Removed. * Makefile.in: Regenerated. * configure.tgt: Remove i[3-7]86-*-kaos*. * emulparams/elf_i386_chaos.sh: Removed.
2019-04-09 02:58:51 +08:00
2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
* configure.tgt: Remove i386-*-kaos* and i386-*-chaos targets.
* testsuite/gas/i386/i386.exp: Remove *-*-caos* and "*-*-kaos*
check.
x86: Add assembler -mx86-used-note=yes test Check assembler -mx86-used-note=yes option and readelf -n output. * testsuite/gas/i386/i386.exp: Run -mx86-used-note=yes tests. * testsuite/gas/i386/property-2.d: New file. * testsuite/gas/i386/property-2.s: Likewise. * testsuite/gas/i386/x86-64-property-2.d: Likewise.
2019-04-06 03:41:58 +08:00
2019-04-05 H.J. Lu <hongjiu.lu@intel.com>
* testsuite/gas/i386/i386.exp: Run -mx86-used-note=yes tests.
* testsuite/gas/i386/property-2.d: New file.
* testsuite/gas/i386/property-2.s: Likewise.
* testsuite/gas/i386/x86-64-property-2.d: Likewise.
x86: Support Intel AVX512 BF16 Add assembler and disassembler support Intel AVX512 BF16: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference gas/ 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com> * config/tc-i386.c (cpu_arch): Add .avx512_bf16. (cpu_noarch): Add noavx512_bf16. * doc/c-i386.texi: Document avx512_bf16. * testsuite/gas/i386/avx512_bf16.d: New file. * testsuite/gas/i386/avx512_bf16.s: Likewise. * testsuite/gas/i386/avx512_bf16_vl-inval.l: Likewise. * testsuite/gas/i386/avx512_bf16_vl-inval.s: Likewise. * testsuite/gas/i386/avx512_bf16_vl.d: Likewise. * testsuite/gas/i386/avx512_bf16_vl.s: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16.d: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16.s: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.l: Likesie. * testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.s: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16_vl.d: Likewise. * testsuite/gas/i386/x86-64-avx512_bf16_vl.s: Likewise. * testsuite/gas/i386/i386.exp: Add BF16 related tests. opcodes/ 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com> * i386-dis-evex.h (evex_table): Updated to support BF16 instructions. * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1 and EVEX_W_0F3872_P_3. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS. (cpu_flags): Add bitfield for CpuAVX512_BF16. * i386-opc.h (enum): Add CpuAVX512_BF16. (i386_cpu_flags): Add bitfield for cpuavx512_bf16. * i386-opc.tbl: Add AVX512 BF16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2019-04-06 02:03:01 +08:00
2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
* config/tc-i386.c (cpu_arch): Add .avx512_bf16.
(cpu_noarch): Add noavx512_bf16.
* doc/c-i386.texi: Document avx512_bf16.
* testsuite/gas/i386/avx512_bf16.d: New file.
* testsuite/gas/i386/avx512_bf16.s: Likewise.
* testsuite/gas/i386/avx512_bf16_vl-inval.l: Likewise.
* testsuite/gas/i386/avx512_bf16_vl-inval.s: Likewise.
* testsuite/gas/i386/avx512_bf16_vl.d: Likewise.
* testsuite/gas/i386/avx512_bf16_vl.s: Likewise.
* testsuite/gas/i386/x86-64-avx512_bf16.d: Likewise.
* testsuite/gas/i386/x86-64-avx512_bf16.s: Likewise.
* testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.l: Likesie.
* testsuite/gas/i386/x86-64-avx512_bf16_vl-inval.s: Likewise.
* testsuite/gas/i386/x86-64-avx512_bf16_vl.d: Likewise.
* testsuite/gas/i386/x86-64-avx512_bf16_vl.s: Likewise.
* testsuite/gas/i386/i386.exp: Add BF16 related tests.
PowerPC conditional branch test Adds a new test checking conditional branch BO values. * testsuite/gas/ppc/bc.s, * testsuite/gas/ppc/bcat.d, * testsuite/gas/ppc/bcaterr.d, * testsuite/gas/ppc/bcaterr.l, * testsuite/gas/ppc/bcy.d, * testsuite/gas/ppc/bcyerr.d, * testsuite/gas/ppc/bcyerr.l: New tests. * testsuite/gas/ppc/ppc.exp: Run them.
2019-04-04 09:32:31 +08:00
2019-04-05 Alan Modra <amodra@gmail.com>
* testsuite/gas/ppc/bc.s,
* testsuite/gas/ppc/bcat.d,
* testsuite/gas/ppc/bcaterr.d,
* testsuite/gas/ppc/bcaterr.l,
* testsuite/gas/ppc/bcy.d,
* testsuite/gas/ppc/bcyerr.d,
* testsuite/gas/ppc/bcyerr.l: New tests.
* testsuite/gas/ppc/ppc.exp: Run them.
PowerPC disassembler: Don't emit trailing spaces When an instruction has operands, the PowerPC disassembler prints spaces after the opcode so as to line up operands. If the operands are all optional and all default value, then no operands are printed, leaving trailing spaces. This patch fixes that. opcodes/ * ppc-dis.c (print_insn_powerpc): Delay printing spaces after opcode until first operand is output. gas/ * testsuite/gas/ppc/476.d: Remove trailing spaces. * testsuite/gas/ppc/a2.d: Likewise. * testsuite/gas/ppc/booke.d: Likewise. * testsuite/gas/ppc/booke_xcoff.d: Likewise. * testsuite/gas/ppc/e500.d: Likewise. * testsuite/gas/ppc/e500mc.d: Likewise. * testsuite/gas/ppc/e6500.d: Likewise. * testsuite/gas/ppc/htm.d: Likewise. * testsuite/gas/ppc/power6.d: Likewise. * testsuite/gas/ppc/power8.d: Likewise. * testsuite/gas/ppc/power9.d: Likewise. * testsuite/gas/ppc/vle.d: Likewise. ld/ * testsuite/ld-powerpc/tlsexe32.d: Remove trailing spaces. * testsuite/ld-powerpc/tlsopt5.d: Likewise. * testsuite/ld-powerpc/tlsopt5_32.d: Likewise.
2019-04-05 06:50:16 +08:00
2019-04-05 Alan Modra <amodra@gmail.com>
* testsuite/gas/ppc/476.d: Remove trailing spaces.
* testsuite/gas/ppc/a2.d: Likewise.
* testsuite/gas/ppc/booke.d: Likewise.
* testsuite/gas/ppc/booke_xcoff.d: Likewise.
* testsuite/gas/ppc/e500.d: Likewise.
* testsuite/gas/ppc/e500mc.d: Likewise.
* testsuite/gas/ppc/e6500.d: Likewise.
* testsuite/gas/ppc/htm.d: Likewise.
* testsuite/gas/ppc/power6.d: Likewise.
* testsuite/gas/ppc/power8.d: Likewise.
* testsuite/gas/ppc/power9.d: Likewise.
* testsuite/gas/ppc/vle.d: Likewise.
Add extended mnemonics for bctar. Fix setting of 'at' branch hints. opcodes/ PR gas/24349 * ppc-opc.c (valid_bo_pre_v2): Add comments. (valid_bo_post_v2): Add support for 'at' branch hints. (insert_bo): Only error on branch on ctr. (get_bo_hint_mask): New function. (insert_boe): Add new 'branch_taken' formal argument. Add support for inserting 'at' branch hints. (extract_boe): Add new 'branch_taken' formal argument. Add support for extracting 'at' branch hints. (insert_bom, extract_bom, insert_bop, extract_bop): New functions. (BOE): Delete operand. (BOM, BOP): New operands. (RM): Update value. (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete. (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-, bcctrl-, bctar-, bctarl->: Replace BOE with BOM. (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+, bcctrl+, bctar+, bctarl+>: Replace BOE with BOP. <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-, bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar, bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar, bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-, bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-, bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+, bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+, bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl, beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-, bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-, buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+, bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar, bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar, bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+, bttarl+>: New extended mnemonics. gas/ PR gas/24349 * testsuite/gas/ppc/power8.s: (bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-, bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar, bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar, bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-, bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-, bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+, bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+, bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl, beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-, bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-, buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+, bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar, bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar, bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+, bttarl+): Add tests of extended mnemonics. * testsuite/gas/ppc/power8.d: Likewise. Update previous bctar tests to expect new extended mnemonics. * testsuite/gas/ppc/a2.s: <bc, bc-, bc+, bcl, bcl-, bcl+>: Update test to not use illegal BO value. Use a more convenient BI value. * testsuite/gas/ppc/a2.d: Update tests for new expect output.
2019-04-04 22:00:29 +08:00
2019-04-04 Peter Bergner <bergner@linux.ibm.com>
PR gas/24349
* testsuite/gas/ppc/power8.s: (bdnztar, bdnztarl, bdztar, bdztarl,
btar, btarl, bdnztar-, bdnztarl-, bdnztar+, bdnztarl+, bdztar-,
bdztarl-, bdztar+, bdztarl+, bgetar, bnltar, bgetarl, bnltarl,
bletar, bngtar, bletarl, bngtarl, bnetar, bnetarl, bnstar, bnutar,
bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-, bnltarl-, bletar-,
bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-, bnstar-, bnutar-,
bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+, bnltarl+, bletar+,
bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+, bnstar+, bnutar+,
bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl, beqtar,
beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
bttarl+): Add tests of extended mnemonics.
* testsuite/gas/ppc/power8.d: Likewise. Update previous bctar tests
to expect new extended mnemonics.
* testsuite/gas/ppc/a2.s: <bc, bc-, bc+, bcl, bcl-, bcl+>: Update test
to not use illegal BO value. Use a more convenient BI value.
* testsuite/gas/ppc/a2.d: Update tests for new expect output.
gas: use literals/const16 for xtensa loop relaxation Loop opcode relaxation that uses addi/addmi doesn't work well with other relaxations that may cause code movement. Instead of encoding fixed loop end offset in the relaxed sequence use l32r or a pair of const16 to load loop end address. This way the address of the loop end gets a relocation record and it gets updated appropriately. gas/ 2019-04-03 Max Filippov <jcmvbkbc@gmail.com> * config/tc-xtensa.c (convert_frag_immed): Drop convert_frag_immed_finish_loop invocation. (convert_frag_immed_finish_loop): Drop declaration and definition. * config/xtensa-relax.c (widen_spec_list): Replace loop widening that uses addi/addmi with widening that uses l32r and const16.
2019-04-03 05:32:42 +08:00
2019-04-03 Max Filippov <jcmvbkbc@gmail.com>
* config/tc-xtensa.c (convert_frag_immed): Drop
convert_frag_immed_finish_loop invocation.
(convert_frag_immed_finish_loop): Drop declaration and
definition.
* config/xtensa-relax.c (widen_spec_list): Replace loop
widening that uses addi/addmi with widening that uses l32r
and const16.
[GAS, Arm] CLI with architecture sensitive extensions This patch adds a new framework to add architecture sensitive extensions, like GCC does. This patch also implements all architecture extensions currently available in GCC. This framework works as follows. To enable architecture sensitive extensions for a particular architecture, that architecture must contain an ARM_ARCH_OPT2 entry in the 'arm_archs' table. All fields here are the same as previous, with the addition of a new extra field at the end to <name> it's extension table. This <name>, corresponds to a <name>_ext_table of type 'struct arm_ext_table'. This struct can be filled with three types of entries: ARM_ADD (string <ext>, arm_feature_set <enable_bits>), which means +<ext> will enable <enable_bits> ARM_REMOVE (string <ext>, arm_feature_set <disable_bits>), which means +no<ext> will disable <disable_bits> ARM_EXT (string <ext>, arm_feature_set <enable_bits>, arm_feature_set <disable_bits>), which means +<ext> will enable <enable_bits> and +no<ext> will disable <disable_bits> (this is to be used instead of adding an ARM_ADD and ARM_REMOVE for the same <ext>) This patch does not disable the use of the old extensions, even if some of them are duplicated in the new tables. This is a "in-between-step" as we may want to deprecate the old table of extensions in later patches. For now, GAS will first look for the +<ext> or +no<ext> in the new table and if no entry is found it will continue searching in the old table, following old behaviour. If only an ARM_ADD or an ARM_REMOVE is defined for <ext> and +no<ext> or +<ext> resp. is used then it also continues to search the old table for it. A couple of caveats: - This patch does not enable the use of these architecture extensions with the '.arch_extension' directive. This is future work that I will tend to later. - This patch does not enable the use of these architecture extensions with the -mcpu option. This is future work that I will tend to later. - This patch does not change the current behaviour when combining an architecture extension and using -mfpu on the command-line. The current behaviour of GAS is to stage the union of feature bits enabled by both -march and -mfpu. GCC behaves differently here, so this is something we may want to revisit on a later date.
2019-04-01 17:43:32 +08:00
2019-04-01 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (arm_ext_table): New struct type.
(arm_arch_option_table): Add new 'arm_ext_table' field.
(ARM_EXT,ARM_ADD,ARM_REMOVE, ALL_FP): New macros.
(armv5te_ext_table, armv7ve_ext_table, armv7a_ext_table,
armv7r_ext_table, armv7em_ext_table, armv8a_ext_table,
armv81a_ext_table, armv82a_ext_table, armv84a_ext_table,
armv85a_ext_table, armv8m_main_ext_table,
armv8r_ext_table): New architecture extension tables.
(ARM_ARCH_OPT): Add new default field.
(ARM_ARCH_OPT2): New macro.
(arm_archs): Extend some architectures with the new architecture
extension tables mentioned above.
(arm_extensions): Add DEPRECATED comment with instructions to
use new table.
(arm_parse_extension): Change to use new extension tables.
(arm_parse_cpu): Don't change existing behavior.
(arm_parse_arch): Change to use new extension tables.
* doc/c-arm.texi: Document new architecture extensions.
* testsuite/gas/arm/attr-mfpu-neon-fp16.d: Change test to use new
extension option rather than -mfpu and change expected behaviour to
sane outputs.
* testsuite/gas/arm/armv8-2-fp16-scalar-bad-ext.d: New.
* testsuite/gas/arm/armv8-2-fp16-scalar-ext.d: New.
* testsuite/gas/arm/armv8-2-fp16-scalar-thumb-ext.d: New.
* testsuite/gas/arm/armv8-2-fp16-simd-ext.d: New.
* testsuite/gas/arm/armv8-2-fp16-simd-thumb-ext.d: New.
* testsuite/gas/arm/armv8-2-fp16-simd-warning-ext.d: New.
* testsuite/gas/arm/armv8-2-fp16-simd-warning-thumb-ext.d: New.
* testsuite/gas/arm/armv8_2+rdma-ext.d: New.
* testsuite/gas/arm/armv8_2-a-fp16-thumb2-ext.d: New.
* testsuite/gas/arm/armv8_2-a-fp16_ext.d: New.
* testsuite/gas/arm/armv8_3-a-fp-bad-ext.d: New.
* testsuite/gas/arm/armv8_3-a-fp-ext.d: New.
* testsuite/gas/arm/armv8_3-a-fp16-ext.d: New.
* testsuite/gas/arm/armv8_3-a-simd-bad-ext.d: New.
* testsuite/gas/arm/armv8_4-a-fp16-ext.d: New.
* testsuite/gas/arm/armv8m.main+fp.d: New.
* testsuite/gas/arm/armv8m.main+fp.dp.d: New.
* testsuite/gas/arm/attr-ext-fpv5-d16.d: New.
* testsuite/gas/arm/attr-ext-fpv5.d: New.
* testsuite/gas/arm/attr-ext-idiv.d: New.
* testsuite/gas/arm/attr-ext-mp.d: New.
* testsuite/gas/arm/attr-ext-neon-fp16.d: New.
* testsuite/gas/arm/attr-ext-neon-vfpv3.d: New.
* testsuite/gas/arm/attr-ext-neon-vfpv4.d: New.
* testsuite/gas/arm/attr-ext-sec.d: New.
* testsuite/gas/arm/attr-ext-vfpv3-d16-fp16.d: New.
* testsuite/gas/arm/attr-ext-vfpv3-d16.d: New.
* testsuite/gas/arm/attr-ext-vfpv3-fp16.d: New.
* testsuite/gas/arm/attr-ext-vfpv3.d: New.
* testsuite/gas/arm/attr-ext-vfpv3xd-fp.d: New.
* testsuite/gas/arm/attr-ext-vfpv3xd.d: New.
* testsuite/gas/arm/attr-ext-vfpv4-d16.d: New.
* testsuite/gas/arm/attr-ext-vfpv4-sp-d16.d: New.
* testsuite/gas/arm/attr-ext-vfpv4.d: New.
* testsuite/gas/arm/dotprod-mandatory-ext.d: New.
* testsuite/gas/arm/fpv5-d16.s: New.
* testsuite/gas/arm/fpv5-sp-d16.s: New.
PR24390, Don't decode mtfsb field as a cr field "mtfsb0 4*cr7+lt" doesn't make all that much sense, but unfortunately glibc uses just that instead of "mtfsb0 28" to clear the fpscr xe bit. So for backwards compatibility accept cr field expressions when assembling mtfsb operands, but disassemble to a plain number. PR 24390 include/ * opcode/ppc.h (PPC_OPERAND_CR_REG): Comment. opcodes/ * ppc-opc.c (BTF): Define. (powerpc_opcodes): Use for mtfsb*. * ppc-dis.c (print_insn_powerpc): Print fields with both PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number. gas/ * testsuite/gas/ppc/476.d: Update mtfsb*. * testsuite/gas/ppc/a2.d: Likewise.
2019-03-28 08:06:55 +08:00
2019-03-28 Alan Modra <amodra@gmail.com>
PR 24390
* testsuite/gas/ppc/476.d: Update mtfsb*.
* testsuite/gas/ppc/a2.d: Likewise.
Remove strip_underscore from struct emulation This field is unused. I would have liked to also remove leading_underscore and fake_label_name but in an i386-elf/coff/aout multi-obj setup those fields are used to select a different fake_label_name for aout. * emul.h (struct emulation): Delete strip_underscore. * emul-target.h (emul_strip_underscore): Don't define. (emul_struct_name): Update initialization.
2019-03-20 16:05:16 +08:00
2019-03-21 Alan Modra <amodra@gmail.com>
* emul.h (struct emulation): Delete strip_underscore.
* emul-target.h (emul_strip_underscore): Don't define.
(emul_struct_name): Update initialization.
Teach a few targets to resolve BFD_RELOC_8 and tidy "forward" test. I've removed some checks in d30v md_apply_fix that have no business being there. Any symbol problems will be caught later in tc_gen_reloc, and overflow checking is done in gas/write.c. * config/tc-d10v.c (md_apply_fix): Apply BFD_RELOC_8. * config/tc-pdp11.c (md_apply_fix): Likewise. * config/tc-d30v.c (md_apply_fix): Don't emit errors for BFD_RELOC_8, BFD_RELOC_16, and BFD_RELOC_64. * testsuite/gas/all/gas.exp: Move target exclusions for forward test, but not cr16, to.. * testsuite/gas/all/forward.d: ..here, with explanation. Remove d10v, d30v, and pdp11 xfails.
2019-03-20 06:50:55 +08:00
2019-03-21 Alan Modra <amodra@gmail.com>
* config/tc-d10v.c (md_apply_fix): Apply BFD_RELOC_8.
* config/tc-pdp11.c (md_apply_fix): Likewise.
* config/tc-d30v.c (md_apply_fix): Don't emit errors for BFD_RELOC_8,
BFD_RELOC_16, and BFD_RELOC_64.
* testsuite/gas/all/gas.exp: Move target exclusions for forward
test, but not cr16, to..
* testsuite/gas/all/forward.d: ..here, with explanation. Remove
d10v, d30v, and pdp11 xfails.
x86: Correct EVEX vector load/store optimization Update EVEX vector load/store optimization: 1. There is no need to check AVX since AVX2 is required for AVX512F. 2. We need to check both operands for ZMM register since AT&T syntax may not set zmmword on the first operand. 3. Update Opcode_SIMD_IntD check and set. 4. Since the VEX prefix has 2 or 3 bytes, the EVEX prefix has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4 bytes, we choose EVEX Disp8 over VEX Disp32. * config/tc-i386.c (optimize_encoding): Don't check AVX for EVEX vector load/store optimization. Check both operands for ZMM register. Update EVEX vector load/store opcode check. Choose EVEX Disp8 over VEX Disp32. * testsuite/gas/i386/optimize-1.d: Updated. * testsuite/gas/i386/optimize-1a.d: Likewise. * testsuite/gas/i386/optimize-2.d: Likewise. * testsuite/gas/i386/optimize-4.d: Likewise. * testsuite/gas/i386/optimize-5.d: Likewise. * testsuite/gas/i386/x86-64-optimize-2.d: Likewise. * testsuite/gas/i386/x86-64-optimize-2a.d: Likewise. * testsuite/gas/i386/x86-64-optimize-2b.d: Likewise. * testsuite/gas/i386/x86-64-optimize-3.d: Likewise. * testsuite/gas/i386/x86-64-optimize-5.d: Likewise. * testsuite/gas/i386/x86-64-optimize-6.d: Likewise. * testsuite/gas/i386/optimize-1.s: Add ZMM register load test. * testsuite/gas/i386/x86-64-optimize-2.s: Likewise.
2019-03-19 21:12:47 +08:00
2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (optimize_encoding): Don't check AVX for
EVEX vector load/store optimization. Check both operands for
ZMM register. Update EVEX vector load/store opcode check.
Choose EVEX Disp8 over VEX Disp32.
* testsuite/gas/i386/optimize-1.d: Updated.
* testsuite/gas/i386/optimize-1a.d: Likewise.
* testsuite/gas/i386/optimize-2.d: Likewise.
* testsuite/gas/i386/optimize-4.d: Likewise.
* testsuite/gas/i386/optimize-5.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-2a.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-2b.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-3.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-5.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-6.d: Likewise.
* testsuite/gas/i386/optimize-1.s: Add ZMM register load
test.
* testsuite/gas/i386/x86-64-optimize-2.s: Likewise.
x86: Correct EVEX to 128-bit EVEX optimization Since not all AVX512F processors support AVX512VL, we can optimize 512-bit EVEX to 128-bit EVEX encoding for upper 16 vector registers only when AVX512VL is enabled explicitly at command-line or via ".arch .avx512vl" directive. PR gas/24352 * config/tc-i386.c (optimize_encoding): Check only cpu_arch_flags.bitfield.cpuavx512vl. * testsuite/gas/i386/i386.exp: Run x86-64-optimize-2b. * testsuite/gas/i386/x86-64-optimize-2.d: Revert the last change. * testsuite/gas/i386/x86-64-optimize-2b.d: New file. * testsuite/gas/i386/x86-64-optimize-2b.s: Likewise.
2019-03-19 21:10:21 +08:00
2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
PR gas/24352
* config/tc-i386.c (optimize_encoding): Check only
cpu_arch_flags.bitfield.cpuavx512vl.
* testsuite/gas/i386/i386.exp: Run x86-64-optimize-2b.
* testsuite/gas/i386/x86-64-optimize-2.d: Revert the last
change.
* testsuite/gas/i386/x86-64-optimize-2b.d: New file.
* testsuite/gas/i386/x86-64-optimize-2b.s: Likewise.
ix86: Disable AVX512F when disabling AVX2 Since AVX2 is required for AVX512F, we should disable AVX512F when AVX2 is disabled. gas/ PR gas/24359 * testsuite/gas/i386/i386.exp: Change optimize-6a, optimize-7, x86-64-optimize-7a and x86-64-optimize-8 tests to run_list_test. Remove optimize-6c and x86-64-optimize-7c tests. * testsuite/gas/i386/noavx-3.l: Updated. * testsuite/gas/i386/noavx-4.d: Likewise. * testsuite/gas/i386/noavx-5.d: Likewise. * testsuite/gas/i386/noavx-3.s: Add AVX512F tests. * testsuite/gas/i386/noavx-4.s: Remove AVX512F tests. * testsuite/gas/i386/nosse-5.s: Likewise. * testsuite/gas/i386/optimize-6a.d: Removed. * testsuite/gas/i386/optimize-6c.d: Likewise. * testsuite/gas/i386/optimize-7.d: Likewise. * testsuite/gas/i386/x86-64-optimize-7a.d: Likewise. * testsuite/gas/i386/x86-64-optimize-7c.d: Likewise. * testsuite/gas/i386/x86-64-optimize-8.d: Likewise. * testsuite/gas/i386/optimize-6a.l: New file. * testsuite/gas/i386/optimize-6a.s: Likewise. * testsuite/gas/i386/optimize-7.l: Likewise. * testsuite/gas/i386/x86-64-optimize-7a.l: Likewise. * testsuite/gas/i386/x86-64-optimize-7a.s: Likewise. * testsuite/gas/i386/x86-64-optimize-8.l: Likewise. opcodes/ PR gas/24359 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to CPU_ANY_AVX2_FLAGS. * i386-init.h: Regenerated.
2019-03-19 21:08:15 +08:00
2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
PR gas/24359
* testsuite/gas/i386/i386.exp: Change optimize-6a, optimize-7,
x86-64-optimize-7a and x86-64-optimize-8 tests to run_list_test.
Remove optimize-6c and x86-64-optimize-7c tests.
* testsuite/gas/i386/noavx-3.l: Updated.
* testsuite/gas/i386/noavx-4.d: Likewise.
* testsuite/gas/i386/noavx-5.d: Likewise.
* testsuite/gas/i386/noavx-3.s: Add AVX512F tests.
* testsuite/gas/i386/noavx-4.s: Remove AVX512F tests.
* testsuite/gas/i386/nosse-5.s: Likewise.
* testsuite/gas/i386/optimize-6a.d: Removed.
* testsuite/gas/i386/optimize-6c.d: Likewise.
* testsuite/gas/i386/optimize-7.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-7a.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-7c.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-8.d: Likewise.
* testsuite/gas/i386/optimize-6a.l: New file.
* testsuite/gas/i386/optimize-6a.s: Likewise.
* testsuite/gas/i386/optimize-7.l: Likewise.
* testsuite/gas/i386/x86-64-optimize-7a.l: Likewise.
* testsuite/gas/i386/x86-64-optimize-7a.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-8.l: Likewise.
Fix MRI mode testsuite failures These fails were introduced by git commit 2469b3c584 with the inroduction of "input_from_string": m68k-linux FAIL: MRI structured for m68k-linux FAIL: MRI structured if m68k-linux FAIL: MRI structured repeat m68k-linux FAIL: MRI structured while Since the m68k parser called expression() without setting input_from_string, get_symbol_name rejected FAKE_LABEL_CHAR in names. * config/m68k-parse.y (yylex): Use temp_ilp and restore_ilp.
2019-03-18 19:46:24 +08:00
2019-03-18 Alan Modra <amodra@gmail.com>
* config/m68k-parse.y (yylex): Use temp_ilp and restore_ilp.
Use temp_ilp and restore_ilp in more places * as.c (macro_expr): Use temp_ilp and restore_ilp. * macro.c (buffer_and_nest): Likewise. * read.c (temp_ilp): Remove FIXME.
2019-03-18 20:04:36 +08:00
* as.c (macro_expr): Likewise.
* macro.c (buffer_and_nest): Likewise.
* read.c (temp_ilp): Remove FIXME.
Fix MRI mode testsuite failures These fails were introduced by git commit 2469b3c584 with the inroduction of "input_from_string": m68k-linux FAIL: MRI structured for m68k-linux FAIL: MRI structured if m68k-linux FAIL: MRI structured repeat m68k-linux FAIL: MRI structured while Since the m68k parser called expression() without setting input_from_string, get_symbol_name rejected FAKE_LABEL_CHAR in names. * config/m68k-parse.y (yylex): Use temp_ilp and restore_ilp.
2019-03-18 19:46:24 +08:00
x86: Pass -O0 to assembler for some tests * testsuite/gas/i386/att-regs.d: Pass -O0 to assembler. * testsuite/gas/i386/avx512bw-intel.d: Likewise. * testsuite/gas/i386/avx512bw.d: Likewise. * testsuite/gas/i386/avx512f-intel.d: Likewise. * testsuite/gas/i386/avx512f.d: Likewise. * testsuite/gas/i386/disp32.d: Likewise. * testsuite/gas/i386/intel-regs.d: Likewise. * testsuite/gas/i386/pseudos.d: Likewise. * testsuite/gas/i386/x86-64-disp32.d: Likewise. * testsuite/gas/i386/x86-64-pseudos.d: Likewise.
2019-03-18 09:19:45 +08:00
2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
* testsuite/gas/i386/att-regs.d: Pass -O0 to assembler.
* testsuite/gas/i386/avx512bw-intel.d: Likewise.
* testsuite/gas/i386/avx512bw.d: Likewise.
* testsuite/gas/i386/avx512f-intel.d: Likewise.
* testsuite/gas/i386/avx512f.d: Likewise.
* testsuite/gas/i386/disp32.d: Likewise.
* testsuite/gas/i386/intel-regs.d: Likewise.
* testsuite/gas/i386/pseudos.d: Likewise.
* testsuite/gas/i386/x86-64-disp32.d: Likewise.
* testsuite/gas/i386/x86-64-pseudos.d: Likewise.
x86: Optimize EVEX vector load/store instructions When there is no write mask, we can encode lower 16 128-bit/256-bit EVEX vector register load and store instructions as VEX vector register load and store instructions with -O1. gas/ PR gas/24348 * config/tc-i386.c (optimize_encoding): Encode 128-bit and 256-bit EVEX vector register load/store instructions as VEX vector register load/store instructions for -O1. * doc/c-i386.texi: Update -O1 documentation. * testsuite/gas/i386/i386.exp: Run PR gas/24348 tests. * testsuite/gas/i386/optimize-1.s: Add tests for EVEX vector load/store instructions. * testsuite/gas/i386/optimize-2.s: Likewise. * testsuite/gas/i386/optimize-3.s: Likewise. * testsuite/gas/i386/optimize-5.s: Likewise. * testsuite/gas/i386/x86-64-optimize-2.s: Likewise. * testsuite/gas/i386/x86-64-optimize-3.s: Likewise. * testsuite/gas/i386/x86-64-optimize-4.s: Likewise. * testsuite/gas/i386/x86-64-optimize-5.s: Likewise. * testsuite/gas/i386/x86-64-optimize-6.s: Likewise. * testsuite/gas/i386/optimize-1.d: Updated. * testsuite/gas/i386/optimize-2.d: Likewise. * testsuite/gas/i386/optimize-3.d: Likewise. * testsuite/gas/i386/optimize-4.d: Likewise. * testsuite/gas/i386/optimize-5.d: Likewise. * testsuite/gas/i386/x86-64-optimize-2.d: Likewise. * testsuite/gas/i386/x86-64-optimize-3.d: Likewise. * testsuite/gas/i386/x86-64-optimize-4.d: Likewise. * testsuite/gas/i386/x86-64-optimize-5.d: Likewise. * testsuite/gas/i386/x86-64-optimize-6.d: Likewise. * testsuite/gas/i386/optimize-7.d: New file. * testsuite/gas/i386/optimize-7.s: Likewise. * testsuite/gas/i386/x86-64-optimize-8.d: Likewise. * testsuite/gas/i386/x86-64-optimize-8.s: Likewise. opcodes/ PR gas/24348 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32 and vmovdqu64. * i386-tbl.h: Regenerated.
2019-03-18 08:56:10 +08:00
2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
PR gas/24348
* config/tc-i386.c (optimize_encoding): Encode 128-bit and
256-bit EVEX vector register load/store instructions as VEX
vector register load/store instructions for -O1.
* doc/c-i386.texi: Update -O1 documentation.
* testsuite/gas/i386/i386.exp: Run PR gas/24348 tests.
* testsuite/gas/i386/optimize-1.s: Add tests for EVEX vector
load/store instructions.
* testsuite/gas/i386/optimize-2.s: Likewise.
* testsuite/gas/i386/optimize-3.s: Likewise.
* testsuite/gas/i386/optimize-5.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-2.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-3.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-4.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-5.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-6.s: Likewise.
* testsuite/gas/i386/optimize-1.d: Updated.
* testsuite/gas/i386/optimize-2.d: Likewise.
* testsuite/gas/i386/optimize-3.d: Likewise.
* testsuite/gas/i386/optimize-4.d: Likewise.
* testsuite/gas/i386/optimize-5.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-3.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-4.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-5.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-6.d: Likewise.
* testsuite/gas/i386/optimize-7.d: New file.
* testsuite/gas/i386/optimize-7.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-8.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-8.s: Likewise.
x86: Encode 256-bit/512-bit VEX/EVEX insns with 128-bit VEX Since all AVX512 processors support AVX, we can encode 256-bit/512-bit VEX/EVEX vector register clearing instructions with 128-bit VEX vector register clearing instructions at -O1. * config/tc-i386.c (optimize_encoding): Encode 256-bit/512-bit VEX/EVEX vector register clearing instructions with 128-bit VEX vector register clearing instructions at -O1. * doc/c-i386.texi: Update -O1 and -O2 documentation. * testsuite/gas/i386/i386.exp: Run optimize-1a and x86-64-optimize-2a. * testsuite/gas/i386/optimize-1a.d: New file. * testsuite/gas/i386/x86-64-optimize-2a.d: Likewise.
2019-03-18 03:50:45 +08:00
2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (optimize_encoding): Encode 256-bit/512-bit
VEX/EVEX vector register clearing instructions with 128-bit VEX
vector register clearing instructions at -O1.
* doc/c-i386.texi: Update -O1 and -O2 documentation.
* testsuite/gas/i386/i386.exp: Run optimize-1a and
x86-64-optimize-2a.
* testsuite/gas/i386/optimize-1a.d: New file.
* testsuite/gas/i386/x86-64-optimize-2a.d: Likewise.
x86: Set optimize to INT_MAX for -Os Set optimize to INT_MAX, instead of -1, for -Os so that -Os will include -O2 optimization. PR gas/24353 * config/tc-i386.c (md_parse_option): Set optimize to INT_MAX for -Os. * testsuite/gas/i386/optimize-2.s: Add a test. * testsuite/gas/i386/x86-64-optimize-3.s: Likewise. * testsuite/gas/i386/optimize-2.d: Updated. * testsuite/gas/i386/x86-64-optimize-3.d: Likewise.
2019-03-17 07:39:18 +08:00
2019-03-17 H.J. Lu <hongjiu.lu@intel.com>
PR gas/24353
* config/tc-i386.c: Include <limits.h> if it exists and try
including <sys/param.h> if we have it.
(INT_MAX): Define if not defined.
(md_parse_option): Set optimize to INT_MAX for -Os.
* testsuite/gas/i386/optimize-2.s: Add a test.
* testsuite/gas/i386/x86-64-optimize-3.s: Likewise.
* testsuite/gas/i386/optimize-2.d: Updated.
* testsuite/gas/i386/x86-64-optimize-3.d: Likewise.
x86: Correctly optimize EVEX to 128-bit VEX/EVEX We can optimize 512-bit EVEX to 128-bit EVEX encoding for upper 16 vector registers only when AVX512VL is enabled. We can't optimize EVEX to 128-bit VEX encoding when AVX isn't enabled. PR gas/24352 * config/tc-i386.c (optimize_encoding): Encode 512-bit EVEX with 128-bit VEX encoding only when AVX is enabled and with 128-bit EVEX encoding only when AVX512VL is enabled. * testsuite/gas/i386/i386.exp: Run PR gas/24352 tests. * testsuite/gas/i386/optimize-6.s: New file. * testsuite/gas/i386/optimize-6a.d: Likewise. * testsuite/gas/i386/optimize-6b.d: Likewise. * testsuite/gas/i386/optimize-6c.d: Likewise. * testsuite/gas/i386/x86-64-optimize-7.s: Likewise. * testsuite/gas/i386/x86-64-optimize-7a.d: Likewise. * testsuite/gas/i386/x86-64-optimize-7b.d: Likewise. * testsuite/gas/i386/x86-64-optimize-7c.d: Likewise. * testsuite/gas/i386/x86-64-optimize-2.d: Updated.
2019-03-17 07:25:08 +08:00
2019-03-17 H.J. Lu <hongjiu.lu@intel.com>
PR gas/24352
* config/tc-i386.c (optimize_encoding): Encode 512-bit EVEX
with 128-bit VEX encoding only when AVX is enabled and with
128-bit EVEX encoding only when AVX512VL is enabled.
* testsuite/gas/i386/i386.exp: Run PR gas/24352 tests.
* testsuite/gas/i386/optimize-6.s: New file.
* testsuite/gas/i386/optimize-6a.d: Likewise.
* testsuite/gas/i386/optimize-6b.d: Likewise.
* testsuite/gas/i386/optimize-6c.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-7.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-7a.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-7b.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-7c.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-2.d: Updated.
Fix a potential illegal memory access whilt parsing an x86 insn. PR 24308 * config/tc-i386.c (parse_insn): Check mnemp before using it to determine if a suffix can be trimmed.
2019-03-15 19:58:05 +08:00
2019-03-15 Li Hao <li.hao296@zte.com.cn>
PR 24308
* config/tc-i386.c (parse_insn): Check mnemp before using it to
determine if a suffix can be trimmed.
dwarf2: Align relocation within .debug_line section All relocations specify a byte address. As dwarf debug information is organized in octets, some relocations may not be aligned. While it might be possible to define special relocations that operate at an octet offset from their address, it's easier to ensure the relocations are aligned by padding with "nop" statements. In most dwarf sections this requirement is already fulfilled, only relocations for symbol address within the .debug_line section can be misaligned. * dwarf2dbg.c (out_set_addr): Align relocation within .debug_line.
2019-03-11 02:21:58 +08:00
2019-03-13 Christian Eggers <ceggers@gmx.de>
* dwarf2dbg.c (out_set_addr): Align relocation within .debug_line.
dwarf2: Pad size of .debug_line section. As all dwarf debug information is organized in octets, the size of all dwarf sections must be aligned to OCTETS_PER_BYTE. Most DWARF sections meet this requirement, only the .debug_line section can reach an arbitrary octet size. In order to align the size to a multiple of OCTETS_PER_BYTE, the section is padded with "nop" statements at the end. * dwarf2dbg.c (out_debug_line): Pad size of .debug_line section.
2019-03-11 02:21:57 +08:00
2019-03-13 Christian Eggers <ceggers@gmx.de>
* dwarf2dbg.c (out_debug_line): Pad size of .debug_line section.
dwarf2: Use octets for .debug_string offsets Like other dwarf2 offsets, also the string offsets in the .debug_info section which points into the .debug_str section must be expressed in octets instead of bytes. * dwarf2dbg.c (out_debug_str): Use octets for .debug_string pointers.
2019-03-11 02:21:56 +08:00
2019-03-13 Christian Eggers <ceggers@gmx.de>
* dwarf2dbg.c (out_debug_str): Use octets for .debug_string pointers.
dwarf2: Use octets for .debug_line prologue Like the u32 size field at the beginning of the section, also the prologue size must be expressed in octets. * dwarf2dbg.c (out_debug_line): Use octets for .debug_line prologue.
2019-03-11 02:21:55 +08:00
2019-03-13 Christian Eggers <ceggers@gmx.de>
* dwarf2dbg.c (out_debug_line): Use octets for .debug_line prologue.
dwarf2: Use octets for dwarf2 headers The content of the dwarf2 sections .debug_line, .debug_aranges and .debug_info starts with an u32 containing the the size of the remaining data. According to the dwarf2 specification this value must be expressed in octets instead of bytes. * dwarf2dbg.c (out_debug_line): Use octets for dwarf2 headers. (out_debug_aranges, out_debug_info): Likewise.
2019-03-11 02:21:54 +08:00
2019-03-13 Christian Eggers <ceggers@gmx.de>
* dwarf2dbg.c (out_debug_line): Use octets for dwarf2 headers.
(out_debug_aranges, out_debug_info): Likewise.
Symbols with octets value Up to now, all symbol values are in units of bytes, where a "byte" can consist of one or more octets (e.g. 8 bit or 16 bit). Allow to specfiy that the "unit" of a newly created symbol is octets (exactly 8 bit), instead of bytes. * symbols.h (symbol_temp_new_now_octets): Declare. (symbol_set_value_now_octets, symbol_octets_p): Declare. * symbols.c (struct symbol_flags): New member sy_octets. (symbol_temp_new_now_octets): New function. (resolve_symbol_value): Return octets instead of bytes if sy_octets is set. (symbol_set_value_now_octets): New function. (symbol_octets_p): New function.
2019-03-11 02:21:53 +08:00
2019-03-13 Christian Eggers <ceggers@gmx.de>
* symbols.h (symbol_temp_new_now_octets): Declare.
(symbol_set_value_now_octets, symbol_octets_p): Declare.
* symbols.c (struct symbol_flags): New member sy_octets.
(symbol_temp_new_now_octets): New function.
(resolve_symbol_value): Return octets instead of bytes if
sy_octets is set.
(symbol_set_value_now_octets): New function.
(symbol_octets_p): New function.
dwarf2: Fix calculation of line info offset The units of the value returned by "frag_now_fix()" and "size" do not match. "frag_now_fix()" returns bytes (can be 8, 16 or 32 bit), while "size" is octets (exactly 8 bit). * dwarf2dbg.c (dwarf2_emit_insn): Fix calculation of line info offset.
2019-03-11 02:21:52 +08:00
2019-03-13 Christian Eggers <ceggers@gmx.de>
* dwarf2dbg.c (dwarf2_emit_insn): Fix calculation of line info offset.
Add missing changelogs for previous commits.
2019-03-12 21:23:10 +08:00
2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
* testsuite/gas/s390/zarch-arch13.s: Adjust testcase to optable changes.
* testsuite/gas/s390/zarch-arch13.d: Likewise.
Testsuite: Allow multiple lines of "as" in testsuite. Committed on behalf of Matthew Malcomson. This allows checking the command line parsing more easily than before by allowing many command line invokations from the same .d file. Each line is used as a set of flags, and the tests are ran against the output of the assembler with each set. Each line of assembler is treated as another set of tests (as if the test file were copied to another with a different #as: line). This patch includes some example uses where multiple testcases can be merged into one file using this new functionality. binutils/ChangeLog: * testsuite/lib/binutils-common.exp: Allow multiple "as" lines. gas/ChangeLog: * testsuite/gas/aarch64/dotproduct.d: Use multiple "as" lines. * testsuite/gas/aarch64/dotproduct_armv8_4.d: Remove. * testsuite/gas/aarch64/dotproduct_armv8_4.s: Remove. * testsuite/gas/aarch64/illegal-dotproduct.d: Use multiple "as" lines. * testsuite/gas/aarch64/ldst-rcpc-armv8_2.d: Remove. * testsuite/gas/aarch64/ldst-rcpc.d: Use multiple "as" lines.
2019-02-27 21:15:10 +08:00
2019-02-27 Matthew Malcomson <matthew.malcomson@arm.com>
* testsuite/gas/aarch64/dotproduct.d: Use multiple "as" lines.
* testsuite/gas/aarch64/dotproduct_armv8_4.d: Remove.
* testsuite/gas/aarch64/dotproduct_armv8_4.s: Remove.
* testsuite/gas/aarch64/illegal-dotproduct.d: Use multiple "as"
lines.
* testsuite/gas/aarch64/ldst-rcpc-armv8_2.d: Remove.
* testsuite/gas/aarch64/ldst-rcpc.d: Use multiple "as" lines.
Re: PowerPC __tls_get_addr arg parsing Fixes non-ELF powerpc build failure: tc-ppc.c:3009:1: error: ‘parse_tls_arg’ defined but not used * config/tc-ppc.c (parse_tls_arg): Wrap in #ifdef OBJ_ELF.
2019-02-24 15:31:08 +08:00
2019-02-24 Alan Modra <amodra@gmail.com>
* config/tc-ppc.c (parse_tls_arg): Wrap in #ifdef OBJ_ELF.
PR24144, pdp11-ld overwriting section data with zeros bfd/ PR 24144 * pdp11.c (set_section_contents): Revert 2015-02-24 change. gas/ PR 24144 * config/obj-aout.c (obj_aout_frob_file_before_fix): Write to end of section to ensure file contents cover aligned section size.
2019-02-24 14:14:48 +08:00
2019-02-24 Alan Modra <amodra@gmail.com>
PR 24144
* config/obj-aout.c (obj_aout_frob_file_before_fix): Write to end
of section to ensure file contents cover aligned section size.
[arm][gas] Add support for Neoverse N1 This adds support for the Neoverse N1 CPU [1] to gas. This was previously enabled under the Ares codename, which remains as a valid option for -mcpu for compatibility reasons. make check-gas passes on arm-none-eabi. [1] https://community.arm.com/processors/b/blog/posts/arm-neoverse-n1-platform-accelerating-the-transformation-to-a-scalable-cloud-to-edge-infrastructure 2019-02-21 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/tc-arm.c (arm_cpus): Add neoverse-n1. * doc/c-arm.texi (-mcpu): Document neoverse-n1 value.
2019-02-22 17:59:05 +08:00
2019-02-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/tc-arm.c (arm_cpus): Add neoverse-n1.
* doc/c-arm.texi (-mcpu): Document neoverse-n1 value.
[AArch64][gas] Add support for Neoverse E1 This adds support for the Neoverse E1 CPU [1] to gas. make check-gas passes on aarch64-none-elf. [1] https://community.arm.com/processors/b/blog/posts/arm-neoverse-e1-platform-empowering-the-infrastructure-to-meet-next-generation-throughput-demands 2019-02-21 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/tc-aarch64.c (aarch64_cpus): Add neoverse-e1. * doc/c-aarch64.texi (-mcpu): Document neoverse-e1 value.
2019-02-22 17:57:45 +08:00
2019-02-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/tc-aarch64.c (aarch64_cpus): Add neoverse-e1.
* doc/c-aarch64.texi (-mcpu): Document neoverse-e1 value.
[AArch64][gas] Add support for Neoverse N1 This adds support for the Neoverse N1 [1] CPU to gas. This was previously enabled under the Ares codename, which remains as a valid option for -mcpu for compatibility reasons. make check-gas passes on aarch64-none-elf. [1] https://community.arm.com/processors/b/blog/posts/arm-neoverse-n1-platform-accelerating-the-transformation-to-a-scalable-cloud-to-edge-infrastructure 2019-02-21 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/tc-aarch64.c (aarch64_cpus): Add neoverse-n1. * doc/c-aarch64.texi (-mcpu): Document neoverse-n1 value.
2019-02-22 17:56:50 +08:00
2019-02-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/tc-aarch64.c (aarch64_cpus): Add neoverse-n1.
* doc/c-aarch64.texi (-mcpu): Document neoverse-n1 value.
Fix a potential deadlock in some older Loongson 3A1000 MIPS processors. * NEWS: Mention -m[no-]fix-loongson3-llsc. * configure.ac: Add --enable-mips-fix-loongson3-llsc. Define DEFAULT_MIPS_FIX_LOONGSON3_LLSC. * config.in: Regenerated. * configure: Likewise. * config/tc-mips.c (sync_insn, mips_fix_loongson3_llsc): New variables. (options): New OPTION_FIX_LOONGSON3_LLSC, OPTION_NO_FIX_LOONGSON3_LLSC. (md_longopts): Add -m[no-]fix-loongson3-llsc. (md_begin): Initialize sync insn. (fix_loongson3_llsc): New. (append_insn): Call fix_loongson3_llsc. (md_parse_option): Handle OPTION_FIX_LOONGSON3_LLSC, OPTION_NO_FIX_LOONGSON3_LLSC. (md_show_usage): Display -m[no-]fix-loongson3-llsc. * doc/c-mips.texi: Document -m[no-]fix-loongson3-llsc, --enable-mips-fix-loongson3-llsc=[yes|no].
2019-02-20 01:57:16 +08:00
2019-02-19 Paul Hua <paul.hua.gm@gmail.com>
* NEWS: Mention -m[no-]fix-loongson3-llsc.
* configure.ac: Add --enable-mips-fix-loongson3-llsc.
Define DEFAULT_MIPS_FIX_LOONGSON3_LLSC.
* config.in: Regenerated.
* configure: Likewise.
* config/tc-mips.c (sync_insn, mips_fix_loongson3_llsc):
New variables.
(options): New OPTION_FIX_LOONGSON3_LLSC,
OPTION_NO_FIX_LOONGSON3_LLSC.
(md_longopts): Add -m[no-]fix-loongson3-llsc.
(md_begin): Initialize sync insn.
(fix_loongson3_llsc): New.
(append_insn): Call fix_loongson3_llsc.
(md_parse_option): Handle OPTION_FIX_LOONGSON3_LLSC,
OPTION_NO_FIX_LOONGSON3_LLSC.
(md_show_usage): Display -m[no-]fix-loongson3-llsc.
* doc/c-mips.texi: Document -m[no-]fix-loongson3-llsc,
--enable-mips-fix-loongson3-llsc=[yes|no].
gas: Pass max_bytes to TC_FRAG_INIT ommit 3ae729d5a4f63740ed9a778960b17c2912b0bbdd Author: H.J. Lu <hjl.tools@gmail.com> Date: Wed Mar 7 04:18:45 2018 -0800 x86: Rewrite NOP generation for fill and alignment increased MAX_MEM_FOR_RS_ALIGN_CODE to 4095 which resulted in increase of assembler time and memory usage by 5 times for inputs with many .p2align directives, which is typical for LTO output. This patch passes max_bytes to TC_FRAG_INIT so that MAX_MEM_FOR_RS_ALIGN_CODE can be set as needed and tracked by backend it so that HANDLE_ALIGN can check the maximum alignment for each rs_align_code frag. Wall time to assemble the same cc1plus.s: before: 423.78user 0.89system 7:05.71elapsed 99%CPU after: 102.35user 0.27system 1:42.89elapsed 99%CPU PR gas/24165 * frags.c (frag_var_init): Pass max_chars to TC_FRAG_INIT as max_bytes. * config/tc-aarch64.h (TC_FRAG_INIT): Add and pass max_bytes to aarch64_init_frag. * /config/tc-arm.h (TC_FRAG_INIT): And and pass max_bytes to arm_init_frag. * config/tc-avr.h (TC_FRAG_INIT): And and ignore max_bytes. * config/tc-ia64.h (TC_FRAG_INIT): Likewise. * config/tc-mmix.h (TC_FRAG_INIT): Likewise. * config/tc-nds32.h (TC_FRAG_INIT): Likewise. * config/tc-ns32k.h (TC_FRAG_INIT): Likewise. * config/tc-rl78.h (TC_FRAG_INIT): Likewise. * config/tc-rx.h (TC_FRAG_INIT): Likewise. * config/tc-score.h (TC_FRAG_INIT): Likewise. * config/tc-tic54x.h (TC_FRAG_INIT): Likewise. * config/tc-tic6x.h (TC_FRAG_INIT): Likewise. * config/tc-xtensa.h (TC_FRAG_INIT): Likewise. * config/tc-i386.h (MAX_MEM_FOR_RS_ALIGN_CODE): Set to (alignment ? ((1 << alignment) - 1) : 1) (i386_tc_frag_data): Add max_bytes. (TC_FRAG_INIT): Add and track max_bytes. (HANDLE_ALIGN): Replace MAX_MEM_FOR_RS_ALIGN_CODE with fragP->tc_frag_data.max_bytes. * doc/internals.texi: Update TC_FRAG_TYPE with max_bytes.
2019-02-10 20:34:10 +08:00
2019-02-10 H.J. Lu <hongjiu.lu@intel.com>
PR gas/24165
* frags.c (frag_var_init): Pass max_chars to TC_FRAG_INIT as
max_bytes.
* config/tc-aarch64.h (TC_FRAG_INIT): Add and pass max_bytes to
aarch64_init_frag.
* /config/tc-arm.h (TC_FRAG_INIT): And and pass max_bytes to
arm_init_frag.
* config/tc-avr.h (TC_FRAG_INIT): And and ignore max_bytes.
* config/tc-ia64.h (TC_FRAG_INIT): Likewise.
* config/tc-mmix.h (TC_FRAG_INIT): Likewise.
* config/tc-nds32.h (TC_FRAG_INIT): Likewise.
* config/tc-ns32k.h (TC_FRAG_INIT): Likewise.
* config/tc-rl78.h (TC_FRAG_INIT): Likewise.
* config/tc-rx.h (TC_FRAG_INIT): Likewise.
* config/tc-score.h (TC_FRAG_INIT): Likewise.
* config/tc-tic54x.h (TC_FRAG_INIT): Likewise.
* config/tc-tic6x.h (TC_FRAG_INIT): Likewise.
* config/tc-xtensa.h (TC_FRAG_INIT): Likewise.
* config/tc-i386.h (MAX_MEM_FOR_RS_ALIGN_CODE): Set to
(alignment ? ((1 << alignment) - 1) : 1)
(i386_tc_frag_data): Add max_bytes.
(TC_FRAG_INIT): Add and track max_bytes.
(HANDLE_ALIGN): Replace MAX_MEM_FOR_RS_ALIGN_CODE with
fragP->tc_frag_data.max_bytes.
* doc/internals.texi: Update TC_FRAG_TYPE with max_bytes.
Add missing ChangeLog files for previous patch.
2019-02-09 05:21:52 +08:00
2019-02-08 Jim Wilson <jimw@sifive.com>
* config/tc-riscv.c (validate_riscv_insn) <'C'>: Add 'z' support.
(riscv_ip) <'C'>: Add 'z' support.
Arm: Backport hlt to all architectures. The software trap instruction HLT that was introduced in Armv8-a is used as the semihosting trap instruction in AArch64. In order to allow systems configured to run AArch64 code to also run AArch32 with semihosting it was decided that AArch32 should also use HLT in the case of the "mixed mode" environment. This requires that HLT also be backported to all earlier architectures. The instruction is in the undefined encoding space earlier architectures but must trigger a semihosting trap [3]. The Arm Architectural Reference Manual [1] doesn't explicitly mention this however this is an explicit requirement in the Semihosting-v2 protocol [2]. [1] https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile [2] https://developer.arm.com/docs/100863/latest/the-semihosting-interface [3] https://github.com/qemu/qemu/commit/19a6e31c9d2701ef648b70ddcfc3bf64cec8c37e gas/ChangeLog: * config/tc-arm.c (insns): Redefine THUMB_VARIANT and ARM_VARIANT for hlt to armv1. * testsuite/gas/arm/armv8a-automatic-hlt.d: Update TAGs * testsuite/gas/arm/hlt.d: New test. * testsuite/gas/arm/hlt.s: New test. opcodes/ChangeLog: * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2019-02-08 01:12:23 +08:00
2019-02-07 Tamar Christina <tamar.christina@arm.com>
* config/tc-arm.c (insns): Redefine THUMB_VARIANT and ARM_VARIANT for
hlt to armv1.
* testsuite/gas/arm/armv8a-automatic-hlt.d: Update TAGs
* testsuite/gas/arm/hlt.d: New test.
* testsuite/gas/arm/hlt.s: New test.
AArch64: Add negative tests for Armv8.3-a complex number instructions instructions. This patch just adds a few negative tests for the Armv8.3-a complex instructions. These already do the right disassembly without needing a verifier, but adding some tests to make sure that stays that way. gas/ChangeLog: * testsuite/gas/aarch64/undefined_advsimd_armv8_3.d: New test. * testsuite/gas/aarch64/undefined_advsimd_armv8_3.s: New test.
2019-02-08 00:58:29 +08:00
2019-02-07 Tamar Christina <tamar.christina@arm.com>
* testsuite/gas/aarch64/undefined_advsimd_armv8_3.d: New test.
* testsuite/gas/aarch64/undefined_advsimd_armv8_3.s: New test.
AArch64: Add verifier for By elem Single and Double sized instructions. The AArch64 instruction set has cut-outs inside instructions encodings for when a given encoding that would normally fall within the encoding space of an instruction is instead undefined. This updates the first few instructions FMLA, FMLA, FMUL and FMULX in the case where sz:L == 11. gas/ChangeLog: PR binutils/23212 * testsuite/gas/aarch64/undefined_by_elem_sz_l.s: New test. * testsuite/gas/aarch64/undefined_by_elem_sz_l.d: New test. opcodes/ChangeLog: PR binutils/23212 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz. * aarch64-opc.c (verify_elem_sd): New. (fields): Add FLD_sz entr. * aarch64-tbl.h (_SIMD_INSN): New. (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and fmulx scalar and vector by element isns.
2019-02-08 00:55:23 +08:00
2019-02-07 Tamar Christina <tamar.christina@arm.com>
PR binutils/23212
* testsuite/gas/aarch64/undefined_by_elem_sz_l.s: New test.
* testsuite/gas/aarch64/undefined_by_elem_sz_l.d: New test.
Visium: align branch absolute instruction for the GR6 This is done in order to avoid a pipeline hazard on the GR6. gas/ * config/tc-visium.c (md_assemble) <mode_cad>: Align instruction on 64-bit boundaries for the GR6. * testsuite/gas/visium/allinsn_gr6.s: Tweak. * testsuite/gas/visium/allinsn_gr6.d: Likewise. * testsuite/gas/visium/bra-1.d: New test. * testsuite/gas/visium/bra-1.s: Likewise. * testsuite/gas/visium/visium.exp: Run bra-1 test.
2019-02-07 23:58:47 +08:00
2019-02-07 Eric Botcazou <ebotcazou@adacore.com>
* config/tc-visium.c (md_assemble) <mode_cad>: Align instruction on
64-bit boundaries for the GR6.
* testsuite/gas/visium/allinsn_gr6.s: Tweak.
* testsuite/gas/visium/allinsn_gr6.d: Likewise.
* testsuite/gas/visium/bra-1.d: New test.
* testsuite/gas/visium/bra-1.s: Likewise.
* testsuite/gas/visium/visium.exp: Run bra-1 test.
S12Z: GAS: Allow #_symbol operands as mov source mov.l, mov.p and mov.w (but not mov.b) when called with an immediate source operand should be accepted a relocatable expression. This change makes that possible. gas/ * config/tc-s12z.c (lex_imm): Add new argument exp_o. (emit_reloc): New function. (md_apply_fix): [BFD_RELOC_S12Z_OPR] Recognise that it can be either 2 bytes or 3 bytes long. * testsuite/gas/s12z/mov-imm-reloc.d: New file. * testsuite/gas/s12z/mov-imm-reloc.s: New file. * testsuite/gas/s12z/s12z.exp: Add them.
2019-02-02 00:42:54 +08:00
2019-01-31 John Darrington <john@darrington.wattle.id.au>
.file file number checking This adds another test for file numbers given in .file directives, checking that the value can be represented as an unsigned int and that a memory allocation expression doesn't overflow. I removed a test added recently since an earlier test (num < 1) already covers the (num < 0) case. * dwarf2dbg.c: Whitespace fixes. (get_filenum): Don't strdup "file". Adjust error message. (dwarf2_directive_filename): Use an unsigned type for "num". Catch truncation of file number and overflow of get_filenum XRESIZEVEC multiplication. Delete dead code.
2019-05-15 09:54:09 +08:00
* config/tc-s12z.c (lex_imm): Add new argument exp_o.
S12Z: GAS: Allow #_symbol operands as mov source mov.l, mov.p and mov.w (but not mov.b) when called with an immediate source operand should be accepted a relocatable expression. This change makes that possible. gas/ * config/tc-s12z.c (lex_imm): Add new argument exp_o. (emit_reloc): New function. (md_apply_fix): [BFD_RELOC_S12Z_OPR] Recognise that it can be either 2 bytes or 3 bytes long. * testsuite/gas/s12z/mov-imm-reloc.d: New file. * testsuite/gas/s12z/mov-imm-reloc.s: New file. * testsuite/gas/s12z/s12z.exp: Add them.
2019-02-02 00:42:54 +08:00
(emit_reloc): New function.
(md_apply_fix): [BFD_RELOC_S12Z_OPR] Recognise that it
can be either 2 bytes or 3 bytes long.
* testsuite/gas/s12z/mov-imm-reloc.d: New file.
* testsuite/gas/s12z/mov-imm-reloc.s: New file.
* testsuite/gas/s12z/s12z.exp: Add them.
S12Z: GAS: Fix incorrect range test for 16-bit PC relative offsets. The limits for PC relative offsets were incorrect. This change fixes them and adds some tests. gas/ * config/tc-s12z.c (md_apply_fix): Fix incorrect limits. * testsuite/gas/s12z/pc-rel-bad.d: New file. * testsuite/gas/s12z/pc-rel-bad.l: New file. * testsuite/gas/s12z/pc-rel-bad.s: New file. * testsuite/gas/s12z/pc-rel-good.d: New file. * testsuite/gas/s12z/pc-rel-good.s: New file. * testsuite/gas/s12z/s12z.exp: Add them.
2019-02-02 00:42:54 +08:00
2019-01-31 John Darrington <john@darrington.wattle.id.au>
* config/tc-s12z.c (md_apply_fix): Fix incorrect limits.
* testsuite/gas/s12z/pc-rel-bad.d: New file.
* testsuite/gas/s12z/pc-rel-bad.l: New file.
* testsuite/gas/s12z/pc-rel-bad.s: New file.
* testsuite/gas/s12z/pc-rel-good.d: New file.
* testsuite/gas/s12z/pc-rel-good.s: New file.
* testsuite/gas/s12z/s12z.exp: Add them.
S12Z: GAS: Issue warning if TFR/EXG have identical source and destination. It is permissible for the source and destination operands of TFR and EXG to be the same register. However it is a pointless instruction and anyone writing it has probably made a mistake. This change emits a warning if such an instruction is encountered. gas/ * config/tc-s12z.c (tfr): Emit warning if operands are the same. * testsuite/gas/s12z/exg.d: New test case. * testsuite/gas/s12z/exg.l: New file.
2019-02-02 00:42:54 +08:00
2019-01-31 John Darrington <john@darrington.wattle.id.au>
* config/tc-s12z.c (tfr): Emit warning if operands are the same.
* testsuite/gas/s12z/exg.d: New test case.
* testsuite/gas/s12z/exg.l: New file.
S12Z: GAS: Disallow immediate destination operands The assembler permitted instructions which attempted to assign to an immediate operand. Bizarrely there is a valid machine code for such operations (although the documentation says it's "inappropriate"). This change causes such attempts to fail with an error message. gas/ * config/tc-s12z.c (lex_opr): Add a parameter to indicate whether immediate mode operands should be permitted. * testsuite/s12z/imm-dest.d: New file. * testsuite/s12z/imm-dest.l: New file. * testsuite/s12z/imm-dest.s: New file. * testsuite/s12z/s12z.exp: Add them.
2019-02-02 00:42:54 +08:00
2019-01-31 John Darrington <john@darrington.wattle.id.au>
* config/tc-s12z.c (lex_opr): Add a parameter to indicate whether
immediate mode operands should be permitted.
* testsuite/s12z/imm-dest.d: New file.
* testsuite/s12z/imm-dest.l: New file.
* testsuite/s12z/imm-dest.s: New file.
* testsuite/s12z/s12z.exp: Add them.
S/390: Implement instruction set extensions opcodes/ChangeLog: 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com> * s390-mkopc.c (main): Accept arch13 as cpu string. * s390-opc.c: Add new instruction formats and instruction opcode masks. * s390-opc.txt: Add new arch13 instructions. include/ChangeLog: 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com> * opcode/s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_ARCH13. gas/ChangeLog: 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com> * config/tc-s390.c (s390_parse_cpu): New entry for arch13. * doc/c-s390.texi: Document arch13 march option. * testsuite/gas/s390/s390.exp: Run the arch13 related tests. * testsuite/gas/s390/zarch-arch13.d: New test. * testsuite/gas/s390/zarch-arch13.s: New test. * testsuite/gas/s390/zarch-z13.d: Expect the renamed mnemonics also for z13.
2019-02-01 00:01:27 +08:00
2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
* config/tc-s390.c (s390_parse_cpu): New entry for arch13.
* doc/c-s390.texi: Document arch13 march option.
* testsuite/gas/s390/s390.exp: Run the arch13 related tests.
* testsuite/gas/s390/zarch-arch13.d: New test.
* testsuite/gas/s390/zarch-arch13.s: New test.
* testsuite/gas/s390/zarch-z13.d: Expect the renamed mnemonics
also for z13.
Assorted warning fixes gcc-9 flagged warnings at the places I'm patching here, all real bugs. * config/tc-alpha.c (md_apply_fix): Correct range checks for BFD_RELOC_ALPHA_NOP, BFD_RELOC_ALPHA_LDA, BFD_RELOC_ALPHA_BSR. * config/tc-arm.c (md_apply_fix): Use llabs rather than abs. * config/tc-csky.c (get_macro_reg_vals): Pass s to csky_show_error.
2019-01-31 12:08:45 +08:00
2019-01-31 Alan Modra <amodra@gmail.com>
* config/tc-alpha.c (md_apply_fix): Correct range checks for
BFD_RELOC_ALPHA_NOP, BFD_RELOC_ALPHA_LDA, BFD_RELOC_ALPHA_BSR.
* config/tc-arm.c (md_apply_fix): Use llabs rather than abs.
* config/tc-csky.c (get_macro_reg_vals): Pass s to csky_show_error.
xtensa: gas: don't keep relocations for constants xtensa gas chokes on 8/16 bit data entries representing constant symbols because it leaves BFD_RELOC_8/BFD_RELOC_16 fixups for which xtensa BFD cannot emit relocations. Resolve fixups for constant symbols in md_apply_fix. gas/ 2019-01-28 Max Filippov <jcmvbkbc@gmail.com> * config/tc-xtensa.c (md_apply_fix): Mark fixups for constant symbols as done in md_apply_fix. * testsuite/gas/all/forward.d: Don't XFAIL for xtensa.
2019-01-26 10:52:32 +08:00
2019-01-28 Max Filippov <jcmvbkbc@gmail.com>
* config/tc-xtensa.c (md_apply_fix): Mark fixups for constant
symbols as done in md_apply_fix.
* testsuite/gas/all/forward.d: Don't XFAIL for xtensa.
Updated Russian and French translations for the gas sub-directory
2019-01-28 23:21:58 +08:00
2019-01-28 Nick Clifton <nickc@redhat.com>
* po/fr.po: Updated French translation.
* po/ru.po: Updated Russian translation.
Control gas enable-checking default by bfd/development.sh * configure.ac (ac_checking): Set from bfd/development.sh development variable. * configure: Regenerate.
2019-01-28 07:03:28 +08:00
2019-01-28 Alan Modra <amodra@gmail.com>
* configure.ac (ac_checking): Set from bfd/development.sh
development variable.
* configure: Regenerate.
AArch64: Add missing changelog for Update encodings for stg, st2g, stzg and st2zg
2019-01-25 23:50:01 +08:00
2019-01-25 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (warn_unpredictable_ldst): Exempt
stg, st2g, stzg and stz2g from Xt == Xn with writeback warning.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Change tests for
stg, stzg, st2g and stz2g.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
AArch64: Add new STZGM instruction for Armv8.5-A Memory Tagging Extension. This patch is part of a series of patches to introduce a few changes to the Armv8.5-A Memory Tagging Extension. This patch adds the new STZGM instruction. STGZM Xt, [<Xn|SP>] Committed on behalf of Sudakshina Das. *** gas/ChangeLog *** * testsuite/gas/aarch64/armv8_5-a-memtag.d: New tests for stzgm. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. *** opcodes/ChangeLog *** * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2019-01-25 22:15:45 +08:00
2019-01-25 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/armv8_5-a-memtag.d: New tests for stzgm.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
AArch64: Remove ldgv and stgv instructions from Armv8.5-A Memory Tagging Extension. This patch is part of a series of patches to introduce a few changes to the Armv8.5-A Memory Tagging Extension. This patch removes the LDGV and STGV instructions. These instructions needed special infrastructure to support [base]! style for addressing mode. That is also removed now. Committed on behalf of Sudakshina Das. *** gas/ChangeLog *** * config/tc-aarch64.c (parse_address_main): Remove support for [base]! address expression. (parse_operands): Remove support for AARCH64_OPND_ADDR_SIMPLE_2. (warn_unpredictable_ldst): Remove support for ldstgv_indexed. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Remove tests for ldgv and stgv. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. *** include/ChangeLog *** * opcode/aarch64.h (enum aarch64_opnd): Remove AARCH64_OPND_ADDR_SIMPLE_2. (enum aarch64_insn_class): Remove ldstgv_indexed. *** opcodes/ChangeLog *** * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove. * aarch64-asm.h (ins_addr_simple_2): Likeiwse. * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise. * aarch64-dis.h (ext_addr_simple_2): Likewise. * aarch64-opc.c (operand_general_constraint_met_p): Remove case for ldstgv_indexed. (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2. * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv. (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
2019-01-25 21:57:14 +08:00
2019-01-25 Sudakshina Das <sudi.das@arm.com>
Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* config/tc-aarch64.c (parse_address_main): Remove support for
[base]! address expression.
(parse_operands): Remove support for AARCH64_OPND_ADDR_SIMPLE_2.
(warn_unpredictable_ldst): Remove support for ldstgv_indexed.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Remove tests for ldgv
and stgv.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
PR23940, check bounds before using PR gas/23940 * macro.c (getstring): Check array bound before accessing.
2019-01-25 11:11:47 +08:00
2019-01-25 Wu Heng <wu.heng@zte.com.cn>
PR gas/23940
* macro.c (getstring): Check array bound before accessing.
PR24125, Assertion failure with embedded NULs in string An assertion that can be triggered by user input is wrong, so remove it. I believe the NUL would have been accepted before the PR20902 patch. PR 20902 PR 24125 * read.c (stringer): Delete assertion.
2019-01-25 07:04:14 +08:00
2019-01-25 Alan Modra <amodra@gmail.com>
PR 20902
PR 24125
* read.c (stringer): Delete assertion.
Updated translations for various binutils subdirectories.
2019-01-21 20:59:20 +08:00
2019-01-21 Nick Clifton <nickc@redhat.com>
* po/uk.po: Updated Ukranian translation.
Change version to 2.32.51 and regenerate configure and pot files.
2019-01-20 00:51:42 +08:00
2019-01-19 Nick Clifton <nickc@redhat.com>
* config.in: Regenerate.
* configure: Regenerate.
* po/gas.pot: Regenerate.
Add markers for 2.32 branch to NEWS and ChangeLog files.
2019-01-19 23:55:50 +08:00
2018-06-24 Nick Clifton <nickc@redhat.com>
2.32 branch created.
Arm: Clean up PE GAS testsuite correct THUMB tests. The PE targets don't support mapping symbols and so the disassembler is unable to correctly output thumb instructions when the input was thumb. So for testcases that only have thumb output, I have copied them and skipped the ones for which auto-detection is supposed to work on PE, and added a new one that will force thumb output. This so that the tests still check the mapping symbols. For the tests that switch between thumb and arm in one file I just skip them entirely on PE targets. This cleans up the PE GAS testsuite. gas/ * testsuite/gas/arm/archv6t2-1-pe.d: New test. * testsuite/gas/arm/archv6t2-1.d: Skip pe. * testsuite/gas/arm/csdb.d: Skip pe. * testsuite/gas/arm/sb-thumb1-pe.d: New test. * testsuite/gas/arm/sb-thumb1.d: Skip pe. * testsuite/gas/arm/sb-thumb2-pe.d: New test. * testsuite/gas/arm/sb-thumb2.d: Skip pe. * testsuite/gas/arm/udf.d: Skip pe.
2019-01-18 00:05:37 +08:00
2019-01-17 Tamar Christina <tamar.christina@arm.com>
* testsuite/gas/arm/archv6t2-1-pe.d: New test.
* testsuite/gas/arm/archv6t2-1.d: Skip pe.
* testsuite/gas/arm/csdb.d: Skip pe.
* testsuite/gas/arm/sb-thumb1-pe.d: New test.
* testsuite/gas/arm/sb-thumb1.d: Skip pe.
* testsuite/gas/arm/sb-thumb2-pe.d: New test.
* testsuite/gas/arm/sb-thumb2.d: Skip pe.
* testsuite/gas/arm/udf.d: Skip pe.
Don't emit vendor attribute section if there is no attribute to emit. 2019-01-16 Kito Cheng <kito@andestech.com> bfd/ * elf-attrs.c (vendor_obj_attr_size): Return 0 if size is 0 even for OBJ_ATTR_PROC. gas/ * testsuite/gas/riscv/attribute-empty.d: New.
2019-01-17 05:37:35 +08:00
2019-01-16 Kito Cheng <kito@andestech.com>
* testsuite/gas/riscv/attribute-empty.d: New.
RISC-V: Support ELF attribute for gas and readelf. 2019-01-16 Kito Cheng <kito@andestech.com> Nelson Chu <nelson@andestech.com> bfd/ * elfnn-riscv.c (riscv_elf_obj_attrs_arg_type): New. (elf_backend_obj_attrs_vendor): Define. (elf_backend_obj_attrs_section_type): Likewise. (elf_backend_obj_attrs_section): Likewise. (elf_backend_obj_attrs_arg_type): Define as riscv_elf_obj_attrs_arg_type. * elfxx-riscv.c (riscv_estimate_digit): New. (riscv_estimate_arch_strlen1): Likewise. (riscv_estimate_arch_strlen): Likewise. (riscv_arch_str1): Likewise. (riscv_arch_str): Likewise. * elfxx-riscv.h (riscv_arch_str): Declare. binutils/ * readelf.c (get_riscv_section_type_name): New function. (get_section_type_name): Add handler for RISC-V. (riscv_attr_tag_t): Declare. (riscv_attr_tag): New. (display_riscv_attribute): New function. (process_attributes): Add handler for RISC-V. * testsuite/binutils-all/strip-3.d: Remove .riscv.attribute section. gas/ * config/tc-riscv.c (DEFAULT_RISCV_ATTR): Define to 0 if not defined. (riscv_set_options): Add `arch_attr` field. (riscv_opts): Set default value for arch_attr. (riscv_write_out_arch_attr): New. (riscv_set_public_attributes): Likewise. (riscv_md_end): Likewise. (riscv_convert_symbolic_attribute): Likewise. (s_riscv_attribute): Likewise. (explicit_arch_attr): Likewise. (riscv_pseudo_table): Add .attribute to the table. (options): Add OPTION_ARCH_ATTR and OPTION_NO_ARCH_ATTR enumeration constants. (md_longopts): Add `march-attr' and `mno-arch-attr' options. (md_parse_option): Handle the new options. (md_show_usage): Document the `march-attr' option. * config/tc-riscv.h (md_end): Define as riscv_md_end (riscv_md_end): Declare. (CONVERT_SYMBOLIC_ATTRIBUTE): Define as riscv_convert_symbolic_attribute. (riscv_convert_symbolic_attribute): Declare. (start_assemble): Declare. * testsuite/gas/elf/elf.exp: Adjust test case for section2.e. * testsuite/gas/elf/section2.e-riscv: New. * testsuite/gas/riscv/attribute-01.d: New test * testsuite/gas/riscv/attribute-02.d: Likewise. * testsuite/gas/riscv/attribute-03.d: Likewise. * testsuite/gas/riscv/attribute-04.d: Likewise. * testsuite/gas/riscv/attribute-04.s: Likewise. * testsuite/gas/riscv/attribute-05.d: Likewise. * testsuite/gas/riscv/attribute-05.s: Likewise. * testsuite/gas/riscv/attribute-06.d: Likewise. * testsuite/gas/riscv/attribute-06.s: Likewise. * testsuite/gas/riscv/attribute-07.d: Likewise. * testsuite/gas/riscv/attribute-07.s: Likewise. * testsuite/gas/riscv/attribute-08.d: Likewise. * testsuite/gas/riscv/attribute-08.s: Likewise. * testsuite/gas/riscv/attribute-unknown.d: Likewise. * testsuite/gas/riscv/attribute-unknown.s: Likewise. * testsuite/gas/riscv/empty.l: Likewise. * doc/c-riscv.texi (.attribute): Add documentation. * configure.ac (--enable-default-riscv-attribute): New options. * configure: Re-generate. * config.in: Re-generate. include/ * elf/riscv.h (SHT_RISCV_ATTRIBUTES): Define. (Tag_RISCV_arch): Likewise. (Tag_RISCV_priv_spec): Likewise. (Tag_RISCV_priv_spec_minor): Likewise. (Tag_RISCV_priv_spec_revision): Likewise. (Tag_RISCV_unaligned_access): Likewise. (Tag_RISCV_stack_align): Likewise.
2019-01-17 05:14:59 +08:00
2019-01-16 Kito Cheng <kito@andestech.com>
Nelson Chu <nelson@andestech.com>
* config/tc-riscv.c (DEFAULT_RISCV_ATTR): Define to 0 if not defined.
(riscv_set_options): Add `arch_attr` field.
(riscv_opts): Set default value for arch_attr.
(riscv_write_out_arch_attr): New.
(riscv_set_public_attributes): Likewise.
(riscv_md_end): Likewise.
(riscv_convert_symbolic_attribute): Likewise.
(s_riscv_attribute): Likewise.
(explicit_arch_attr): Likewise.
(riscv_pseudo_table): Add .attribute to the table.
(options): Add OPTION_ARCH_ATTR and OPTION_NO_ARCH_ATTR
enumeration constants.
(md_longopts): Add `march-attr' and `mno-arch-attr' options.
(md_parse_option): Handle the new options.
(md_show_usage): Document the `march-attr' option.
* config/tc-riscv.h (md_end): Define as riscv_md_end
(riscv_md_end): Declare.
(CONVERT_SYMBOLIC_ATTRIBUTE): Define as
riscv_convert_symbolic_attribute.
(riscv_convert_symbolic_attribute): Declare.
(start_assemble): Declare.
* testsuite/gas/elf/elf.exp: Adjust test case for section2.e.
* testsuite/gas/elf/section2.e-riscv: New.
* testsuite/gas/riscv/attribute-01.d: New test
* testsuite/gas/riscv/attribute-02.d: Likewise.
* testsuite/gas/riscv/attribute-03.d: Likewise.
* testsuite/gas/riscv/attribute-04.d: Likewise.
* testsuite/gas/riscv/attribute-04.s: Likewise.
* testsuite/gas/riscv/attribute-05.d: Likewise.
* testsuite/gas/riscv/attribute-05.s: Likewise.
* testsuite/gas/riscv/attribute-06.d: Likewise.
* testsuite/gas/riscv/attribute-06.s: Likewise.
* testsuite/gas/riscv/attribute-07.d: Likewise.
* testsuite/gas/riscv/attribute-07.s: Likewise.
* testsuite/gas/riscv/attribute-08.d: Likewise.
* testsuite/gas/riscv/attribute-08.s: Likewise.
* testsuite/gas/riscv/attribute-unknown.d: Likewise.
* testsuite/gas/riscv/attribute-unknown.s: Likewise.
* testsuite/gas/riscv/empty.l: Likewise.
* doc/c-riscv.texi (.attribute): Add documentation.
* configure.ac (--enable-default-riscv-attribute): New options.
* configure: Re-generate.
* config.in: Re-generate.
S12Z: Emit RELOC_S12Z_OPR instead of RELOC_EXT24 where appropriate. When assembling instructions which involve OPR references, emit RELOC_S12Z_OPR instead of RELOC_EXT24. bfd/ * bfd-in2.h [BFD_RELOC_S12Z_OPR]: New reloc. * libbfd.h: regen. * elf32-s12z.c (eld_s12z_howto_table): R_S12Z_OPR takes non zero source field. (md_apply_fix): Apply final fix to BFD_RELOC_S12Z_OPR. * reloc.c[BFD_RELOC_S12Z_OPR]: New reloc. gas/ * config/tc-s12z.c (emit_opr): Emit BFD_RELOC_S12Z_OPR instead of BFD_RELOC_24. * testsuite/gas/s12z/opr-indirect-expr.d: Expect R_S12Z_OPR instead of R_S12Z_EXT24.
2019-01-16 21:34:50 +08:00
2019-01-16 John Darrington <john@darrington.wattle.id.au>
S12Z: gas: Fix bug when a symbol name was the single letter 'c'. The assembler incorrectly recognised "c" as a register name, and refused to allow it where it expected a symbol/label. gas/ * config/tc-s12z.c (lex_reg_name): Compare the length of the strings before the contents. * testsuite/gas/s12z/labels.d: New file. * testsuite/gas/s12z/labels.s: New file. * testsuite/gas/s12z/s12z.exp: Add them.
2019-01-14 23:55:17 +08:00
* config/tc-s12z.c (lex_reg_name): Compare the length of the strings
before the contents.
* testsuite/gas/s12z/labels.d: New file.
* testsuite/gas/s12z/labels.s: New file.
* testsuite/gas/s12z/s12z.exp: Add them.
* config/tc-s12z.c (tfr): Change as_bad to as_warn.
S12Z: gas: Permit "extend" instructions which don't actually extend. Other assemblers permit "extending" a register into a register of a smaller size or the same size. It doesn't make much sense to do this but would appear to be a valid instruction. So change the error to a warning. gas/ * config/tc-s12z.c (tfr): Change as_bad to as_warn. Also fix message typo and semantics.
2019-01-16 21:34:50 +08:00
Also fix message typo and semantics.
S12Z: gas: Fix bug when a symbol name was the single letter 'c'. The assembler incorrectly recognised "c" as a register name, and refused to allow it where it expected a symbol/label. gas/ * config/tc-s12z.c (lex_reg_name): Compare the length of the strings before the contents. * testsuite/gas/s12z/labels.d: New file. * testsuite/gas/s12z/labels.s: New file. * testsuite/gas/s12z/s12z.exp: Add them.
2019-01-14 23:55:17 +08:00
* config/tc-s12z.c (emit_opr): Emit BFD_RELOC_S12Z_OPR instead of
S12Z: Emit RELOC_S12Z_OPR instead of RELOC_EXT24 where appropriate. When assembling instructions which involve OPR references, emit RELOC_S12Z_OPR instead of RELOC_EXT24. bfd/ * bfd-in2.h [BFD_RELOC_S12Z_OPR]: New reloc. * libbfd.h: regen. * elf32-s12z.c (eld_s12z_howto_table): R_S12Z_OPR takes non zero source field. (md_apply_fix): Apply final fix to BFD_RELOC_S12Z_OPR. * reloc.c[BFD_RELOC_S12Z_OPR]: New reloc. gas/ * config/tc-s12z.c (emit_opr): Emit BFD_RELOC_S12Z_OPR instead of BFD_RELOC_24. * testsuite/gas/s12z/opr-indirect-expr.d: Expect R_S12Z_OPR instead of R_S12Z_EXT24.
2019-01-16 21:34:50 +08:00
BFD_RELOC_24.
* testsuite/gas/s12z/opr-indirect-expr.d: Expect R_S12Z_OPR instead
of R_S12Z_EXT24.
Implement the assembly instructions yield, wfe, wfi and sev for ARMv6T2 in both ARM mode and Thumb mode. * config/tc-arm.c (arm_ext_v6k_v6t2): Define. (insns) [ARM_VARIANT]: Modified. (insns) [THUMB_VARIANT]: To implement few ARMv6K instructions in ARMv6T2 as well. * testsuite/gas/arm/archv6t2-1.d: New test. * testsuite/gas/arm/archv6t2-1.s: Likewise. * testsuite/gas/arm/archv6t2-2.d: Likewise.
2019-01-14 18:35:50 +08:00
2019-01-14 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config/tc-arm.c (arm_ext_v6k_v6t2): Define.
(insns) [ARM_VARIANT]: Modified.
(insns) [THUMB_VARIANT]: To implement few ARMv6K instructions
in ARMv6T2 as well.
* testsuite/gas/arm/archv6t2-1.d: New test.
* testsuite/gas/arm/archv6t2-1.s: Likewise.
* testsuite/gas/arm/archv6t2-2.d: Likewise.
More fallout from PR 23963 change PR 23963 * testsuite/gas/m68hc11/lbranch-dwarf2.d: Adjust for PR23963 change. * testsuite/gas/m68hc11/opers12-dwarf2.d: Likewise.
2019-01-11 19:52:30 +08:00
2019-01-11 Alan Modra <amodra@gmail.com>
PR 23963
* testsuite/gas/m68hc11/lbranch-dwarf2.d: Adjust for PR23963 change.
* testsuite/gas/m68hc11/opers12-dwarf2.d: Likewise.
Stop objdump from displaying control codes embedded in symbol names. PR 23963 binutils* objdump.c (sanitize_string): New function. Removes control characters from symbol names. (dump_section_header): Use new function. (objdump_print_symname): Likewise. (objdump_print_addr_with_sym): Likewise. (show_line): Likewise. (disassemble_bytes): Likewise. (disassemble_section): Likewise. (load_specific_debug_section): Likewise. (read_section_stabs): Likewise. (print_section_stabs): Likewise. (dump_section): Likewise. (dump_reloc_set): Likewise. (dump_relocs_in_section): Likewise. (dump_bfd): Likewise. (display_any_bfd): Likewise. gas * testsuite/gas/mips/mips16-branch-absolute-1.d: Adjust for the fact that control characters are now displayed as escape sequences. * testsuite/gas/mips/mips16-e.d: Likewise. * testsuite/gas/mips/mips16-pcrel-0.d: Likewise. * testsuite/gas/mips/mips16-pcrel-1.d: Likewise. * testsuite/gas/mips/mips16-pcrel-delay-0.d: Likewise. * testsuite/gas/mips/mips16-pcrel-delay-1.d: Likewise. * testsuite/gas/mips/mips16-pcrel-n32-0.d: Likewise. * testsuite/gas/mips/mips16-pcrel-n32-1.d: Likewise. * testsuite/gas/mips/mips16-pcrel-n64-sym32-0.d: Likewise. * testsuite/gas/mips/mips16-pcrel-n64-sym32-1.d: Likewise. * testsuite/gas/mips/mips16e2@mips16-pcrel-0.d: Likewise. * testsuite/gas/mips/mips16e2@mips16-pcrel-1.d: Likewise. * testsuite/gas/mips/mips16e2@mips16-pcrel-delay-0.d: Likewise. * testsuite/gas/mips/mips16e2@mips16-pcrel-delay-1.d: Likewise. * testsuite/gas/mips/mips16e2@mips16-pcrel-n32-0.d: Likewise. * testsuite/gas/mips/mips16e2@mips16-pcrel-n32-1.d: Likewise. * testsuite/gas/mips/mips16e2@mips16-pcrel-n64-sym32-0.d: Likewise. * testsuite/gas/mips/mips16e2@mips16-pcrel-n64-sym32-1.d: Likewise. * testsuite/gas/mips/mipsel16-e.d: Likewise. * testsuite/gas/mips/mipsr6@msa.d: Likewise. * testsuite/gas/mips/mipsr6@relax-swap3.d: Likewise. * testsuite/gas/mips/r6-64-n32.d: Likewise. * testsuite/gas/mips/r6-64-n64.d: Likewise. * testsuite/gas/mips/r6-n32.d: Likewise. * testsuite/gas/mips/r6-n64.d: Likewise. * testsuite/gas/mips/r6.d: Likewise. * testsuite/gas/mips/tmips16-e.d: Likewise. * testsuite/gas/mips/tmipsel16-e.d: Likewise. * testsuite/gas/mn10300/relax.d: Likewise.
2019-01-10 23:19:33 +08:00
2019-01-10 Nick Clifton <nickc@redhat.com>
PR 23963
Correct changelog entry.
2019-01-10 23:23:03 +08:00
* testsuite/gas/mips/mips16-branch-absolute-1.d: Adjust for the
fact that control characters are now displayed as escape
sequences.
Stop objdump from displaying control codes embedded in symbol names. PR 23963 binutils* objdump.c (sanitize_string): New function. Removes control characters from symbol names. (dump_section_header): Use new function. (objdump_print_symname): Likewise. (objdump_print_addr_with_sym): Likewise. (show_line): Likewise. (disassemble_bytes): Likewise. (disassemble_section): Likewise. (load_specific_debug_section): Likewise. (read_section_stabs): Likewise. (print_section_stabs): Likewise. (dump_section): Likewise. (dump_reloc_set): Likewise. (dump_relocs_in_section): Likewise. (dump_bfd): Likewise. (display_any_bfd): Likewise. gas * testsuite/gas/mips/mips16-branch-absolute-1.d: Adjust for the fact that control characters are now displayed as escape sequences. * testsuite/gas/mips/mips16-e.d: Likewise. * testsuite/gas/mips/mips16-pcrel-0.d: Likewise. * testsuite/gas/mips/mips16-pcrel-1.d: Likewise. * testsuite/gas/mips/mips16-pcrel-delay-0.d: Likewise. * testsuite/gas/mips/mips16-pcrel-delay-1.d: Likewise. * testsuite/gas/mips/mips16-pcrel-n32-0.d: Likewise. * testsuite/gas/mips/mips16-pcrel-n32-1.d: Likewise. * testsuite/gas/mips/mips16-pcrel-n64-sym32-0.d: Likewise. * testsuite/gas/mips/mips16-pcrel-n64-sym32-1.d: Likewise. * testsuite/gas/mips/mips16e2@mips16-pcrel-0.d: Likewise. * testsuite/gas/mips/mips16e2@mips16-pcrel-1.d: Likewise. * testsuite/gas/mips/mips16e2@mips16-pcrel-delay-0.d: Likewise. * testsuite/gas/mips/mips16e2@mips16-pcrel-delay-1.d: Likewise. * testsuite/gas/mips/mips16e2@mips16-pcrel-n32-0.d: Likewise. * testsuite/gas/mips/mips16e2@mips16-pcrel-n32-1.d: Likewise. * testsuite/gas/mips/mips16e2@mips16-pcrel-n64-sym32-0.d: Likewise. * testsuite/gas/mips/mips16e2@mips16-pcrel-n64-sym32-1.d: Likewise. * testsuite/gas/mips/mipsel16-e.d: Likewise. * testsuite/gas/mips/mipsr6@msa.d: Likewise. * testsuite/gas/mips/mipsr6@relax-swap3.d: Likewise. * testsuite/gas/mips/r6-64-n32.d: Likewise. * testsuite/gas/mips/r6-64-n64.d: Likewise. * testsuite/gas/mips/r6-n32.d: Likewise. * testsuite/gas/mips/r6-n64.d: Likewise. * testsuite/gas/mips/r6.d: Likewise. * testsuite/gas/mips/tmips16-e.d: Likewise. * testsuite/gas/mips/tmipsel16-e.d: Likewise. * testsuite/gas/mn10300/relax.d: Likewise.
2019-01-10 23:19:33 +08:00
* testsuite/gas/mips/mips16-e.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-0.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-1.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-delay-0.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-delay-1.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-n32-0.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-n32-1.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-n64-sym32-0.d: Likewise.
* testsuite/gas/mips/mips16-pcrel-n64-sym32-1.d: Likewise.
* testsuite/gas/mips/mips16e2@mips16-pcrel-0.d: Likewise.
* testsuite/gas/mips/mips16e2@mips16-pcrel-1.d: Likewise.
* testsuite/gas/mips/mips16e2@mips16-pcrel-delay-0.d: Likewise.
* testsuite/gas/mips/mips16e2@mips16-pcrel-delay-1.d: Likewise.
* testsuite/gas/mips/mips16e2@mips16-pcrel-n32-0.d: Likewise.
* testsuite/gas/mips/mips16e2@mips16-pcrel-n32-1.d: Likewise.
* testsuite/gas/mips/mips16e2@mips16-pcrel-n64-sym32-0.d:
Likewise.
* testsuite/gas/mips/mips16e2@mips16-pcrel-n64-sym32-1.d:
Likewise.
* testsuite/gas/mips/mipsel16-e.d: Likewise.
* testsuite/gas/mips/mipsr6@msa.d: Likewise.
* testsuite/gas/mips/mipsr6@relax-swap3.d: Likewise.
* testsuite/gas/mips/r6-64-n32.d: Likewise.
* testsuite/gas/mips/r6-64-n64.d: Likewise.
* testsuite/gas/mips/r6-n32.d: Likewise.
* testsuite/gas/mips/r6-n64.d: Likewise.
* testsuite/gas/mips/r6.d: Likewise.
* testsuite/gas/mips/tmips16-e.d: Likewise.
* testsuite/gas/mips/tmipsel16-e.d: Likewise.
* testsuite/gas/mn10300/relax.d: Likewise.
S12Z: Fix disassembly of indexed OPR operands with zero index. gas/ * testsuite/gas/s12z/jsr.s: New case. * testsuite/gas/s12z/jsr.d: New case. opcodes/ * s12z-dis.c (opr_emit_disassembly): Do not omit an index if it is zero.
2018-12-31 15:48:10 +08:00
2019-01-09 John Darrington <john@darrington.wattle.id.au>
.file file number checking This adds another test for file numbers given in .file directives, checking that the value can be represented as an unsigned int and that a memory allocation expression doesn't overflow. I removed a test added recently since an earlier test (num < 1) already covers the (num < 0) case. * dwarf2dbg.c: Whitespace fixes. (get_filenum): Don't strdup "file". Adjust error message. (dwarf2_directive_filename): Use an unsigned type for "num". Catch truncation of file number and overflow of get_filenum XRESIZEVEC multiplication. Delete dead code.
2019-05-15 09:54:09 +08:00
* testsuite/gas/s12z/jsr.s: New case.
S12Z: Fix disassembly of indexed OPR operands with zero index. gas/ * testsuite/gas/s12z/jsr.s: New case. * testsuite/gas/s12z/jsr.d: New case. opcodes/ * s12z-dis.c (opr_emit_disassembly): Do not omit an index if it is zero.
2018-12-31 15:48:10 +08:00
* testsuite/gas/s12z/jsr.d: New case.
Adjust bfd/warning.m4 egrep patterns Adjust the `bfd/warning.m4` `egrep` patterns to handle preprocessors that do not define `__GNUC__`, leaving the string in the output. bfd/ * warning.m4: Adjust egrep pattern for non-GNU compilers. * configure: Regenerate. binutils/ * configure: Regenerate. gas/ * configure: Regenerate. gold/ * configure: Regenerate. gprof/ * configure: Regenerate. ld/ * configure: Regenerate. opcodes/ * configure: Regenerate.
2019-01-09 11:21:08 +08:00
2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
* configure: Regenerate.
[AArch64][gas] Add -mcpu support for Arm Ares This adds support for the Arm Ares CPU for AArch64. It implements the Armv8.2-A architecture with the optional features of statistical profiling, dot product and FP16 on by default. Note: Ares is a codename to enable early adopters and in time we will add the final product name once it's announced. * config/tc-aarch64.c (aarch64_cpus): Add ares. * doc/c-aarch64.texi (-mcpu): Document ares value.
2019-01-08 23:18:32 +08:00
2019-01-08 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/tc-aarch64.c (aarch64_cpus): Add ares.
* doc/c-aarch64.texi (-mcpu): Document ares value.
run_dump_test source in build directory Some existing tests build .s and .d files for run_dump_test, using an absolute #source: line in the .d file. This patch changes that scheme a little to instead use "#source: ./..." in .d files rather than "#source: $objdir/...", which is more useful in cases where the .d file is not generated. This allows RX gas test files to be built in the build directory, rather than in a source directory (which might be read-only). binutils/ * testsuite/lib/binutils-common.exp (run_dump_test): Don't prepend $srcdir/$subdir to source file name if it starts with "./". gas/ * testsuite/gas/rx/rx.exp: Create generated test source in current directory. * testsuite/gas/rx/Xtod.d, * testsuite/gas/rx/abs.d, * testsuite/gas/rx/adc.d, * testsuite/gas/rx/add.d, * testsuite/gas/rx/and.d, * testsuite/gas/rx/bclr.d, * testsuite/gas/rx/bcnd.d, * testsuite/gas/rx/bfmov.d, * testsuite/gas/rx/bmcnd.d, * testsuite/gas/rx/bnot.d, * testsuite/gas/rx/bra.d, * testsuite/gas/rx/brk.d, * testsuite/gas/rx/bset.d, * testsuite/gas/rx/bsr.d, * testsuite/gas/rx/btst.d, * testsuite/gas/rx/clrpsw.d, * testsuite/gas/rx/cmp.d, * testsuite/gas/rx/dabs.d, * testsuite/gas/rx/dadd.d, * testsuite/gas/rx/dbt.d, * testsuite/gas/rx/dcmp.d, * testsuite/gas/rx/ddiv.d, * testsuite/gas/rx/div.d, * testsuite/gas/rx/divu.d, * testsuite/gas/rx/dmov.d, * testsuite/gas/rx/dmul.d, * testsuite/gas/rx/dneg.d, * testsuite/gas/rx/dpopm.d, * testsuite/gas/rx/dpushm.d, * testsuite/gas/rx/dround.d, * testsuite/gas/rx/dsqrt.d, * testsuite/gas/rx/dsub.d, * testsuite/gas/rx/dtoX.d, * testsuite/gas/rx/emaca.d, * testsuite/gas/rx/emsba.d, * testsuite/gas/rx/emul.d, * testsuite/gas/rx/emula.d, * testsuite/gas/rx/emulu.d, * testsuite/gas/rx/fadd.d, * testsuite/gas/rx/fcmp.d, * testsuite/gas/rx/fdiv.d, * testsuite/gas/rx/fmul.d, * testsuite/gas/rx/fsqrt.d, * testsuite/gas/rx/fsub.d, * testsuite/gas/rx/ftoi.d, * testsuite/gas/rx/ftou.d, * testsuite/gas/rx/gprel.d, * testsuite/gas/rx/int.d, * testsuite/gas/rx/itof.d, * testsuite/gas/rx/jmp.d, * testsuite/gas/rx/jsr.d, * testsuite/gas/rx/machi.d, * testsuite/gas/rx/maclh.d, * testsuite/gas/rx/maclo.d, * testsuite/gas/rx/max.d, * testsuite/gas/rx/min.d, * testsuite/gas/rx/mov.d, * testsuite/gas/rx/movco.d, * testsuite/gas/rx/movli.d, * testsuite/gas/rx/movu.d, * testsuite/gas/rx/msbhi.d, * testsuite/gas/rx/msblh.d, * testsuite/gas/rx/msblo.d, * testsuite/gas/rx/mul.d, * testsuite/gas/rx/mulhi.d, * testsuite/gas/rx/mullh.d, * testsuite/gas/rx/mullo.d, * testsuite/gas/rx/mvfacgu.d, * testsuite/gas/rx/mvfachi.d, * testsuite/gas/rx/mvfaclo.d, * testsuite/gas/rx/mvfacmi.d, * testsuite/gas/rx/mvfc.d, * testsuite/gas/rx/mvfcp.d, * testsuite/gas/rx/mvfdc.d, * testsuite/gas/rx/mvfdr.d, * testsuite/gas/rx/mvtacgu.d, * testsuite/gas/rx/mvtachi.d, * testsuite/gas/rx/mvtaclo.d, * testsuite/gas/rx/mvtc.d, * testsuite/gas/rx/mvtcp.d, * testsuite/gas/rx/mvtdc.d, * testsuite/gas/rx/neg.d, * testsuite/gas/rx/nop.d, * testsuite/gas/rx/not.d, * testsuite/gas/rx/opecp.d, * testsuite/gas/rx/or.d, * testsuite/gas/rx/pop.d, * testsuite/gas/rx/popc.d, * testsuite/gas/rx/popm.d, * testsuite/gas/rx/push.d, * testsuite/gas/rx/pushc.d, * testsuite/gas/rx/pushm.d, * testsuite/gas/rx/r-bcc.d, * testsuite/gas/rx/r-bra.d, * testsuite/gas/rx/racl.d, * testsuite/gas/rx/racw.d, * testsuite/gas/rx/rdacl.d, * testsuite/gas/rx/rdacw.d, * testsuite/gas/rx/revl.d, * testsuite/gas/rx/revw.d, * testsuite/gas/rx/rmpa.d, * testsuite/gas/rx/rolc.d, * testsuite/gas/rx/rorc.d, * testsuite/gas/rx/rotl.d, * testsuite/gas/rx/rotr.d, * testsuite/gas/rx/round.d, * testsuite/gas/rx/rstr.d, * testsuite/gas/rx/rte.d, * testsuite/gas/rx/rtfi.d, * testsuite/gas/rx/rts.d, * testsuite/gas/rx/rtsd.d, * testsuite/gas/rx/sat.d, * testsuite/gas/rx/satr.d, * testsuite/gas/rx/save.d, * testsuite/gas/rx/sbb.d, * testsuite/gas/rx/sccnd.d, * testsuite/gas/rx/scmpu.d, * testsuite/gas/rx/setpsw.d, * testsuite/gas/rx/shar.d, * testsuite/gas/rx/shll.d, * testsuite/gas/rx/shlr.d, * testsuite/gas/rx/smovb.d, * testsuite/gas/rx/smovf.d, * testsuite/gas/rx/smovu.d, * testsuite/gas/rx/sstr.d, * testsuite/gas/rx/stnz.d, * testsuite/gas/rx/stz.d, * testsuite/gas/rx/sub.d, * testsuite/gas/rx/suntil.d, * testsuite/gas/rx/swhile.d, * testsuite/gas/rx/tst.d, * testsuite/gas/rx/utof.d, * testsuite/gas/rx/wait.d, * testsuite/gas/rx/xchg.d, * testsuite/gas/rx/xor.d: Add #source line. ld/ * testsuite/ld-elf/sec64k.exp: Use . rather than $objdir in generated source file names. * testsuite/ld-m68k/m68k-got.exp: Likewise.
2019-01-08 14:17:52 +08:00
2019-01-08 Alan Modra <amodra@gmail.com>
* testsuite/gas/rx/rx.exp: Create generated test source in
current directory.
* testsuite/gas/rx/Xtod.d, * testsuite/gas/rx/abs.d,
* testsuite/gas/rx/adc.d, * testsuite/gas/rx/add.d,
* testsuite/gas/rx/and.d, * testsuite/gas/rx/bclr.d,
* testsuite/gas/rx/bcnd.d, * testsuite/gas/rx/bfmov.d,
* testsuite/gas/rx/bmcnd.d, * testsuite/gas/rx/bnot.d,
* testsuite/gas/rx/bra.d, * testsuite/gas/rx/brk.d,
* testsuite/gas/rx/bset.d, * testsuite/gas/rx/bsr.d,
* testsuite/gas/rx/btst.d, * testsuite/gas/rx/clrpsw.d,
* testsuite/gas/rx/cmp.d, * testsuite/gas/rx/dabs.d,
* testsuite/gas/rx/dadd.d, * testsuite/gas/rx/dbt.d,
* testsuite/gas/rx/dcmp.d, * testsuite/gas/rx/ddiv.d,
* testsuite/gas/rx/div.d, * testsuite/gas/rx/divu.d,
* testsuite/gas/rx/dmov.d, * testsuite/gas/rx/dmul.d,
* testsuite/gas/rx/dneg.d, * testsuite/gas/rx/dpopm.d,
* testsuite/gas/rx/dpushm.d, * testsuite/gas/rx/dround.d,
* testsuite/gas/rx/dsqrt.d, * testsuite/gas/rx/dsub.d,
* testsuite/gas/rx/dtoX.d, * testsuite/gas/rx/emaca.d,
* testsuite/gas/rx/emsba.d, * testsuite/gas/rx/emul.d,
* testsuite/gas/rx/emula.d, * testsuite/gas/rx/emulu.d,
* testsuite/gas/rx/fadd.d, * testsuite/gas/rx/fcmp.d,
* testsuite/gas/rx/fdiv.d, * testsuite/gas/rx/fmul.d,
* testsuite/gas/rx/fsqrt.d, * testsuite/gas/rx/fsub.d,
* testsuite/gas/rx/ftoi.d, * testsuite/gas/rx/ftou.d,
* testsuite/gas/rx/gprel.d, * testsuite/gas/rx/int.d,
* testsuite/gas/rx/itof.d, * testsuite/gas/rx/jmp.d,
* testsuite/gas/rx/jsr.d, * testsuite/gas/rx/machi.d,
* testsuite/gas/rx/maclh.d, * testsuite/gas/rx/maclo.d,
* testsuite/gas/rx/max.d, * testsuite/gas/rx/min.d,
* testsuite/gas/rx/mov.d, * testsuite/gas/rx/movco.d,
* testsuite/gas/rx/movli.d, * testsuite/gas/rx/movu.d,
* testsuite/gas/rx/msbhi.d, * testsuite/gas/rx/msblh.d,
* testsuite/gas/rx/msblo.d, * testsuite/gas/rx/mul.d,
* testsuite/gas/rx/mulhi.d, * testsuite/gas/rx/mullh.d,
* testsuite/gas/rx/mullo.d, * testsuite/gas/rx/mvfacgu.d,
* testsuite/gas/rx/mvfachi.d, * testsuite/gas/rx/mvfaclo.d,
* testsuite/gas/rx/mvfacmi.d, * testsuite/gas/rx/mvfc.d,
* testsuite/gas/rx/mvfcp.d, * testsuite/gas/rx/mvfdc.d,
* testsuite/gas/rx/mvfdr.d, * testsuite/gas/rx/mvtacgu.d,
* testsuite/gas/rx/mvtachi.d, * testsuite/gas/rx/mvtaclo.d,
* testsuite/gas/rx/mvtc.d, * testsuite/gas/rx/mvtcp.d,
* testsuite/gas/rx/mvtdc.d, * testsuite/gas/rx/neg.d,
* testsuite/gas/rx/nop.d, * testsuite/gas/rx/not.d,
* testsuite/gas/rx/opecp.d, * testsuite/gas/rx/or.d,
* testsuite/gas/rx/pop.d, * testsuite/gas/rx/popc.d,
* testsuite/gas/rx/popm.d, * testsuite/gas/rx/push.d,
* testsuite/gas/rx/pushc.d, * testsuite/gas/rx/pushm.d,
* testsuite/gas/rx/r-bcc.d, * testsuite/gas/rx/r-bra.d,
* testsuite/gas/rx/racl.d, * testsuite/gas/rx/racw.d,
* testsuite/gas/rx/rdacl.d, * testsuite/gas/rx/rdacw.d,
* testsuite/gas/rx/revl.d, * testsuite/gas/rx/revw.d,
* testsuite/gas/rx/rmpa.d, * testsuite/gas/rx/rolc.d,
* testsuite/gas/rx/rorc.d, * testsuite/gas/rx/rotl.d,
* testsuite/gas/rx/rotr.d, * testsuite/gas/rx/round.d,
* testsuite/gas/rx/rstr.d, * testsuite/gas/rx/rte.d,
* testsuite/gas/rx/rtfi.d, * testsuite/gas/rx/rts.d,
* testsuite/gas/rx/rtsd.d, * testsuite/gas/rx/sat.d,
* testsuite/gas/rx/satr.d, * testsuite/gas/rx/save.d,
* testsuite/gas/rx/sbb.d, * testsuite/gas/rx/sccnd.d,
* testsuite/gas/rx/scmpu.d, * testsuite/gas/rx/setpsw.d,
* testsuite/gas/rx/shar.d, * testsuite/gas/rx/shll.d,
* testsuite/gas/rx/shlr.d, * testsuite/gas/rx/smovb.d,
* testsuite/gas/rx/smovf.d, * testsuite/gas/rx/smovu.d,
* testsuite/gas/rx/sstr.d, * testsuite/gas/rx/stnz.d,
* testsuite/gas/rx/stz.d, * testsuite/gas/rx/sub.d,
* testsuite/gas/rx/suntil.d, * testsuite/gas/rx/swhile.d,
* testsuite/gas/rx/tst.d, * testsuite/gas/rx/utof.d,
* testsuite/gas/rx/wait.d, * testsuite/gas/rx/xchg.d,
* testsuite/gas/rx/xor.d: Add #source line.
[arm][gas] Add -mcpu support for Arm Ares This adds support for the Arm Ares CPU in the arm port. It implements the Armv8.2-A architecture with the relevant optional features of dot product and FP16 on by default. Note: Ares is a codename to enable early adopters and in time we will add the final product name once it's announced. * config/tc-arm.c (arm_cpus): Add ares. * doc/c-arm.texi (-mcpu): Document ares value.
2019-01-07 17:22:55 +08:00
2019-01-07 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/tc-arm.c (arm_cpus): Add ares.
* doc/c-arm.texi (-mcpu): Document ares value.
RX: gas - Add RXv3 instruction support. Instruction manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01us0316ej0100-rxv3sm.pdf * config/rx-defs.h (rx_cpu_types): Add type RXV3 and RXV3FPU. (rx_bfield): Add prototype. (rx_post): Likewise. * config/rx-parse.y: Add v3 instructions and Double FPU registers. (DSIZE): Define. (POST): Define. (rx_check_v3): New. check v3 type. (rx_check_dfpu): New. check have double support. (double_condition_table): New. dcmp<cond> contiditon. (check_condition): Multiple condition support. (rx_lex): RXv3 instructions support. Add parse dcmp<cond> instruction and Double FPU registers. (immediate): Disable optimize in dmov #imm case. (displacement): Add double displacement in dmov instraction. * config/tc-rx.c (rx_use_conventional_section_names): Invert default value in rx-*-linux target. (cpu_type): Add additional ELF flags. (cpu_type_list): Add RXv3. (md_parse_option): Refer elf_flags from cpu_type_list. (md_show_usage): Add rxv3 and rxv3-dfpu. (rx_bytesT): Add post byte. (rx_bfield): New. generate bfmov / bfmovz "imm" field. (rx_post): New. Set instruction post byte. (md_assemble): Add post byte. doc/c-rx.texi: Add cpu types. * testsuite/gas/rx/Xtod.d: New. * testsuite/gas/rx/Xtod.sm: New. * testsuite/gas/rx/bfmov.d: New. * testsuite/gas/rx/bfmov.sm: New. * testsuite/gas/rx/dabs.d: New. * testsuite/gas/rx/dabs.sm: New. * testsuite/gas/rx/dadd.d: New. * testsuite/gas/rx/dadd.sm: New. * testsuite/gas/rx/dcmp.d: New. * testsuite/gas/rx/dcmp.sm: New. * testsuite/gas/rx/ddiv.d: New. * testsuite/gas/rx/ddiv.sm: New. * testsuite/gas/rx/dmov.d: New. * testsuite/gas/rx/dmov.sm: New. * testsuite/gas/rx/dmul.d: New. * testsuite/gas/rx/dmul.sm: New. * testsuite/gas/rx/dneg.d: New. * testsuite/gas/rx/dneg.sm: New. * testsuite/gas/rx/dpopm.d: New. * testsuite/gas/rx/dpopm.sm: New. * testsuite/gas/rx/dpushm.d: New. * testsuite/gas/rx/dpushm.sm: New. * testsuite/gas/rx/dround.d: New. * testsuite/gas/rx/dround.sm: New. * testsuite/gas/rx/dsqrt.d: New. * testsuite/gas/rx/dsqrt.sm: New. * testsuite/gas/rx/dsub.d: New. * testsuite/gas/rx/dsub.sm: New. * testsuite/gas/rx/dtoX.d: New. * testsuite/gas/rx/dtoX.sm: New. * testsuite/gas/rx/macros.inc: Add double FPU registers. * testsuite/gas/rx/mvfdc.d: New. * testsuite/gas/rx/mvfdc.sm: New. * testsuite/gas/rx/mvfdr.d: New. * testsuite/gas/rx/mvfdr.sm: New. * testsuite/gas/rx/mvtdc.d: New. * testsuite/gas/rx/mvtdc.sm: New. * testsuite/gas/rx/rstr.d: New. * testsuite/gas/rx/rstr.sm: New. * testsuite/gas/rx/rx.exp: Use rxv3-dfpu option. * testsuite/gas/rx/save.d: New. * testsuite/gas/rx/save.sm: New. * testsuite/gas/rx/xor.d: New. * testsuite/gas/rx/xor.sm: Add pattern.
2018-12-25 19:52:53 +08:00
2019-01-05 Yoshinori Sato <ysato@users.sourceforge.jp>
* config/rx-defs.h (rx_cpu_types): Add type RXV3 and RXV3FPU.
(rx_bfield): Add prototype.
(rx_post): Likewise.
* config/rx-parse.y: Add v3 instructions and Double FPU registers.
(DSIZE): Define.
(POST): Define.
(rx_check_v3): New. check v3 type.
(rx_check_dfpu): New. check have double support.
(double_condition_table): New. dcmp<cond> contiditon.
(check_condition): Multiple condition support.
(rx_lex): RXv3 instructions support.
Add parse dcmp<cond> instruction and Double FPU registers.
(immediate): Disable optimize in dmov #imm case.
(displacement): Add double displacement in dmov instraction.
* config/tc-rx.c (rx_use_conventional_section_names):
Invert default value in rx-*-linux target.
(cpu_type): Add additional ELF flags.
(cpu_type_list): Add RXv3.
(md_parse_option): Refer elf_flags from cpu_type_list.
(md_show_usage): Add rxv3 and rxv3-dfpu.
(rx_bytesT): Add post byte.
(rx_bfield): New. generate bfmov / bfmovz "imm" field.
(rx_post): New. Set instruction post byte.
(md_assemble): Add post byte.
doc/c-rx.texi: Add cpu types.
* testsuite/gas/rx/Xtod.d: New.
* testsuite/gas/rx/Xtod.sm: New.
* testsuite/gas/rx/bfmov.d: New.
* testsuite/gas/rx/bfmov.sm: New.
* testsuite/gas/rx/dabs.d: New.
* testsuite/gas/rx/dabs.sm: New.
* testsuite/gas/rx/dadd.d: New.
* testsuite/gas/rx/dadd.sm: New.
* testsuite/gas/rx/dcmp.d: New.
* testsuite/gas/rx/dcmp.sm: New.
* testsuite/gas/rx/ddiv.d: New.
* testsuite/gas/rx/ddiv.sm: New.
* testsuite/gas/rx/dmov.d: New.
* testsuite/gas/rx/dmov.sm: New.
* testsuite/gas/rx/dmul.d: New.
* testsuite/gas/rx/dmul.sm: New.
* testsuite/gas/rx/dneg.d: New.
* testsuite/gas/rx/dneg.sm: New.
* testsuite/gas/rx/dpopm.d: New.
* testsuite/gas/rx/dpopm.sm: New.
* testsuite/gas/rx/dpushm.d: New.
* testsuite/gas/rx/dpushm.sm: New.
* testsuite/gas/rx/dround.d: New.
* testsuite/gas/rx/dround.sm: New.
* testsuite/gas/rx/dsqrt.d: New.
* testsuite/gas/rx/dsqrt.sm: New.
* testsuite/gas/rx/dsub.d: New.
* testsuite/gas/rx/dsub.sm: New.
* testsuite/gas/rx/dtoX.d: New.
* testsuite/gas/rx/dtoX.sm: New.
* testsuite/gas/rx/macros.inc: Add double FPU registers.
* testsuite/gas/rx/mvfdc.d: New.
* testsuite/gas/rx/mvfdc.sm: New.
* testsuite/gas/rx/mvfdr.d: New.
* testsuite/gas/rx/mvfdr.sm: New.
* testsuite/gas/rx/mvtdc.d: New.
* testsuite/gas/rx/mvtdc.sm: New.
* testsuite/gas/rx/rstr.d: New.
* testsuite/gas/rx/rstr.sm: New.
* testsuite/gas/rx/rx.exp: Use rxv3-dfpu option.
* testsuite/gas/rx/save.d: New.
* testsuite/gas/rx/save.sm: New.
* testsuite/gas/rx/xor.d: New.
* testsuite/gas/rx/xor.sm: Add pattern.
Fix potential buffer overrun whilst scanning macro strings. PR 24010 * macro.c (get_any_string): Check for end of input whilst scanning for separators.
2019-01-05 00:18:59 +08:00
2019-01-04 Wu Heng <wu.heng@zte.com.cn>
PR 24010
* macro.c (get_any_string): Check for end of input whilst scanning
for separators.
Fix bug parsing angle bracketed string sequences. PR 24009 * read.c (stringer): Fix handling of missing '>' character at end of <...> sequence.
2019-01-04 23:58:02 +08:00
2019-01-04 Wu Heng <wu.heng@zte.com.cn>
PR 24009
* read.c (stringer): Fix handling of missing '>' character at end
of <...> sequence.
Update year range in copyright notice of binutils files
2019-01-01 18:31:27 +08:00
2019-01-01 Alan Modra <amodra@gmail.com>
Update year range in copyright notice of all files.
ChangeLog rotation
2019-01-01 18:53:15 +08:00
For older changes see ChangeLog-2018
New 2016 binutils ChangeLog files Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog and include/*/ChangeLog files.
2016-01-01 18:44:31 +08:00
ChangeLog rotation
2019-01-01 18:53:15 +08:00
Copyright (C) 2019 Free Software Foundation, Inc.
New 2016 binutils ChangeLog files Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog and include/*/ChangeLog files.
2016-01-01 18:44:31 +08:00
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.
Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
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