2017-05-23 02:02:46 +08:00
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2017-05-22 H.J. Lu <hongjiu.lu@intel.com>
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* include/opcode/i386.h (NOTRACK_PREFIX_OPCODE): New.
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binutils: support for the SPARC M8 processor
This patch adds support for the new SPARC M8 processor (implementing OSA
2017) to binutils.
New instructions:
- Dictionary Unpack
+ dictunpack
- Partitioned Compare with shifted result
+ Signed variants: fpcmp{le,gt,eq,ne}{8,16,32}shl
+ Unsigned variants: fpcmpu{le,gt}{8,16,32}shl
- Partitioned Dual-Equal compared, with shifted result
+ fpcmpde{8,16,32}shl
- Partitioned Unsigned Range Compare, with shifted result
+ fpcmpur{8,16,32}shl
- 64-bit shifts on Floating-Point registers
+ fps{ll,ra,rl}64x
- Misaligned loads and stores
+ ldm{sh,uh,sw,uw,x,ux}
+ ldm{sh,uh,sw,uw,x,ux}a
+ ldmf{s,d}
+ ldmf{s,d}a
+ stm{h,w,x}
+ stm{h,w,x}a
+ stmf{s,d}
+ stmf{s,d}a
- Oracle Numbers
+ on{add,sub,mul,div}
- Reverse Bytes/Bits
+ revbitsb
+ revbytes{h,w,x}
- Run-Length instructions
+ rle_burst
+ rle_length
- New crypto instructions
+ sha3
- Instruction to read the new register %entropy
+ rd %entropy
New Alternate Address Identifiers:
- 0x24, #ASI_CORE_COMMIT_COUNT
- 0x24, #ASI_CORE_SELECT_COUNT
- 0x48, #ASI_ARF_ECC_REG
- 0x53, #ASI_ITLB_PROBE
- 0x58, #ASI_DSFAR
- 0x5a, #ASI_DTLB_PROBE_PRIMARY
- 0x5b, #ASI_DTLB_PROBE_REAL
- 0x64, #ASI_CORE_SELECT_COMMIT_NHT
The new assembler command-line options for selecting the M8 architecture
are:
-Av9m8 or -Asparc6 for 64-bit binaries.
-Av8plusm8 for 32-bit (v8+) binaries.
The corresponding disassembler command-line options are:
-msparc:v9m8 for 64-bit binaries.
-msparc:v8plusm8 for 32-bit (v8+) binaries.
Tested for regressions in the following targets:
sparc-aout sparc-linux sparc-vxworks sparc64-linux
bfd/ChangeLog:
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* archures.c (bfd_mach_sparc_v9m8): Define.
(bfd_mach_sparc_v8plusm8): Likewise.
(bfd_mach_sparc_v9_p): Adjust to M8.
(bfd_mach_sparc_64bit_p): Likewise.
* aoutx.h (machine_type): Handle bfd_mach_sparc_v9m8 and
bfd_mach_sparc_v8plusm8.
* bfd-in2.h: Regenerated.
* cpu-sparc.c (arch_info_struct): Entries for sparc:v9m8 and
sparc:v8plusm8.
* elfxx-sparc.c (_bfd_sparc_elf_object_p): Handle
bfd_mach_sparc_v8plusm8 and bfd_mach_sparc_v9m8 using the new hw
capabilities ONADDSUB, ONMUL, ONDIV, DICTUNP, FPCPSHL, RLE and
SHA3.
* elf32-sparc.c (elf32_sparc_final_write_processing): Handle
bfd_mach_sparc_v8plusm8.
binutils/ChangeLog:
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* NEWS: Mention the SPARC M8 support.
gas/ChangeLog:
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_arch_table): Entries for `sparc6',
`v9m8' and `v8plusm8'.
(sparc_md_end): Handle SPARC_OPCODE_ARCH_M8.
(get_hwcap_name): Support the M8 hardware capabilities.
(sparc_ip): Handle new operand types.
* doc/c-sparc.texi (Sparc-Opts): Document -Av9m8, -Av8plusm8 and
-Asparc6, and the corresponding -xarch aliases.
* testsuite/gas/sparc/sparc6.s: New file.
* testsuite/gas/sparc/sparc6.d: Likewise.
* testsuite/gas/sparc/sparc6-diag.s: Likewise.
* testsuite/gas/sparc/sparc6-diag.l: Likewise.
* testsuite/gas/sparc/fpcmpshl.s: Likewise.
* testsuite/gas/sparc/fpcmpshl.d: Likewise.
* testsuite/gas/sparc/fpcmpshl-diag.s: Likewise.
* testsuite/gas/sparc/fpcmpshl-diag.l: Likewise.
* testsuite/gas/sparc/ldm-stm.s: Likewise.
* testsuite/gas/sparc/ldm-stm.d: Likewise.
* testsuite/gas/sparc/ldm-stm-diag.s: Likewise.
* testsuite/gas/sparc/ldm-stm-diag.l: Likewise.
* testsuite/gas/sparc/ldmf-stmf.s: Likewise.
* testsuite/gas/sparc/ldmf-stmf.d: Likewise.
* testsuite/gas/sparc/ldmf-stmf-diag.s: Likewise.
* testsuite/gas/sparc/ldmf-stmf-diag.l: Likewise.
* testsuite/gas/sparc/on.s: Likewise.
* testsuite/gas/sparc/on.d: Likewise.
* testsuite/gas/sparc/on-diag.s: Likewise.
* testsuite/gas/sparc/on-diag.l: Likewise.
* testsuite/gas/sparc/rle.s: Likewise.
* testsuite/gas/sparc/rle.d: Likewise.
* testsuite/gas/sparc/sparc.exp (gas_64_check): Run new tests.
* testsuite/gas/sparc/rdasr.s: Add test for RDENTROPY.
* testsuite/gas/sparc/rdasr.d: Likewise.
include/ChangeLog:
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* elf/sparc.h (ELF_SPARC_HWCAP2_SPARC6): Define.
(ELF_SPARC_HWCAP2_ONADDSUB): Likewise.
(ELF_SPARC_HWCAP2_ONMUL): Likewise.
(ELF_SPARC_HWCAP2_ONDIV): Likewise.
(ELF_SPARC_HWCAP2_DICTUNP): Likewise.
(ELF_SPARC_HWCAP2_FPCMPSHL): Likewise.
(ELF_SPARC_HWCAP2_RLE): Likewise.
(ELF_SPARC_HWCAP2_SHA3): Likewise.
* opcode/sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_M8
and adjust SPARC_OPCODE_ARCH_MAX.
(HWCAP2_SPARC6): Define.
(HWCAP2_ONADDSUB): Likewise.
(HWCAP2_ONMUL): Likewise.
(HWCAP2_ONDIV): Likewise.
(HWCAP2_DICTUNP): Likewise.
(HWCAP2_FPCMPSHL): Likewise.
(HWCAP2_RLE): Likewise.
(HWCAP2_SHA3): Likewise.
(OPM): Likewise.
(OPMI): Likewise.
(ONFCN): Likewise.
(REVFCN): Likewise.
(SIMM10): Likewise.
opcodes/ChangeLog:
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
(X_IMM2): Define.
(compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
bfd_mach_sparc_v9m8.
(print_insn_sparc): Handle new operand types.
* sparc-opc.c (MASK_M8): Define.
(v6): Add MASK_M8.
(v6notlet): Likewise.
(v7): Likewise.
(v8): Likewise.
(v9): Likewise.
(v9a): Likewise.
(v9b): Likewise.
(v9c): Likewise.
(v9d): Likewise.
(v9e): Likewise.
(v9v): Likewise.
(v9m): Likewise.
(v9andleon): Likewise.
(m8): Define.
(HWS_VM8): Define.
(HWS2_VM8): Likewise.
(sparc_opcode_archs): Add entry for "m8".
(sparc_opcodes): Add OSA2017 and M8 instructions
dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
fpx{ll,ra,rl}64x,
ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
(asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
ASI_CORE_SELECT_COMMIT_NHT.
2017-05-20 00:27:08 +08:00
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2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
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* elf/sparc.h (ELF_SPARC_HWCAP2_SPARC6): Define.
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(ELF_SPARC_HWCAP2_ONADDSUB): Likewise.
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(ELF_SPARC_HWCAP2_ONMUL): Likewise.
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(ELF_SPARC_HWCAP2_ONDIV): Likewise.
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(ELF_SPARC_HWCAP2_DICTUNP): Likewise.
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(ELF_SPARC_HWCAP2_FPCMPSHL): Likewise.
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(ELF_SPARC_HWCAP2_RLE): Likewise.
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(ELF_SPARC_HWCAP2_SHA3): Likewise.
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* opcode/sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_M8
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and adjust SPARC_OPCODE_ARCH_MAX.
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(HWCAP2_SPARC6): Define.
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(HWCAP2_ONADDSUB): Likewise.
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(HWCAP2_ONMUL): Likewise.
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(HWCAP2_ONDIV): Likewise.
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(HWCAP2_DICTUNP): Likewise.
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(HWCAP2_FPCMPSHL): Likewise.
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(HWCAP2_RLE): Likewise.
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(HWCAP2_SHA3): Likewise.
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(OPM): Likewise.
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(OPMI): Likewise.
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(ONFCN): Likewise.
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(REVFCN): Likewise.
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(SIMM10): Likewise.
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2017-05-16 06:28:14 +08:00
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2017-05-16 Alan Modra <amodra@gmail.com>
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* bfdlink.h (struct bfd_link_hash_entry <non_ir_ref>): Rename to
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non_ir_ref_regular.
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2017-05-16 06:26:41 +08:00
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2017-05-16 Alan Modra <amodra@gmail.com>
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* bfdlink.h (struct bfd_link_hash_entry): Update non_ir_ref
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comment. Rename dynamic_ref_after_ir_def to non_ir_ref_dynamic.
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MIPS16e2: Add MIPS16e2 ASE support
Add MIPS16e2 ASE support as per the architecture specification[1],
including in particular:
1. A new ELF ASE flag to mark MIPS16e2 binaries.
2. MIPS16e2 instruction assembly support, including a relaxation update
to use LUI rather than an LI/SLL instruction pair for loading the
high part of 32-bit addresses.
3. MIPS16e2 instruction disassembly support, including updated rules for
extended forms of instructions that are now subdecoded and therefore
do not alias to the original MIPS16 ISA revision instructions even
for encodings that are not valid in the MIPS16e2 instruction set.
Add `-mmips16e2' and `-mno-mips16e2' GAS command-line options and their
corresponding `mips16e2' and `no-mips16e2' settings for the `.set' and
`.module' pseudo-ops. Control the availability of the MT ASE subset of
the MIPS16e2 instruction set with a combination of these controls and
the preexisting MT ASE controls.
Parts of this change by Matthew Fortune and Andrew Bennett.
References:
[1] "MIPS32 Architecture for Programmers: MIPS16e2 Application-Specific
Extension Technical Reference Manual", Imagination Technologies
Ltd., Document Number: MD01172, Revision 01.00, April 26, 2016
include/
* elf/mips.h (AFL_ASE_MIPS16E2): New macro.
(AFL_ASE_MASK): Adjust accordingly.
* opcode/mips.h: Document new operand codes defined.
(mips_operand_type): Add OP_REG28 enum value.
(INSN2_SHORT_ONLY): Update description.
(ASE_MIPS16E2, ASE_MIPS16E2_MT): New macros.
bfd/
* elfxx-mips.c (print_mips_ases): Handle MIPS16e2 ASE.
opcodes/
* mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
(mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
(print_insn_arg) <OP_REG28>: Add handler.
(validate_insn_args) <OP_REG28>: Handle.
(print_mips16_insn_arg): Handle MIPS16 instructions that require
32-bit encoding and 9-bit immediates.
(print_insn_mips16): Handle MIPS16 instructions that require
32-bit encoding and MFC0/MTC0 operand decoding.
* mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
<'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
(RD_C0, WR_C0, E2, E2MT): New macros.
(mips16_opcodes): Add entries for MIPS16e2 instructions:
GP-relative "addiu" and its "addu" spelling, "andi", "cache",
"di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
"lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
"movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
"pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
instructions, "swl", "swr", "sync" and its "sync_acquire",
"sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
"xori", "dmt", "dvpe", "emt" and "evpe". Add split
regular/extended entries for original MIPS16 ISA revision
instructions whose extended forms are subdecoded in the MIPS16e2
ISA revision: "li", "sll" and "srl".
binutils/
* readelf.c (print_mips_ases): Handle MIPS16e2 ASE.
* NEWS: Mention MIPS16e2 ASE support.
gas/
* config/tc-mips.c (RELAX_MIPS16_ENCODE): Add `e2' flag.
(RELAX_MIPS16_E2): New macro.
(RELAX_MIPS16_PIC, RELAX_MIPS16_SYM32, RELAX_MIPS16_NOMACRO)
(RELAX_MIPS16_USER_SMALL, RELAX_MIPS16_USER_EXT)
(RELAX_MIPS16_DSLOT, RELAX_MIPS16_JAL_DSLOT)
(RELAX_MIPS16_EXTENDED, RELAX_MIPS16_MARK_EXTENDED)
(RELAX_MIPS16_CLEAR_EXTENDED, RELAX_MIPS16_ALWAYS_EXTENDED)
(RELAX_MIPS16_MARK_ALWAYS_EXTENDED)
(RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED, RELAX_MIPS16_MACRO)
(RELAX_MIPS16_MARK_MACRO, RELAX_MIPS16_CLEAR_MACRO): Shift bits.
(mips16_immed_extend): New prototype.
(options): Add OPTION_MIPS16E2 and OPTION_NO_MIPS16E2 enum
values.
(md_longopts): Add "mmips16e2" and "mno-mips16e2" options.
(mips_ases): Add "mips16e2" entry.
(mips_set_ase): Handle MIPS16e2 ASE.
(insn_insert_operand): Explicitly handle immediates with MIPS16
instructions that require 32-bit encoding.
(is_opcode_valid_16): Pass enabled ASE bitmask on to
`opcode_is_member'.
(validate_mips_insn): Explicitly handle immediates with MIPS16
instructions that require 32-bit encoding.
(operand_reg_mask) <OP_REG28>: Add handler.
(match_reg28_operand): New function.
(match_operand) <OP_REG28>: Add handler.
(append_insn): Pass ASE_MIPS16E2 setting to RELAX_MIPS16_ENCODE.
(match_mips16_insn): Handle MIPS16 instructions that require
32-bit encoding and `V' and `u' operand codes.
(mips16_ip): Allow any characters except from `.' in opcodes.
(mips16_immed_extend): Handle 9-bit immediates. Do not shuffle
immediates whose width is not one of these listed.
(md_estimate_size_before_relax): Handle MIPS16e2 relaxation.
(mips_relax_frag): Likewise.
(md_convert_frag): Likewise.
(mips_convert_ase_flags): Handle MIPS16e2 ASE.
* doc/as.texinfo (Target MIPS options): Add `-mmips16e2' and
`-mno-mips16e2' options.
(-mmips16e2, -mno-mips16e2): New options.
* doc/c-mips.texi (MIPS Options): Add `-mmips16e2' and
`-mno-mips16e2' options.
(MIPS ASE Instruction Generation Overrides): Add `.set mips16e2'
and `.set nomips16e2'.
2017-05-15 20:26:01 +08:00
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2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
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Matthew Fortune <matthew.fortune@imgtec.com>
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* elf/mips.h (AFL_ASE_MIPS16E2): New macro.
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(AFL_ASE_MASK): Adjust accordingly.
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* opcode/mips.h: Document new operand codes defined.
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(mips_operand_type): Add OP_REG28 enum value.
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(INSN2_SHORT_ONLY): Update description.
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(ASE_MIPS16E2, ASE_MIPS16E2_MT): New macros.
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2017-05-15 04:06:06 +08:00
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2017-05-14 John David Anglin <danglin@gcc.gnu.org>
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* opcode/hppa.h: Fix match and mask for 64-bit bb opcode.
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[ARC] Object attributes.
gas/
2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/attr-arc600.d: New file.
* testsuite/gas/arc/attr-arc600_mul32x16.d: Likewise.
* testsuite/gas/arc/attr-arc600_norm.d: Likewise.
* testsuite/gas/arc/attr-arc601.d: Likewise.
* testsuite/gas/arc/attr-arc601_mul32x16.d: Likewise.
* testsuite/gas/arc/attr-arc601_mul64.d: Likewise.
* testsuite/gas/arc/attr-arc601_norm.d: Likewise.
* testsuite/gas/arc/attr-arc700.d: Likewise.
* testsuite/gas/arc/attr-arcem.d: Likewise.
* testsuite/gas/arc/attr-archs.d: Likewise.
* testsuite/gas/arc/attr-autodetect-1.d: Likewise.
* testsuite/gas/arc/attr-autodetect-1.s: Likewise.
* testsuite/gas/arc/attr-cpu-a601.d: Likewise.
* testsuite/gas/arc/attr-cpu-a601.s: Likewise.
* testsuite/gas/arc/attr-cpu-a700.d: Likewise.
* testsuite/gas/arc/attr-cpu-a700.s: Likewise.
* testsuite/gas/arc/attr-cpu-em.d: Likewise.
* testsuite/gas/arc/attr-cpu-em.s: Likewise.
* testsuite/gas/arc/attr-cpu-hs.d: Likewise.
* testsuite/gas/arc/attr-cpu-hs.s: Likewise.
* testsuite/gas/arc/attr-em.d: Likewise.
* testsuite/gas/arc/attr-em4.d: Likewise.
* testsuite/gas/arc/attr-em4_dmips.d: Likewise.
* testsuite/gas/arc/attr-em4_fpuda.d: Likewise.
* testsuite/gas/arc/attr-em4_fpus.d: Likewise.
* testsuite/gas/arc/attr-hs.d: Likewise.
* testsuite/gas/arc/attr-hs34.d: Likewise.
* testsuite/gas/arc/attr-hs38.d: Likewise.
* testsuite/gas/arc/attr-hs38_linux.d: Likewise.
* testsuite/gas/arc/attr-mul64.d: Likewise.
* testsuite/gas/arc/attr-name.d: Likewise.
* testsuite/gas/arc/attr-name.s: Likewise.
* testsuite/gas/arc/attr-nps400.d: Likewise.
* testsuite/gas/arc/attr-override-mcpu.d: Likewise.
* testsuite/gas/arc/attr-override-mcpu.s
* testsuite/gas/arc/attr-quarkse_em.d: Likewise.
* testsuite/gas/arc/blank.s: Likewise.
* testsuite/gas/elf/section2.e-arc: Likewise.
* testsuite/gas/arc/cpu-pseudop-1.d: Update test.
* testsuite/gas/arc/cpu-pseudop-2.d: Likewise.
* testsuite/gas/arc/nps400-0.d: Likewise.
* testsuite/gas/elf/elf.exp: Set target_machine for ARC.
* config/tc-arc.c (opcode/arc-attrs.h): Include.
(ARC_GET_FLAG, ARC_SET_FLAG, streq): Define.
(arc_attribute): Declare new function.
(md_pseudo_table): Add arc_attribute.
(cpu_types): Rename default cpu features.
(selected_cpu): Set the default OSABI flag.
(mpy_option): New variable.
(pic_option): Likewise.
(sda_option): Likewise.
(tls_option): Likewise.
(feature_type, feature_list): Remove.
(arc_initial_eflag): Likewise.
(attributes_set_explicitly): New variable.
(arc_check_feature): Check also for the conflicting features.
(arc_select_cpu): Refactor assignment of selected_cpu.eflags.
(arc_option): Remove setting of private flags and architecture.
(check_cpu_feature): Refactor feature names.
(autodetect_attributes): New function.
(assemble_tokens): Use above function.
(md_parse_option): Refactor feature names.
(arc_attribute): New function.
(arc_set_attribute_int): Likewise.
(arc_set_attribute_string): Likewise.
(arc_stralloc): Likewise.
(arc_set_public_attributes): Likewise.
(arc_md_end): Likewise.
(arc_copy_symbol_attributes): Likewise.
(rc_convert_symbolic_attribute): Likewise.
* config/tc-arc.h (md_end): Define.
(CONVERT_SYMBOLIC_ATTRIBUTE): Likewise.
(TC_COPY_SYMBOL_ATTRIBUTES): Likewise.
* doc/c-arc.texi: Document ARC object attributes.
binutils/
2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
* readelf.c (decode_ARC_machine_flags): Recognize OSABI v4.
(get_arc_section_type_name): New function.
(get_section_type_name): Use the above function.
(display_arc_attribute): New function.
(process_arc_specific): Likewise.
(process_arch_specific): Handle ARC specific information.
* testsuite/binutils-all/strip-3.d: Consider ARC.attributes
section.
include/
2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
* elf/arc.h (SHT_ARC_ATTRIBUTES): Define.
(Tag_ARC_*): Define.
(E_ARC_OSABI_V4): Define.
(E_ARC_OSABI_CURRENT): Reassign it.
(TAG_CPU_*): Define.
* opcode/arc-attrs.h: New file.
* opcode/arc.h (insn_subclass_t): Assign enum values.
(insn_subclass_t): Update enum with QUARKSE1, QUARKSE2, and LL64.
(ARC_EA, ARC_CD, ARC_LLOCK, ARC_ATOMIC, ARC_MPY, ARC_MULT)
(ARC_NPS400, ARC_DPFP, ARC_SPFP, ARC_FPU, ARC_FPUDA, ARC_SWAP)
(ARC_NORM, ARC_BSCAN, ARC_UIX, ARC_TSTAMP, ARC_VBFDW)
(ARC_BARREL, ARC_DSPA, ARC_SHIFT, ARC_INTR, ARC_DIV, ARC_XMAC)
(ARC_CRC): Delete.
bfd/
2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
* elf32-arc.c (FEATURE_LIST_NAME): Define.
(CONFLICT_LIST): Likewise.
(opcode/arc-attrs.h): Include.
(arc_elf_print_private_bfd_data): Print OSABI v4 flag.
(arc_extract_features): New file.
(arc_stralloc): Likewise.
(arc_elf_merge_attributes): Likewise.
(arc_elf_merge_private_bfd_data): Use object attributes.
(bfd_arc_get_mach_from_attributes): New function.
(arc_elf_object_p): Use object attributes.
(arc_elf_final_write_processing): Likewise.
(elf32_arc_obj_attrs_arg_type): New function.
(elf32_arc_obj_attrs_handle_unknown): Likewise.
(elf32_arc_section_from_shdr): Likewise.
(elf_backend_obj_attrs_vendor): Define.
(elf_backend_obj_attrs_section): Likewise.
(elf_backend_obj_attrs_arg_type): Likewise.
(elf_backend_obj_attrs_section_type): Likewise.
(elf_backend_obj_attrs_handle_unknown): Likewise.
(elf_backend_section_from_shdr): Likewise.
ld/
2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/ld-arc/attr-merge-0.d: New file.
* testsuite/ld-arc/attr-merge-0.s: Likewise.
* testsuite/ld-arc/attr-merge-0e.s: Likewise.
* testsuite/ld-arc/attr-merge-1.d: Likewise.
* testsuite/ld-arc/attr-merge-1.s: Likewise.
* testsuite/ld-arc/attr-merge-1e.s: Likewise.
* testsuite/ld-arc/attr-merge-2.d: Likewise.
* testsuite/ld-arc/attr-merge-2.s: Likewise.
* testsuite/ld-arc/attr-merge-3.d: Likewise.
* testsuite/ld-arc/attr-merge-3.s: Likewise.
* testsuite/ld-arc/attr-merge-3e.s: Likewise.
* testsuite/ld-arc/attr-merge-4.s: Likewise.
* testsuite/ld-arc/attr-merge-5.d: Likewise.
* testsuite/ld-arc/attr-merge-5a.s: Likewise.
* testsuite/ld-arc/attr-merge-5b.s: Likewise.
* testsuite/ld-arc/attr-merge-conflict-isa.d: Likewise.
* testsuite/ld-arc/attr-merge-err-isa.d: Likewise.
* testsuite/ld-arc/attr-merge-incompatible-cpu.d: Likewise.
* testsuite/ld-arc/got-01.d: Update test.
* testsuite/ld-arc/attr-merge-err-quarkse.d: New file.
* testsuite/ld-arc/attr-quarkse.s: Likewise.
* testsuite/ld-arc/attr-quarkse2.s: Likewise.
opcodes/
2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
* arc-dis.c (parse_option): Update quarkse_em option..
* arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
QUARKSE1.
(dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
2017-05-10 20:42:22 +08:00
|
|
|
|
2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
|
|
|
|
|
|
|
|
|
|
|
|
* elf/arc.h (SHT_ARC_ATTRIBUTES): Define.
|
|
|
|
|
|
(Tag_ARC_*): Define.
|
|
|
|
|
|
(E_ARC_OSABI_V4): Define.
|
|
|
|
|
|
(E_ARC_OSABI_CURRENT): Reassign it.
|
|
|
|
|
|
(TAG_CPU_*): Define.
|
|
|
|
|
|
* opcode/arc-attrs.h: New file.
|
|
|
|
|
|
* opcode/arc.h (insn_subclass_t): Assign enum values.
|
|
|
|
|
|
(insn_subclass_t): Update enum with QUARKSE1, QUARKSE2, and LL64.
|
|
|
|
|
|
(ARC_EA, ARC_CD, ARC_LLOCK, ARC_ATOMIC, ARC_MPY, ARC_MULT)
|
|
|
|
|
|
(ARC_NPS400, ARC_DPFP, ARC_SPFP, ARC_FPU, ARC_FPUDA, ARC_SWAP)
|
|
|
|
|
|
(ARC_NORM, ARC_BSCAN, ARC_UIX, ARC_TSTAMP, ARC_VBFDW)
|
|
|
|
|
|
(ARC_BARREL, ARC_DSPA, ARC_SHIFT, ARC_INTR, ARC_DIV, ARC_XMAC)
|
|
|
|
|
|
(ARC_CRC): Delete.
|
|
|
|
|
|
|
2017-04-20 22:48:24 +08:00
|
|
|
|
2017-04-20 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR ld/21382
|
|
|
|
|
|
* bfdlink.h (bfd_link_hash_entry): Add dynamic_ref_after_ir_def.
|
|
|
|
|
|
|
2017-04-18 23:56:57 +08:00
|
|
|
|
2017-04-19 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* bfdlink.h (struct bfd_link_info <dynamic_undefined_weak>):
|
|
|
|
|
|
Revise comment.
|
|
|
|
|
|
|
2017-04-11 06:03:50 +08:00
|
|
|
|
2017-04-11 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/ppc.h (PPC_OPCODE_ALTIVEC2): Delete.
|
2017-04-11 06:06:43 +08:00
|
|
|
|
(PPC_OPCODE_VSX3): Delete.
|
2017-04-11 06:10:24 +08:00
|
|
|
|
(PPC_OPCODE_HTM): Delete.
|
2017-04-11 06:13:21 +08:00
|
|
|
|
(PPC_OPCODE_*): Renumber and order chronologically.
|
|
|
|
|
|
(PPC_OPCODE_SPE): Comment on this and other bits used for APUinfo.
|
2017-04-11 06:03:50 +08:00
|
|
|
|
|
2017-04-07 00:17:15 +08:00
|
|
|
|
2017-04-06 Pip Cet <pipcet@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* dis-asm.h: Add prototypes for wasm32 disassembler.
|
|
|
|
|
|
|
2017-04-06 02:21:33 +08:00
|
|
|
|
2017-04-05 Pedro Alves <palves@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* dis-asm.h (disassemble_info) <disassembler_options>: Now a
|
|
|
|
|
|
"const char *".
|
|
|
|
|
|
(next_disassembler_option): Constify.
|
|
|
|
|
|
|
Support ELF SHF_GNU_MBIND and PT_GNU_MBIND_XXX
Mark an ALLOC section, which should be placed in special memory area,
with SHF_GNU_MBIND. Its sh_info field indicates the special memory
type. GNU_MBIND section names start with ".mbind" so that they are
placed as orphan sections by linker. All input GNU_MBIND sections
with the same sh_type, sh_flags and sh_info are placed in one output
GNU_MBIND section. In executable and shared object, create a
GNU_MBIND segment for each GNU_MBIND section and its segment type is
PT_GNU_MBIND_LO plus the sh_info value. Each GNU_MBIND segment is
aligned at page boundary.
The assembler syntax:
.section .mbind.foo,"adx",%progbits
^ 0: Special memory type.
|
'd' for SHF_GNU_MBIND.
.section .mbind.foo,"adx",%progbits,0x1
^ 1: Special memory type.
|
'd' for SHF_GNU_MBIND.
.section .mbind.bar,"adG",%progbits,.foo_group,comdat,0x2
^ 2: Special memory type.
|
'd' for SHF_GNU_MBIND.
bfd/
* elf.c (get_program_header_size): Add a GNU_MBIND segment for
each GNU_MBIND section and align GNU_MBIND section to page size.
(_bfd_elf_map_sections_to_segments): Create a GNU_MBIND
segment for each GNU_MBIND section.
(_bfd_elf_init_private_section_data): Copy sh_info from input
for GNU_MBIND section.
binutils/
* NEWS: Mention support for ELF SHF_GNU_MBIND and
PT_GNU_MBIND_XXX.
* readelf.c (get_segment_type): Handle PT_GNU_MBIND_XXX.
(get_elf_section_flags): Handle SHF_GNU_MBIND.
(process_section_headers): Likewise.
* testsuite/binutils-all/mbind1.s: New file.
* testsuite/binutils-all/objcopy.exp: Run readelf test on
mbind1.s.
gas/
* NEWS: Mention support for ELF SHF_GNU_MBIND.
* config/obj-elf.c (section_match): New.
(get_section): Match both sh_info and group name.
(obj_elf_change_section): Add argument for sh_info. Pass both
sh_info and group name to get_section. Issue an error for
SHF_GNU_MBIND section without SHF_ALLOC. Set sh_info.
(obj_elf_parse_section_letters): Set SHF_GNU_MBIND for 'd'.
(obj_elf_section): Support SHF_GNU_MBIND section info.
* config/obj-elf.h (obj_elf_change_section): Add argument for
sh_info.
* config/tc-arm.c (start_unwind_section): Pass 0 as sh_info to
obj_elf_change_section.
* config/tc-ia64.c (obj_elf_vms_common): Likewise.
* config/tc-microblaze.c (microblaze_s_data): Likewise.
(microblaze_s_sdata): Likewise.
(microblaze_s_rdata): Likewise.
(microblaze_s_bss): Likewise.
* config/tc-mips.c (s_change_section): Likewise.
* config/tc-msp430.c (msp430_profiler): Likewise.
* config/tc-rx.c (parse_rx_section): Likewise.
* config/tc-tic6x.c (tic6x_start_unwind_section): Likewise.
* doc/as.texinfo: Document 'd' for SHF_GNU_MBIND.
* testsuite/gas/elf/elf.exp: Run section12a, section12b and
section13.
* testsuite/gas/elf/section10.d: Updated.
* testsuite/gas/elf/section10.s: Likewise.
* testsuite/gas/elf/section12.s: New file.
* testsuite/gas/elf/section12a.d: Likewise.
* testsuite/gas/elf/section12b.d: Likewise.
* testsuite/gas/elf/section13.l: Likewise.
* testsuite/gas/elf/section13.d: Likewise.
* testsuite/gas/elf/section13.s: Likewise.
include/
* elf/common.h (PT_GNU_MBIND_NUM): New.
(PT_GNU_MBIND_LO): Likewise.
(PT_GNU_MBIND_HI): Likewise.
(SHF_GNU_MBIND): Likewise.
ld/
* NEWS: Mention support for ELF SHF_GNU_MBIND and
PT_GNU_MBIND_XXX.
* emultempl/elf32.em (gld${EMULATION_NAME}_place_orphan): Place
input GNU_MBIND sections with the same type, attributes and
sh_info field into a single output GNU_MBIND section.
* testsuite/ld-elf/elf.exp: Run mbind2a and mbind2b.
* testsuite/ld-elf/mbind1.s: New file.
* testsuite/ld-elf/mbind1a.d: Likewise.
* testsuite/ld-elf/mbind1b.d: Likewise.
* testsuite/ld-elf/mbind1c.d: Likewise.
* testsuite/ld-elf/mbind2a.s: Likewise.
* testsuite/ld-elf/mbind2b.c: Likewise.
2017-04-05 00:05:48 +08:00
|
|
|
|
2017-04-04 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* elf/common.h (PT_GNU_MBIND_NUM): New.
|
|
|
|
|
|
(PT_GNU_MBIND_LO): Likewise.
|
|
|
|
|
|
(PT_GNU_MBIND_HI): Likewise.
|
|
|
|
|
|
(SHF_GNU_MBIND): Likewise.
|
|
|
|
|
|
|
2017-04-04 01:08:29 +08:00
|
|
|
|
2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
|
|
|
|
|
|
|
|
|
|
|
|
* elf/riscv.h (RISCV_GP_SYMBOL): New define.
|
|
|
|
|
|
|
2017-03-22 17:09:56 +08:00
|
|
|
|
2017-03-27 Andrew Waterman <andrew@sifive.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/riscv-opc.h (CSR_PMPCFG0): New define.
|
|
|
|
|
|
(CSR_PMPCFG1): Likewise.
|
|
|
|
|
|
(CSR_PMPCFG2): Likewise.
|
|
|
|
|
|
(CSR_PMPCFG3): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR0): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR1): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR2): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR3): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR4): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR5): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR6): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR7): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR8): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR9): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR10): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR11): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR12): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR13): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR14): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR15): Likewise.
|
|
|
|
|
|
(pmpcfg0): Declare register.
|
|
|
|
|
|
(pmpcfg1): Likewise.
|
|
|
|
|
|
(pmpcfg2): Likewise.
|
|
|
|
|
|
(pmpcfg3): Likewise.
|
|
|
|
|
|
(pmpaddr0): Likewise.
|
|
|
|
|
|
(pmpaddr1): Likewise.
|
|
|
|
|
|
(pmpaddr2): Likewise.
|
|
|
|
|
|
(pmpaddr3): Likewise.
|
|
|
|
|
|
(pmpaddr4): Likewise.
|
|
|
|
|
|
(pmpaddr5): Likewise.
|
|
|
|
|
|
(pmpaddr6): Likewise.
|
|
|
|
|
|
(pmpaddr7): Likewise.
|
|
|
|
|
|
(pmpaddr8): Likewise.
|
|
|
|
|
|
(pmpaddr9): Likewise.
|
|
|
|
|
|
(pmpaddr10): Likewise.
|
|
|
|
|
|
(pmpaddr11): Likewise.
|
|
|
|
|
|
(pmpaddr12): Likewise.
|
|
|
|
|
|
(pmpaddr13): Likewise.
|
|
|
|
|
|
(pmpaddr14): Likewise.
|
|
|
|
|
|
(pmpaddr15): Likewise.
|
|
|
|
|
|
|
2017-03-30 17:57:21 +08:00
|
|
|
|
2017-03-30 Pip Cet <pipcet@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/wasm.h: New file to support wasm32 architecture.
|
|
|
|
|
|
* elf/wasm32.h: Add R_WASM32_32 relocation.
|
|
|
|
|
|
|
2017-03-29 11:13:06 +08:00
|
|
|
|
2017-03-29 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/ppc.h (PPC_OPCODE_RAW): Define.
|
|
|
|
|
|
(PPC_OPCODE_*): Make them all unsigned long long constants.
|
|
|
|
|
|
|
2017-03-27 18:39:50 +08:00
|
|
|
|
2017-03-27 Pip Cet <pipcet@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* elf/wasm32.h: New file to support wasm32 architecture.
|
|
|
|
|
|
|
Implement ARC NPS-400 Ultra Ip and Miscellaneous instructions.
opcodes * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
* arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR, F_NPS_M, F_NPS_CORE, F_NPS_ALL.
(insert_nps_misc_imm_offset): New function.
(extract_nps_misc imm_offset): New function.
(arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
(arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
include * opcode/arc.h (insn_class_t): Add ULTRAIP and MISC class.
gas * testsuite/gas/arc/nps400-12.s: New file.
* testsuite/gas/arc/nps400-12.d: New file.
2017-03-27 18:14:30 +08:00
|
|
|
|
2017-03-27 Rinat Zelig <rinat@mellanox.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/arc.h (insn_class_t): Add ULTRAIP and MISC class.
|
|
|
|
|
|
|
2017-03-21 21:21:02 +08:00
|
|
|
|
2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/s390.h (S390_INSTR_FLAG_VX2): Remove.
|
|
|
|
|
|
(S390_INSTR_FLAG_FACILITY_MASK): Adjust value.
|
|
|
|
|
|
|
2017-03-21 19:37:33 +08:00
|
|
|
|
2017-03-21 Rinat Zelig <rinat@mellanox.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/arc.h (insn_class_t): Add DMA class.
|
|
|
|
|
|
|
2017-03-17 00:44:55 +08:00
|
|
|
|
2017-03-16 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* elf/common.h (GNU_BUILD_ATTRIBUTE_SHORT_ENUM): New GNU BUILD
|
|
|
|
|
|
note type.
|
|
|
|
|
|
|
2017-03-15 03:56:49 +08:00
|
|
|
|
2017-03-14 Jakub Jelinek <jakub@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR debug/77589
|
|
|
|
|
|
* dwarf2.def (DW_OP_GNU_variable_value): New opcode.
|
|
|
|
|
|
|
2017-03-14 01:49:32 +08:00
|
|
|
|
2017-03-13 Markus Trippelsdorf <markus@trippelsdorf.de>
|
|
|
|
|
|
|
|
|
|
|
|
PR demangler/70909
|
|
|
|
|
|
PR demangler/67264
|
|
|
|
|
|
* demangle.h (struct demangle_component): Add d_printing field.
|
|
|
|
|
|
(cplus_demangle_print): Remove const qualifier from tree
|
|
|
|
|
|
parameter.
|
|
|
|
|
|
(cplus_demangle_print_callback): Likewise.
|
|
|
|
|
|
|
2017-03-13 17:58:04 +08:00
|
|
|
|
2017-03-13 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/21202
|
|
|
|
|
|
* elf/aarch64.h (R_AARCH64_TLSDESC_LD64_LO12_NC): Rename to
|
|
|
|
|
|
R_AARCH64_TLSDESC_LD64_LO12.
|
|
|
|
|
|
(R_AARCH64_TLSDESC_ADD_LO12_NC): Rename to
|
|
|
|
|
|
R_AARCH64_TLSDESC_ADD_LO12_NC.
|
|
|
|
|
|
|
2017-03-10 18:50:34 +08:00
|
|
|
|
2017-03-10 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* elf/common.h (EM_LANAI): New machine number.
|
|
|
|
|
|
(EM_BPF): Likewise.
|
|
|
|
|
|
(EM_WEBASSEMBLY): Likewise.
|
|
|
|
|
|
Move low value, deprecated, numbers to their numerical
|
|
|
|
|
|
equivalents.
|
|
|
|
|
|
|
2017-03-08 23:44:04 +08:00
|
|
|
|
2017-03-08 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/21231
|
|
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|
|
* elf/common.h (GNU_PROPERTY_LOPROC): New.
|
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|
|
(GNU_PROPERTY_HIPROC): Likewise.
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(GNU_PROPERTY_LOUSER): Likewise.
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(GNU_PROPERTY_HIUSER): Likewise.
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2017-03-01 19:09:46 +08:00
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|
|
2017-03-01 Nick Clifton <nickc@redhat.com>
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|
|
* elf/common.h (SHF_GNU_BUILD_NOTE): Define.
|
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|
|
(NT_GNU_PROPERTY_TYPE_0): Define.
|
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|
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(NT_GNU_BUILD_ATTRIBUTE_OPEN): Define.
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(NT_GNU_BUILD_ATTRIBUTE_FUN): Define.
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(GNU_BUILD_ATTRIBUTE_TYPE_NUMERIC): Define.
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|
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(GNU_BUILD_ATTRIBUTE_TYPE_STRING): Define.
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|
|
(GNU_BUILD_ATTRIBUTE_TYPE_BOOL_TRUE): Define.
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(GNU_BUILD_ATTRIBUTE_TYPE_BOOL_FALSE): Define.
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(GNU_BUILD_ATTRIBUTE_VERSION): Define.
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(GNU_BUILD_ATTRIBUTE_STACK_PROT): Define.
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(GNU_BUILD_ATTRIBUTE_RELRO): Define.
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(GNU_BUILD_ATTRIBUTE_STACK_SIZE): Define.
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(GNU_BUILD_ATTRIBUTE_TOOL): Define.
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(GNU_BUILD_ATTRIBUTE_ABI): Define.
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(GNU_BUILD_ATTRIBUTE_PIC): Define.
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(NOTE_GNU_PROPERTY_SECTION_NAME): Define.
|
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(GNU_BUILD_ATTRS_SECTION_NAME): Define.
|
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|
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(GNU_PROPERTY_STACK_SIZE): Define.
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|
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(GNU_PROPERTY_NO_COPY_ON_PROTECTED): Define.
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(GNU_PROPERTY_X86_ISA_1_USED): Define.
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|
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(GNU_PROPERTY_X86_ISA_1_NEEDED): Define.
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|
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(GNU_PROPERTY_X86_ISA_1_486): Define.
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|
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(GNU_PROPERTY_X86_ISA_1_586): Define.
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|
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(GNU_PROPERTY_X86_ISA_1_686): Define.
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|
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(GNU_PROPERTY_X86_ISA_1_SSE): Define.
|
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|
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(GNU_PROPERTY_X86_ISA_1_SSE2): Define.
|
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|
|
(GNU_PROPERTY_X86_ISA_1_SSE3): Define.
|
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|
|
(GNU_PROPERTY_X86_ISA_1_SSSE3): Define.
|
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|
|
(GNU_PROPERTY_X86_ISA_1_SSE4_1): Define.
|
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|
|
|
(GNU_PROPERTY_X86_ISA_1_SSE4_2): Define.
|
|
|
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|
|
(GNU_PROPERTY_X86_ISA_1_AVX): Define.
|
|
|
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|
|
(GNU_PROPERTY_X86_ISA_1_AVX2): Define.
|
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|
|
|
|
(GNU_PROPERTY_X86_ISA_1_AVX512F): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_AVX512CD): Define.
|
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|
|
|
|
(GNU_PROPERTY_X86_ISA_1_AVX512ER): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_AVX512PF): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_AVX512VL): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_AVX512DQ): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_AVX512BW): Define.
|
|
|
|
|
|
|
2017-03-01 02:32:07 +08:00
|
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|
|
2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
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|
|
* dis-asm.h (disasm_options_t): New typedef.
|
|
|
|
|
|
(parse_arm_disassembler_option): Remove prototype.
|
|
|
|
|
|
(set_arm_regname_option): Likewise.
|
|
|
|
|
|
(get_arm_regnames): Likewise.
|
|
|
|
|
|
(get_arm_regname_num_options): Likewise.
|
|
|
|
|
|
(disassemble_init_s390): New prototype.
|
|
|
|
|
|
(disassembler_options_powerpc): Likewise.
|
|
|
|
|
|
(disassembler_options_arm): Likewise.
|
|
|
|
|
|
(disassembler_options_s390): Likewise.
|
|
|
|
|
|
(remove_whitespace_and_extra_commas): Likewise.
|
|
|
|
|
|
(disassembler_options_cmp): Likewise.
|
|
|
|
|
|
(next_disassembler_option): New inline function.
|
|
|
|
|
|
(FOR_EACH_DISASSEMBLER_OPTION): New macro.
|
|
|
|
|
|
|
2017-02-28 06:02:36 +08:00
|
|
|
|
2017-02-28 Alan Modra <amodra@gmail.com>
|
|
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|
|
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|
|
|
* elf/ppc64.h (R_PPC64_16DX_HA): New. Expand fake reloc comment.
|
|
|
|
|
|
* elf/ppc.h (R_PPC_16DX_HA): Likewise.
|
|
|
|
|
|
|
[AArch64] Additional SVE instructions
This patch supports some additions to the SVE architecture prior to
its public release.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4x16)
(AARCH64_OPND_SVE_IMM_ROT1, AARCH64_OPND_SVE_IMM_ROT2)
(AARCH64_OPND_SVE_Zm3_INDEX, AARCH64_OPND_SVE_Zm3_22_INDEX)
(AARCH64_OPND_SVE_Zm4_INDEX): New aarch64_opnds.
opcodes/
* aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
(OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
(OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
(OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
(OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
(OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
(OP_SVE_V_HSD): New macros.
(OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
(OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
(OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
(aarch64_opcode_table): Add new SVE instructions.
(aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
for rotation operands. Add new SVE operands.
* aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
(ins_sve_quad_index): Likewise.
(ins_imm_rotate): Split into...
(ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
* aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
(aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
functions.
(aarch64_ins_sve_addr_ri_s4): New function.
(aarch64_ins_sve_quad_index): Likewise.
(do_misc_encoding): Handle "MOV Zn.Q, Qm".
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
(ext_sve_quad_index): Likewise.
(ext_imm_rotate): Split into...
(ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
* aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
(aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
functions.
(aarch64_ext_sve_addr_ri_s4): New function.
(aarch64_ext_sve_quad_index): Likewise.
(aarch64_ext_sve_index): Allow quad indices.
(do_misc_decoding): Likewise.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
aarch64_field_kinds.
(OPD_F_OD_MASK): Widen by one bit.
(OPD_F_NO_ZR): Bump accordingly.
(get_operand_field_width): New function.
* aarch64-opc.c (fields): Add new SVE fields.
(operand_general_constraint_met_p): Handle new SVE operands.
(aarch64_print_operand): Likewise.
* aarch64-opc-2.c: Regenerate.
gas/
* doc/c-aarch64.texi: Document that sve implies fp16, simd and compnum.
* config/tc-aarch64.c (parse_vector_type_for_operand): Allow .q
to be used with SVE registers.
(parse_operands): Handle new SVE operands.
(aarch64_features): Make "sve" require F16 rather than FP. Also
require COMPNUM.
* testsuite/gas/aarch64/sve.s: Add tests for new instructions.
Include compnum tests.
* testsuite/gas/aarch64/sve.d: Update accordingly.
* testsuite/gas/aarch64/sve-invalid.s: Add tests for new instructions.
* testsuite/gas/aarch64/sve-invalid.l: Update accordingly. Also
update expected output for new FMOV and MOV alternatives.
2017-02-25 02:29:00 +08:00
|
|
|
|
2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4x16)
|
|
|
|
|
|
(AARCH64_OPND_SVE_IMM_ROT1, AARCH64_OPND_SVE_IMM_ROT2)
|
|
|
|
|
|
(AARCH64_OPND_SVE_Zm3_INDEX, AARCH64_OPND_SVE_Zm3_22_INDEX)
|
|
|
|
|
|
(AARCH64_OPND_SVE_Zm4_INDEX): New aarch64_opnds.
|
|
|
|
|
|
|
2017-02-25 02:27:26 +08:00
|
|
|
|
2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/aarch64.h (AARCH64_FEATURE_COMPNUM): New macro.
|
|
|
|
|
|
(AARCH64_ARCH_V8_3): Include AARCH64_FEATURE_COMPNUM.
|
|
|
|
|
|
|
2017-02-23 13:23:05 +08:00
|
|
|
|
2017-02-22 Andrew Waterman <andrew@sifive.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/riscv-opc.h (CSR_SCOUNTEREN): New define.
|
|
|
|
|
|
(CSR_MCOUNTEREN): Likewise.
|
|
|
|
|
|
(scounteren): Declare register.
|
|
|
|
|
|
(mcounteren): Likewise.
|
|
|
|
|
|
|
2017-02-15 07:37:04 +08:00
|
|
|
|
2017-02-14 Andrew Waterman <andrew@sifive.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/riscv-opc.h (MATCH_SFENCE_VMA): New define.
|
|
|
|
|
|
(MASK_SFENCE_VMA): Likewise.
|
|
|
|
|
|
(sfence_vma): Declare instruction.
|
|
|
|
|
|
|
2017-02-14 18:08:21 +08:00
|
|
|
|
2017-02-14 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 21118
|
|
|
|
|
|
* opcode/ppc.h (PPC_OPERAND_*): Reassign values, regs first.
|
|
|
|
|
|
(PPC_OPERAND_SPR, PPC_OPERAND_GQR): Define.
|
|
|
|
|
|
|
2017-01-25 20:19:27 +08:00
|
|
|
|
2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/hppa.h: Clarify that file is part of GNU opcodes.
|
|
|
|
|
|
* opcode/i860.h: Ditto.
|
|
|
|
|
|
* opcode/nios2.h: Ditto.
|
|
|
|
|
|
* opcode/nios2r1.h: Ditto.
|
|
|
|
|
|
* opcode/nios2r2.h: Ditto.
|
|
|
|
|
|
* opcode/pru.h: Ditto.
|
|
|
|
|
|
|
2017-01-25 20:24:02 +08:00
|
|
|
|
2017-01-24 Alan Hayward <alan.hayward@arm.com>
|
2017-01-24 18:37:13 +08:00
|
|
|
|
|
|
|
|
|
|
* elf/common.h (NT_ARM_SVE): Define.
|
|
|
|
|
|
|
2017-01-04 22:27:52 +08:00
|
|
|
|
2017-01-04 Jiong Wang <jiong.wang@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* dwarf2.def: Sync with mainline gcc sources.
|
|
|
|
|
|
|
|
|
|
|
|
2017-01-04 Richard Earnshaw <rearnsha@arm.com>
|
|
|
|
|
|
Jiong Wang <jiong.wang@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* dwarf2.def (DW_OP_AARCH64_operation): Reserve the number 0xea.
|
|
|
|
|
|
(DW_CFA_GNU_window_save): Comments the multiplexing on AArch64.
|
|
|
|
|
|
|
2017-01-04 20:27:10 +08:00
|
|
|
|
2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/aarch64.h (AARCH64_FEATURE_RCPC): Define.
|
|
|
|
|
|
(AARCH64_ARCH_V8_3): Update.
|
|
|
|
|
|
|
2017-01-04 01:42:01 +08:00
|
|
|
|
2017-01-03 Kito Cheng <kito.cheng@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/riscv-opc.h: Add support for the "q" ISA extension.
|
|
|
|
|
|
|
2017-01-03 23:17:48 +08:00
|
|
|
|
2017-01-03 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* dwarf2.def: Sync with mainline gcc sources
|
|
|
|
|
|
* dwarf2.h: Likewise.
|
|
|
|
|
|
|
|
|
|
|
|
2016-12-21 Jakub Jelinek <jakub@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* dwarf2.def (DW_FORM_ref_sup): Renamed to ...
|
|
|
|
|
|
(DW_FORM_ref_sup4): ... this. New form.
|
|
|
|
|
|
(DW_FORM_ref_sup8): New form.
|
|
|
|
|
|
|
|
|
|
|
|
2016-10-17 Jakub Jelinek <jakub@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* dwarf2.h (enum dwarf_calling_convention): Add new DWARF5
|
|
|
|
|
|
calling convention codes.
|
|
|
|
|
|
(enum dwarf_line_number_content_type): New.
|
|
|
|
|
|
(enum dwarf_location_list_entry_type): Add DWARF5 DW_LLE_*
|
|
|
|
|
|
codes.
|
|
|
|
|
|
(enum dwarf_source_language): Add new DWARF5 DW_LANG_* codes.
|
|
|
|
|
|
(enum dwarf_macro_record_type): Add DWARF5 DW_MACRO_* codes.
|
|
|
|
|
|
(enum dwarf_name_index_attribute): New.
|
|
|
|
|
|
(enum dwarf_range_list_entry): New.
|
|
|
|
|
|
(enum dwarf_unit_type): New.
|
|
|
|
|
|
* dwarf2.def: Add new DWARF5 DW_TAG_*, DW_FORM_*, DW_AT_*,
|
|
|
|
|
|
DW_OP_* and DW_ATE_* entries.
|
|
|
|
|
|
|
|
|
|
|
|
2016-08-15 Jakub Jelinek <jakub@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* dwarf2.def (DW_AT_string_length_bit_size,
|
|
|
|
|
|
DW_AT_string_length_byte_size): New attributes.
|
|
|
|
|
|
|
|
|
|
|
|
2016-08-12 Alexandre Oliva <aoliva@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR debug/63240
|
|
|
|
|
|
* dwarf2.def (DW_AT_deleted, DW_AT_defaulted): New.
|
|
|
|
|
|
* dwarf2.h (enum dwarf_defaulted_attribute): New.
|
|
|
|
|
|
|
2017-01-02 11:36:43 +08:00
|
|
|
|
2017-01-02 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
Update year range in copyright notice of all files.
|
|
|
|
|
|
|
2017-01-02 11:25:05 +08:00
|
|
|
|
For older changes see ChangeLog-2016
|
2016-01-01 18:44:31 +08:00
|
|
|
|
|
2017-01-02 11:25:05 +08:00
|
|
|
|
Copyright (C) 2017 Free Software Foundation, Inc.
|
2016-01-01 18:44:31 +08:00
|
|
|
|
|
|
|
|
|
|
Copying and distribution of this file, with or without modification,
|
|
|
|
|
|
are permitted in any medium without royalty provided the copyright
|
|
|
|
|
|
notice and this notice are preserved.
|
|
|
|
|
|
|
|
|
|
|
|
Local Variables:
|
|
|
|
|
|
mode: change-log
|
|
|
|
|
|
left-margin: 8
|
|
|
|
|
|
fill-column: 74
|
|
|
|
|
|
version-control: never
|
|
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|
End:
|
