2007-03-15 22:31:24 +08:00
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/* Declarations for Intel 80386 opcode table
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Copyright 2007
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Free Software Foundation, Inc.
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This file is part of GAS, the GNU Assembler.
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GAS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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GAS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GAS; see the file COPYING. If not, write to the Free
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Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
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02110-1301, USA. */
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#include "opcode/i386.h"
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typedef struct template
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{
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/* instruction name sans width suffix ("mov" for movl insns) */
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char *name;
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/* how many operands */
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unsigned int operands;
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/* base_opcode is the fundamental opcode byte without optional
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prefix(es). */
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unsigned int base_opcode;
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#define Opcode_D 0x2 /* Direction bit:
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set if Reg --> Regmem;
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unset if Regmem --> Reg. */
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#define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */
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#define Opcode_FloatD 0x400 /* Direction bit for float insns. */
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/* extension_opcode is the 3 bit extension for group <n> insns.
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This field is also used to store the 8-bit opcode suffix for the
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AMD 3DNow! instructions.
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If this template has no extension opcode (the usual case) use None */
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unsigned int extension_opcode;
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#define None 0xffff /* If no extension_opcode is possible. */
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/* cpu feature flags */
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unsigned int cpu_flags;
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#define Cpu186 0x1 /* i186 or better required */
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#define Cpu286 0x2 /* i286 or better required */
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#define Cpu386 0x4 /* i386 or better required */
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#define Cpu486 0x8 /* i486 or better required */
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#define Cpu586 0x10 /* i585 or better required */
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#define Cpu686 0x20 /* i686 or better required */
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#define CpuP4 0x40 /* Pentium4 or better required */
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#define CpuK6 0x80 /* AMD K6 or better required*/
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#define CpuSledgehammer 0x100 /* Sledgehammer or better required */
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#define CpuMMX 0x200 /* MMX support required */
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#define CpuMMX2 0x400 /* extended MMX support (with SSE or 3DNow!Ext) required */
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#define CpuSSE 0x800 /* Streaming SIMD extensions required */
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#define CpuSSE2 0x1000 /* Streaming SIMD extensions 2 required */
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#define Cpu3dnow 0x2000 /* 3dnow! support required */
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#define Cpu3dnowA 0x4000 /* 3dnow!Extensions support required */
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#define CpuSSE3 0x8000 /* Streaming SIMD extensions 3 required */
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#define CpuPadLock 0x10000 /* VIA PadLock required */
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#define CpuSVME 0x20000 /* AMD Secure Virtual Machine Ext-s required */
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#define CpuVMX 0x40000 /* VMX Instructions required */
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#define CpuSSSE3 0x80000 /* Supplemental Streaming SIMD extensions 3 required */
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#define CpuSSE4a 0x100000 /* SSE4a New Instuctions required */
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#define CpuABM 0x200000 /* ABM New Instructions required */
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/* These flags are set by gas depending on the flag_code. */
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#define Cpu64 0x4000000 /* 64bit support required */
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#define CpuNo64 0x8000000 /* Not supported in the 64bit mode */
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/* The default value for unknown CPUs - enable all features to avoid problems. */
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#define CpuUnknownFlags (Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \
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|CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuVMX \
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|Cpu3dnow|Cpu3dnowA|CpuK6|CpuPadLock|CpuSVME|CpuSSSE3|CpuABM|CpuSSE4a)
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/* the bits in opcode_modifier are used to generate the final opcode from
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the base_opcode. These bits also are used to detect alternate forms of
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the same instruction */
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unsigned int opcode_modifier;
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/* opcode_modifier bits: */
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#define D 0x1 /* has direction bit. */
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#define W 0x2 /* set if operands can be words or dwords
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encoded the canonical way */
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#define Modrm 0x4 /* insn has a modrm byte. */
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#define ShortForm 0x10 /* register is in low 3 bits of opcode */
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#define Jump 0x40 /* special case for jump insns. */
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#define JumpDword 0x80 /* call and jump */
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#define JumpByte 0x100 /* loop and jecxz */
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#define JumpInterSegment 0x200 /* special case for intersegment leaps/calls */
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#define FloatMF 0x400 /* FP insn memory format bit, sized by 0x4 */
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#define FloatR 0x800 /* src/dest swap for floats. */
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#define FloatD 0x1000 /* has float insn direction bit. */
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#define Size16 0x2000 /* needs size prefix if in 32-bit mode */
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#define Size32 0x4000 /* needs size prefix if in 16-bit mode */
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#define Size64 0x8000 /* needs size prefix if in 64-bit mode */
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#define IgnoreSize 0x10000 /* instruction ignores operand size prefix */
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#define DefaultSize 0x20000 /* default insn size depends on mode */
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#define No_bSuf 0x40000 /* b suffix on instruction illegal */
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#define No_wSuf 0x80000 /* w suffix on instruction illegal */
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#define No_lSuf 0x100000 /* l suffix on instruction illegal */
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#define No_sSuf 0x200000 /* s suffix on instruction illegal */
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#define No_qSuf 0x400000 /* q suffix on instruction illegal */
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#define No_xSuf 0x800000 /* x suffix on instruction illegal */
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#define FWait 0x1000000 /* instruction needs FWAIT */
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#define IsString 0x2000000 /* quick test for string instructions */
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#define regKludge 0x4000000 /* fake an extra reg operand for clr, imul */
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#define IsPrefix 0x8000000 /* opcode is a prefix */
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#define ImmExt 0x10000000 /* instruction has extension in 8 bit imm */
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#define NoRex64 0x20000000 /* instruction don't need Rex64 prefix. */
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#define Rex64 0x40000000 /* instruction require Rex64 prefix. */
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#define Ugh 0x80000000 /* deprecated fp insn, gets a warning */
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/* operand_types[i] describes the type of operand i. This is made
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by OR'ing together all of the possible type masks. (e.g.
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'operand_types[i] = Reg|Imm' specifies that operand i can be
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either a register or an immediate operand. */
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unsigned int operand_types[MAX_OPERANDS];
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/* operand_types[i] bits */
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/* register */
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#define Reg8 0x1 /* 8 bit reg */
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#define Reg16 0x2 /* 16 bit reg */
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#define Reg32 0x4 /* 32 bit reg */
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#define Reg64 0x8 /* 64 bit reg */
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/* immediate */
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#define Imm8 0x10 /* 8 bit immediate */
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#define Imm8S 0x20 /* 8 bit immediate sign extended */
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#define Imm16 0x40 /* 16 bit immediate */
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#define Imm32 0x80 /* 32 bit immediate */
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#define Imm32S 0x100 /* 32 bit immediate sign extended */
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#define Imm64 0x200 /* 64 bit immediate */
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#define Imm1 0x400 /* 1 bit immediate */
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/* memory */
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#define BaseIndex 0x800
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/* Disp8,16,32 are used in different ways, depending on the
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instruction. For jumps, they specify the size of the PC relative
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displacement, for baseindex type instructions, they specify the
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size of the offset relative to the base register, and for memory
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offset instructions such as `mov 1234,%al' they specify the size of
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the offset relative to the segment base. */
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#define Disp8 0x1000 /* 8 bit displacement */
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#define Disp16 0x2000 /* 16 bit displacement */
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#define Disp32 0x4000 /* 32 bit displacement */
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#define Disp32S 0x8000 /* 32 bit signed displacement */
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#define Disp64 0x10000 /* 64 bit displacement */
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/* specials */
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#define InOutPortReg 0x20000 /* register to hold in/out port addr = dx */
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#define ShiftCount 0x40000 /* register to hold shift count = cl */
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#define Control 0x80000 /* Control register */
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#define Debug 0x100000 /* Debug register */
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#define Test 0x200000 /* Test register */
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#define FloatReg 0x400000 /* Float register */
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#define FloatAcc 0x800000 /* Float stack top %st(0) */
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#define SReg2 0x1000000 /* 2 bit segment register */
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#define SReg3 0x2000000 /* 3 bit segment register */
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#define Acc 0x4000000 /* Accumulator %al or %ax or %eax */
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#define JumpAbsolute 0x8000000
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#define RegMMX 0x10000000 /* MMX register */
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#define RegXMM 0x20000000 /* XMM registers in PIII */
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#define EsSeg 0x40000000 /* String insn operand with fixed es segment */
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/* InvMem is for instructions with a modrm byte that only allow a
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general register encoding in the i.tm.mode and i.tm.regmem fields,
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eg. control reg moves. They really ought to support a memory form,
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but don't, so we add an InvMem flag to the register operand to
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indicate that it should be encoded in the i.tm.regmem field. */
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#define InvMem 0x80000000
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#define Reg (Reg8|Reg16|Reg32|Reg64) /* gen'l register */
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#define WordReg (Reg16|Reg32|Reg64)
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#define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
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#define Imm (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */
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#define EncImm (Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */
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#define Disp (Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */
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#define AnyMem (Disp8|Disp16|Disp32|Disp32S|BaseIndex|InvMem) /* General memory */
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/* The following aliases are defined because the opcode table
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carefully specifies the allowed memory types for each instruction.
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At the moment we can only tell a memory reference size by the
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instruction suffix, so there's not much point in defining Mem8,
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Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use
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the suffix directly to check memory operands. */
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#define LLongMem AnyMem /* 64 bits (or more) */
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#define LongMem AnyMem /* 32 bit memory ref */
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#define ShortMem AnyMem /* 16 bit memory ref */
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#define WordMem AnyMem /* 16, 32 or 64 bit memory ref */
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#define ByteMem AnyMem /* 8 bit memory ref */
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}
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template;
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extern const template i386_optab[];
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/* these are for register name --> number & type hash lookup */
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typedef struct
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{
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char *reg_name;
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unsigned int reg_type;
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unsigned int reg_flags;
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#define RegRex 0x1 /* Extended register. */
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#define RegRex64 0x2 /* Extended 8 bit register. */
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unsigned int reg_num;
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}
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reg_entry;
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/* Entries in i386_regtab. */
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#define REGNAM_AL 1
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#define REGNAM_AX 25
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#define REGNAM_EAX 41
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extern const reg_entry i386_regtab[];
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2007-03-16 01:30:31 +08:00
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extern const unsigned int i386_regtab_size;
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2007-03-15 22:31:24 +08:00
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extern const reg_entry i386_float_regtab[];
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2007-03-16 01:30:31 +08:00
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extern const unsigned int i386_float_regtab_size;
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2007-03-15 22:31:24 +08:00
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typedef struct
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{
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char *seg_name;
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unsigned int seg_prefix;
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}
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seg_entry;
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extern const seg_entry cs;
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extern const seg_entry ds;
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extern const seg_entry ss;
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extern const seg_entry es;
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extern const seg_entry fs;
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extern const seg_entry gs;
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