mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2025-01-06 12:09:26 +08:00
431 lines
9.9 KiB
ArmAsm
431 lines
9.9 KiB
ArmAsm
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//Original:/testcases/core/c_dsp32shift_ahh/c_dsp32shift_ahh.dsp
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// Spec Reference: dsp32shift ashift/ashift
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# mach: bfin
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.include "testutils.inc"
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start
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// ashift/ashift : positive data, count (+)=left (half reg)
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// d_reg = ashift/ashift (d BY d_lo)
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// Rx by RLx
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imm32 r0, 0x01230000;
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imm32 r1, 0x12345678;
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imm32 r2, 0x23456789;
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imm32 r3, 0x3456789a;
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imm32 r4, 0x456789ab;
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imm32 r5, 0x56789abc;
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imm32 r6, 0x6789abcd;
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imm32 r7, 0x789abcde;
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R5 = ASHIFT R0 BY R0.L (V);
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R0 = ASHIFT R1 BY R0.L (V);
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R1 = ASHIFT R2 BY R0.L (V);
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R2 = ASHIFT R3 BY R0.L (V);
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R3 = ASHIFT R4 BY R0.L (V);
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R4 = ASHIFT R5 BY R0.L (V);
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R7 = ASHIFT R6 BY R0.L (V);
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R6 = ASHIFT R7 BY R0.L (V);
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CHECKREG r0, 0x12345678;
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CHECKREG r1, 0x00230067;
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CHECKREG r2, 0x00340078;
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CHECKREG r3, 0x0045FF89;
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CHECKREG r4, 0x00010000;
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CHECKREG r5, 0x01230000;
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CHECKREG r6, 0x0000FFFF;
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CHECKREG r7, 0x0067FFAB;
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imm32 r0, 0x01230002;
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imm32 r1, 0x12345678;
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imm32 r2, 0x23456789;
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imm32 r3, 0x3456789a;
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imm32 r4, 0x456789ab;
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imm32 r5, 0x56789abc;
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imm32 r6, 0x6789abcd;
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imm32 r7, 0x789abcde;
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R1.L = 5;
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R2 = ASHIFT R0 BY R1.L (V);
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R3 = ASHIFT R1 BY R1.L (V);
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R4 = ASHIFT R2 BY R1.L (V);
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R5 = ASHIFT R3 BY R1.L (V);
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R6 = ASHIFT R4 BY R1.L (V);
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R7 = ASHIFT R5 BY R1.L (V);
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R0 = ASHIFT R6 BY R1.L (V);
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R1 = ASHIFT R7 BY R1.L (V);
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CHECKREG r0, 0x00000000;
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CHECKREG r1, 0x00000000;
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CHECKREG r2, 0x24600040;
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CHECKREG r3, 0x468000A0;
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CHECKREG r4, 0x8C000800;
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CHECKREG r5, 0xD0001400;
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CHECKREG r6, 0x80000000;
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CHECKREG r7, 0x00008000;
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imm32 r0, 0x01230002;
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imm32 r1, 0x12345678;
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imm32 r2, 0x23456789;
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imm32 r3, 0x3456789a;
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imm32 r4, 0x456789ab;
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imm32 r5, 0x56789abc;
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imm32 r6, 0x6789abcd;
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imm32 r7, 0x789abcde;
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R2 = 15;
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R3 = ASHIFT R0 BY R2.L (V);
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R4 = ASHIFT R1 BY R2.L (V);
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R5 = ASHIFT R2 BY R2.L (V);
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R6 = ASHIFT R3 BY R2.L (V);
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R7 = ASHIFT R4 BY R2.L (V);
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R0 = ASHIFT R5 BY R2.L (V);
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R1 = ASHIFT R6 BY R2.L (V);
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R2 = ASHIFT R7 BY R2.L (V);
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CHECKREG r0, 0x00000000;
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CHECKREG r1, 0x00000000;
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CHECKREG r2, 0x00000000;
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CHECKREG r3, 0x80000000;
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CHECKREG r4, 0x00000000;
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CHECKREG r5, 0x00008000;
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CHECKREG r6, 0x00000000;
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CHECKREG r7, 0x00000000;
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imm32 r0, 0x01230002;
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imm32 r1, 0x12345678;
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imm32 r2, 0x23456789;
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imm32 r3, 0x3456789a;
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imm32 r4, 0x456789ab;
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imm32 r5, 0x56789abc;
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imm32 r6, 0x6789abcd;
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imm32 r7, 0x789abcde;
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R3.L = 16;
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R4 = ASHIFT R0 BY R3.L (V);
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R5 = ASHIFT R1 BY R3.L (V);
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R6 = ASHIFT R2 BY R3.L (V);
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R7 = ASHIFT R3 BY R3.L (V);
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R0 = ASHIFT R4 BY R3.L (V);
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R1 = ASHIFT R5 BY R3.L (V);
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R2 = ASHIFT R6 BY R3.L (V);
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R3 = ASHIFT R7 BY R3.L (V);
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CHECKREG r0, 0x00000000;
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CHECKREG r1, 0x00000000;
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CHECKREG r2, 0x00000000;
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CHECKREG r3, 0x00000000;
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CHECKREG r4, 0x00000000;
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CHECKREG r5, 0x00000000;
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CHECKREG r6, 0x00000000;
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CHECKREG r7, 0x00000000;
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imm32 r0, 0x01230002;
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imm32 r1, 0x12345678;
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imm32 r2, 0x23456789;
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imm32 r3, 0x3456789a;
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imm32 r4, 0x456789ab;
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imm32 r5, 0x56789abc;
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imm32 r6, 0x6789abcd;
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imm32 r7, 0x789abcde;
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R4.L = -1;
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R0 = ASHIFT R0 BY R4.L (V);
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R1 = ASHIFT R1 BY R4.L (V);
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R2 = ASHIFT R2 BY R4.L (V);
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R3 = ASHIFT R3 BY R4.L (V);
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R4 = ASHIFT R4 BY R4.L (V);
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R5 = ASHIFT R5 BY R4.L (V);
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R6 = ASHIFT R6 BY R4.L (V);
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R7 = ASHIFT R7 BY R4.L (V);
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CHECKREG r0, 0x00910001;
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CHECKREG r1, 0x091A2B3C;
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CHECKREG r2, 0x11A233C4;
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CHECKREG r3, 0x1A2B3C4D;
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CHECKREG r4, 0x22B3FFFF;
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CHECKREG r5, 0x2B3CCD5E;
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CHECKREG r6, 0x33C4D5E6;
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CHECKREG r7, 0x3C4DDE6F;
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imm32 r0, 0x01230002;
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imm32 r1, 0x12345678;
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imm32 r2, 0x23456789;
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imm32 r3, 0x3456789a;
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imm32 r4, 0x456789ab;
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imm32 r5, 0x56789abc;
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imm32 r6, 0x6789abcd;
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imm32 r7, 0x789abcde;
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R5.L = -6;
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R6 = ASHIFT R0 BY R5.L (V);
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R7 = ASHIFT R1 BY R5.L (V);
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R0 = ASHIFT R2 BY R5.L (V);
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R1 = ASHIFT R3 BY R5.L (V);
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R2 = ASHIFT R4 BY R5.L (V);
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R3 = ASHIFT R5 BY R5.L (V);
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R4 = ASHIFT R6 BY R5.L (V);
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R5 = ASHIFT R7 BY R5.L (V);
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CHECKREG r0, 0x008D019E;
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CHECKREG r1, 0x00D101E2;
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CHECKREG r2, 0x0115FE26;
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CHECKREG r3, 0x0159FFFF;
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CHECKREG r4, 0x00000000;
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CHECKREG r5, 0x00010005;
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CHECKREG r6, 0x00040000;
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CHECKREG r7, 0x00480159;
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imm32 r0, 0x01230002;
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imm32 r1, 0x12345678;
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imm32 r2, 0x23456789;
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imm32 r3, 0x3456789a;
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imm32 r4, 0x456789ab;
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imm32 r5, 0x56789abc;
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imm32 r6, 0x6789abcd;
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imm32 r7, 0x789abcde;
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R6.L = -15;
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R7 = ASHIFT R0 BY R6.L (V);
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R0 = ASHIFT R1 BY R6.L (V);
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R1 = ASHIFT R2 BY R6.L (V);
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R2 = ASHIFT R3 BY R6.L (V);
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R3 = ASHIFT R4 BY R6.L (V);
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R4 = ASHIFT R5 BY R6.L (V);
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R5 = ASHIFT R6 BY R6.L (V);
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R6 = ASHIFT R7 BY R6.L (V);
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CHECKREG r0, 0x00000000;
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CHECKREG r1, 0x00000000;
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CHECKREG r2, 0x00000000;
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CHECKREG r3, 0x0000FFFF;
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CHECKREG r4, 0x0000FFFF;
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CHECKREG r5, 0x0000FFFF;
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CHECKREG r6, 0x00000000;
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CHECKREG r7, 0x00000000;
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imm32 r0, 0x01230002;
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imm32 r1, 0x12345678;
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imm32 r2, 0x23456789;
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imm32 r3, 0x3456789a;
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imm32 r4, 0x456789ab;
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imm32 r5, 0x56789abc;
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imm32 r6, 0x6789abcd;
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imm32 r7, 0x789abcde;
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R7.L = -16;
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R0 = ASHIFT R0 BY R7.L (V);
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R1 = ASHIFT R1 BY R7.L (V);
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R2 = ASHIFT R2 BY R7.L (V);
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R3 = ASHIFT R3 BY R7.L (V);
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R4 = ASHIFT R4 BY R7.L (V);
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R5 = ASHIFT R5 BY R7.L (V);
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R6 = ASHIFT R6 BY R7.L (V);
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R7 = ASHIFT R7 BY R7.L (V);
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CHECKREG r0, 0x00000000;
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CHECKREG r1, 0x00000000;
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CHECKREG r2, 0x00000000;
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CHECKREG r3, 0x00000000;
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CHECKREG r4, 0x0000FFFF;
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CHECKREG r5, 0x0000FFFF;
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CHECKREG r6, 0x0000FFFF;
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CHECKREG r7, 0x0000FFFF;
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imm32 r0, 0x01230002;
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imm32 r1, 0x12345678;
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imm32 r2, 0x23456789;
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imm32 r3, 0x3456789a;
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imm32 r4, 0x456789ab;
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imm32 r5, 0x56789abc;
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imm32 r6, 0x6789abcd;
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imm32 r7, 0x789abcde;
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R0.L = 4;
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//r0 = ashift/ashift (r0 by rl0);
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R1 = ASHIFT R1 BY R0.L (V);
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R2 = ASHIFT R2 BY R0.L (V);
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R3 = ASHIFT R3 BY R0.L (V);
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R4 = ASHIFT R4 BY R0.L (V);
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R5 = ASHIFT R5 BY R0.L (V);
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R6 = ASHIFT R6 BY R0.L (V);
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R7 = ASHIFT R7 BY R0.L (V);
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CHECKREG r0, 0x01230004;
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CHECKREG r1, 0x23406780;
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CHECKREG r2, 0x34507890;
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CHECKREG r3, 0x456089A0;
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CHECKREG r4, 0x56709AB0;
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CHECKREG r5, 0x6780ABC0;
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CHECKREG r6, 0x7890BCD0;
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CHECKREG r7, 0x89A0CDE0;
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imm32 r0, 0x01230002;
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imm32 r1, 0x12345678;
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imm32 r2, 0x23456789;
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imm32 r3, 0x3456789a;
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imm32 r4, 0x456789ab;
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imm32 r5, 0x56789abc;
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imm32 r6, 0x6789abcd;
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imm32 r7, 0x789abcde;
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R1.L = 6;
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R0 = ASHIFT R0 BY R1.L (V);
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//r1 = ashift/ashift (r1 by rl1);
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R2 = ASHIFT R2 BY R1.L (V);
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R3 = ASHIFT R3 BY R1.L (V);
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R4 = ASHIFT R4 BY R1.L (V);
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R5 = ASHIFT R5 BY R1.L (V);
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R6 = ASHIFT R6 BY R1.L (V);
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R7 = ASHIFT R7 BY R1.L (V);
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CHECKREG r0, 0x48C00080;
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CHECKREG r1, 0x12340006;
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CHECKREG r2, 0xD140E240;
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CHECKREG r3, 0x15802680;
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CHECKREG r4, 0x59C06AC0;
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CHECKREG r5, 0x9E00AF00;
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CHECKREG r6, 0xE240F340;
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CHECKREG r7, 0x26803780;
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imm32 r0, 0x01230002;
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imm32 r1, 0x12345678;
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imm32 r2, 0x23456789;
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imm32 r3, 0x3456789a;
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imm32 r4, 0x456789ab;
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imm32 r5, 0x56789abc;
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imm32 r6, 0x6789abcd;
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imm32 r7, 0x789abcde;
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R2.L = 15;
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R0 = ASHIFT R0 BY R2.L (V);
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R1 = ASHIFT R1 BY R2.L (V);
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//r2 = ashift/ashift (r2 by rl2);
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R3 = ASHIFT R3 BY R2.L (V);
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R4 = ASHIFT R4 BY R2.L (V);
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R5 = ASHIFT R5 BY R2.L (V);
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R6 = ASHIFT R6 BY R2.L (V);
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R7 = ASHIFT R7 BY R2.L (V);
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CHECKREG r0, 0x80000000;
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CHECKREG r1, 0x00000000;
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CHECKREG r2, 0x2345000F;
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CHECKREG r3, 0x00000000;
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CHECKREG r4, 0x80008000;
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CHECKREG r5, 0x00000000;
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CHECKREG r6, 0x80008000;
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CHECKREG r7, 0x00000000;
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imm32 r0, 0x01230002;
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imm32 r1, 0x12345678;
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imm32 r2, 0x23456789;
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imm32 r3, 0x3456789a;
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imm32 r4, 0x456789ab;
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imm32 r5, 0x56789abc;
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imm32 r6, 0x6789abcd;
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imm32 r7, 0x789abcde;
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R3.L = 16;
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R0 = ASHIFT R0 BY R3.L (V);
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R1 = ASHIFT R1 BY R3.L (V);
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R2 = ASHIFT R2 BY R3.L (V);
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//r3 = ashift/ashift (r3 by rl3);
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R4 = ASHIFT R4 BY R3.L (V);
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R5 = ASHIFT R5 BY R3.L (V);
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R6 = ASHIFT R6 BY R3.L (V);
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R7 = ASHIFT R7 BY R3.L (V);
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CHECKREG r0, 0x00000000;
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CHECKREG r1, 0x00000000;
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CHECKREG r2, 0x00000000;
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CHECKREG r3, 0x34560010;
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CHECKREG r4, 0x00000000;
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CHECKREG r5, 0x00000000;
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||
|
|
CHECKREG r6, 0x00000000;
|
||
|
|
CHECKREG r7, 0x00000000;
|
||
|
|
|
||
|
|
imm32 r0, 0x01230002;
|
||
|
|
imm32 r1, 0x12345678;
|
||
|
|
imm32 r2, 0x23456789;
|
||
|
|
imm32 r3, 0x3456789a;
|
||
|
|
imm32 r4, 0x456789ab;
|
||
|
|
imm32 r5, 0x56789abc;
|
||
|
|
imm32 r6, 0x6789abcd;
|
||
|
|
imm32 r7, 0x789abcde;
|
||
|
|
R4.L = -9;
|
||
|
|
R0 = ASHIFT R0 BY R4.L (V);
|
||
|
|
R1 = ASHIFT R1 BY R4.L (V);
|
||
|
|
R2 = ASHIFT R2 BY R4.L (V);
|
||
|
|
R3 = ASHIFT R3 BY R4.L (V);
|
||
|
|
//r4 = ashift/ashift (r4 by rl4);
|
||
|
|
R5 = ASHIFT R5 BY R4.L (V);
|
||
|
|
R6 = ASHIFT R6 BY R4.L (V);
|
||
|
|
R7 = ASHIFT R7 BY R4.L (V);
|
||
|
|
CHECKREG r0, 0x00000000;
|
||
|
|
CHECKREG r1, 0x0009002B;
|
||
|
|
CHECKREG r2, 0x00110033;
|
||
|
|
CHECKREG r3, 0x001A003C;
|
||
|
|
CHECKREG r4, 0x4567FFF7;
|
||
|
|
CHECKREG r5, 0x002BFFCD;
|
||
|
|
CHECKREG r6, 0x0033FFD5;
|
||
|
|
CHECKREG r7, 0x003CFFDE;
|
||
|
|
|
||
|
|
imm32 r0, 0x01230002;
|
||
|
|
imm32 r1, 0x12345678;
|
||
|
|
imm32 r2, 0x23456789;
|
||
|
|
imm32 r3, 0x3456789a;
|
||
|
|
imm32 r4, 0x456789ab;
|
||
|
|
imm32 r5, 0x56789abc;
|
||
|
|
imm32 r6, 0x6789abcd;
|
||
|
|
imm32 r7, 0x789abcde;
|
||
|
|
R5.L = -14;
|
||
|
|
R0 = ASHIFT R0 BY R5.L (V);
|
||
|
|
R1 = ASHIFT R1 BY R5.L (V);
|
||
|
|
R2 = ASHIFT R2 BY R5.L (V);
|
||
|
|
R3 = ASHIFT R3 BY R5.L (V);
|
||
|
|
R4 = ASHIFT R4 BY R5.L (V);
|
||
|
|
//r5 = ashift/ashift (r5 by rl5);
|
||
|
|
R6 = ASHIFT R6 BY R5.L (V);
|
||
|
|
R7 = ASHIFT R7 BY R5.L (V);
|
||
|
|
CHECKREG r0, 0x00000000;
|
||
|
|
CHECKREG r1, 0x00000001;
|
||
|
|
CHECKREG r2, 0x00000001;
|
||
|
|
CHECKREG r3, 0x00000001;
|
||
|
|
CHECKREG r4, 0x0001FFFE;
|
||
|
|
CHECKREG r5, 0x5678FFF2;
|
||
|
|
CHECKREG r6, 0x0001FFFE;
|
||
|
|
CHECKREG r7, 0x0001FFFE;
|
||
|
|
|
||
|
|
|
||
|
|
imm32 r0, 0x01230002;
|
||
|
|
imm32 r1, 0x12345678;
|
||
|
|
imm32 r2, 0x23456789;
|
||
|
|
imm32 r3, 0x3456789a;
|
||
|
|
imm32 r4, 0x456789ab;
|
||
|
|
imm32 r5, 0x56789abc;
|
||
|
|
imm32 r6, 0x6789abcd;
|
||
|
|
imm32 r7, 0x789abcde;
|
||
|
|
R6.L = -15;
|
||
|
|
R0 = ASHIFT R0 BY R6.L (V);
|
||
|
|
R1 = ASHIFT R1 BY R6.L (V);
|
||
|
|
R2 = ASHIFT R2 BY R6.L (V);
|
||
|
|
R3 = ASHIFT R3 BY R6.L (V);
|
||
|
|
R4 = ASHIFT R4 BY R6.L (V);
|
||
|
|
R5 = ASHIFT R5 BY R6.L (V);
|
||
|
|
//r6 = ashift/ashift (r6 by rl6);
|
||
|
|
R7 = ASHIFT R7 BY R6.L (V);
|
||
|
|
CHECKREG r0, 0x00000000;
|
||
|
|
CHECKREG r1, 0x00000000;
|
||
|
|
CHECKREG r2, 0x00000000;
|
||
|
|
CHECKREG r3, 0x00000000;
|
||
|
|
CHECKREG r4, 0x0000FFFF;
|
||
|
|
CHECKREG r5, 0x0000FFFF;
|
||
|
|
CHECKREG r6, 0x6789FFF1;
|
||
|
|
CHECKREG r7, 0x0000FFFF;
|
||
|
|
|
||
|
|
imm32 r0, 0x01230002;
|
||
|
|
imm32 r1, 0x12345678;
|
||
|
|
imm32 r2, 0x23456789;
|
||
|
|
imm32 r3, 0x3456789a;
|
||
|
|
imm32 r4, 0x456789ab;
|
||
|
|
imm32 r5, 0x56789abc;
|
||
|
|
imm32 r6, 0x6789abcd;
|
||
|
|
imm32 r7, 0x789abcde;
|
||
|
|
R7.L = -16;
|
||
|
|
R0 = ASHIFT R0 BY R7.L (V);
|
||
|
|
R1 = ASHIFT R1 BY R7.L (V);
|
||
|
|
R2 = ASHIFT R2 BY R7.L (V);
|
||
|
|
R3 = ASHIFT R3 BY R7.L (V);
|
||
|
|
R4 = ASHIFT R4 BY R7.L (V);
|
||
|
|
R5 = ASHIFT R5 BY R7.L (V);
|
||
|
|
R6 = ASHIFT R6 BY R7.L (V);
|
||
|
|
R7 = ASHIFT R7 BY R7.L (V);
|
||
|
|
CHECKREG r0, 0x00000000;
|
||
|
|
CHECKREG r1, 0x00000000;
|
||
|
|
CHECKREG r2, 0x00000000;
|
||
|
|
CHECKREG r3, 0x00000000;
|
||
|
|
CHECKREG r4, 0x0000ffff;
|
||
|
|
CHECKREG r5, 0x0000ffff;
|
||
|
|
CHECKREG r6, 0x0000ffff;
|
||
|
|
CHECKREG r7, 0x0000ffff;
|
||
|
|
|
||
|
|
pass
|