mirror of
https://sourceware.org/git/binutils-gdb.git
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187 lines
3.5 KiB
ArmAsm
187 lines
3.5 KiB
ArmAsm
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//Original:/testcases/core/c_alu2op_conv_mix/c_alu2op_conv_mix.dsp
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// Spec Reference: alu2op convert mix
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# mach: bfin
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.include "testutils.inc"
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start
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imm32 r0, 0x00789abc;
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imm32 r1, 0x12345678;
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imm32 r2, 0x23456789;
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imm32 r3, 0x3456789a;
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imm32 r4, 0x856789ab;
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imm32 r5, 0x96789abc;
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imm32 r6, 0xa789abcd;
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imm32 r7, 0xb89abcde;
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R0 = R0.B (X);
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R1 = R1.L (X);
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R2 = R2.L (Z);
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R3 = R3.B (X);
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R4 = R4.B (Z);
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R5 = - R5;
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R6 = ~ R6;
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R7 = R7.L (X);
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CHECKREG r0, 0xFFFFFFBC;
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CHECKREG r1, 0x00005678;
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CHECKREG r2, 0x00006789;
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CHECKREG r3, 0xFFFFFF9A;
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CHECKREG r4, 0x000000AB;
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CHECKREG r5, 0x69876544;
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CHECKREG r6, 0x58765432;
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CHECKREG r7, 0xFFFFBCDE;
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imm32 r0, 0x01230002;
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imm32 r1, 0x00374659;
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imm32 r2, 0x93456789;
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imm32 r3, 0xa456789a;
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imm32 r4, 0xb56789ab;
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imm32 r5, 0xc6789abc;
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imm32 r6, 0xd789abcd;
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imm32 r7, 0xe89abcde;
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R6 = R0.B (X);
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R7 = R1.L (X);
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R0 = R2.L (Z);
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R1 = R3.B (X);
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R2 = R4.B (Z);
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R3 = - R5;
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R4 = ~ R6;
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R5 = R7.L (X);
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CHECKREG r0, 0x00006789;
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CHECKREG r1, 0xFFFFFF9A;
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CHECKREG r2, 0x000000AB;
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CHECKREG r3, 0x39876544;
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CHECKREG r4, 0xFFFFFFFD;
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CHECKREG r5, 0x00004659;
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CHECKREG r6, 0x00000002;
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CHECKREG r7, 0x00004659;
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imm32 r0, 0x51230002;
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imm32 r1, 0x12345678;
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imm32 r2, 0x91203450;
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imm32 r3, 0x3456789a;
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imm32 r4, 0x956789ab;
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imm32 r5, 0x86789abc;
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imm32 r6, 0xa789abcd;
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imm32 r7, 0x789abcde;
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R5 = R0.B (X);
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R6 = R1.L (X);
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R7 = R2.L (Z);
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R0 = R3.B (X);
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R1 = R4.B (Z);
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R2 = - R5;
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R3 = ~ R6;
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R4 = R7.L (X);
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CHECKREG r0, 0xFFFFFF9A;
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CHECKREG r1, 0x000000AB;
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CHECKREG r2, 0xFFFFFFFE;
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CHECKREG r3, 0xFFFFA987;
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CHECKREG r4, 0x00003450;
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CHECKREG r5, 0x00000002;
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CHECKREG r6, 0x00005678;
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CHECKREG r7, 0x00003450;
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imm32 r0, 0x01230002;
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imm32 r1, 0x82345678;
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imm32 r2, 0x93456789;
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imm32 r3, 0x00000000;
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imm32 r4, 0xb56789ab;
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imm32 r5, 0xc6789abc;
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imm32 r6, 0xd789abcd;
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imm32 r7, 0xe89abcde;
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R4 = R0.B (X);
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R5 = R1.L (X);
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R6 = R2.L (Z);
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R7 = R3.B (X);
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R0 = R4.B (Z);
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R1 = - R5;
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R2 = ~ R6;
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R3 = R7.L (X);
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CHECKREG r0, 0x00000002;
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CHECKREG r1, 0xFFFFA988;
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CHECKREG r2, 0xFFFF9876;
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CHECKREG r3, 0x00000000;
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CHECKREG r4, 0x00000002;
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CHECKREG r5, 0x00005678;
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CHECKREG r6, 0x00006789;
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CHECKREG r7, 0x00000000;
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imm32 r0, 0xadf00001;
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imm32 r1, 0x12345678;
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imm32 r2, 0x23456789;
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imm32 r3, 0x3456789a;
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imm32 r4, 0x00000000;
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imm32 r5, 0x96789abc;
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imm32 r6, 0xa789abcd;
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imm32 r7, 0xb89abcde;
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R3 = R0.B (X);
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R4 = R1.L (X);
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R5 = R2.L (Z);
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R6 = R3.B (X);
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R7 = R4.B (Z);
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R0 = - R5;
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R1 = ~ R6;
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R2 = R7.L (X);
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CHECKREG r0, 0xFFFF9877;
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CHECKREG r1, 0xFFFFFFFE;
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CHECKREG r2, 0x00000078;
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CHECKREG r3, 0x00000001;
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CHECKREG r4, 0x00005678;
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CHECKREG r5, 0x00006789;
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CHECKREG r6, 0x00000001;
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CHECKREG r7, 0x00000078;
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imm32 r0, 0x01230002;
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imm32 r1, 0x00000000;
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imm32 r2, 0x93456789;
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imm32 r3, 0xa456789a;
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imm32 r4, 0xb56789ab;
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imm32 r5, 0x54238900;
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imm32 r6, 0xd789abcd;
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imm32 r7, 0xe89abcde;
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R2 = R0.B (X);
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R3 = R1.L (X);
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R4 = R2.L (Z);
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R5 = R3.B (X);
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R6 = R4.B (Z);
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R7 = - R5;
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R0 = ~ R6;
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R1 = R7.L (X);
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CHECKREG r0, 0xFFFFFFFD;
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CHECKREG r1, 0x00000000;
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CHECKREG r2, 0x00000002;
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CHECKREG r3, 0x00000000;
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CHECKREG r4, 0x00000002;
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CHECKREG r5, 0x00000000;
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CHECKREG r6, 0x00000002;
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CHECKREG r7, 0x00000000;
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imm32 r0, 0x51230002;
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imm32 r1, 0x12345678;
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imm32 r2, 0x00000000;
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imm32 r3, 0x3456789a;
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imm32 r4, 0x956789ab;
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imm32 r5, 0x86789abc;
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imm32 r6, 0x00000000;
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imm32 r7, 0x789abcde;
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R1 = R0.B (X);
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R2 = R1.L (X);
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R3 = R2.L (Z);
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R4 = R3.B (X);
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R5 = R4.B (Z);
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R6 = - R5;
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R0 = ~ R6;
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R7 = R7.L (X);
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CHECKREG r0, 0x00000001;
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CHECKREG r1, 0x00000002;
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CHECKREG r2, 0x00000002;
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CHECKREG r3, 0x00000002;
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CHECKREG r4, 0x00000002;
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CHECKREG r5, 0x00000002;
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CHECKREG r6, 0xFFFFFFFE;
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CHECKREG r7, 0xFFFFBCDE;
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pass
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