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binutils-gdb/binutils/testsuite/binutils-all/mips/mips-xpa-virt-1.d

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MIPS: Fix XPA base and Virtualization ASE instruction handling Correct a commit 7d64c587c15f ("Add support for the MIPS eXtended Physical Address (XPA) ASE.") bug, causing XPA base and Virtualization ASE instructions to be wrongly always enabled with the selection of the MIPS32r2 or higher ISA. For example this source assembles successfully as shown below: $ cat xpa.s mfhc0 $2, $1 $ as -32 -mips32 -o xpa.o xpa.s xpa.s: Assembler messages: xpa.s:1: Error: opcode not supported on this processor: mips32 (mips32) `mfhc0 $2,$1' $ as -32 -mips32r2 -o xpa.o xpa.s $ objdump -d xpa.o xpa.o: file format elf32-tradbigmips Disassembly of section .text: 00000000 <.text>: 0: 40420800 mfhc0 v0,c0_random ... $ To address this issue remove the I33 (INSN_ISA32R2) marking from all XPA instructions in the opcode table. Additionally, for XPA Virtualization ASE instructions implement an XPAVZ (ASE_XPA_VIRT) combination ASE flag and use it in place of IVIRT|XPA (ASE_VIRT|ASE_XPA). Now the same source is correctly rejected unless the `-mxpa' option is also used: $ as -32 -mips32r2 -o xpa.o xpa.s xpa.s: Assembler messages: xpa.s:1: Error: opcode not supported on this processor: mips32r2 (mips32r2) `mfhc0 $2,$1' $ as -32 -mips32r2 -mxpa -o xpa.o xpa.s $ Add test cases for XPA base and XPA Virtualization ASE instructions. Parts of this change by Andrew Bennett. include/ * opcode/mips.h (ASE_XPA_VIRT): New macro. opcodes/ * mips-dis.c (mips_calculate_combination_ases): Handle the ASE_XPA_VIRT flag. (parse_mips_ase_option): New function. (parse_mips_dis_option): Factor out ASE option handling to the new function. Call `mips_calculate_combination_ases'. * mips-opc.c (XPAVZ): New macro. (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0", "mfhgc0", "mthc0" and "mthgc0". gas/ * config/tc-mips.c (mips_set_ase): Handle the ASE_XPA_VIRT flag. * testsuite/gas/mips/xpa.d: Remove `xpa' from `-M' in `objdump' flags. Add `-mvirt' to `as' flags. * testsuite/gas/mips/xpa-err.d: New test. * testsuite/gas/mips/xpa-virt-err.d: New test. * testsuite/gas/mips/xpa-err.l: New stderr output. * testsuite/gas/mips/xpa-virt-err.l: New stderr output. * testsuite/gas/mips/xpa-err.s: New test source. * testsuite/gas/mips/xpa-virt-err.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. binutils/ * testsuite/binutils-all/mips/mips-xpa-virt-1.d: New test. * testsuite/binutils-all/mips/mips-xpa-virt-2.d: New test. * testsuite/binutils-all/mips/mips-xpa-virt-3.d: New test. * testsuite/binutils-all/mips/mips-xpa-virt-4.d: New test. * testsuite/binutils-all/mips/mips-xpa-virt.s: New test source. * testsuite/binutils-all/mips/mips.exp: Run the new tests.
2017-06-30 14:21:55 +08:00
#PROG: objcopy
MIPS/binutils/testsuite: Fix XPA and Virtualization ASE cases Fix commit 9785fc2a4d22 ("MIPS: Fix XPA base and Virtualization ASE instruction handling") and explicitly use the `mips:3000' machine for disassembly across the XPA base and XPA Virtualization ASE test cases, providing actual coverage for the `virt' and `xpa' disassembler options and removing failures for targets that default to those ASEs enabled: mipsisa32r2-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa32r2-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa32r2-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa32r2-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa32r2-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa32r2-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa32r2el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa32r2el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa32r2el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa32r2el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa32r2el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa32r2el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa32r3-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa32r3-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa32r3-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa32r3-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa32r3-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa32r3-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa32r3el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa32r3el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa32r3el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa32r3el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa32r3el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa32r3el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa32r5-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa32r5-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa32r5-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa32r5-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa32r5-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa32r5-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa32r5el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa32r5el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa32r5el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa32r5el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa32r5el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa32r5el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa32r6-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa32r6-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa32r6-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa32r6-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa32r6-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa32r6-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa32r6el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa32r6el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa32r6el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa32r6el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa32r6el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa32r6el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa64r2-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa64r2-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa64r2-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa64r2-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa64r2-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa64r2-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa64r2el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa64r2el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa64r2el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa64r2el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa64r2el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa64r2el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa64r3-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa64r3-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa64r3-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa64r3-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa64r3-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa64r3-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa64r3el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa64r3el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa64r3el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa64r3el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa64r3el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa64r3el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa64r5-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa64r5-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa64r5-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa64r5-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa64r5-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa64r5-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa64r5el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa64r5el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa64r5el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa64r5el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa64r5el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa64r5el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa64r6-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa64r6-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa64r6-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa64r6-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa64r6-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa64r6-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa64r6el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa64r6el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa64r6el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 mipsisa64r6el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1 mipsisa64r6el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2 mipsisa64r6el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3 This is because the test cases rely on these ASEs being disabled for disassembly by default and expect instructions belonging to these ASEs not to be shown unless explicitly enabled. The `mips-xpa-virt-4' test case passes regardless, but we want it to verify the explicit options do work, so use the `mips:3000' machine to set the defaults there as well. binutils/ * testsuite/binutils-all/mips/mips-xpa-virt-1.d: Use `mips:3000' machine for disassembly. * testsuite/binutils-all/mips/mips-xpa-virt-2.d: Likewise. * testsuite/binutils-all/mips/mips-xpa-virt-3.d: Likewise. * testsuite/binutils-all/mips/mips-xpa-virt-4.d: Likewise.
2021-05-29 09:26:32 +08:00
#objdump: -d --prefix-addresses --show-raw-insn -m mips:3000 -M cp0-names=mips32
MIPS: Fix XPA base and Virtualization ASE instruction handling Correct a commit 7d64c587c15f ("Add support for the MIPS eXtended Physical Address (XPA) ASE.") bug, causing XPA base and Virtualization ASE instructions to be wrongly always enabled with the selection of the MIPS32r2 or higher ISA. For example this source assembles successfully as shown below: $ cat xpa.s mfhc0 $2, $1 $ as -32 -mips32 -o xpa.o xpa.s xpa.s: Assembler messages: xpa.s:1: Error: opcode not supported on this processor: mips32 (mips32) `mfhc0 $2,$1' $ as -32 -mips32r2 -o xpa.o xpa.s $ objdump -d xpa.o xpa.o: file format elf32-tradbigmips Disassembly of section .text: 00000000 <.text>: 0: 40420800 mfhc0 v0,c0_random ... $ To address this issue remove the I33 (INSN_ISA32R2) marking from all XPA instructions in the opcode table. Additionally, for XPA Virtualization ASE instructions implement an XPAVZ (ASE_XPA_VIRT) combination ASE flag and use it in place of IVIRT|XPA (ASE_VIRT|ASE_XPA). Now the same source is correctly rejected unless the `-mxpa' option is also used: $ as -32 -mips32r2 -o xpa.o xpa.s xpa.s: Assembler messages: xpa.s:1: Error: opcode not supported on this processor: mips32r2 (mips32r2) `mfhc0 $2,$1' $ as -32 -mips32r2 -mxpa -o xpa.o xpa.s $ Add test cases for XPA base and XPA Virtualization ASE instructions. Parts of this change by Andrew Bennett. include/ * opcode/mips.h (ASE_XPA_VIRT): New macro. opcodes/ * mips-dis.c (mips_calculate_combination_ases): Handle the ASE_XPA_VIRT flag. (parse_mips_ase_option): New function. (parse_mips_dis_option): Factor out ASE option handling to the new function. Call `mips_calculate_combination_ases'. * mips-opc.c (XPAVZ): New macro. (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0", "mfhgc0", "mthc0" and "mthgc0". gas/ * config/tc-mips.c (mips_set_ase): Handle the ASE_XPA_VIRT flag. * testsuite/gas/mips/xpa.d: Remove `xpa' from `-M' in `objdump' flags. Add `-mvirt' to `as' flags. * testsuite/gas/mips/xpa-err.d: New test. * testsuite/gas/mips/xpa-virt-err.d: New test. * testsuite/gas/mips/xpa-err.l: New stderr output. * testsuite/gas/mips/xpa-virt-err.l: New stderr output. * testsuite/gas/mips/xpa-err.s: New test source. * testsuite/gas/mips/xpa-virt-err.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. binutils/ * testsuite/binutils-all/mips/mips-xpa-virt-1.d: New test. * testsuite/binutils-all/mips/mips-xpa-virt-2.d: New test. * testsuite/binutils-all/mips/mips-xpa-virt-3.d: New test. * testsuite/binutils-all/mips/mips-xpa-virt-4.d: New test. * testsuite/binutils-all/mips/mips-xpa-virt.s: New test source. * testsuite/binutils-all/mips/mips.exp: Run the new tests.
2017-06-30 14:21:55 +08:00
#name: MIPS XPA and Virtualization ASE instruction disassembly 1
#source: mips-xpa-virt.s
.*: +file format .*mips.*
Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 40020800 mfc0 v0,c0_random
MIPS/opcodes: Do not use CP0 register names for control registers The CP0 control register set has never been defined, however encodings for the CFC0 and CTC0 instructions remained available for implementers up until the MIPS32 ISA declared them invalid and causing the Reserved Instruction exception[1]. Therefore we handle them for both assembly and disassembly, however in the latter case the names of CP0 registers from the regular set are incorrectly printed if named registers are requested. This is because we do not define separate operand classes for coprocessor regular and control registers respectively, which means the disassembler has no way to tell the two cases apart. Consequently nonsensical disassembly is produced like: cfc0 v0,c0_random Later the MIPSr5 ISA reused the encodings for XPA ASE MFHC0 and MTHC0 instructions[2] although it failed to document them in the relevant opcode table until MIPSr6 only. Correct the issue then by defining a new register class, OP_REG_CONTROL, and corresponding operand codes, `g' and `y' for the two positions in the machine instruction a control register operand can take. Adjust the test cases affected accordingly. While at it swap the regular MIPS opcode table "cfc0" and "ctc0" entries with each other so that they come in the alphabetical order. References: [1] "MIPS32 Architecture For Programmers, Volume II: The MIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, Revision 1.00, August 29, 2002, Table A-9 "MIPS32 COP0 Encoding of rs Field", p. 242 [2] "MIPS Architecture For Programmers, Volume II-A: The MIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, Revision 5.04, December 11, 2013, Section 3.2 "Alphabetical List of Instructions", pp. 195, 216 include/ * opcode/mips.h: Document `g' and `y' operand codes. (mips_reg_operand_type): Add OP_REG_CONTROL enumeration constant. gas/ * tc-mips.c (convert_reg_type) <OP_REG_CONTROL>: New case. (macro) <M_TRUNCWS, M_TRUNCWD>: Use the `g' rather than `G' operand code. opcodes/ * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register handling code over to... <OP_REG_CONTROL>: ... this new case. * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases. (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2", "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries replacing the `G' operand code with `g'. Update "cftc1" and "cftc2" entries replacing the `E' operand code with `y'. * micromips-opc.c (decode_micromips_operand) <'g'>: New case. (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2" entries replacing the `G' operand code with `g'. binutils/ * testsuite/binutils-all/mips/mips-xpa-virt-1.d: Correct CFC0 operand disassembly. * testsuite/binutils-all/mips/mips-xpa-virt-3.d: Likewise.
2021-05-29 09:26:32 +08:00
[0-9a-f]+ <[^>]*> 40420800 cfc0 v0,\$1
MIPS: Fix XPA base and Virtualization ASE instruction handling Correct a commit 7d64c587c15f ("Add support for the MIPS eXtended Physical Address (XPA) ASE.") bug, causing XPA base and Virtualization ASE instructions to be wrongly always enabled with the selection of the MIPS32r2 or higher ISA. For example this source assembles successfully as shown below: $ cat xpa.s mfhc0 $2, $1 $ as -32 -mips32 -o xpa.o xpa.s xpa.s: Assembler messages: xpa.s:1: Error: opcode not supported on this processor: mips32 (mips32) `mfhc0 $2,$1' $ as -32 -mips32r2 -o xpa.o xpa.s $ objdump -d xpa.o xpa.o: file format elf32-tradbigmips Disassembly of section .text: 00000000 <.text>: 0: 40420800 mfhc0 v0,c0_random ... $ To address this issue remove the I33 (INSN_ISA32R2) marking from all XPA instructions in the opcode table. Additionally, for XPA Virtualization ASE instructions implement an XPAVZ (ASE_XPA_VIRT) combination ASE flag and use it in place of IVIRT|XPA (ASE_VIRT|ASE_XPA). Now the same source is correctly rejected unless the `-mxpa' option is also used: $ as -32 -mips32r2 -o xpa.o xpa.s xpa.s: Assembler messages: xpa.s:1: Error: opcode not supported on this processor: mips32r2 (mips32r2) `mfhc0 $2,$1' $ as -32 -mips32r2 -mxpa -o xpa.o xpa.s $ Add test cases for XPA base and XPA Virtualization ASE instructions. Parts of this change by Andrew Bennett. include/ * opcode/mips.h (ASE_XPA_VIRT): New macro. opcodes/ * mips-dis.c (mips_calculate_combination_ases): Handle the ASE_XPA_VIRT flag. (parse_mips_ase_option): New function. (parse_mips_dis_option): Factor out ASE option handling to the new function. Call `mips_calculate_combination_ases'. * mips-opc.c (XPAVZ): New macro. (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0", "mfhgc0", "mthc0" and "mthgc0". gas/ * config/tc-mips.c (mips_set_ase): Handle the ASE_XPA_VIRT flag. * testsuite/gas/mips/xpa.d: Remove `xpa' from `-M' in `objdump' flags. Add `-mvirt' to `as' flags. * testsuite/gas/mips/xpa-err.d: New test. * testsuite/gas/mips/xpa-virt-err.d: New test. * testsuite/gas/mips/xpa-err.l: New stderr output. * testsuite/gas/mips/xpa-virt-err.l: New stderr output. * testsuite/gas/mips/xpa-err.s: New test source. * testsuite/gas/mips/xpa-virt-err.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. binutils/ * testsuite/binutils-all/mips/mips-xpa-virt-1.d: New test. * testsuite/binutils-all/mips/mips-xpa-virt-2.d: New test. * testsuite/binutils-all/mips/mips-xpa-virt-3.d: New test. * testsuite/binutils-all/mips/mips-xpa-virt-4.d: New test. * testsuite/binutils-all/mips/mips-xpa-virt.s: New test source. * testsuite/binutils-all/mips/mips.exp: Run the new tests.
2017-06-30 14:21:55 +08:00
[0-9a-f]+ <[^>]*> 40620800 0x40620800
[0-9a-f]+ <[^>]*> 40620c00 0x40620c00
\.\.\.
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