2016-05-11 20:24:05 +08:00
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#source: tlsopt5_32.s
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#as: -a32
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2017-07-14 17:07:26 +08:00
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#ld: -shared --gc-sections --secure-plt tlsdll32.so
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2016-05-11 20:24:05 +08:00
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#objdump: -dr
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#target: powerpc*-*-*
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.*
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Disassembly of section \.text:
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2017-08-06 20:34:25 +08:00
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.* <_start>:
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2017-07-14 17:07:26 +08:00
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.*: (f0 ff 21 94|94 21 ff f0) stwu r1,-16\(r1\)
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.*: (a6 02 08 7c|7c 08 02 a6) mflr r0
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.*: (05 00 9f 42|42 9f 00 05) bcl .*
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.*: (08 00 c1 93|93 c1 00 08) stw r30,8\(r1\)
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.*: (a6 02 c8 7f|7f c8 02 a6) mflr r30
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.*: (01 00 de 3f|3f de 00 01) addis r30,r30,1
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.*: (14 00 01 90|90 01 00 14) stw r0,20\(r1\)
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2017-08-06 20:34:25 +08:00
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.*: (.. .. de 3b|3b de .. ..) addi r30,r30,.*
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2017-07-14 17:07:26 +08:00
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.*: (f8 ff 7e 38|38 7e ff f8) addi r3,r30,-8
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2017-08-06 20:34:25 +08:00
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.*: (1d 00 00 48|48 00 00 1d) bl .* <.*__tls_get_addr_opt.*>
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2017-07-14 17:07:26 +08:00
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.*: (14 00 01 80|80 01 00 14) lwz r0,20\(r1\)
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.*: (08 00 c1 83|83 c1 00 08) lwz r30,8\(r1\)
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.*: (a6 03 08 7c|7c 08 03 a6) mtlr r0
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.*: (10 00 21 38|38 21 00 10) addi r1,r1,16
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.*: (20 00 80 4e|4e 80 00 20) blr
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.*
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2016-05-11 20:24:05 +08:00
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2017-08-06 20:34:25 +08:00
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.* <.*__tls_get_addr_opt.*>:
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2016-05-11 20:24:05 +08:00
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.*: (00 00 63 81|81 63 00 00) lwz r11,0\(r3\)
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.*: (04 00 83 81|81 83 00 04) lwz r12,4\(r3\)
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.*: (78 1b 60 7c|7c 60 1b 78) mr r0,r3
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.*: (00 00 0b 2c|2c 0b 00 00) cmpwi r11,0
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.*: (14 12 6c 7c|7c 6c 12 14) add r3,r12,r2
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.*: (20 00 82 4d|4d 82 00 20) beqlr
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.*: (78 03 03 7c|7c 03 03 78) mr r3,r0
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.*: (00 00 00 60|60 00 00 00) nop
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2017-07-14 17:07:26 +08:00
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.*: (0c 00 7e 81|81 7e 00 0c) lwz r11,12\(r30\)
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2016-05-11 20:24:05 +08:00
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.*: (a6 03 69 7d|7d 69 03 a6) mtctr r11
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.*: (20 04 80 4e|4e 80 04 20) bctr
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2017-07-14 17:07:26 +08:00
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.*: (00 00 00 60|60 00 00 00) nop
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2016-05-11 20:24:05 +08:00
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PowerPC PLT stub tidy
This is in preparation for the next patch adding Spectre variant 2
mitigation for PowerPC and PowerPC64. Besides tidying code involved
in stub output (to reduce the number of places where bctr is output),
the patch adds some user visible features:
1) PowerPC64 ELFv2 global entry stubs now are aligned under the
control of --plt-align, with a default alignment of 32 bytes.
2) PowerPC64 __glink_PLTresolve is no longer padded out with nops.
3) PowerPC32 PLT stubs are aligned under the control of --plt-align,
with the default alignment being 16 bytes as before.
4) The PowerPC32 branch/nop table emitted before __glink_PLTresolve
is now smaller in many cases. It was sized incorrectly when the
__tls_get_addr_opt stub was used, and unnecessarily included space
for local ifuncs.
bfd/
* elf32-ppc.c (GLINK_ENTRY_SIZE): Add parameters, handle
__tls_get_addr_opt, and alignment sizing.
(TLS_GET_ADDR_GLINK_SIZE): Delete.
(is_nonpic_glink_stub): Don't use GLINK_ENTRY_SIZE.
(ppc_elf_get_synthetic_symtab): Recognize stubs spaced at 4, 6,
or 8 insns.
(ppc_elf_link_hash_table_create): Init new ppc_elf_params field.
(allocate_dynrelocs): Use new GLINK_ENTRY_SIZE.
(ppc_elf_size_dynamic_sections): Likewise. Size branch table
by PLT reloc count.
(write_glink_stub): Handle __tls_get_addr_opt stub.
Pad out to size given by GLINK_ENTRY_SIZE.
(ppc_elf_relocate_section): Adjust write_glink_stub call.
(ppc_elf_finish_dynamic_symbol): Likewise.
(ppc_elf_finish_dynamic_sections): Write PLTresolve without using
insn array since so many need rewriting.
* elf32-ppc.h (struct ppc_elf_params): Add plt_stub_align.
* elf64-ppc.c (GLINK_PLTRESOLVE_SIZE): Rename from
GLINK_CALL_STUB_SIZE. Add htab param and evaluate to size without
nops. Adjust all uses.
(ppc64_elf_get_synthetic_symtab): Don't use GLINK_CALL_STUB_SIZE
in glink_vma calculation.
(struct ppc_link_hash_table): Add global_entry section pointer.
(create_linkage_sections): Create separate section for global
entry stubs.
(PPC_LO, PPC_HI, PPC_HA): Move earlier.
(size_global_entry_stubs): Handle sizing for aligned stubs.
(ppc64_elf_size_dynamic_sections): Handle global_entry alloc,
and don't stash end of glink branch table in rawsize.
(ppc_build_one_stub): Rewrite stub size calculations.
(build_global_entry_stubs): Use new section.
(ppc64_elf_build_stubs): Don't pad __glink_PLTresolve with nops.
Build lazy link stubs out to end of section. Build global entry
stubs in new section.
gold/
* options.h (plt_align): Support for PowerPC32 too.
* powerpc.cc (Stub_table::stub_align): Heed --plt-align for 32-bit.
(Stub_table::plt_call_size, branch_stub_size): Tidy.
(Stub_table::plt_call_align): Implement using stub_align.
(Output_data_glink::global_entry_align): New function.
(Output_data_glink::global_entry_off): New function.
(Output_data_glink::global_entry_address): Use global_entry_off.
(Output_data_glink::pltresolve_size): New function, replacing
pltresolve_size_ constant. Update all uses.
(Output_data_glink::add_global_entry): Align offset.
(Output_data_glink::set_final_data_size): Use global_entry_align.
(Stub_table::do_write): Don't pad __glink_PLTrelsolve with nops.
Tidy stub output. Use global_entry_off.
ld/
* emultempl/ppc32elf.em (params): Init new field.
(enum ppc32_opt): New enum to define OPTION_* values. Add
OPTION_PLT_ALIGN and OPTION_NO_PLT_ALIGN.
(PARSE_AND_LIST_LONGOPTS): Handle new options.
(PARSE_AND_LIST_ARGS_CASES): Likewise.
(PARSE_AND_LIST_OPTIONS): Likewise. Break up help output.
* emultempl/ppc64elf.em (ppc_add_stub_section): Init alignment
correctly for negative --plt-stub-align.
* testsuite/ld-powerpc/elfv2exe.d,
* testsuite/ld-powerpc/elfv2so.d,
* testsuite/ld-powerpc/relbrlt.d,
* testsuite/ld-powerpc/relbrlt.s,
* testsuite/ld-powerpc/tlsexe.d,
* testsuite/ld-powerpc/tlsexe.r,
* testsuite/ld-powerpc/tlsexe32.d,
* testsuite/ld-powerpc/tlsexe32.g,
* testsuite/ld-powerpc/tlsexe32.r,
* testsuite/ld-powerpc/tlsexetoc.d,
* testsuite/ld-powerpc/tlsexetoc.r,
* testsuite/ld-powerpc/tlsopt5_32.d,
* testsuite/ld-powerpc/tlsso.d,
* testsuite/ld-powerpc/tlstocso.d: Update for changed stub order.
2018-01-13 16:23:41 +08:00
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.* <__glink(_PLTresolve)?>:
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2017-07-14 17:07:26 +08:00
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.*: (00 00 6b 3d|3d 6b 00 00) addis r11,r11,0
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.*: (a6 02 08 7c|7c 08 02 a6) mflr r0
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.*: (05 00 9f 42|42 9f 00 05) bcl .*
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PowerPC PLT stub tidy
This is in preparation for the next patch adding Spectre variant 2
mitigation for PowerPC and PowerPC64. Besides tidying code involved
in stub output (to reduce the number of places where bctr is output),
the patch adds some user visible features:
1) PowerPC64 ELFv2 global entry stubs now are aligned under the
control of --plt-align, with a default alignment of 32 bytes.
2) PowerPC64 __glink_PLTresolve is no longer padded out with nops.
3) PowerPC32 PLT stubs are aligned under the control of --plt-align,
with the default alignment being 16 bytes as before.
4) The PowerPC32 branch/nop table emitted before __glink_PLTresolve
is now smaller in many cases. It was sized incorrectly when the
__tls_get_addr_opt stub was used, and unnecessarily included space
for local ifuncs.
bfd/
* elf32-ppc.c (GLINK_ENTRY_SIZE): Add parameters, handle
__tls_get_addr_opt, and alignment sizing.
(TLS_GET_ADDR_GLINK_SIZE): Delete.
(is_nonpic_glink_stub): Don't use GLINK_ENTRY_SIZE.
(ppc_elf_get_synthetic_symtab): Recognize stubs spaced at 4, 6,
or 8 insns.
(ppc_elf_link_hash_table_create): Init new ppc_elf_params field.
(allocate_dynrelocs): Use new GLINK_ENTRY_SIZE.
(ppc_elf_size_dynamic_sections): Likewise. Size branch table
by PLT reloc count.
(write_glink_stub): Handle __tls_get_addr_opt stub.
Pad out to size given by GLINK_ENTRY_SIZE.
(ppc_elf_relocate_section): Adjust write_glink_stub call.
(ppc_elf_finish_dynamic_symbol): Likewise.
(ppc_elf_finish_dynamic_sections): Write PLTresolve without using
insn array since so many need rewriting.
* elf32-ppc.h (struct ppc_elf_params): Add plt_stub_align.
* elf64-ppc.c (GLINK_PLTRESOLVE_SIZE): Rename from
GLINK_CALL_STUB_SIZE. Add htab param and evaluate to size without
nops. Adjust all uses.
(ppc64_elf_get_synthetic_symtab): Don't use GLINK_CALL_STUB_SIZE
in glink_vma calculation.
(struct ppc_link_hash_table): Add global_entry section pointer.
(create_linkage_sections): Create separate section for global
entry stubs.
(PPC_LO, PPC_HI, PPC_HA): Move earlier.
(size_global_entry_stubs): Handle sizing for aligned stubs.
(ppc64_elf_size_dynamic_sections): Handle global_entry alloc,
and don't stash end of glink branch table in rawsize.
(ppc_build_one_stub): Rewrite stub size calculations.
(build_global_entry_stubs): Use new section.
(ppc64_elf_build_stubs): Don't pad __glink_PLTresolve with nops.
Build lazy link stubs out to end of section. Build global entry
stubs in new section.
gold/
* options.h (plt_align): Support for PowerPC32 too.
* powerpc.cc (Stub_table::stub_align): Heed --plt-align for 32-bit.
(Stub_table::plt_call_size, branch_stub_size): Tidy.
(Stub_table::plt_call_align): Implement using stub_align.
(Output_data_glink::global_entry_align): New function.
(Output_data_glink::global_entry_off): New function.
(Output_data_glink::global_entry_address): Use global_entry_off.
(Output_data_glink::pltresolve_size): New function, replacing
pltresolve_size_ constant. Update all uses.
(Output_data_glink::add_global_entry): Align offset.
(Output_data_glink::set_final_data_size): Use global_entry_align.
(Stub_table::do_write): Don't pad __glink_PLTrelsolve with nops.
Tidy stub output. Use global_entry_off.
ld/
* emultempl/ppc32elf.em (params): Init new field.
(enum ppc32_opt): New enum to define OPTION_* values. Add
OPTION_PLT_ALIGN and OPTION_NO_PLT_ALIGN.
(PARSE_AND_LIST_LONGOPTS): Handle new options.
(PARSE_AND_LIST_ARGS_CASES): Likewise.
(PARSE_AND_LIST_OPTIONS): Likewise. Break up help output.
* emultempl/ppc64elf.em (ppc_add_stub_section): Init alignment
correctly for negative --plt-stub-align.
* testsuite/ld-powerpc/elfv2exe.d,
* testsuite/ld-powerpc/elfv2so.d,
* testsuite/ld-powerpc/relbrlt.d,
* testsuite/ld-powerpc/relbrlt.s,
* testsuite/ld-powerpc/tlsexe.d,
* testsuite/ld-powerpc/tlsexe.r,
* testsuite/ld-powerpc/tlsexe32.d,
* testsuite/ld-powerpc/tlsexe32.g,
* testsuite/ld-powerpc/tlsexe32.r,
* testsuite/ld-powerpc/tlsexetoc.d,
* testsuite/ld-powerpc/tlsexetoc.r,
* testsuite/ld-powerpc/tlsopt5_32.d,
* testsuite/ld-powerpc/tlsso.d,
* testsuite/ld-powerpc/tlstocso.d: Update for changed stub order.
2018-01-13 16:23:41 +08:00
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.*: (0c 00 6b 39|39 6b 00 0c) addi r11,r11,12
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2017-07-14 17:07:26 +08:00
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.*: (a6 02 88 7d|7d 88 02 a6) mflr r12
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.*: (a6 03 08 7c|7c 08 03 a6) mtlr r0
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.*: (50 58 6c 7d|7d 6c 58 50) subf r11,r12,r11
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.*: (01 00 8c 3d|3d 8c 00 01) addis r12,r12,1
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2017-08-06 20:34:25 +08:00
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.*: (.. .. 0c 80|80 0c .. ..) lwz r0,.*\(r12\)
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.*: (.. .. 8c 81|81 8c .. ..) lwz r12,.*\(r12\)
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2016-05-11 20:24:05 +08:00
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.*: (a6 03 09 7c|7c 09 03 a6) mtctr r0
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.*: (14 5a 0b 7c|7c 0b 5a 14) add r0,r11,r11
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.*: (14 5a 60 7d|7d 60 5a 14) add r11,r0,r11
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.*: (20 04 80 4e|4e 80 04 20) bctr
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.*: (00 00 00 60|60 00 00 00) nop
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.*: (00 00 00 60|60 00 00 00) nop
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