mirror/binutils-gdb
2
0
Fork 0
mirror of https://sourceware.org/git/binutils-gdb.git synced 2025-01-12 12:16:04 +08:00
Code Issues Packages Projects Releases Wiki Activity
80d49d6a1b
binutils-gdb/ld/testsuite/ld-arm/thumb-plt-got.d

15 lines
522 B
D
Raw Normal View History

Arm: Fix LSB of GOT for Thumb2 only PLT. When you have a Thumb only PLT then the address in the GOT for PLT0 needs to have the Thumb bit set since the instruction used in PLTn to get there is `ldr.w pc` which is an inter-working instruction: the PLT sequence in question is 00000120 <foo@plt>: 120: f240 0c98 movw ip, #152 ; 0x98 124: f2c0 0c01 movt ip, #1 128: 44fc add ip, pc 12a: f8dc f000 ldr.w pc, [ip] 12e: e7fc b.n 12a <foo@plt+0xa> Disassembly of section .text: 00000130 <bar>: 130: b580 push {r7, lr} 132: af00 add r7, sp, #0 134: f7ff fff4 bl 120 <foo@plt> and previously the linker would generate Hex dump of section '.got': ... 0x000101b8 40010100 00000000 00000000 10010000 @............... Which would make it jump and transition out of thumb mode and crash since you only have thumb mode on such cores. Now it correctly generates Hex dump of section '.got': ... 0x000101b8 40010100 00000000 00000000 11010000 @............... Thanks to Amol for testing patch and to rgujju for reporting it. bfd/ChangeLog: PR ld/16017 * elf32-arm.c (elf32_arm_populate_plt_entry): Set LSB of the PLT0 address in the GOT if in thumb only mode. ld/ChangeLog: PR ld/16017 * testsuite/ld-arm/arm-elf.exp (thumb-plt-got): New. * testsuite/ld-arm/thumb-plt-got.d: New test.
2020-04-01 17:47:18 +08:00
#source: thumb-plt.s
#name: Thumb only PLT and GOT LSB Symbol
#ld: -shared -e0
#readelf: -rx .got
#skip: *-*-pe *-*-wince *-*-vxworks armeb-*-* *-*-gnueabihf
Relocation section '.rel.plt' at offset 0x108 contains 1 entry:
Offset Info Type Sym.Value Sym. Name
AArch64: Relax thumb-plt testcases regexpr. The regexpr in these two files are a bit strict in that they don't account for the slight changes in tags in certain arm targets which cause our address offsets to change. This changes the tests to allow slight movement in locations while still strictly checking the rest. ld/ChangeLog: 2020-08-03 Tamar Christina <tamar.christina@arm.com> * testsuite/ld-arm/thumb-plt-got.d: Relax regexpr. * testsuite/ld-arm/thumb-plt.d: Likewise.
2020-08-14 14:51:03 +08:00
000101.+ 00000116 R_ARM_JUMP_SLOT 00000000 foo
Arm: Fix LSB of GOT for Thumb2 only PLT. When you have a Thumb only PLT then the address in the GOT for PLT0 needs to have the Thumb bit set since the instruction used in PLTn to get there is `ldr.w pc` which is an inter-working instruction: the PLT sequence in question is 00000120 <foo@plt>: 120: f240 0c98 movw ip, #152 ; 0x98 124: f2c0 0c01 movt ip, #1 128: 44fc add ip, pc 12a: f8dc f000 ldr.w pc, [ip] 12e: e7fc b.n 12a <foo@plt+0xa> Disassembly of section .text: 00000130 <bar>: 130: b580 push {r7, lr} 132: af00 add r7, sp, #0 134: f7ff fff4 bl 120 <foo@plt> and previously the linker would generate Hex dump of section '.got': ... 0x000101b8 40010100 00000000 00000000 10010000 @............... Which would make it jump and transition out of thumb mode and crash since you only have thumb mode on such cores. Now it correctly generates Hex dump of section '.got': ... 0x000101b8 40010100 00000000 00000000 11010000 @............... Thanks to Amol for testing patch and to rgujju for reporting it. bfd/ChangeLog: PR ld/16017 * elf32-arm.c (elf32_arm_populate_plt_entry): Set LSB of the PLT0 address in the GOT if in thumb only mode. ld/ChangeLog: PR ld/16017 * testsuite/ld-arm/arm-elf.exp (thumb-plt-got): New. * testsuite/ld-arm/thumb-plt-got.d: New test.
2020-04-01 17:47:18 +08:00
Hex dump of section '.got':
NOTE: This section has relocations against it, but these have NOT been applied to this dump.
AArch64: Relax thumb-plt testcases regexpr. The regexpr in these two files are a bit strict in that they don't account for the slight changes in tags in certain arm targets which cause our address offsets to change. This changes the tests to allow slight movement in locations while still strictly checking the rest. ld/ChangeLog: 2020-08-03 Tamar Christina <tamar.christina@arm.com> * testsuite/ld-arm/thumb-plt-got.d: Relax regexpr. * testsuite/ld-arm/thumb-plt.d: Likewise.
2020-08-14 14:51:03 +08:00
0x000101.+ 40010100 00000000 00000000 11010000 @...............
Arm: Fix LSB of GOT for Thumb2 only PLT. When you have a Thumb only PLT then the address in the GOT for PLT0 needs to have the Thumb bit set since the instruction used in PLTn to get there is `ldr.w pc` which is an inter-working instruction: the PLT sequence in question is 00000120 <foo@plt>: 120: f240 0c98 movw ip, #152 ; 0x98 124: f2c0 0c01 movt ip, #1 128: 44fc add ip, pc 12a: f8dc f000 ldr.w pc, [ip] 12e: e7fc b.n 12a <foo@plt+0xa> Disassembly of section .text: 00000130 <bar>: 130: b580 push {r7, lr} 132: af00 add r7, sp, #0 134: f7ff fff4 bl 120 <foo@plt> and previously the linker would generate Hex dump of section '.got': ... 0x000101b8 40010100 00000000 00000000 10010000 @............... Which would make it jump and transition out of thumb mode and crash since you only have thumb mode on such cores. Now it correctly generates Hex dump of section '.got': ... 0x000101b8 40010100 00000000 00000000 11010000 @............... Thanks to Amol for testing patch and to rgujju for reporting it. bfd/ChangeLog: PR ld/16017 * elf32-arm.c (elf32_arm_populate_plt_entry): Set LSB of the PLT0 address in the GOT if in thumb only mode. ld/ChangeLog: PR ld/16017 * testsuite/ld-arm/arm-elf.exp (thumb-plt-got): New. * testsuite/ld-arm/thumb-plt-got.d: New test.
2020-04-01 17:47:18 +08:00
Reference in New Issue Copy Permalink