binutils-gdb/ld/testsuite/ld-aarch64/erratum843419_tls_ie.s

	.text
	.align  2
	.global main
	.type   main, %function
main:
	sub     sp, sp, #16
	mov     x7, 13
	str     w7, [sp,12]
	b       farbranch
	ret
	.size   main, .-main

	.section .e843419, "xa"
	.align  2
	.global farbranch
	.type   farbranch, %function
farbranch:
	sub     sp, sp, #16
	mov     x7, 13
	str     w7, [sp,12]
	b       e843419
	 .fill 4072,1,0
e843419:
	adrp x0, :gottprel:l_tlsievar
	str x7, [x0,12]
	mov	x8, 9
	str x8, [x0, :gottprel_lo12:l_tlsievar]

	add x0, x1, x5
	ldr     w7, [sp,12]
	add     w0, w7, w7
	add     sp, sp, 16
	ret
	.size   farbranch, .-farbranch

# ---

	.section	.tbss,"awT",%nobits
	.align  2
	.type   l_tlsievar, %object
	.size   l_tlsievar, 4
l_tlsievar:
	.zero   4
AArch64: Fix regression in Cortex A53 erratum when PIE. (PR ld/23904) The fix for PR ld/22263 causes TLS relocations using ADRP to be relaxed into MOVZ, however this causes issues for the erratum code. The erratum code scans the input sections looking for ADRP instructions and notes their location in the stream. It then later tries to find them again in order to generate the linker stubs. Due to the relaxation it instead finds a MOVZ and hard aborts. Since this relaxation is a valid one, and in which case the erratum no longer applies, it shouldn't abort but instead just continue. This changes the TLS relaxation code such that when it finds an ADRP and it relaxes it, it removes the erratum entry from the work list by changing the stub type into none so the stub is ignored. The entry is not actually removed as removal is a more expensive operation and we have already allocated the memory anyway. The clearing is done for IE->LE and GD->LE relaxations, and a testcase is added for the IE case. The GD case I believe to be impossible to get together with the erratum sequence due to the required BL which would break the sequence. However to cover all basis I have added the guard there as well. build on native hardware and regtested on aarch64-none-elf, aarch64-none-elf (32 bit host), aarch64-none-linux-gnu, aarch64-none-linux-gnu (32 bit host) Cross-compiled and regtested on aarch64-none-linux-gnu, aarch64_be-none-linux-gnu Testcase in PR23940 tested and works as expected now and benchmarks ran on A53 showing no regressions and no issues. bfd/ChangeLog: PR ld/23904 * elfnn-aarch64.c (_bfd_aarch64_adrp_p): Use existing constants. (_bfd_aarch64_erratum_843419_branch_to_stub): Use _bfd_aarch64_adrp_p. (struct erratum_835769_branch_to_stub_clear_data): New. (_bfd_aarch64_erratum_843419_clear_stub): New. (clear_erratum_843419_entry): New. (elfNN_aarch64_tls_relax): Use it. (elfNN_aarch64_relocate_section): Pass input_section. (aarch64_map_one_stub): Handle branch type none as valid. ld/ChangeLog: PR ld/23904 * testsuite/ld-aarch64/aarch64-elf.exp: Add erratum843419_tls_ie. * testsuite/ld-aarch64/erratum843419_tls_ie.d: New test. * testsuite/ld-aarch64/erratum843419_tls_ie.s: New test. 2018-11-27 20:33:21 +08:00			`.text`
			`.align 2`
			`.global main`
			`.type main, %function`
			`main:`
			`sub sp, sp, #16`
			`mov x7, 13`
			`str w7, [sp,12]`
			`b farbranch`
			`ret`
			`.size main, .-main`

			`.section .e843419, "xa"`
			`.align 2`
			`.global farbranch`
			`.type farbranch, %function`
			`farbranch:`
			`sub sp, sp, #16`
			`mov x7, 13`
			`str w7, [sp,12]`
			`b e843419`
			`.fill 4072,1,0`
			`e843419:`
			`adrp x0, :gottprel:l_tlsievar`
			`str x7, [x0,12]`
			`mov x8, 9`
			`str x8, [x0, :gottprel_lo12:l_tlsievar]`

			`add x0, x1, x5`
			`ldr w7, [sp,12]`
			`add w0, w7, w7`
			`add sp, sp, 16`
			`ret`
			`.size farbranch, .-farbranch`

			`# ---`

			`.section .tbss,"awT",%nobits`
			`.align 2`
			`.type l_tlsievar, %object`
			`.size l_tlsievar, 4`
			`l_tlsievar:`
			`.zero 4`