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82 lines
1.5 KiB
ArmAsm
82 lines
1.5 KiB
ArmAsm
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//Original:/testcases/core/c_ldimmhalf_lz_dr/c_ldimmhalf_lz_dr.dsp
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// Spec Reference: ldimmhalf lz dreg
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# mach: bfin
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.include "testutils.inc"
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start
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INIT_R_REGS -1;
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// test Dreg
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R0 = 0x0001 (Z);
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R1 = 0x0003 (Z);
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R2 = 0x0005 (Z);
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R3 = 0x0007 (Z);
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R4 = 0x0009 (Z);
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R5 = 0x000b (Z);
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R6 = 0x000d (Z);
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R7 = 0x000f (Z);
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CHECKREG r0, 0x00000001;
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CHECKREG r1, 0x00000003;
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CHECKREG r2, 0x00000005;
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CHECKREG r3, 0x00000007;
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CHECKREG r4, 0x00000009;
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CHECKREG r5, 0x0000000b;
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CHECKREG r6, 0x0000000d;
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CHECKREG r7, 0x0000000f;
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R0 = 0x0010 (Z);
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R1 = 0x0030 (Z);
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R2 = 0x0050 (Z);
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R3 = 0x0070 (Z);
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R4 = 0x0090 (Z);
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R5 = 0x00b0 (Z);
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R6 = 0x00d0 (Z);
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R7 = 0x00f0 (Z);
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CHECKREG r0, 0x00000010;
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CHECKREG r1, 0x00000030;
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CHECKREG r2, 0x00000050;
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CHECKREG r3, 0x00000070;
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CHECKREG r4, 0x00000090;
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CHECKREG r5, 0x000000b0;
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CHECKREG r6, 0x000000d0;
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CHECKREG r7, 0x000000f0;
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R0 = 0x0100 (Z);
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R1 = 0x0300 (Z);
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R2 = 0x0500 (Z);
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R3 = 0x0700 (Z);
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R4 = 0x0900 (Z);
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R5 = 0x0b00 (Z);
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R6 = 0x0d00 (Z);
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R7 = 0x0f00 (Z);
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CHECKREG r0, 0x00000100;
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CHECKREG r1, 0x00000300;
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CHECKREG r2, 0x00000500;
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CHECKREG r3, 0x00000700;
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CHECKREG r4, 0x00000900;
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CHECKREG r5, 0x00000b00;
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CHECKREG r6, 0x00000d00;
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CHECKREG r7, 0x00000f00;
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R0 = 0x1000 (Z);
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R1 = 0x3000 (Z);
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R2 = 0x5000 (Z);
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R3 = 0x7000 (Z);
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R4 = 0x9000 (Z);
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R5 = 0xb000 (Z);
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R6 = 0xd000 (Z);
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R7 = 0xf000 (Z);
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CHECKREG r0, 0x00001000;
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CHECKREG r1, 0x00003000;
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CHECKREG r2, 0x00005000;
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CHECKREG r3, 0x00007000;
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CHECKREG r4, 0x00009000;
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CHECKREG r5, 0x0000b000;
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CHECKREG r6, 0x0000d000;
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CHECKREG r7, 0x0000f000;
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pass
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