mirror of
https://sourceware.org/git/binutils-gdb.git
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127 lines
2.9 KiB
ArmAsm
127 lines
2.9 KiB
ArmAsm
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//Original:/testcases/core/c_dsp32shift_bxor/c_dsp32shift_bxor.dsp
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// Spec Reference: dsp32shift bxor
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# mach: bfin
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.include "testutils.inc"
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start
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R0 = 0;
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R1 = 58;
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A0 = R1;
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ASTAT = R0;
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imm32 r0, 0x12345678;
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imm32 r1, 0x22334455;
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imm32 r2, 0x66778890;
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imm32 r3, 0xaabbccdd;
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imm32 r4, 0x34567890;
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imm32 r5, 0xa2d3d5f6;
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imm32 r6, 0x456bda06;
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imm32 r7, 0x56789abc;
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R0.L = CC = BXORSHIFT( A0 , R0 );
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R1.L = CC = BXORSHIFT( A0 , R1 );
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R2.L = CC = BXORSHIFT( A0 , R2 );
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R3.L = CC = BXORSHIFT( A0 , R3 );
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R4.L = CC = BXORSHIFT( A0 , R4 );
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R5.L = CC = BXORSHIFT( A0 , R5 );
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R6.L = CC = BXORSHIFT( A0 , R6 );
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R7.L = CC = BXORSHIFT( A0 , R7 );
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CHECKREG r0, 0x12340001;
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CHECKREG r1, 0x22330001;
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CHECKREG r2, 0x66770000;
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CHECKREG r3, 0xAABB0001;
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CHECKREG r4, 0x34560000;
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CHECKREG r5, 0xA2D30000;
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CHECKREG r6, 0x456B0000;
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CHECKREG r7, 0x56780001;
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imm32 r0, 0xa1001001;
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imm32 r1, 0x1b001001;
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imm32 r2, 0x11c01002;
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imm32 r3, 0x110d1003;
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imm32 r4, 0x1100e004;
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imm32 r5, 0x11001f05;
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imm32 r6, 0x11001006;
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imm32 r7, 0x11001001;
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R5.L = CC = BXORSHIFT( A0 , R0 );
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R4.L = CC = BXORSHIFT( A0 , R1 );
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R2.L = CC = BXORSHIFT( A0 , R2 );
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R7.L = CC = BXORSHIFT( A0 , R3 );
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R0.L = CC = BXORSHIFT( A0 , R4 );
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R1.L = CC = BXORSHIFT( A0 , R5 );
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R3.L = CC = BXORSHIFT( A0 , R6 );
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R6.L = CC = BXORSHIFT( A0 , R7 );
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CHECKREG r0, 0xA1000000;
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CHECKREG r1, 0x1B000000;
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CHECKREG r2, 0x11C00001;
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CHECKREG r3, 0x110D0000;
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CHECKREG r4, 0x11000000;
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CHECKREG r5, 0x11000001;
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CHECKREG r6, 0x11000000;
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CHECKREG r7, 0x11000001;
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imm32 r0, 0xa2001001;
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imm32 r1, 0x1b341001;
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imm32 r2, 0x71c01002;
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imm32 r3, 0x810d1003;
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imm32 r4, 0x1600e004;
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imm32 r5, 0x41001405;
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imm32 r6, 0x31003006;
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imm32 r7, 0x21004671;
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R2.L = CC = BXOR( A0 , R0 );
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R3.L = CC = BXOR( A0 , R1 );
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R5.L = CC = BXOR( A0 , R2 );
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R6.L = CC = BXOR( A0 , R3 );
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R0.L = CC = BXOR( A0 , R4 );
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R1.L = CC = BXOR( A0 , R5 );
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R7.L = CC = BXOR( A0 , R6 );
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R4.L = CC = BXOR( A0 , R7 );
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CHECKREG r0, 0xA2000000;
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CHECKREG r1, 0x1B340000;
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CHECKREG r2, 0x71C00000;
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CHECKREG r3, 0x810D0000;
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CHECKREG r4, 0x16000000;
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CHECKREG r5, 0x41000000;
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CHECKREG r6, 0x31000001;
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CHECKREG r7, 0x21000000;
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imm32 r0, 0x4a502001;
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imm32 r1, 0x6b343001;
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imm32 r2, 0x71c04002;
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imm32 r3, 0x810d5003;
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imm32 r4, 0x5600e004;
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imm32 r5, 0x47001405;
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imm32 r6, 0x91003006;
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imm32 r7, 0xa1004671;
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A1 = R3;
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R0.L = CC = BXOR( A0 , A1, CC );
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A0 = BXORSHIFT( A0 , A1, CC );
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R1.L = CC = BXOR( A0 , A1, CC );
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A0 = BXORSHIFT( A0 , A1, CC );
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R2.L = CC = BXOR( A0 , A1, CC );
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A0 = BXORSHIFT( A0 , A1, CC );
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R3.L = CC = BXOR( A0 , A1, CC );
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A0 = BXORSHIFT( A0 , A1, CC );
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R4.L = CC = BXOR( A0 , A1, CC );
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A0 = BXORSHIFT( A0 , A1, CC );
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R5.L = CC = BXOR( A0 , A1, CC );
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A0 = BXORSHIFT( A0 , A1, CC );
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R6.L = CC = BXOR( A0 , A1, CC );
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A0 = BXORSHIFT( A0 , A1, CC );
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R7.L = CC = BXOR( A0 , A1, CC );
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A0 = BXORSHIFT( A0 , A1, CC );
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CHECKREG r0, 0x4A500001;
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CHECKREG r1, 0x6B340000;
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CHECKREG r2, 0x71C00000;
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CHECKREG r3, 0x810D0000;
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CHECKREG r4, 0x56000001;
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CHECKREG r5, 0x47000000;
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CHECKREG r6, 0x91000001;
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CHECKREG r7, 0xA1000001;
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pass
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