mirror of
https://sourceware.org/git/binutils-gdb.git
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212 lines
4.0 KiB
ArmAsm
212 lines
4.0 KiB
ArmAsm
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//Original:/testcases/core/c_alu2op_conv_h/c_alu2op_conv_h.dsp
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// Spec Reference: alu2op convert h
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# mach: bfin
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.include "testutils.inc"
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start
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imm32 r0, 0x00789abc;
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imm32 r1, 0x12345678;
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imm32 r2, 0x23456789;
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imm32 r3, 0x3456789a;
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imm32 r4, 0x856789ab;
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imm32 r5, 0x96789abc;
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imm32 r6, 0xa789abcd;
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imm32 r7, 0xb89abcde;
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R0 = R0.L (Z);
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R1 = R0.L (Z);
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R2 = R0.L (Z);
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R3 = R0.L (Z);
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R4 = R0.L (Z);
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R5 = R0.L (Z);
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R6 = R0.L (Z);
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R7 = R0.L (Z);
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CHECKREG r0, 0x00009ABC;
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CHECKREG r1, 0x00009ABC;
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CHECKREG r2, 0x00009ABC;
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CHECKREG r3, 0x00009ABC;
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CHECKREG r4, 0x00009ABC;
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CHECKREG r5, 0x00009ABC;
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CHECKREG r6, 0x00009ABC;
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CHECKREG r7, 0x00009ABC;
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imm32 r0, 0x01230002;
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imm32 r1, 0x00374659;
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imm32 r2, 0x93456789;
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imm32 r3, 0xa456789a;
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imm32 r4, 0xb56789ab;
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imm32 r5, 0xc6789abc;
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imm32 r6, 0xd789abcd;
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imm32 r7, 0xe89abcde;
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R0 = R1.L (Z);
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R2 = R1.L (Z);
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R3 = R1.L (Z);
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R4 = R1.L (Z);
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R5 = R1.L (Z);
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R6 = R1.L (Z);
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R7 = R1.L (Z);
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R1 = R1.L (Z);
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CHECKREG r0, 0x00004659;
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CHECKREG r1, 0x00004659;
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CHECKREG r2, 0x00004659;
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CHECKREG r3, 0x00004659;
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CHECKREG r4, 0x00004659;
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CHECKREG r5, 0x00004659;
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CHECKREG r6, 0x00004659;
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CHECKREG r7, 0x00004659;
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imm32 r0, 0x10789abc;
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imm32 r1, 0x11345678;
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imm32 r2, 0x93156789;
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imm32 r3, 0xd451789a;
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imm32 r4, 0x856719ab;
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imm32 r5, 0x267891bc;
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imm32 r6, 0xa789ab1d;
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imm32 r7, 0x989ab1de;
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R0 = R2.L (Z);
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R1 = R2.L (Z);
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R3 = R2.L (Z);
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R4 = R2.L (Z);
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R5 = R2.L (Z);
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R6 = R2.L (Z);
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R7 = R2.L (Z);
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R2 = R2.L (Z);
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CHECKREG r0, 0x00006789;
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CHECKREG r1, 0x00006789;
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CHECKREG r2, 0x00006789;
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CHECKREG r3, 0x00006789;
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CHECKREG r4, 0x00006789;
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CHECKREG r5, 0x00006789;
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CHECKREG r6, 0x00006789;
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CHECKREG r7, 0x00006789;
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imm32 r0, 0x21230002;
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imm32 r1, 0x02374659;
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imm32 r2, 0x93256789;
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imm32 r3, 0xa952789a;
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imm32 r4, 0xb59729ab;
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imm32 r5, 0xc67992bc;
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imm32 r6, 0xd7899b2d;
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imm32 r7, 0xe89ab9d2;
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R0 = R3.L (Z);
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R1 = R3.L (Z);
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R2 = R3.L (Z);
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R4 = R3.L (Z);
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R5 = R3.L (Z);
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R6 = R3.L (Z);
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R7 = R3.L (Z);
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R3 = R3.L (Z);
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CHECKREG r0, 0x0000789A;
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CHECKREG r1, 0x0000789A;
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CHECKREG r2, 0x0000789A;
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CHECKREG r3, 0x0000789A;
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CHECKREG r4, 0x0000789A;
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CHECKREG r5, 0x0000789A;
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CHECKREG r6, 0x0000789A;
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CHECKREG r7, 0x0000789A;
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imm32 r0, 0xa0789abc;
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imm32 r1, 0x1a345678;
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imm32 r2, 0x23a56789;
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imm32 r3, 0x645a789a;
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imm32 r4, 0x8667a9ab;
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imm32 r5, 0x96689abc;
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imm32 r6, 0xa787abad;
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imm32 r7, 0xb89a7cda;
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R0 = R4.L (Z);
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R1 = R4.L (Z);
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R2 = R4.L (Z);
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R3 = R4.L (Z);
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R4 = R4.L (Z);
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R5 = R4.L (Z);
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R6 = R4.L (Z);
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R7 = R4.L (Z);
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CHECKREG r0, 0x0000A9AB;
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CHECKREG r1, 0x0000A9AB;
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CHECKREG r2, 0x0000A9AB;
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CHECKREG r3, 0x0000A9AB;
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CHECKREG r4, 0x0000A9AB;
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CHECKREG r5, 0x0000A9AB;
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CHECKREG r6, 0x0000A9AB;
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CHECKREG r7, 0x0000A9AB;
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imm32 r0, 0xf1230002;
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imm32 r1, 0x0f374659;
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imm32 r2, 0x93f56789;
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imm32 r3, 0xa45f789a;
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imm32 r4, 0xb567f9ab;
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imm32 r5, 0xc6789fbc;
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imm32 r6, 0xd789abfd;
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imm32 r7, 0xe89abcdf;
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R0 = R5.L (Z);
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R1 = R5.L (Z);
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R2 = R5.L (Z);
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R3 = R5.L (Z);
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R4 = R5.L (Z);
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R6 = R5.L (Z);
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R7 = R5.L (Z);
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R5 = R5.L (Z);
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CHECKREG r0, 0x00009FBC;
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CHECKREG r1, 0x00009FBC;
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CHECKREG r2, 0x00009FBC;
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CHECKREG r3, 0x00009FBC;
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CHECKREG r4, 0x00009FBC;
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CHECKREG r5, 0x00009FBC;
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CHECKREG r6, 0x00009FBC;
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CHECKREG r7, 0x00009FBC;
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imm32 r0, 0xe0789abc;
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imm32 r1, 0xe2345678;
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imm32 r2, 0x2e456789;
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imm32 r3, 0x34e6789a;
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imm32 r4, 0x856e89ab;
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imm32 r5, 0x9678eabc;
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imm32 r6, 0xa789aecd;
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imm32 r7, 0xb89abcee;
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R0 = R6.L (Z);
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R1 = R6.L (Z);
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R2 = R6.L (Z);
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R3 = R6.L (Z);
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R4 = R6.L (Z);
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R5 = R6.L (Z);
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R7 = R6.L (Z);
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R6 = R6.L (Z);
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CHECKREG r0, 0x0000AECD;
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CHECKREG r1, 0x0000AECD;
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CHECKREG r2, 0x0000AECD;
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CHECKREG r3, 0x0000AECD;
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CHECKREG r4, 0x0000AECD;
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CHECKREG r5, 0x0000AECD;
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CHECKREG r6, 0x0000AECD;
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CHECKREG r7, 0x0000AECD;
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imm32 r0, 0x012300f5;
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imm32 r1, 0x80374659;
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imm32 r2, 0x98456589;
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imm32 r3, 0xa486589a;
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imm32 r4, 0xb56589ab;
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imm32 r5, 0xc6588abc;
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imm32 r6, 0xd589a8cd;
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imm32 r7, 0x589abc88;
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R0 = R7.L (Z);
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R1 = R7.L (Z);
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R2 = R7.L (Z);
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R3 = R7.L (Z);
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R4 = R7.L (Z);
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R5 = R7.L (Z);
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R6 = R7.L (Z);
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R7 = R7.L (Z);
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CHECKREG r0, 0x0000BC88;
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CHECKREG r1, 0x0000BC88;
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CHECKREG r2, 0x0000BC88;
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CHECKREG r3, 0x0000BC88;
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CHECKREG r4, 0x0000BC88;
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CHECKREG r5, 0x0000BC88;
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CHECKREG r6, 0x0000BC88;
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CHECKREG r7, 0x0000BC88;
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pass
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