2015-11-24 16:47:59 +08:00
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/* cpustate.h -- Prototypes for AArch64 cpu state functions.
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2016-01-01 12:33:14 +08:00
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Copyright (C) 2015-2016 Free Software Foundation, Inc.
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2015-11-24 16:47:59 +08:00
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Contributed by Red Hat.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef _CPU_STATE_H
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#define _CPU_STATE_H
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#include <sys/types.h>
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#include <stdint.h>
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#include <inttypes.h>
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#include "gdb/remote-sim.h"
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/* Symbolic names used to identify general registers which also match
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the registers indices in machine code.
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We have 32 general registers which can be read/written as 32 bit or
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64 bit sources/sinks and are appropriately referred to as Wn or Xn
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in the assembly code. Some instructions mix these access modes
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(e.g. ADD X0, X1, W2) so the implementation of the instruction
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needs to *know* which type of read or write access is required. */
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typedef enum GReg
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{
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R0,
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R1,
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R2,
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R3,
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R4,
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R5,
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R6,
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R7,
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R8,
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R9,
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R10,
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R11,
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R12,
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R13,
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R14,
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R15,
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R16,
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R17,
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R18,
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R19,
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R20,
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R21,
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R22,
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R23,
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R24,
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R25,
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R26,
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R27,
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R28,
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R29,
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R30,
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R31,
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FP = R29,
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LR = R30,
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SP = R31,
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ZR = R31
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} GReg;
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/* Symbolic names used to refer to floating point registers which also
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match the registers indices in machine code.
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We have 32 FP registers which can be read/written as 8, 16, 32, 64
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and 128 bit sources/sinks and are appropriately referred to as Bn,
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Hn, Sn, Dn and Qn in the assembly code. Some instructions mix these
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access modes (e.g. FCVT S0, D0) so the implementation of the
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instruction needs to *know* which type of read or write access is
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required. */
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typedef enum VReg
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{
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V0,
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V1,
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V2,
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V3,
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V4,
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V5,
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V6,
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V7,
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V8,
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V9,
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V10,
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V11,
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V12,
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V13,
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V14,
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V15,
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V16,
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V17,
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V18,
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V19,
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V20,
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V21,
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V22,
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V23,
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V24,
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V25,
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V26,
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V27,
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V28,
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V29,
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V30,
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V31,
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} VReg;
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/* All the different integer bit patterns for the components of a
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general register are overlaid here using a union so as to allow all
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reading and writing of the desired bits.
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N.B. the ARM spec says that when you write a 32 bit register you
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are supposed to write the low 32 bits and zero the high 32
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bits. But we don't actually have to care about this because Java
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will only ever consume the 32 bits value as a 64 bit quantity after
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an explicit extend. */
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typedef union GRegisterValue
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{
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int8_t s8;
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int16_t s16;
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int32_t s32;
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int64_t s64;
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uint8_t u8;
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uint16_t u16;
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uint32_t u32;
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uint64_t u64;
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} GRegister;
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/* Float registers provide for storage of a single, double or quad
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word format float in the same register. Single floats are not
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paired within each double register as per 32 bit arm. Instead each
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128 bit register Vn embeds the bits for Sn, and Dn in the lower
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quarter and half, respectively, of the bits for Qn.
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The upper bits can also be accessed as single or double floats by
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the float vector operations using indexing e.g. V1.D[1], V1.S[3]
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etc and, for SIMD operations using a horrible index range notation.
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The spec also talks about accessing float registers as half words
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and bytes with Hn and Bn providing access to the low 16 and 8 bits
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of Vn but it is not really clear what these bits represent. We can
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probably ignore this for Java anyway. However, we do need to access
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the raw bits at 32 and 64 bit resolution to load to/from integer
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registers.
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Note - we do not use the long double type. Aliasing issues between
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integer and float values mean that it is unreliable to use them. */
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typedef union FRegisterValue
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{
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float s;
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double d;
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2016-03-24 01:37:30 +08:00
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uint64_t v[2];
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uint32_t w[4];
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uint16_t h[8];
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uint8_t b[16];
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int64_t V[2];
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int32_t W[4];
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int16_t H[8];
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int8_t B[16];
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float S[4];
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double D[2];
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} FRegister;
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/* Condition register bit select values.
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The order of bits here is important because some of
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the flag setting conditional instructions employ a
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bit field to populate the flags when a false condition
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bypasses execution of the operation and we want to
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be able to assign the flags register using the
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supplied value. */
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typedef enum FlagIdx
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{
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V_IDX = 0,
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C_IDX = 1,
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Z_IDX = 2,
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N_IDX = 3
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} FlagIdx;
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typedef enum FlagMask
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{
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V = 1 << V_IDX,
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C = 1 << C_IDX,
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Z = 1 << Z_IDX,
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N = 1 << N_IDX
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} FlagMask;
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#define CPSR_ALL_FLAGS (V | C | Z | N)
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typedef uint32_t FlagsRegister;
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/* FPSR register -- floating point status register
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This register includes IDC, IXC, UFC, OFC, DZC, IOC and QC bits,
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and the floating point N, Z, C, V bits but the latter are unused in
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aarch64 mode. The sim ignores QC for now.
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Bit positions are as per the ARMv7 FPSCR register
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IDC : 7 ==> Input Denormal (cumulative exception bit)
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IXC : 4 ==> Inexact
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UFC : 3 ==> Underflow
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OFC : 2 ==> Overflow
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DZC : 1 ==> Division by Zero
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IOC : 0 ==> Invalid Operation
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The rounding mode is held in bits [23,22] defined as follows:
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0b00 Round to Nearest (RN) mode
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0b01 Round towards Plus Infinity (RP) mode
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0b10 Round towards Minus Infinity (RM) mode
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0b11 Round towards Zero (RZ) mode. */
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/* Indices for bits in the FPSR register value. */
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typedef enum FPSRIdx
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{
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IO_IDX = 0,
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DZ_IDX = 1,
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OF_IDX = 2,
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UF_IDX = 3,
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IX_IDX = 4,
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ID_IDX = 7
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} FPSRIdx;
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/* Corresponding bits as numeric values. */
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typedef enum FPSRMask
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{
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IO = (1 << IO_IDX),
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DZ = (1 << DZ_IDX),
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OF = (1 << OF_IDX),
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UF = (1 << UF_IDX),
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IX = (1 << IX_IDX),
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ID = (1 << ID_IDX)
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} FPSRMask;
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#define FPSR_ALL_FPSRS (IO | DZ | OF | UF | IX | ID)
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/* General Register access functions. */
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extern uint64_t aarch64_get_reg_u64 (sim_cpu *, GReg, int);
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extern int64_t aarch64_get_reg_s64 (sim_cpu *, GReg, int);
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extern uint32_t aarch64_get_reg_u32 (sim_cpu *, GReg, int);
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extern int32_t aarch64_get_reg_s32 (sim_cpu *, GReg, int);
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extern uint32_t aarch64_get_reg_u16 (sim_cpu *, GReg, int);
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extern int32_t aarch64_get_reg_s16 (sim_cpu *, GReg, int);
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extern uint32_t aarch64_get_reg_u8 (sim_cpu *, GReg, int);
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extern int32_t aarch64_get_reg_s8 (sim_cpu *, GReg, int);
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extern void aarch64_set_reg_u64 (sim_cpu *, GReg, int, uint64_t);
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extern void aarch64_set_reg_u32 (sim_cpu *, GReg, int, uint32_t);
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extern void aarch64_set_reg_s64 (sim_cpu *, GReg, int, int64_t);
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extern void aarch64_set_reg_s32 (sim_cpu *, GReg, int, int32_t);
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/* FP Register access functions. */
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extern float aarch64_get_FP_half (sim_cpu *, VReg);
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extern float aarch64_get_FP_float (sim_cpu *, VReg);
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extern double aarch64_get_FP_double (sim_cpu *, VReg);
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extern void aarch64_get_FP_long_double (sim_cpu *, VReg, FRegister *);
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extern void aarch64_set_FP_half (sim_cpu *, VReg, float);
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extern void aarch64_set_FP_float (sim_cpu *, VReg, float);
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extern void aarch64_set_FP_double (sim_cpu *, VReg, double);
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extern void aarch64_set_FP_long_double (sim_cpu *, VReg, FRegister);
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/* PC register accessors. */
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extern uint64_t aarch64_get_PC (sim_cpu *);
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extern uint64_t aarch64_get_next_PC (sim_cpu *);
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extern void aarch64_set_next_PC (sim_cpu *, uint64_t);
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extern void aarch64_set_next_PC_by_offset (sim_cpu *, int64_t);
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extern void aarch64_update_PC (sim_cpu *);
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extern void aarch64_save_LR (sim_cpu *);
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/* Instruction accessor - implemented as a
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macro as we do not need to annotate it. */
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#define aarch64_get_instr(cpu) ((cpu)->instr)
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/* Flag register accessors. */
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extern uint32_t aarch64_get_CPSR (sim_cpu *);
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extern void aarch64_set_CPSR (sim_cpu *, uint32_t);
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extern uint32_t aarch64_get_CPSR_bits (sim_cpu *, uint32_t);
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extern void aarch64_set_CPSR_bits (sim_cpu *, uint32_t, uint32_t);
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extern uint32_t aarch64_test_CPSR_bit (sim_cpu *, FlagMask);
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extern void aarch64_set_CPSR_bit (sim_cpu *, FlagMask);
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extern void aarch64_clear_CPSR_bit (sim_cpu *, FlagMask);
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extern void aarch64_set_FPSR (sim_cpu *, uint32_t);
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extern uint32_t aarch64_get_FPSR (sim_cpu *);
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extern void aarch64_set_FPSR_bits (sim_cpu *, uint32_t, uint32_t);
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extern uint32_t aarch64_get_FPSR_bits (sim_cpu *, uint32_t);
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extern int aarch64_test_FPSR_bit (sim_cpu *, FPSRMask);
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/* Vector register accessors. */
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extern uint64_t aarch64_get_vec_u64 (sim_cpu *, VReg, unsigned);
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extern uint32_t aarch64_get_vec_u32 (sim_cpu *, VReg, unsigned);
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extern uint16_t aarch64_get_vec_u16 (sim_cpu *, VReg, unsigned);
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extern uint8_t aarch64_get_vec_u8 (sim_cpu *, VReg, unsigned);
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extern void aarch64_set_vec_u64 (sim_cpu *, VReg, unsigned, uint64_t);
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extern void aarch64_set_vec_u32 (sim_cpu *, VReg, unsigned, uint32_t);
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extern void aarch64_set_vec_u16 (sim_cpu *, VReg, unsigned, uint16_t);
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extern void aarch64_set_vec_u8 (sim_cpu *, VReg, unsigned, uint8_t);
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extern int64_t aarch64_get_vec_s64 (sim_cpu *, VReg, unsigned);
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extern int32_t aarch64_get_vec_s32 (sim_cpu *, VReg, unsigned);
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extern int16_t aarch64_get_vec_s16 (sim_cpu *, VReg, unsigned);
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extern int8_t aarch64_get_vec_s8 (sim_cpu *, VReg, unsigned);
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extern void aarch64_set_vec_s64 (sim_cpu *, VReg, unsigned, int64_t);
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extern void aarch64_set_vec_s32 (sim_cpu *, VReg, unsigned, int32_t);
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extern void aarch64_set_vec_s16 (sim_cpu *, VReg, unsigned, int16_t);
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extern void aarch64_set_vec_s8 (sim_cpu *, VReg, unsigned, int8_t);
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extern float aarch64_get_vec_float (sim_cpu *, VReg, unsigned);
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extern double aarch64_get_vec_double (sim_cpu *, VReg, unsigned);
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extern void aarch64_set_vec_float (sim_cpu *, VReg, unsigned, float);
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extern void aarch64_set_vec_double (sim_cpu *, VReg, unsigned, double);
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2016-03-24 01:37:30 +08:00
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/* System register accessors. */
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extern uint64_t aarch64_get_thread_id (sim_cpu *);
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extern uint32_t aarch64_get_FPCR (sim_cpu *);
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extern void aarch64_set_FPCR (sim_cpu *, uint32_t);
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2015-11-24 16:47:59 +08:00
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#endif /* _CPU_STATE_H */
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