2014-09-12 17:11:42 +08:00
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/* Cache and manage the values of registers
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2024-01-12 23:30:44 +08:00
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Copyright (C) 2014-2024 Free Software Foundation, Inc.
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2014-09-12 17:11:42 +08:00
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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2019-01-28 03:51:36 +08:00
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#ifndef COMMON_COMMON_REGCACHE_H
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#define COMMON_COMMON_REGCACHE_H
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2014-09-12 17:11:42 +08:00
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2023-12-02 00:27:15 +08:00
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struct reg_buffer_common;
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2014-09-12 17:11:42 +08:00
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/* This header is a stopgap until we have an independent regcache. */
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2018-06-10 10:08:06 +08:00
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enum register_status : signed char
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2015-12-19 00:33:59 +08:00
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{
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/* The register value is not in the cache, and we don't know yet
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whether it's available in the target (or traceframe). */
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REG_UNKNOWN = 0,
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/* The register value is valid and cached. */
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REG_VALID = 1,
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/* The register value is unavailable. E.g., we're inspecting a
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traceframe, and this register wasn't collected. Note that this
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is different a different "unavailable" from saying the register
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does not exist in the target's architecture --- in that case,
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the target should have given us a target description that does
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not include the register in the first place. */
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REG_UNAVAILABLE = -1
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};
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2014-09-12 17:11:42 +08:00
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/* Return a pointer to the register cache associated with the
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thread specified by PTID. This function must be provided by
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the client. */
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2023-12-02 00:27:15 +08:00
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extern reg_buffer_common *get_thread_regcache_for_ptid (ptid_t ptid);
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2014-09-12 17:11:42 +08:00
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aarch64 multi-arch part 6: HW breakpoint on unaligned address
Nowadays, both aarch64 GDB and linux kernel assumes that address for
setting breakpoint should be 4-byte aligned. However that is not true
after we support multi-arch, because thumb instruction can be at 2-byte
aligned address. Patch http://lists.infradead.org/pipermail/linux-arm-kernel/2015-October/375141.html
to linux kernel is to teach kernel to handle 2-byte aligned address for
HW breakpoint, while this patch is to teach aarch64 GDB handle 2-byte
aligned address.
First of all, we call gdbarch_breakpoint_from_pc to get the instruction
length rather than using hard-coded 4. Secondly, in GDBserver, we set
length back to 2 if it is 3, because GDB encode 3 in it to indicate it
is a 32-bit thumb breakpoint. Then we relax the address alignment
check from 4-byte aligned to 2-byte aligned.
This patch enables some tests (such as gdb.base/break-idempotent.exp,
gdb.base/cond-eval-mode.exp, gdb.base/watchpoint-reuse-slot.exp,) and
fixes many fails (such as gdb.base/hbreak2.exp) when the program is
compiled in thumb mode on aarch64.
Regression tested on aarch64-linux, both native and gdbserver. This
is the last patch of multi-arch work.
gdb:
2015-10-15 Yao Qi <yao.qi@linaro.org>
* aarch64-linux-nat.c (aarch64_linux_insert_hw_breakpoint):
Call gdbarch_breakpoint_from_pc to instruction length.
(aarch64_linux_remove_hw_breakpoint): Likewise.
* common/common-regcache.h (regcache_register_size): Declare.
* nat/aarch64-linux-hw-point.c: Include "common-regcache.h".
(aarch64_point_is_aligned): Set alignment to 2 for breakpoint if
the process is 32bit, otherwise set alignment to 4.
(aarch64_handle_breakpoint): Update comments.
* regcache.c (regcache_register_size): New function.
gdb/gdbserver:
2015-10-15 Yao Qi <yao.qi@linaro.org>
* linux-aarch64-low.c (aarch64_insert_point): Set len to 2
if it is 3.
(aarch64_remove_point): Likewise.
* regcache.c (regcache_register_size): New function.
2015-10-15 22:05:10 +08:00
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/* Return the size of register numbered N in REGCACHE. This function
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must be provided by the client. */
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2023-12-02 00:27:15 +08:00
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extern int regcache_register_size (const reg_buffer_common *regcache, int n);
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aarch64 multi-arch part 6: HW breakpoint on unaligned address
Nowadays, both aarch64 GDB and linux kernel assumes that address for
setting breakpoint should be 4-byte aligned. However that is not true
after we support multi-arch, because thumb instruction can be at 2-byte
aligned address. Patch http://lists.infradead.org/pipermail/linux-arm-kernel/2015-October/375141.html
to linux kernel is to teach kernel to handle 2-byte aligned address for
HW breakpoint, while this patch is to teach aarch64 GDB handle 2-byte
aligned address.
First of all, we call gdbarch_breakpoint_from_pc to get the instruction
length rather than using hard-coded 4. Secondly, in GDBserver, we set
length back to 2 if it is 3, because GDB encode 3 in it to indicate it
is a 32-bit thumb breakpoint. Then we relax the address alignment
check from 4-byte aligned to 2-byte aligned.
This patch enables some tests (such as gdb.base/break-idempotent.exp,
gdb.base/cond-eval-mode.exp, gdb.base/watchpoint-reuse-slot.exp,) and
fixes many fails (such as gdb.base/hbreak2.exp) when the program is
compiled in thumb mode on aarch64.
Regression tested on aarch64-linux, both native and gdbserver. This
is the last patch of multi-arch work.
gdb:
2015-10-15 Yao Qi <yao.qi@linaro.org>
* aarch64-linux-nat.c (aarch64_linux_insert_hw_breakpoint):
Call gdbarch_breakpoint_from_pc to instruction length.
(aarch64_linux_remove_hw_breakpoint): Likewise.
* common/common-regcache.h (regcache_register_size): Declare.
* nat/aarch64-linux-hw-point.c: Include "common-regcache.h".
(aarch64_point_is_aligned): Set alignment to 2 for breakpoint if
the process is 32bit, otherwise set alignment to 4.
(aarch64_handle_breakpoint): Update comments.
* regcache.c (regcache_register_size): New function.
gdb/gdbserver:
2015-10-15 Yao Qi <yao.qi@linaro.org>
* linux-aarch64-low.c (aarch64_insert_point): Set len to 2
if it is 3.
(aarch64_remove_point): Likewise.
* regcache.c (regcache_register_size): New function.
2015-10-15 22:05:10 +08:00
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2014-09-12 17:11:42 +08:00
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/* Read the PC register. This function must be provided by the
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client. */
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2023-12-02 00:27:15 +08:00
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extern CORE_ADDR regcache_read_pc (reg_buffer_common *regcache);
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2014-09-12 17:11:42 +08:00
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2020-05-14 19:59:53 +08:00
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/* Read the PC register. If PC cannot be read, return 0.
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This is a wrapper around 'regcache_read_pc'. */
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2023-12-02 00:27:15 +08:00
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extern CORE_ADDR regcache_read_pc_protected (reg_buffer_common *regcache);
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2020-05-14 19:59:53 +08:00
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2015-12-19 00:33:59 +08:00
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/* Read a raw register into a unsigned integer. */
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2023-12-02 00:27:15 +08:00
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extern enum register_status
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regcache_raw_read_unsigned (reg_buffer_common *regcache, int regnum,
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ULONGEST *val);
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2015-12-19 00:33:59 +08:00
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2023-12-02 00:27:15 +08:00
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ULONGEST regcache_raw_get_unsigned (reg_buffer_common *regcache, int regnum);
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2015-12-19 00:33:59 +08:00
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2018-06-11 17:09:16 +08:00
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struct reg_buffer_common
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{
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virtual ~reg_buffer_common () = default;
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/* Get the availability status of the value of register REGNUM in this
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buffer. */
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virtual register_status get_register_status (int regnum) const = 0;
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gdb: change regcache interface to use array_view
Change most of regcache (and base classes) to use array_view when
possible, instead of raw pointers. By propagating the use of array_view
further, it enables having some runtime checks to make sure the what we
read from or write to regcaches has the expected length (such as the one
in the `copy(array_view, array_view)` function. It also integrates well
when connecting with other APIs already using gdb::array_view.
Add some overloads of the methods using raw pointers to avoid having to
change all call sites at once (which is both a lot of work and risky).
I tried to do this change in small increments, but since many of these
functions use each other, it ended up simpler to do it in one shot than
having a lot of intermediary / transient changes.
This change extends into gdbserver as well, because there is some part
of the regcache interface that is shared.
Changing the reg_buffer_common interface to use array_view caused some
build failures in nat/aarch64-scalable-linux-ptrace.c. That file
currently "takes advantage" of the fact that
reg_buffer_common::{raw_supply,raw_collect} operates on `void *`, which
IMO is dangerous. It uses raw_supply/raw_collect directly on
uint64_t's, which I guess is fine because it is expected that native
code will have the same endianness as the debugged process. To
accomodate that, add some overloads of raw_collect and raw_supply that
work on uint64_t.
This file also uses raw_collect and raw_supply on `char` pointers.
Change it to use `gdb_byte` pointers instead. Add overloads of
raw_collect and raw_supply that work on `gdb_byte *` and make an
array_view on the fly using the register's size. Those call sites could
be converted to use array_view with not much work, in which case these
overloads could be removed, but I didn't want to do it in this patch, to
avoid starting to dig in arch-specific code.
During development, I inadvertently changed reg_buffer::raw_compare's
behavior to not accept an offset equal to the register size. This
behavior (effectively comparing 0 bytes, returning true) change was
caught by the AArch64 SME core tests. Add a selftest to make sure that
this raw_compare behavior is preserved in the future.
Change-Id: I9005f04114543ddff738949e12d85a31855304c2
Reviewed-By: John Baldwin <jhb@FreeBSD.org>
2023-12-02 00:27:18 +08:00
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/* Supply register REGNUM, whose contents are stored in SRC, to this register
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buffer. */
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virtual void raw_supply (int regnum, gdb::array_view<const gdb_byte> src)
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= 0;
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void raw_supply (int regnum, const uint64_t *src)
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{
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raw_supply (regnum,
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gdb::make_array_view ((const gdb_byte *) src, sizeof (*src)));
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}
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void raw_supply (int regnum, const gdb_byte *src)
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{
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raw_supply (regnum,
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gdb::make_array_view (src,
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regcache_register_size (this, regnum)));
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}
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2018-06-11 17:09:16 +08:00
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gdb: change regcache interface to use array_view
Change most of regcache (and base classes) to use array_view when
possible, instead of raw pointers. By propagating the use of array_view
further, it enables having some runtime checks to make sure the what we
read from or write to regcaches has the expected length (such as the one
in the `copy(array_view, array_view)` function. It also integrates well
when connecting with other APIs already using gdb::array_view.
Add some overloads of the methods using raw pointers to avoid having to
change all call sites at once (which is both a lot of work and risky).
I tried to do this change in small increments, but since many of these
functions use each other, it ended up simpler to do it in one shot than
having a lot of intermediary / transient changes.
This change extends into gdbserver as well, because there is some part
of the regcache interface that is shared.
Changing the reg_buffer_common interface to use array_view caused some
build failures in nat/aarch64-scalable-linux-ptrace.c. That file
currently "takes advantage" of the fact that
reg_buffer_common::{raw_supply,raw_collect} operates on `void *`, which
IMO is dangerous. It uses raw_supply/raw_collect directly on
uint64_t's, which I guess is fine because it is expected that native
code will have the same endianness as the debugged process. To
accomodate that, add some overloads of raw_collect and raw_supply that
work on uint64_t.
This file also uses raw_collect and raw_supply on `char` pointers.
Change it to use `gdb_byte` pointers instead. Add overloads of
raw_collect and raw_supply that work on `gdb_byte *` and make an
array_view on the fly using the register's size. Those call sites could
be converted to use array_view with not much work, in which case these
overloads could be removed, but I didn't want to do it in this patch, to
avoid starting to dig in arch-specific code.
During development, I inadvertently changed reg_buffer::raw_compare's
behavior to not accept an offset equal to the register size. This
behavior (effectively comparing 0 bytes, returning true) change was
caught by the AArch64 SME core tests. Add a selftest to make sure that
this raw_compare behavior is preserved in the future.
Change-Id: I9005f04114543ddff738949e12d85a31855304c2
Reviewed-By: John Baldwin <jhb@FreeBSD.org>
2023-12-02 00:27:18 +08:00
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/* Collect register REGNUM from this register buffer and store its contents in
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DST. */
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virtual void raw_collect (int regnum, gdb::array_view<gdb_byte> dst) const
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= 0;
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void raw_collect (int regnum, uint64_t *dst) const
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{
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raw_collect (regnum,
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gdb::make_array_view ((gdb_byte *) dst, sizeof (*dst)));
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};
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void raw_collect (int regnum, gdb_byte *dst)
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{
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raw_collect (regnum,
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gdb::make_array_view (dst,
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regcache_register_size (this, regnum)));
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}
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2018-06-11 17:09:30 +08:00
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/* Compare the contents of the register stored in the regcache (ignoring the
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first OFFSET bytes) to the contents of BUF (without any offset). Returns
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true if the same. */
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virtual bool raw_compare (int regnum, const void *buf, int offset) const = 0;
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2018-06-11 17:09:16 +08:00
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};
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2019-01-28 03:51:36 +08:00
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#endif /* COMMON_COMMON_REGCACHE_H */
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