binutils-gdb/ld/testsuite/ld-mips-elf/lsi-4010-isa.d

#readelf: -Ah
#name: LSI 4010 processor ISA level
#source: empty.s
#as: -EB -32 -m4010
#ld: -EB -r

ELF Header:
#...
  Flags:                             0x1082[01]000, 4010(?:, o32)?, mips2
#...

MIPS ABI Flags Version: 0

ISA: MIPS2
GPR size: 32
CPR1 size: 32
CPR2 size: 0
FP ABI: .*
ISA Extension: LSI R4010
ASEs:
	None
FLAGS 1: .*
FLAGS 2: .*
MIPS/BFD: Consistently mark the LSI CW4010 as a MIPS II processor Make BFD agree with GAS and mark the LSI MiniRISC CW4010 processor core (for an odd reason referred to as LSI R4010 across our code base) as a MIPS II processor in BFD as well, fixing a bug that has been there since forever and addressing linker warnings like: $ as -m4010 empty.s -o 4010.o $ ld -r 4010.o -o 4010-r.o ld: 4010.o: warning: Inconsistent ISA between e_flags and .MIPS.abiflags $ due to the ISA level being recorded as MIPS III in ELF file header's `e_flags' vs MIPS II in the MIPS ABI Flags section: $ readelf -Ah 4010.o ELF Header: Magic: 7f 45 4c 46 01 02 01 00 00 00 00 00 00 00 00 00 Class: ELF32 Data: 2's complement, big endian Version: 1 (current) OS/ABI: UNIX - System V ABI Version: 0 Type: REL (Relocatable file) Machine: MIPS R3000 Version: 0x1 Entry point address: 0x0 Start of program headers: 0 (bytes into file) Start of section headers: 348 (bytes into file) Flags: 0x20821000, 4010, o32, mips3 Size of this header: 52 (bytes) Size of program headers: 0 (bytes) Number of program headers: 0 Size of section headers: 40 (bytes) Number of section headers: 11 Section header string table index: 10 Attribute Section: gnu File Attributes Tag_GNU_MIPS_ABI_FP: Hard float (double precision) MIPS ABI Flags Version: 0 ISA: MIPS2 GPR size: 32 CPR1 size: 32 CPR2 size: 0 FP ABI: Hard float (double precision) ISA Extension: LSI R4010 ASEs: None FLAGS 1: 00000000 FLAGS 2: 00000000 $ Available documentation[1][2] clearly indicates the LSI CW4010 processor is only backwards compatible with the MIPS R4000 processor as far as the latter's 32-bit instructions are concerned and consequently can only be considered a MIPS II ISA implementation (with vendor extensions). This fixes an LD testsuite failure: FAIL: MIPS incompatible objects: "-march=r4010 -32" "-march=r4650 -32" triggered for the `mips-sgi-irix5' and `mips-sgi-irix6' targets. References: [1] Paul Cobb, Bob Caulk, Joe Cesana, "The MiniRISC CW4010: A Superscalar MIPS Processor ASIC Core", LSI Logic, July 1995, presented at Hot Chips VII, Stanford University, Stanford, California, August 1995 [2] "MiniRISC MR4010 Superscalar Microprocessor Reference Device", LSI Logic, November 1996, Doc. No. DB09-000028-00, Order No. C15017 bfd/ * cpu-mips.c (arch_info_struct): Mark the 4010 32-bit. * elfxx-mips.c (mips_set_isa_flags) <bfd_mach_mips4010>: Set E_MIPS_ARCH_2 rather than E_MIPS_ARCH_3 in `e_flags'. (mips_mach_extensions): Mark `bfd_mach_mips4010' as extending `bfd_mach_mips6000' rather than `bfd_mach_mips4000'. ld/ * testsuite/ld-mips-elf/lsi-4010-isa.d: New test. * ld/testsuite/ld-mips-elf/mips-elf.exp: Run the new test. 2017-06-27 02:20:50 +08:00			`#readelf: -Ah`
			`#name: LSI 4010 processor ISA level`
			`#source: empty.s`
			`#as: -EB -32 -m4010`
			`#ld: -EB -r`

			`ELF Header:`
			`#...`
			`Flags: 0x1082[01]000, 4010(?:, o32)?, mips2`
			`#...`

			`MIPS ABI Flags Version: 0`

			`ISA: MIPS2`
			`GPR size: 32`
			`CPR1 size: 32`
			`CPR2 size: 0`
			`FP ABI: .*`
			`ISA Extension: LSI R4010`
			`ASEs:`
			`None`
			`FLAGS 1: .*`
			`FLAGS 2: .*`