1997-05-17 06:37:02 +08:00
|
|
|
Fri May 16 16:36:17 1997 Jeffrey A Law (law@cygnus.com)
|
|
|
|
|
|
|
|
|
|
* interp.c (load_mem): If we get a load from an out of range
|
|
|
|
|
address, abort.
|
|
|
|
|
(store_mem): Likewise for stores.
|
|
|
|
|
(max_mem): New variable.
|
|
|
|
|
|
1997-05-07 03:27:22 +08:00
|
|
|
Tue May 6 13:24:36 1997 Jeffrey A Law (law@cygnus.com)
|
|
|
|
|
|
1997-05-07 03:42:17 +08:00
|
|
|
* mn10300_sim.h: Fix ordering of bits in the PSW.
|
|
|
|
|
|
1997-05-07 03:27:22 +08:00
|
|
|
* interp.c: Improve hashing routine to avoid long list
|
|
|
|
|
traversals for common instructions. Add HASH_STAT support.
|
|
|
|
|
Rewrite opcode dispatch code using a big switch instead of
|
|
|
|
|
cascaded if/else statements. Avoid useless calls to load_mem.
|
|
|
|
|
|
1997-05-06 08:35:42 +08:00
|
|
|
Mon May 5 18:07:48 1997 Jeffrey A Law (law@cygnus.com)
|
|
|
|
|
|
|
|
|
|
* mn10300_sim.h (struct _state): Add space for mdrq register.
|
|
|
|
|
(REG_MDRQ): Define.
|
|
|
|
|
* simops.c: Don't abort for trap. Add support for the extended
|
|
|
|
|
instructions, "getx", "putx", "mulq", "mulqu", "sat16", "sat24",
|
|
|
|
|
and "bsch".
|
|
|
|
|
|
|
|
|
|
Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
|
|
|
|
|
|
|
|
|
|
* configure: Regenerated to track ../common/aclocal.m4 changes.
|
|
|
|
|
|
1997-04-18 20:24:52 +08:00
|
|
|
Fri Apr 18 14:04:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
|
|
|
|
|
|
|
|
|
|
* interp.c (sim_stop): Add stub function.
|
|
|
|
|
|
1997-04-17 18:27:47 +08:00
|
|
|
Thu Apr 17 03:26:59 1997 Doug Evans <dje@canuck.cygnus.com>
|
|
|
|
|
|
|
|
|
|
* Makefile.in (SIM_OBJS): Add sim-load.o.
|
|
|
|
|
* interp.c (sim_kind, myname): New static locals.
|
|
|
|
|
(sim_open): Set sim_kind, myname. Ignore -E arg.
|
|
|
|
|
(sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
|
|
|
|
|
load file into simulator. Set start address from bfd.
|
|
|
|
|
(sim_create_inferior): Return SIM_RC. Delete arg start_address.
|
|
|
|
|
|
1997-04-17 14:05:19 +08:00
|
|
|
Wed Apr 16 19:30:44 1997 Andrew Cagney <cagney@b1.cygnus.com>
|
|
|
|
|
|
|
|
|
|
* simops.c (OP_F020): SYS_execv, SYS_time, SYS_times, SYS_utime
|
|
|
|
|
only include if implemented by host.
|
|
|
|
|
(OP_F020): Typecast arg passed to time function;
|
|
|
|
|
|
|
|
|
|
Mon Apr 7 23:57:49 1997 Jeffrey A Law (law@cygnus.com)
|
|
|
|
|
|
|
|
|
|
* simops.c (syscall): Handle new mn10300 calling conventions.
|
|
|
|
|
|
1997-04-07 13:58:59 +08:00
|
|
|
Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
|
|
|
|
|
|
|
|
|
|
* configure: Regenerated to track ../common/aclocal.m4 changes.
|
|
|
|
|
* config.in: Ditto.
|
|
|
|
|
|
1997-04-05 09:03:01 +08:00
|
|
|
Fri Apr 4 20:02:37 1997 Ian Lance Taylor <ian@cygnus.com>
|
|
|
|
|
|
|
|
|
|
* Makefile.in: Change mn10300-opc.o to m10300-opc.o, to match
|
|
|
|
|
corresponding change in opcodes directory.
|
|
|
|
|
|
1997-04-03 07:17:50 +08:00
|
|
|
Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
|
|
|
|
|
|
1997-04-03 07:39:50 +08:00
|
|
|
* interp.c (sim_open): New arg `kind'.
|
|
|
|
|
|
1997-04-03 07:17:50 +08:00
|
|
|
* configure: Regenerated to track ../common/aclocal.m4 changes.
|
|
|
|
|
|
1997-04-02 13:04:25 +08:00
|
|
|
Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
|
|
|
|
|
|
|
|
|
|
* configure: Regenerated to track ../common/aclocal.m4 changes.
|
|
|
|
|
|
|
|
|
|
Thu Mar 20 11:58:02 1997 Jeffrey A Law (law@cygnus.com)
|
|
|
|
|
|
|
|
|
|
* simops.c: Fix register extraction for a two "movbu" variants.
|
|
|
|
|
Somewhat simplify "sub" instructions.
|
|
|
|
|
Correctly sign extend operands for "mul". Put the correct
|
|
|
|
|
half of the result in MDR for "mul" and "mulu".
|
|
|
|
|
Implement remaining instructions.
|
|
|
|
|
Tweak opcode for "syscall".
|
|
|
|
|
|
|
|
|
|
Tue Mar 18 14:21:21 1997 Jeffrey A Law (law@cygnus.com)
|
|
|
|
|
|
|
|
|
|
* simops.c: Do syscall emulation in "syscall" instruction. Add
|
|
|
|
|
dummy "trap" instruction.
|
|
|
|
|
|
1997-03-18 22:28:34 +08:00
|
|
|
Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
|
|
|
|
|
|
|
|
|
|
* configure: Regenerated to track ../common/aclocal.m4 changes.
|
|
|
|
|
|
1997-03-17 23:29:29 +08:00
|
|
|
Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
|
|
|
|
|
|
|
|
|
|
* configure: Re-generate.
|
|
|
|
|
|
1997-03-15 00:21:57 +08:00
|
|
|
Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
|
|
|
|
|
|
|
|
|
|
* configure: Regenerate to track ../common/aclocal.m4 changes.
|
|
|
|
|
|
1997-03-14 04:55:26 +08:00
|
|
|
Thu Mar 13 12:54:45 1997 Doug Evans <dje@canuck.cygnus.com>
|
|
|
|
|
|
|
|
|
|
* interp.c (sim_open): New SIM_DESC result. Argument is now
|
|
|
|
|
in argv form.
|
|
|
|
|
(other sim_*): New SIM_DESC argument.
|
|
|
|
|
|
1997-03-13 06:05:49 +08:00
|
|
|
Wed Mar 12 15:04:00 1997 Jeffrey A Law (law@cygnus.com)
|
|
|
|
|
|
1997-03-13 06:20:13 +08:00
|
|
|
* simops.c: Fix carry bit computation for "add" instructions.
|
|
|
|
|
|
1997-03-13 06:05:49 +08:00
|
|
|
* simops.c: Fix typos in bset insns. Fix arguments to store_mem
|
|
|
|
|
for bset imm8,(d8,an) and bclr imm8,(d8,an).
|
|
|
|
|
|
|
|
|
|
Wed Mar 5 15:00:10 1997 Jeffrey A Law (law@cygnus.com)
|
|
|
|
|
|
|
|
|
|
* simops.c: Fix register references when computing Z and N bits
|
|
|
|
|
for lsr imm8,dn.
|
|
|
|
|
|
|
|
|
|
Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
|
|
|
|
|
|
|
|
|
|
* Makefile.in (@COMMON_MAKEFILE_FRAG): Use
|
|
|
|
|
COMMON_{PRE,POST}_CONFIG_FRAG instead.
|
|
|
|
|
* configure.in: sinclude ../common/aclocal.m4.
|
|
|
|
|
* configure: Regenerated.
|
|
|
|
|
|
1997-01-25 01:48:35 +08:00
|
|
|
Fri Jan 24 10:47:25 1997 Jeffrey A Law (law@cygnus.com)
|
|
|
|
|
|
|
|
|
|
* interp.c (init_system): Allocate 2^19 bytes of space for the
|
|
|
|
|
simulator.
|
|
|
|
|
|
1997-01-24 06:09:52 +08:00
|
|
|
Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
|
|
|
|
|
|
|
|
|
|
* configure configure.in Makefile.in: Update to new configure
|
|
|
|
|
scheme which is more compatible with WinGDB builds.
|
|
|
|
|
* configure.in: Improve comment on how to run autoconf.
|
|
|
|
|
* configure: Re-run autoconf to get new ../common/aclocal.m4.
|
|
|
|
|
* Makefile.in: Use autoconf substitution to install common
|
|
|
|
|
makefile fragment.
|
|
|
|
|
|
1997-01-22 06:03:39 +08:00
|
|
|
Tue Jan 21 15:03:04 1997 Jeffrey A Law (law@cygnus.com)
|
|
|
|
|
|
|
|
|
|
* simops.c: Undo last change to "rol" and "ror", original code
|
|
|
|
|
was correct!
|
|
|
|
|
|
1997-01-17 02:28:46 +08:00
|
|
|
Thu Jan 16 11:28:14 1997 Jeffrey A Law (law@cygnus.com)
|
|
|
|
|
|
|
|
|
|
* simops.c: Fix "rol" and "ror".
|
|
|
|
|
|
|
|
|
|
Wed Jan 15 06:45:58 1997 Jeffrey A Law (law@cygnus.com)
|
|
|
|
|
|
|
|
|
|
* simops.c: Fix typo in last change.
|
|
|
|
|
|
1997-01-14 04:28:37 +08:00
|
|
|
Mon Jan 13 13:22:35 1997 Jeffrey A Law (law@cygnus.com)
|
|
|
|
|
|
|
|
|
|
* simops.c: Use REG macros in few places not using them yet.
|
|
|
|
|
|
1997-01-07 07:25:53 +08:00
|
|
|
Mon Jan 6 16:21:19 1997 Jeffrey A Law (law@cygnus.com)
|
|
|
|
|
|
|
|
|
|
* mn10300_sim.h (struct _state): Fix number of registers!
|
|
|
|
|
|
1997-01-01 07:26:11 +08:00
|
|
|
Tue Dec 31 16:20:41 1996 Jeffrey A Law (law@cygnus.com)
|
|
|
|
|
|
|
|
|
|
* mn10300_sim.h (struct _state): Put all registers into a single
|
|
|
|
|
array to make gdb implementation easier.
|
|
|
|
|
(REG_*): Add definitions for all registers in the state array.
|
|
|
|
|
(SEXT32, SEXT40, SEXT44, SEXT60): Remove unused macros.
|
|
|
|
|
* simops.c: Related changes.
|
|
|
|
|
|
1996-12-19 01:15:21 +08:00
|
|
|
Wed Dec 18 10:10:45 1996 Jeffrey A Law (law@cygnus.com)
|
|
|
|
|
|
|
|
|
|
* interp.c (sim_resume): Handle 0xff as a single byte insn.
|
|
|
|
|
|
|
|
|
|
* simops.c: Fix overflow computation for "add" and "inc"
|
|
|
|
|
instructions.
|
|
|
|
|
|
1996-12-17 01:08:10 +08:00
|
|
|
Mon Dec 16 10:03:52 1996 Jeffrey A Law (law@cygnus.com)
|
|
|
|
|
|
1996-12-17 06:31:37 +08:00
|
|
|
* simops.c: Handle "break" instruction.
|
|
|
|
|
|
1996-12-17 01:08:10 +08:00
|
|
|
* simops.c: Fix restoring the PC for "ret" and "retf" instructions.
|
|
|
|
|
|
|
|
|
|
Wed Dec 11 09:53:10 1996 Jeffrey A Law (law@cygnus.com)
|
|
|
|
|
|
|
|
|
|
* gencode.c (write_opcodes): Also write out the format of the
|
|
|
|
|
opcode.
|
|
|
|
|
* mn10300_sim.h (simops): Add "format" field.
|
|
|
|
|
* interp.c (sim_resume): Deal with endianness issues here.
|
|
|
|
|
|
1996-12-11 06:10:07 +08:00
|
|
|
Tue Dec 10 15:05:37 1996 Jeffrey A Law (law@cygnus.com)
|
|
|
|
|
|
|
|
|
|
* simops.c (REG0_4): Define.
|
|
|
|
|
Use REG0_4 for indexed loads/stores.
|
|
|
|
|
|
1996-12-08 00:54:57 +08:00
|
|
|
Sat Dec 7 09:50:28 1996 Jeffrey A Law (law@cygnus.com)
|
|
|
|
|
|
|
|
|
|
* simops.c (REG0_16): Fix typo.
|
|
|
|
|
|
1996-12-07 05:19:37 +08:00
|
|
|
Fri Dec 6 14:13:34 1996 Jeffrey A Law (law@cygnus.com)
|
|
|
|
|
|
1996-12-07 05:49:27 +08:00
|
|
|
* simops.c: Call abort for any instruction that's not currently
|
|
|
|
|
simulated.
|
|
|
|
|
|
1996-12-07 05:47:21 +08:00
|
|
|
* simops.c: Define accessor macros to extract register
|
|
|
|
|
values from instructions. Use them consistently.
|
|
|
|
|
|
1996-12-07 05:33:48 +08:00
|
|
|
* interp.c: Delete unused global variable "OP".
|
|
|
|
|
(sim_resume): Remove unused variable "opcode".
|
|
|
|
|
* simops.c: Fix some uninitialized variable problems, add
|
|
|
|
|
parens to fix various -Wall warnings.
|
|
|
|
|
|
1996-12-07 05:19:37 +08:00
|
|
|
* gencode.c (write_header): Add "insn" and "extension" arguments
|
|
|
|
|
to the OP_* declarations.
|
|
|
|
|
(write_template): Similarly for function templates.
|
|
|
|
|
* interp.c (insn, extension): Remove global variables. Instead
|
|
|
|
|
pass them as arguments to the OP_* functions.
|
|
|
|
|
* mn10300_sim.h: Remove decls for "insn" and "extension".
|
|
|
|
|
* simops.c (OP_*): Accept "insn" and "extension" as arguments
|
|
|
|
|
instead of using globals.
|
|
|
|
|
|
1996-12-06 13:30:24 +08:00
|
|
|
Thu Dec 5 22:26:31 1996 Jeffrey A Law (law@cygnus.com)
|
|
|
|
|
|
1996-12-06 15:57:21 +08:00
|
|
|
* simops.c: Fix typos in "mov am,(d16,an)" and "mov am,(d32,an)"
|
|
|
|
|
|
1996-12-06 13:30:24 +08:00
|
|
|
* simops.c: Fix thinkos in last change to "inc dn".
|
|
|
|
|
|
1996-12-05 02:02:00 +08:00
|
|
|
Wed Dec 4 10:57:53 1996 Jeffrey A Law (law@cygnus.com)
|
|
|
|
|
|
|
|
|
|
* simops.c: "add imm,sp" does not effect the condition codes.
|
|
|
|
|
"inc dn" does effect the condition codes.
|
|
|
|
|
|
1996-12-04 13:00:49 +08:00
|
|
|
Tue Dec 3 17:37:45 1996 Jeffrey A Law (law@cygnus.com)
|
|
|
|
|
|
|
|
|
|
* simops.c: Treat both operands as signed values for
|
|
|
|
|
"div" instruction.
|
|
|
|
|
|
|
|
|
|
* simops.c: Fix simulation of division instructions.
|
|
|
|
|
Fix typos/thinkos in several "cmp" and "sub" instructions.
|
|
|
|
|
|
1996-12-03 03:35:55 +08:00
|
|
|
Mon Dec 2 12:31:40 1996 Jeffrey A Law (law@cygnus.com)
|
|
|
|
|
|
1996-12-04 13:00:49 +08:00
|
|
|
* simops.c: Fix carry bit handling in "sub" and "cmp"
|
|
|
|
|
instructions.
|
|
|
|
|
|
1996-12-03 03:35:55 +08:00
|
|
|
* simops.c: Fix "mov imm8,an" and "mov imm16,dn".
|
|
|
|
|
|
1996-12-02 07:10:04 +08:00
|
|
|
Sun Dec 1 16:05:42 1996 Jeffrey A Law (law@cygnus.com)
|
|
|
|
|
|
1996-12-02 16:35:20 +08:00
|
|
|
* simops.c: Fix overflow computation for many instructions.
|
|
|
|
|
|
1996-12-06 15:57:21 +08:00
|
|
|
* simops.c: Fix "mov dm, an", "movbu dm, (an)", and "movhu dm, (an)".
|
1996-12-02 15:38:10 +08:00
|
|
|
|
1996-12-02 12:23:37 +08:00
|
|
|
* simops.c: Fix "mov am, dn".
|
|
|
|
|
|
1996-12-02 07:10:04 +08:00
|
|
|
* simops.c: Fix more bugs in "add imm,an" and
|
|
|
|
|
"add imm,dn".
|
|
|
|
|
|
1996-11-28 00:25:03 +08:00
|
|
|
Wed Nov 27 09:20:42 1996 Jeffrey A Law (law@cygnus.com)
|
|
|
|
|
|
1996-11-28 07:20:24 +08:00
|
|
|
* simops.c: Fix bugs in "movm" and "add imm,an".
|
|
|
|
|
|
1996-11-28 02:36:54 +08:00
|
|
|
* simops.c: Don't lose the upper 24 bits of the return
|
|
|
|
|
pointer in "call" and "calls" instructions. Rough cut
|
|
|
|
|
at emulated system calls.
|
|
|
|
|
|
1996-11-28 01:56:10 +08:00
|
|
|
* simops.c: Implement the remaining 5, 6 and 7 byte instructions.
|
|
|
|
|
|
1996-11-28 01:19:44 +08:00
|
|
|
* simops.c: Implement remaining 4 byte instructions.
|
|
|
|
|
|
|
|
|
|
* simops.c: Implement remaining 3 byte instructions.
|
1996-11-28 00:51:30 +08:00
|
|
|
|
1996-11-28 00:25:03 +08:00
|
|
|
* simops.c: Implement remaining 2 byte instructions. Call
|
|
|
|
|
abort for instructions we're not implementing now.
|
|
|
|
|
|
1996-11-27 06:58:24 +08:00
|
|
|
Tue Nov 26 15:43:41 1996 Jeffrey A Law (law@cygnus.com)
|
|
|
|
|
|
1996-11-27 15:20:36 +08:00
|
|
|
* simops.c: Implement lots of random instructions.
|
|
|
|
|
|
1996-11-27 13:29:49 +08:00
|
|
|
* simops.c: Implement "movm" and "bCC" insns.
|
|
|
|
|
|
1996-11-27 08:53:25 +08:00
|
|
|
* mn10300_sim.h (_state): Add another register (MDR).
|
|
|
|
|
(REG_MDR): Define.
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* simops.c: Implement "cmp", "calls", "rets", "jmp" and
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a few additional random insns.
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1996-11-27 06:58:24 +08:00
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* mn10300_sim.h (PSW_*): Define for CC status tracking.
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(REG_D0, REG_A0, REG_SP): Define.
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* simops.c: Implement "add", "addc" and a few other random
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instructions.
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1996-11-27 04:40:19 +08:00
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* gencode.c, interp.c: Snapshot current simulator code.
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1996-11-26 03:52:08 +08:00
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Mon Nov 25 12:46:38 1996 Jeffrey A Law (law@cygnus.com)
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* Makefile.in, config.in, configure, configure.in: New files.
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* gencode.c, interp.c, mn10300_sim.h, simops.c: New files.
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