2021-10-22 16:42:04 +08:00
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/* LoongArch opcode support.
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2024-01-04 19:52:08 +08:00
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Copyright (C) 2021-2024 Free Software Foundation, Inc.
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2021-10-22 16:42:04 +08:00
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Contributed by Loongson Ltd.
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; see the file COPYING3. If not,
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see <http://www.gnu.org/licenses/>. */
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#include "sysdep.h"
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#include "disassemble.h"
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#include "opintl.h"
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#include "opcode/loongarch.h"
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#include "libiberty.h"
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#include <stdlib.h>
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LoongArch: support disassembling certain pseudo-instructions
Add a flag in the pinfo field for being able to mark certain specialized
matchers as disassembler-only, so some degree of isolation between
assembler-side and disassembler-side can be achieved.
This isolation is necessary, firstly because some pseudo-instructions
cannot be fully described in the opcode table, like `li.[wd]`, so the
corresponding opcode entry cannot have meaningful match/mask values.
Secondly, some of these pseudo-instructions can be realized in more than
one plausible ways; e.g. `li.w rd, <something between 0 and 0x7ff>` can
be realized on LA64 with any of `addi.w`, `addi.d` or `ori`. If we tie
disassembly of such aliases with the corresponding GAS support, only one
canonical form among the above would be recognized as `li.w`, and it
would mildly impact the readability of disassembly output.
People wanting the exact disassembly can always set `-M no-aliases` to
get the original behavior back.
In addition, in certain cases, information is irreversibly lost after
assembling, so perfect round-trip would not be possible in such cases.
For example, `li.w` and `li.d` of immediates within int32_t range
produce the same code; in this patch, `addi.d rd, $zero, imm` is treated
as `li.d`, while `addi.w` and `ori` immediate loads are shown as `li.w`,
due to the expressible value range well within 32 bits.
gas/ChangeLog:
* config/tc-loongarch.c (get_loongarch_opcode): Ignore
disassembler-only aliases.
* testsuite/gas/loongarch/64_pcrel.d: Update test case.
* testsuite/gas/loongarch/imm_ins.d: Likewise.
* testsuite/gas/loongarch/imm_ins_32.d: Likewise.
* testsuite/gas/loongarch/jmp_op.d: Likewise.
* testsuite/gas/loongarch/li.d: Likewise.
* testsuite/gas/loongarch/macro_op.d: Likewise.
* testsuite/gas/loongarch/macro_op_32.d: Likewise.
* testsuite/gas/loongarch/macro_op_large_abs.d: Likewise.
* testsuite/gas/loongarch/macro_op_large_pc.d: Likewise.
* testsuite/gas/loongarch/nop.d: Likewise.
* testsuite/gas/loongarch/relax_align.d: Likewise.
* testsuite/gas/loongarch/reloc.d: Likewise.
include/ChangeLog:
* opcode/loongarch.h (INSN_DIS_ALIAS): Add.
ld/ChangeLog:
* testsuite/ld-loongarch-elf/jmp_op.d: Update test case.
* testsuite/ld-loongarch-elf/macro_op.d: Likewise.
* testsuite/ld-loongarch-elf/macro_op_32.d: Likewise.
* testsuite/ld-loongarch-elf/relax-align.dd: Likewise.
opcodes/ChangeLog:
* loongarch-dis.c: Move register name map declarations to top.
(get_loongarch_opcode_by_binfmt): Consider aliases when
disassembling without the no-aliases option.
(parse_loongarch_dis_option): Support the no-aliases option.
* loongarch-opc.c: Collect pseudo instructions into a new
dedicated table.
Signed-off-by: WANG Xuerui <git@xen0n.name>
2023-06-30 00:34:58 +08:00
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static bool loongarch_dis_show_aliases = true;
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static const char *const *loongarch_r_disname = NULL;
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static const char *const *loongarch_f_disname = NULL;
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static const char *const *loongarch_fc_disname = NULL;
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static const char *const *loongarch_c_disname = NULL;
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static const char *const *loongarch_cr_disname = NULL;
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static const char *const *loongarch_v_disname = NULL;
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static const char *const *loongarch_x_disname = NULL;
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2021-10-22 16:42:04 +08:00
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static const struct loongarch_opcode *
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get_loongarch_opcode_by_binfmt (insn_t insn)
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{
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const struct loongarch_opcode *it;
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struct loongarch_ase *ase;
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size_t i;
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for (ase = loongarch_ASEs; ase->enabled; ase++)
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{
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if (!*ase->enabled || (ase->include && !*ase->include)
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|| (ase->exclude && *ase->exclude))
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continue;
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if (!ase->opc_htab_inited)
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{
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for (it = ase->opcodes; it->mask; it++)
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if (!ase->opc_htab[LARCH_INSN_OPC (it->match)]
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LoongArch: support disassembling certain pseudo-instructions
Add a flag in the pinfo field for being able to mark certain specialized
matchers as disassembler-only, so some degree of isolation between
assembler-side and disassembler-side can be achieved.
This isolation is necessary, firstly because some pseudo-instructions
cannot be fully described in the opcode table, like `li.[wd]`, so the
corresponding opcode entry cannot have meaningful match/mask values.
Secondly, some of these pseudo-instructions can be realized in more than
one plausible ways; e.g. `li.w rd, <something between 0 and 0x7ff>` can
be realized on LA64 with any of `addi.w`, `addi.d` or `ori`. If we tie
disassembly of such aliases with the corresponding GAS support, only one
canonical form among the above would be recognized as `li.w`, and it
would mildly impact the readability of disassembly output.
People wanting the exact disassembly can always set `-M no-aliases` to
get the original behavior back.
In addition, in certain cases, information is irreversibly lost after
assembling, so perfect round-trip would not be possible in such cases.
For example, `li.w` and `li.d` of immediates within int32_t range
produce the same code; in this patch, `addi.d rd, $zero, imm` is treated
as `li.d`, while `addi.w` and `ori` immediate loads are shown as `li.w`,
due to the expressible value range well within 32 bits.
gas/ChangeLog:
* config/tc-loongarch.c (get_loongarch_opcode): Ignore
disassembler-only aliases.
* testsuite/gas/loongarch/64_pcrel.d: Update test case.
* testsuite/gas/loongarch/imm_ins.d: Likewise.
* testsuite/gas/loongarch/imm_ins_32.d: Likewise.
* testsuite/gas/loongarch/jmp_op.d: Likewise.
* testsuite/gas/loongarch/li.d: Likewise.
* testsuite/gas/loongarch/macro_op.d: Likewise.
* testsuite/gas/loongarch/macro_op_32.d: Likewise.
* testsuite/gas/loongarch/macro_op_large_abs.d: Likewise.
* testsuite/gas/loongarch/macro_op_large_pc.d: Likewise.
* testsuite/gas/loongarch/nop.d: Likewise.
* testsuite/gas/loongarch/relax_align.d: Likewise.
* testsuite/gas/loongarch/reloc.d: Likewise.
include/ChangeLog:
* opcode/loongarch.h (INSN_DIS_ALIAS): Add.
ld/ChangeLog:
* testsuite/ld-loongarch-elf/jmp_op.d: Update test case.
* testsuite/ld-loongarch-elf/macro_op.d: Likewise.
* testsuite/ld-loongarch-elf/macro_op_32.d: Likewise.
* testsuite/ld-loongarch-elf/relax-align.dd: Likewise.
opcodes/ChangeLog:
* loongarch-dis.c: Move register name map declarations to top.
(get_loongarch_opcode_by_binfmt): Consider aliases when
disassembling without the no-aliases option.
(parse_loongarch_dis_option): Support the no-aliases option.
* loongarch-opc.c: Collect pseudo instructions into a new
dedicated table.
Signed-off-by: WANG Xuerui <git@xen0n.name>
2023-06-30 00:34:58 +08:00
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&& it->macro == NULL
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&& (!(it->pinfo & INSN_DIS_ALIAS)
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|| loongarch_dis_show_aliases))
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2021-10-22 16:42:04 +08:00
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ase->opc_htab[LARCH_INSN_OPC (it->match)] = it;
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for (i = 0; i < 16; i++)
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if (!ase->opc_htab[i])
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ase->opc_htab[i] = it;
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ase->opc_htab_inited = 1;
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}
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it = ase->opc_htab[LARCH_INSN_OPC (insn)];
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for (; it->name; it++)
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if ((insn & it->mask) == it->match && it->mask
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&& !(it->include && !*it->include)
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&& !(it->exclude && *it->exclude))
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return it;
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}
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return NULL;
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}
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static void
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set_default_loongarch_dis_options (void)
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{
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LARCH_opts.ase_ilp32 = 1;
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LARCH_opts.ase_lp64 = 1;
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LARCH_opts.ase_sf = 1;
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LARCH_opts.ase_df = 1;
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LARCH_opts.ase_lsx = 1;
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LARCH_opts.ase_lasx = 1;
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2023-06-30 17:04:15 +08:00
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LARCH_opts.ase_lvz = 1;
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LARCH_opts.ase_lbt = 1;
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2021-10-22 16:42:04 +08:00
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2023-10-30 17:07:08 +08:00
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loongarch_r_disname = loongarch_r_alias;
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loongarch_f_disname = loongarch_f_alias;
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2023-06-16 11:16:10 +08:00
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loongarch_fc_disname = loongarch_fc_normal_name;
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2021-10-22 16:42:04 +08:00
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loongarch_c_disname = loongarch_c_normal_name;
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loongarch_cr_disname = loongarch_cr_normal_name;
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loongarch_v_disname = loongarch_v_normal_name;
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loongarch_x_disname = loongarch_x_normal_name;
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}
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static int
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parse_loongarch_dis_option (const char *option)
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{
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LoongArch: support disassembling certain pseudo-instructions
Add a flag in the pinfo field for being able to mark certain specialized
matchers as disassembler-only, so some degree of isolation between
assembler-side and disassembler-side can be achieved.
This isolation is necessary, firstly because some pseudo-instructions
cannot be fully described in the opcode table, like `li.[wd]`, so the
corresponding opcode entry cannot have meaningful match/mask values.
Secondly, some of these pseudo-instructions can be realized in more than
one plausible ways; e.g. `li.w rd, <something between 0 and 0x7ff>` can
be realized on LA64 with any of `addi.w`, `addi.d` or `ori`. If we tie
disassembly of such aliases with the corresponding GAS support, only one
canonical form among the above would be recognized as `li.w`, and it
would mildly impact the readability of disassembly output.
People wanting the exact disassembly can always set `-M no-aliases` to
get the original behavior back.
In addition, in certain cases, information is irreversibly lost after
assembling, so perfect round-trip would not be possible in such cases.
For example, `li.w` and `li.d` of immediates within int32_t range
produce the same code; in this patch, `addi.d rd, $zero, imm` is treated
as `li.d`, while `addi.w` and `ori` immediate loads are shown as `li.w`,
due to the expressible value range well within 32 bits.
gas/ChangeLog:
* config/tc-loongarch.c (get_loongarch_opcode): Ignore
disassembler-only aliases.
* testsuite/gas/loongarch/64_pcrel.d: Update test case.
* testsuite/gas/loongarch/imm_ins.d: Likewise.
* testsuite/gas/loongarch/imm_ins_32.d: Likewise.
* testsuite/gas/loongarch/jmp_op.d: Likewise.
* testsuite/gas/loongarch/li.d: Likewise.
* testsuite/gas/loongarch/macro_op.d: Likewise.
* testsuite/gas/loongarch/macro_op_32.d: Likewise.
* testsuite/gas/loongarch/macro_op_large_abs.d: Likewise.
* testsuite/gas/loongarch/macro_op_large_pc.d: Likewise.
* testsuite/gas/loongarch/nop.d: Likewise.
* testsuite/gas/loongarch/relax_align.d: Likewise.
* testsuite/gas/loongarch/reloc.d: Likewise.
include/ChangeLog:
* opcode/loongarch.h (INSN_DIS_ALIAS): Add.
ld/ChangeLog:
* testsuite/ld-loongarch-elf/jmp_op.d: Update test case.
* testsuite/ld-loongarch-elf/macro_op.d: Likewise.
* testsuite/ld-loongarch-elf/macro_op_32.d: Likewise.
* testsuite/ld-loongarch-elf/relax-align.dd: Likewise.
opcodes/ChangeLog:
* loongarch-dis.c: Move register name map declarations to top.
(get_loongarch_opcode_by_binfmt): Consider aliases when
disassembling without the no-aliases option.
(parse_loongarch_dis_option): Support the no-aliases option.
* loongarch-opc.c: Collect pseudo instructions into a new
dedicated table.
Signed-off-by: WANG Xuerui <git@xen0n.name>
2023-06-30 00:34:58 +08:00
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if (strcmp (option, "no-aliases") == 0)
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loongarch_dis_show_aliases = false;
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2021-10-22 16:42:04 +08:00
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if (strcmp (option, "numeric") == 0)
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{
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loongarch_r_disname = loongarch_r_normal_name;
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loongarch_f_disname = loongarch_f_normal_name;
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}
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return -1;
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}
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static int
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parse_loongarch_dis_options (const char *opts_in)
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{
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set_default_loongarch_dis_options ();
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if (opts_in == NULL)
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return 0;
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char *opts, *opt, *opt_end;
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opts = xmalloc (strlen (opts_in) + 1);
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strcpy (opts, opts_in);
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for (opt = opt_end = opts; opt_end != NULL; opt = opt_end + 1)
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{
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if ((opt_end = strchr (opt, ',')) != NULL)
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*opt_end = 0;
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if (parse_loongarch_dis_option (opt) != 0)
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return -1;
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}
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free (opts);
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return 0;
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}
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static int32_t
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dis_one_arg (char esc1, char esc2, const char *bit_field,
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const char *arg ATTRIBUTE_UNUSED, void *context)
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{
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static int need_comma = 0;
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struct disassemble_info *info = context;
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insn_t insn = *(insn_t *) info->private_data;
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int32_t imm, u_imm;
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2023-06-30 00:35:01 +08:00
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enum disassembler_style style;
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2021-10-22 16:42:04 +08:00
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if (esc1)
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{
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if (need_comma)
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2023-06-30 00:35:00 +08:00
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info->fprintf_styled_func (info->stream, dis_style_text, ", ");
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2021-10-22 16:42:04 +08:00
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need_comma = 1;
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imm = loongarch_decode_imm (bit_field, insn, 1);
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u_imm = loongarch_decode_imm (bit_field, insn, 0);
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}
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switch (esc1)
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{
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case 'r':
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2023-06-30 00:35:00 +08:00
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info->fprintf_styled_func (info->stream, dis_style_register, "%s", loongarch_r_disname[u_imm]);
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2021-10-22 16:42:04 +08:00
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break;
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case 'f':
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2023-06-16 11:16:10 +08:00
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switch (esc2)
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{
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case 'c':
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2023-06-30 00:35:00 +08:00
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info->fprintf_styled_func (info->stream, dis_style_register, "%s", loongarch_fc_disname[u_imm]);
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2023-06-16 11:16:10 +08:00
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break;
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default:
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2023-06-30 00:35:00 +08:00
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info->fprintf_styled_func (info->stream, dis_style_register, "%s", loongarch_f_disname[u_imm]);
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2023-06-16 11:16:10 +08:00
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}
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2021-10-22 16:42:04 +08:00
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break;
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case 'c':
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switch (esc2)
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{
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case 'r':
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2023-06-30 00:35:00 +08:00
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info->fprintf_styled_func (info->stream, dis_style_register, "%s", loongarch_cr_disname[u_imm]);
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2021-10-22 16:42:04 +08:00
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break;
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default:
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2023-06-30 00:35:00 +08:00
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info->fprintf_styled_func (info->stream, dis_style_register, "%s", loongarch_c_disname[u_imm]);
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2021-10-22 16:42:04 +08:00
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}
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break;
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case 'v':
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2023-06-30 00:35:00 +08:00
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info->fprintf_styled_func (info->stream, dis_style_register, "%s", loongarch_v_disname[u_imm]);
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2021-10-22 16:42:04 +08:00
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break;
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case 'x':
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2023-06-30 00:35:00 +08:00
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info->fprintf_styled_func (info->stream, dis_style_register, "%s", loongarch_x_disname[u_imm]);
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2021-10-22 16:42:04 +08:00
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break;
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case 'u':
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2023-06-30 00:35:01 +08:00
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style = esc2 == 'o' ? dis_style_address_offset : dis_style_immediate;
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info->fprintf_styled_func (info->stream, style, "0x%x", u_imm);
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2021-10-22 16:42:04 +08:00
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break;
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case 's':
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2023-06-30 00:35:01 +08:00
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switch (esc2)
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{
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case 'b':
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case 'o':
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/* Both represent address offsets. */
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style = dis_style_address_offset;
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break;
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default:
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style = dis_style_immediate;
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break;
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}
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2023-06-30 00:35:02 +08:00
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info->fprintf_styled_func (info->stream, style, "%d", imm);
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2021-10-22 16:42:04 +08:00
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switch (esc2)
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{
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case 'b':
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info->insn_type = dis_branch;
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info->target += imm;
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}
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|
|
break;
|
|
|
|
case '\0':
|
|
|
|
need_comma = 0;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
disassemble_one (insn_t insn, struct disassemble_info *info)
|
|
|
|
{
|
|
|
|
const struct loongarch_opcode *opc = get_loongarch_opcode_by_binfmt (insn);
|
|
|
|
|
|
|
|
#ifdef LOONGARCH_DEBUG
|
|
|
|
char have_space[32] = { 0 };
|
|
|
|
insn_t t;
|
|
|
|
int i;
|
|
|
|
const char *t_f = opc ? opc->format : NULL;
|
|
|
|
if (t_f)
|
|
|
|
while (*t_f)
|
|
|
|
{
|
|
|
|
while (('a' <= t_f[0] && t_f[0] <= 'z')
|
|
|
|
|| ('A' <= t_f[0] && t_f[0] <= 'Z')
|
|
|
|
|| t_f[0] == ',')
|
|
|
|
t_f++;
|
|
|
|
while (1)
|
|
|
|
{
|
|
|
|
i = strtol (t_f, &t_f, 10);
|
|
|
|
have_space[i] = 1;
|
|
|
|
t_f++; /* ':' */
|
|
|
|
i += strtol (t_f, &t_f, 10);
|
|
|
|
have_space[i] = 1;
|
|
|
|
if (t_f[0] == '|')
|
|
|
|
t_f++;
|
|
|
|
else
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (t_f[0] == '<')
|
|
|
|
t_f += 2; /* '<' '<' */
|
|
|
|
strtol (t_f, &t_f, 10);
|
|
|
|
}
|
|
|
|
|
|
|
|
have_space[28] = 1;
|
|
|
|
have_space[0] = 0;
|
|
|
|
t = ~((insn_t) -1 >> 1);
|
|
|
|
for (i = 31; 0 <= i; i--)
|
|
|
|
{
|
|
|
|
if (t & insn)
|
2023-06-30 00:35:00 +08:00
|
|
|
info->fprintf_styled_func (info->stream, dis_style_text, "1");
|
2021-10-22 16:42:04 +08:00
|
|
|
else
|
2023-06-30 00:35:00 +08:00
|
|
|
info->fprintf_styled_func (info->stream, dis_style_text, "0");
|
2021-10-22 16:42:04 +08:00
|
|
|
if (have_space[i])
|
2023-06-30 00:35:00 +08:00
|
|
|
info->fprintf_styled_func (info->stream, dis_style_text, " ");
|
2021-10-22 16:42:04 +08:00
|
|
|
t = t >> 1;
|
|
|
|
}
|
2023-06-30 00:35:00 +08:00
|
|
|
info->fprintf_styled_func (info->stream, dis_style_text, "\t");
|
2021-10-22 16:42:04 +08:00
|
|
|
#endif
|
|
|
|
|
|
|
|
if (!opc)
|
|
|
|
{
|
|
|
|
info->insn_type = dis_noninsn;
|
2023-06-30 00:35:03 +08:00
|
|
|
info->fprintf_styled_func (info->stream, dis_style_assembler_directive, ".word\t\t");
|
2023-06-30 00:35:00 +08:00
|
|
|
info->fprintf_styled_func (info->stream, dis_style_immediate, "0x%08x", insn);
|
2021-10-22 16:42:04 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
info->insn_type = dis_nonbranch;
|
2024-01-03 19:57:10 +08:00
|
|
|
if (opc->format == NULL || opc->format[0] == '\0')
|
|
|
|
info->fprintf_styled_func (info->stream, dis_style_mnemonic,
|
|
|
|
"%s", opc->name);
|
|
|
|
else
|
|
|
|
info->fprintf_styled_func (info->stream, dis_style_mnemonic,
|
|
|
|
"%-12s", opc->name);
|
2021-10-22 16:42:04 +08:00
|
|
|
|
|
|
|
{
|
|
|
|
char *fake_args = xmalloc (strlen (opc->format) + 1);
|
|
|
|
const char *fake_arg_strs[MAX_ARG_NUM_PLUS_2];
|
|
|
|
strcpy (fake_args, opc->format);
|
|
|
|
if (0 < loongarch_split_args_by_comma (fake_args, fake_arg_strs))
|
2023-06-30 00:35:00 +08:00
|
|
|
info->fprintf_styled_func (info->stream, dis_style_text, "\t");
|
2021-10-22 16:42:04 +08:00
|
|
|
info->private_data = &insn;
|
|
|
|
loongarch_foreach_args (opc->format, fake_arg_strs, dis_one_arg, info);
|
|
|
|
free (fake_args);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (info->insn_type == dis_branch || info->insn_type == dis_condbranch)
|
|
|
|
{
|
2023-06-30 00:35:00 +08:00
|
|
|
info->fprintf_styled_func (info->stream, dis_style_comment_start, "\t# ");
|
2021-10-22 16:42:04 +08:00
|
|
|
info->print_address_func (info->target, info);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
print_insn_loongarch (bfd_vma memaddr, struct disassemble_info *info)
|
|
|
|
{
|
|
|
|
insn_t insn;
|
|
|
|
int status;
|
|
|
|
|
|
|
|
static int not_init_yet = 1;
|
|
|
|
if (not_init_yet)
|
|
|
|
{
|
|
|
|
parse_loongarch_dis_options (info->disassembler_options);
|
|
|
|
not_init_yet = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
info->bytes_per_chunk = 4;
|
|
|
|
info->bytes_per_line = 4;
|
|
|
|
info->display_endian = BFD_ENDIAN_LITTLE;
|
|
|
|
info->insn_info_valid = 1;
|
|
|
|
info->target = memaddr;
|
|
|
|
|
|
|
|
if ((status = info->read_memory_func (memaddr, (bfd_byte *) &insn,
|
|
|
|
sizeof (insn), info)) != 0)
|
|
|
|
{
|
|
|
|
info->memory_error_func (status, memaddr, info);
|
|
|
|
return -1; /* loongarch_insn_length (0); */
|
|
|
|
}
|
|
|
|
|
|
|
|
disassemble_one (insn, info);
|
|
|
|
|
|
|
|
return loongarch_insn_length (insn);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
print_loongarch_disassembler_options (FILE *stream)
|
|
|
|
{
|
|
|
|
fprintf (stream, _("\n\
|
|
|
|
The following LoongArch disassembler options are supported for use\n\
|
|
|
|
with the -M switch (multiple options should be separated by commas):\n"));
|
|
|
|
|
LoongArch: support disassembling certain pseudo-instructions
Add a flag in the pinfo field for being able to mark certain specialized
matchers as disassembler-only, so some degree of isolation between
assembler-side and disassembler-side can be achieved.
This isolation is necessary, firstly because some pseudo-instructions
cannot be fully described in the opcode table, like `li.[wd]`, so the
corresponding opcode entry cannot have meaningful match/mask values.
Secondly, some of these pseudo-instructions can be realized in more than
one plausible ways; e.g. `li.w rd, <something between 0 and 0x7ff>` can
be realized on LA64 with any of `addi.w`, `addi.d` or `ori`. If we tie
disassembly of such aliases with the corresponding GAS support, only one
canonical form among the above would be recognized as `li.w`, and it
would mildly impact the readability of disassembly output.
People wanting the exact disassembly can always set `-M no-aliases` to
get the original behavior back.
In addition, in certain cases, information is irreversibly lost after
assembling, so perfect round-trip would not be possible in such cases.
For example, `li.w` and `li.d` of immediates within int32_t range
produce the same code; in this patch, `addi.d rd, $zero, imm` is treated
as `li.d`, while `addi.w` and `ori` immediate loads are shown as `li.w`,
due to the expressible value range well within 32 bits.
gas/ChangeLog:
* config/tc-loongarch.c (get_loongarch_opcode): Ignore
disassembler-only aliases.
* testsuite/gas/loongarch/64_pcrel.d: Update test case.
* testsuite/gas/loongarch/imm_ins.d: Likewise.
* testsuite/gas/loongarch/imm_ins_32.d: Likewise.
* testsuite/gas/loongarch/jmp_op.d: Likewise.
* testsuite/gas/loongarch/li.d: Likewise.
* testsuite/gas/loongarch/macro_op.d: Likewise.
* testsuite/gas/loongarch/macro_op_32.d: Likewise.
* testsuite/gas/loongarch/macro_op_large_abs.d: Likewise.
* testsuite/gas/loongarch/macro_op_large_pc.d: Likewise.
* testsuite/gas/loongarch/nop.d: Likewise.
* testsuite/gas/loongarch/relax_align.d: Likewise.
* testsuite/gas/loongarch/reloc.d: Likewise.
include/ChangeLog:
* opcode/loongarch.h (INSN_DIS_ALIAS): Add.
ld/ChangeLog:
* testsuite/ld-loongarch-elf/jmp_op.d: Update test case.
* testsuite/ld-loongarch-elf/macro_op.d: Likewise.
* testsuite/ld-loongarch-elf/macro_op_32.d: Likewise.
* testsuite/ld-loongarch-elf/relax-align.dd: Likewise.
opcodes/ChangeLog:
* loongarch-dis.c: Move register name map declarations to top.
(get_loongarch_opcode_by_binfmt): Consider aliases when
disassembling without the no-aliases option.
(parse_loongarch_dis_option): Support the no-aliases option.
* loongarch-opc.c: Collect pseudo instructions into a new
dedicated table.
Signed-off-by: WANG Xuerui <git@xen0n.name>
2023-06-30 00:34:58 +08:00
|
|
|
fprintf (stream, _("\n\
|
|
|
|
no-aliases Use canonical instruction forms.\n"));
|
2021-10-22 16:42:04 +08:00
|
|
|
fprintf (stream, _("\n\
|
|
|
|
numeric Print numeric register names, rather than ABI names.\n"));
|
|
|
|
fprintf (stream, _("\n"));
|
|
|
|
}
|