2024-01-04 19:52:08 +08:00
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/* Copyright (C) 2007-2024 Free Software Foundation, Inc.
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2007-06-28 22:29:56 +08:00
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2007-07-05 17:49:03 +08:00
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This file is part of the GNU opcodes library.
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2007-06-28 22:29:56 +08:00
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2007-07-05 17:49:03 +08:00
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This library is free software; you can redistribute it and/or modify
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2007-06-28 22:29:56 +08:00
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it under the terms of the GNU General Public License as published by
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2007-07-05 17:49:03 +08:00
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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2007-06-28 22:29:56 +08:00
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2007-07-05 17:49:03 +08:00
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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2007-06-28 22:29:56 +08:00
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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2007-07-05 17:49:03 +08:00
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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2007-06-28 22:29:56 +08:00
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2007-09-09 09:22:57 +08:00
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#include "sysdep.h"
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2022-12-22 16:32:29 +08:00
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#include <stdbool.h>
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2007-06-28 22:29:56 +08:00
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#include <stdio.h>
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#include <errno.h>
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#include "getopt.h"
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#include "libiberty.h"
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2008-10-01 03:47:14 +08:00
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#include "hashtab.h"
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2007-06-28 22:29:56 +08:00
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#include "safe-ctype.h"
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#include "i386-opc.h"
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2019-07-17 15:15:49 +08:00
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/* Build-time checks are preferrable over runtime ones. Use this construct
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in preference where possible. */
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#define static_assert(e) ((void)sizeof (struct { int _:1 - 2 * !(e); }))
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2007-06-28 22:29:56 +08:00
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static const char *program_name = NULL;
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static int debug = 0;
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2022-12-22 16:32:29 +08:00
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typedef struct dependency
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2007-09-09 09:22:57 +08:00
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{
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const char *name;
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/* Note: Only direct dependencies should be enumerated. */
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const char *deps;
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} dependency;
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2007-09-09 09:22:57 +08:00
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2022-12-22 16:32:29 +08:00
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static const dependency isa_dependencies[] =
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2007-09-09 09:22:57 +08:00
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{
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2022-12-22 16:32:29 +08:00
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{ "UNKNOWN",
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2022-12-19 16:22:33 +08:00
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"~IAMCU" },
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2022-12-22 16:32:29 +08:00
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{ "GENERIC32",
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"386" },
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{ "GENERIC64",
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"PENTIUMPRO|Clflush|SYSCALL|MMX|SSE2|LM" },
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{ "NONE",
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"0" },
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{ "PENTIUMPRO",
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"686|Nop" },
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{ "P2",
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"PENTIUMPRO|MMX" },
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{ "P3",
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"P2|SSE" },
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{ "P4",
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"P3|Clflush|SSE2" },
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{ "NOCONA",
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2023-02-24 20:59:35 +08:00
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"GENERIC64|FISTTP|SSE3|MONITOR|CX16" },
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2022-12-22 16:32:29 +08:00
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{ "CORE",
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2023-11-09 19:53:30 +08:00
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"P4|FISTTP|SSE3|MONITOR" },
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2022-12-22 16:32:29 +08:00
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{ "CORE2",
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"NOCONA|SSSE3" },
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{ "COREI7",
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2023-02-24 20:58:35 +08:00
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"CORE2|SSE4_2|Rdtscp|LAHF_SAHF" },
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2022-12-22 16:32:29 +08:00
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{ "K6",
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"186|286|386|486|586|SYSCALL|387|MMX" },
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{ "K6_2",
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"K6|3dnow" },
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{ "ATHLON",
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"K6_2|686:min|687|Nop|3dnowA" },
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{ "K8",
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"ATHLON|Rdtscp|SSE2|LM" },
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{ "AMDFAM10",
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2023-02-24 20:59:35 +08:00
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"K8|FISTTP|SSE4A|ABM|MONITOR" },
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2022-12-22 16:32:29 +08:00
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{ "BDVER1",
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2023-09-01 18:29:24 +08:00
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"GENERIC64|FISTTP|Rdtscp|MONITOR|CX16|LAHF_SAHF|XOP|ABM|LWP|SVME|AES|PCLMULQDQ|PRFCHW" },
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2022-12-22 16:32:29 +08:00
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{ "BDVER2",
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"BDVER1|FMA|BMI|TBM|F16C" },
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{ "BDVER3",
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"BDVER2|Xsaveopt|FSGSBase" },
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{ "BDVER4",
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"BDVER3|AVX2|Movbe|BMI2|RdRnd|MWAITX" },
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{ "ZNVER1",
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2023-09-01 18:29:24 +08:00
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"GENERIC64|FISTTP|Rdtscp|MONITOR|CX16|LAHF_SAHF|AVX2|SSE4A|ABM|SVME|AES|PCLMULQDQ|PRFCHW|FMA|BMI|F16C|Xsaveopt|FSGSBase|Movbe|BMI2|RdRnd|ADX|RdSeed|SMAP|SHA|XSAVEC|XSAVES|ClflushOpt|CLZERO|MWAITX" },
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{ "ZNVER2",
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"ZNVER1|CLWB|RDPID|RDPRU|MCOMMIT|WBNOINVD" },
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{ "ZNVER3",
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"ZNVER2|INVLPGB|TLBSYNC|VAES|VPCLMULQDQ|INVPCID|SNP|OSPKE" },
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{ "ZNVER4",
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"ZNVER3|AVX512F|AVX512DQ|AVX512IFMA|AVX512CD|AVX512BW|AVX512VL|AVX512_BF16|AVX512VBMI|AVX512_VBMI2|AVX512_VNNI|AVX512_BITALG|AVX512_VPOPCNTDQ|GFNI|RMPQUERY" },
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2023-12-20 13:10:21 +08:00
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{ "ZNVER5",
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"ZNVER4|AVX_VNNI|MOVDIRI|MOVDIR64B|AVX512_VP2INTERSECT|PREFETCHI" },
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2022-12-22 16:32:29 +08:00
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{ "BTVER1",
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2023-02-24 20:59:35 +08:00
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"GENERIC64|FISTTP|MONITOR|CX16|LAHF_SAHF|Rdtscp|SSSE3|SSE4A|ABM|PRFCHW|Clflush|FISTTP|SVME" },
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2022-12-22 16:32:29 +08:00
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{ "BTVER2",
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2023-09-01 18:29:24 +08:00
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"BTVER1|AVX|BMI|F16C|AES|PCLMULQDQ|Movbe|Xsaveopt|PRFCHW" },
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2022-12-22 16:32:29 +08:00
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{ "286",
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2022-12-19 16:22:33 +08:00
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"186" },
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2022-12-22 16:32:29 +08:00
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{ "386",
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"286" },
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{ "486",
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"386" },
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{ "586",
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"486|387" },
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{ "586:nofpu",
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"486" },
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{ "686",
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"586|687|CMOV|FXSR" },
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{ "686:min",
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"586|687" },
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{ "687",
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2022-12-19 16:22:33 +08:00
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"387" },
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2022-12-22 16:32:29 +08:00
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{ "FISTTP",
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"687" },
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2022-12-22 16:33:26 +08:00
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{ "SSE",
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"FXSR" },
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2022-12-22 16:32:29 +08:00
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{ "SSE2",
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2022-12-19 16:22:33 +08:00
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"SSE" },
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2022-12-22 16:32:29 +08:00
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{ "SSE3",
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"SSE2" },
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{ "SSSE3",
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"SSE3" },
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{ "SSE4_1",
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"SSSE3" },
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{ "SSE4_2",
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"SSE4_1|POPCNT" },
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{ "Xsaveopt",
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"XSAVE" },
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{ "AES",
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"SSE2" },
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2023-09-01 18:29:24 +08:00
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{ "PCLMULQDQ",
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2022-12-22 16:32:29 +08:00
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"SSE2" },
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{ "FMA",
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"AVX" },
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{ "FMA4",
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"AVX" },
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{ "XOP",
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"SSE4A|FMA4" },
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{ "LWP",
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"XSAVE" },
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{ "F16C",
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"AVX" },
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{ "3dnow",
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"MMX" },
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{ "3dnowA",
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"3dnow" },
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{ "SSE4a",
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"SSE3" },
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{ "ABM",
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2022-12-19 16:22:33 +08:00
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"LZCNT|POPCNT" },
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2022-12-22 16:32:29 +08:00
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{ "AVX",
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"SSE4_2|XSAVE" },
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{ "AVX2",
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"AVX" },
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{ "AVX_VNNI",
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"AVX2" },
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{ "AVX_IFMA",
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"AVX2" },
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{ "AVX_VNNI_INT8",
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"AVX2" },
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2023-08-02 19:06:23 +08:00
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{ "AVX_VNNI_INT16",
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"AVX2" },
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2022-12-22 16:32:29 +08:00
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{ "AVX_NE_CONVERT",
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"AVX2" },
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2023-11-09 19:54:23 +08:00
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{ "CX16",
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"64" },
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{ "LKGS",
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"64" },
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2023-05-19 19:00:55 +08:00
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{ "FRED",
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"LKGS" },
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2022-12-22 16:32:29 +08:00
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{ "AVX512F",
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"AVX2" },
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{ "AVX512CD",
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"AVX512F" },
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{ "AVX512ER",
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"AVX512F" },
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{ "AVX512PF",
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"AVX512F" },
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{ "AVX512DQ",
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"AVX512F" },
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{ "AVX512BW",
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"AVX512F" },
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{ "AVX512VL",
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"AVX512F" },
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{ "AVX512IFMA",
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"AVX512F" },
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{ "AVX512VBMI",
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2022-12-22 16:34:50 +08:00
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"AVX512BW" },
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2022-12-22 16:32:29 +08:00
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{ "AVX512_4FMAPS",
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"AVX512F" },
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{ "AVX512_4VNNIW",
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"AVX512F" },
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{ "AVX512_VPOPCNTDQ",
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"AVX512F" },
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{ "AVX512_VBMI2",
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2022-12-22 16:34:50 +08:00
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"AVX512BW" },
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2022-12-22 16:32:29 +08:00
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{ "AVX512_VNNI",
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"AVX512F" },
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{ "AVX512_BITALG",
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2022-12-22 16:34:50 +08:00
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"AVX512BW" },
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2022-12-22 16:32:29 +08:00
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{ "AVX512_VP2INTERSECT",
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"AVX512F" },
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{ "AVX512_BF16",
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2022-12-22 16:34:50 +08:00
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"AVX512BW" },
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2022-12-22 16:32:29 +08:00
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{ "AVX512_FP16",
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"AVX512BW" },
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{ "IAMCU",
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"586:nofpu" },
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2022-12-22 16:35:32 +08:00
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{ "EPT",
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"VMX" },
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{ "VMFUNC",
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"VMX" },
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2022-12-22 16:32:29 +08:00
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{ "MPX",
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"XSAVE" },
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{ "SHA",
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"SSE2" },
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2023-08-02 19:06:23 +08:00
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{ "SHA512",
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"AVX2" },
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{ "SM3",
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"AVX" },
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{ "SM4",
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"AVX2" },
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2022-12-22 16:32:29 +08:00
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{ "XSAVES",
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2022-12-22 16:35:11 +08:00
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"XSAVEC" },
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2022-12-22 16:32:29 +08:00
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{ "XSAVEC",
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"XSAVE" },
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{ "OSPKE",
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"XSAVE" },
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2022-12-22 16:33:26 +08:00
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{ "GFNI",
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"SSE2" },
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2022-12-22 16:33:53 +08:00
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{ "VAES",
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2023-09-14 14:40:58 +08:00
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"AVX2|AES" },
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2022-12-22 16:33:53 +08:00
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{ "VPCLMULQDQ",
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2023-09-14 14:40:58 +08:00
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"AVX2|PCLMULQDQ" },
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2023-09-14 14:42:43 +08:00
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{ "AVX10_1",
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"AVX512VL|AVX512DQ|AVX512CD|AVX512VBMI|AVX512_VBMI2|AVX512IFMA"
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"|AVX512_VNNI|AVX512_BF16|AVX512_FP16|AVX512_VPOPCNTDQ|AVX512_BITALG" },
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2022-12-22 16:35:53 +08:00
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{ "SEV_ES",
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"SVME" },
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{ "SNP",
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"SEV_ES" },
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{ "RMPQUERY",
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2023-11-09 19:54:23 +08:00
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"SNP|64" },
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2022-12-22 16:36:16 +08:00
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{ "TSX",
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"RTM|HLE" },
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{ "TSXLDTRK",
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"RTM" },
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2022-12-22 16:35:11 +08:00
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{ "AMX_TILE",
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2023-11-09 19:54:23 +08:00
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"XSAVE|64" },
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2022-12-22 16:32:29 +08:00
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{ "AMX_INT8",
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"AMX_TILE" },
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{ "AMX_BF16",
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"AMX_TILE" },
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{ "AMX_FP16",
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2022-12-19 16:22:33 +08:00
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"AMX_TILE" },
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2023-04-07 10:02:09 +08:00
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{ "AMX_COMPLEX",
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"AMX_TILE" },
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2022-12-22 16:33:26 +08:00
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{ "KL",
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"SSE2" },
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{ "WIDEKL",
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"KL" },
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2023-11-09 19:54:23 +08:00
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{ "PBNDKB",
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"64" },
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{ "UINTR",
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"64" },
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{ "PREFETCHI",
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"64" },
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{ "CMPCCXADD",
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"64" },
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{ "MSRLIST",
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"64" },
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{ "USER_MSR",
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"64" },
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2023-12-28 09:06:39 +08:00
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{ "APX_F",
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"XSAVE|64" },
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2007-09-09 09:22:57 +08:00
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};
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2022-12-22 16:32:29 +08:00
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/* This array is populated as process_i386_initializers() walks cpu_flags[]. */
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2023-09-15 15:57:05 +08:00
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static unsigned char isa_reverse_deps[CpuMax][CpuMax];
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2022-12-22 16:32:29 +08:00
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2007-09-09 09:22:57 +08:00
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typedef struct bitfield
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{
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int position;
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int value;
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const char *name;
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} bitfield;
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2022-12-19 16:22:33 +08:00
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#define BITFIELD(n) { Cpu##n, 0, #n }
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2007-09-09 09:22:57 +08:00
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static bitfield cpu_flags[] =
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{
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2022-12-19 16:22:33 +08:00
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BITFIELD (186),
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BITFIELD (286),
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BITFIELD (386),
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BITFIELD (486),
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BITFIELD (586),
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BITFIELD (686),
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BITFIELD (CMOV),
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BITFIELD (FXSR),
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BITFIELD (Clflush),
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BITFIELD (Nop),
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BITFIELD (SYSCALL),
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BITFIELD (8087),
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BITFIELD (287),
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BITFIELD (387),
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BITFIELD (687),
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BITFIELD (FISTTP),
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BITFIELD (MMX),
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BITFIELD (SSE),
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BITFIELD (SSE2),
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BITFIELD (SSE3),
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BITFIELD (SSSE3),
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BITFIELD (SSE4_1),
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BITFIELD (SSE4_2),
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BITFIELD (AVX),
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BITFIELD (AVX2),
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BITFIELD (AVX512F),
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BITFIELD (AVX512CD),
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BITFIELD (AVX512ER),
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BITFIELD (AVX512PF),
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BITFIELD (AVX512VL),
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BITFIELD (AVX512DQ),
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BITFIELD (AVX512BW),
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BITFIELD (IAMCU),
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BITFIELD (SSE4a),
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BITFIELD (3dnow),
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BITFIELD (3dnowA),
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BITFIELD (PadLock),
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BITFIELD (SVME),
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BITFIELD (VMX),
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BITFIELD (SMX),
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BITFIELD (Xsave),
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BITFIELD (Xsaveopt),
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BITFIELD (AES),
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2023-09-01 18:29:24 +08:00
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BITFIELD (PCLMULQDQ),
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2022-12-19 16:22:33 +08:00
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BITFIELD (FMA),
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BITFIELD (FMA4),
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BITFIELD (XOP),
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BITFIELD (LWP),
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BITFIELD (BMI),
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BITFIELD (TBM),
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BITFIELD (Movbe),
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BITFIELD (CX16),
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2023-02-24 20:58:35 +08:00
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BITFIELD (LAHF_SAHF),
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2022-12-19 16:22:33 +08:00
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BITFIELD (EPT),
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BITFIELD (Rdtscp),
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BITFIELD (FSGSBase),
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BITFIELD (RdRnd),
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BITFIELD (F16C),
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BITFIELD (BMI2),
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BITFIELD (LZCNT),
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BITFIELD (POPCNT),
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2023-02-24 20:59:35 +08:00
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BITFIELD (MONITOR),
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2022-12-19 16:22:33 +08:00
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BITFIELD (HLE),
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BITFIELD (RTM),
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BITFIELD (INVPCID),
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BITFIELD (VMFUNC),
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BITFIELD (RDSEED),
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BITFIELD (ADX),
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BITFIELD (PRFCHW),
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BITFIELD (SMAP),
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BITFIELD (SHA),
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2023-08-02 19:06:23 +08:00
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BITFIELD (SHA512),
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BITFIELD (SM3),
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BITFIELD (SM4),
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2022-12-19 16:22:33 +08:00
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BITFIELD (ClflushOpt),
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BITFIELD (XSAVES),
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BITFIELD (XSAVEC),
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BITFIELD (PREFETCHWT1),
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BITFIELD (SE1),
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BITFIELD (CLWB),
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BITFIELD (MPX),
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BITFIELD (AVX512IFMA),
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BITFIELD (AVX512VBMI),
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BITFIELD (AVX512_4FMAPS),
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BITFIELD (AVX512_4VNNIW),
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BITFIELD (AVX512_VPOPCNTDQ),
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BITFIELD (AVX512_VBMI2),
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BITFIELD (AVX512_VNNI),
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BITFIELD (AVX512_BITALG),
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BITFIELD (AVX512_BF16),
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BITFIELD (AVX512_VP2INTERSECT),
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BITFIELD (TDX),
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BITFIELD (AVX_VNNI),
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BITFIELD (AVX512_FP16),
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BITFIELD (PREFETCHI),
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BITFIELD (AVX_IFMA),
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BITFIELD (AVX_VNNI_INT8),
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2023-08-02 19:06:23 +08:00
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BITFIELD (AVX_VNNI_INT16),
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2022-12-19 16:22:33 +08:00
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BITFIELD (CMPCCXADD),
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BITFIELD (WRMSRNS),
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BITFIELD (MSRLIST),
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BITFIELD (AVX_NE_CONVERT),
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BITFIELD (RAO_INT),
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2023-05-19 19:00:55 +08:00
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BITFIELD (FRED),
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BITFIELD (LKGS),
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2023-10-31 16:23:53 +08:00
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BITFIELD (USER_MSR),
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2023-12-28 09:06:39 +08:00
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BITFIELD (APX_F),
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2022-12-19 16:22:33 +08:00
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BITFIELD (MWAITX),
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BITFIELD (CLZERO),
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BITFIELD (OSPKE),
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BITFIELD (RDPID),
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BITFIELD (PTWRITE),
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BITFIELD (IBT),
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BITFIELD (SHSTK),
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BITFIELD (GFNI),
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BITFIELD (VAES),
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BITFIELD (VPCLMULQDQ),
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BITFIELD (WBNOINVD),
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BITFIELD (PCONFIG),
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2023-08-02 19:06:23 +08:00
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BITFIELD (PBNDKB),
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2022-12-19 16:22:33 +08:00
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BITFIELD (WAITPKG),
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BITFIELD (UINTR),
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BITFIELD (CLDEMOTE),
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BITFIELD (AMX_INT8),
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BITFIELD (AMX_BF16),
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BITFIELD (AMX_FP16),
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2023-04-07 10:02:09 +08:00
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BITFIELD (AMX_COMPLEX),
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2022-12-19 16:22:33 +08:00
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BITFIELD (AMX_TILE),
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BITFIELD (MOVDIRI),
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BITFIELD (MOVDIR64B),
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BITFIELD (ENQCMD),
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BITFIELD (SERIALIZE),
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BITFIELD (RDPRU),
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BITFIELD (MCOMMIT),
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BITFIELD (SEV_ES),
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BITFIELD (TSXLDTRK),
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BITFIELD (KL),
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BITFIELD (WideKL),
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BITFIELD (HRESET),
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BITFIELD (INVLPGB),
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BITFIELD (TLBSYNC),
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BITFIELD (SNP),
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BITFIELD (RMPQUERY),
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BITFIELD (64),
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BITFIELD (No64),
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2007-09-09 09:22:57 +08:00
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#ifdef CpuUnused
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2022-12-19 16:22:33 +08:00
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BITFIELD (Unused),
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2007-09-09 09:22:57 +08:00
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#endif
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};
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2022-12-19 16:22:33 +08:00
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#undef BITFIELD
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#define BITFIELD(n) { n, 0, #n }
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2007-09-09 09:22:57 +08:00
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static bitfield opcode_modifiers[] =
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{
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BITFIELD (D),
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BITFIELD (W),
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X86: Add pseudo prefixes to control encoding
Many x86 instructions have more than one encodings. Assembler picks
the default one, usually the shortest one. Although the ".s", ".d8"
and ".d32" suffixes can be used to swap register operands or specify
displacement size, they aren't very flexible. This patch adds pseudo
prefixes, {xxx}, to control instruction encoding. The available
pseudo prefixes are {disp8}, {disp32}, {load}, {store}, {vex2}, {vex3}
and {evex}. Pseudo prefixes are preferred over the ".s", ".d8" and
".d32" suffixes, which are deprecated.
gas/
* config/tc-i386.c (_i386_insn): Add dir_encoding and
vec_encoding. Remove swap_operand and need_vrex.
(extra_symbol_chars): Add '}'.
(md_begin): Mark '}' with LEX_BEGIN_NAME. Allow '}' in
mnemonic.
(build_vex_prefix): Don't use 2-byte VEX encoding with
{vex3}. Check dir_encoding and load.
(parse_insn): Check pseudo prefixes. Set dir_encoding.
(VEX_check_operands): Likewise.
(match_template): Check dir_encoding and load.
(parse_real_register): Set vec_encoding instead of need_vrex.
(parse_register): Likewise.
* doc/c-i386.texi: Document {disp8}, {disp32}, {load}, {store},
{vex2}, {vex3} and {evex}. Remove ".s", ".d8" and ".d32"
* testsuite/gas/i386/i386.exp: Run pseudos and x86-64-pseudos.
* testsuite/gas/i386/pseudos.d: New file.
* testsuite/gas/i386/pseudos.s: Likewise.
* testsuite/gas/i386/x86-64-pseudos.d: Likewise.
* testsuite/gas/i386/x86-64-pseudos.s: Likewise.
opcodes/
* i386-gen.c (opcode_modifiers): Replace S with Load.
* i386-opc.h (S): Removed.
(Load): New.
(i386_opcode_modifier): Replace s with load.
* i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
and {evex}. Replace S with Load.
* i386-tbl.h: Regenerated.
2017-03-10 01:58:46 +08:00
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BITFIELD (Load),
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2007-09-09 09:22:57 +08:00
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BITFIELD (Modrm),
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BITFIELD (Jump),
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BITFIELD (FloatMF),
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2018-10-10 14:41:52 +08:00
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BITFIELD (Size),
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2022-12-21 16:07:03 +08:00
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BITFIELD (CheckOperandSize),
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2022-11-15 00:10:14 +08:00
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BITFIELD (OperandConstraint),
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2020-03-04 03:24:16 +08:00
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BITFIELD (MnemonicSize),
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2007-09-09 09:22:57 +08:00
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BITFIELD (No_bSuf),
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BITFIELD (No_wSuf),
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BITFIELD (No_lSuf),
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BITFIELD (No_sSuf),
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BITFIELD (No_qSuf),
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BITFIELD (FWait),
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BITFIELD (IsString),
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2019-07-16 15:31:36 +08:00
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BITFIELD (RegMem),
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2013-07-24 23:47:25 +08:00
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BITFIELD (BNDPrefixOk),
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2021-03-09 15:54:32 +08:00
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BITFIELD (PrefixOk),
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2007-09-09 09:22:57 +08:00
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BITFIELD (IsPrefix),
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BITFIELD (ImmExt),
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BITFIELD (NoRex64),
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binutils/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* dwarf.c (dwarf_regnames_i386): Add AVX registers.
(dwarf_regnames_x86_64): Likewise.
gas/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention AES, CLMUL, AVX/FMA and -msse2avx.
* doc/c-i386.texi: Add avx, aes, clmul and fma to -march=.
Document -msse2avx, .avx, .aes, .clmul and .fma.
* config/tc-i386.c (YMMWORD_MNEM_SUFFIX): New.
(vex_prefix): Likewise.
(sse2avx): Likewise.
(CPU_FLAGS_ARCH_MATCH): Likewise.
(CPU_FLAGS_64BIT_MATCH): Likewise.
(CPU_FLAGS_32BIT_MATCH): Likewise.
(CPU_FLAGS_PERFECT_MATCH): Likewise.
(regymm): Likewise.
(vex_imm4): Likewise.
(fits_in_imm4): Likewise.
(build_vex_prefix): Likewise.
(VEX_check_operands): Likewise.
(bad_implicit_operand): Likewise.
(OPTION_MSSE2AVX): Likewise.
(T_YMMWORD): Likewise.
(_i386_insn): Add vex.
(cpu_arch): Add .avx, .aes, .clmul and .fma.
(cpu_flags_match): Changed to take a pointer to const template.
Enable encoding SSE instructions with VEX prefix for -msse2avx.
(match_mem_size): Also check ymmword.
(operand_type_match): Clear ymmword.
(md_begin): Allow '_' in mnemonic.
(type_names): Add OPERAND_TYPE_VEX_IMM4.
(process_immext): Update assert.
(md_assemble): Don't call process_immext if sse2avx and immext
are true. Call build_vex_prefix if vex is true.
(parse_insn): Updated for cpu_flags_match.
(swap_operands): Handle 5 operands.
(match_template): Handle 5 operands. Updated for cpu_flags_match.
Check regymm. Call VEX_check_operands. Handle YMMWORD_MNEM_SUFFIX.
(process_suffix): Handle YMMWORD_MNEM_SUFFIX.
(check_byte_reg): Check regymm.
(process_operands): Duplicate the destination register for
-msse2avx if needed.
(build_modrm_byte): Updated for instructions with VEX encoding.
(output_insn): Output VEX prefix if needed.
(md_longopts): Add msse2avx.
(md_parse_option): Handle OPTION_MSSE2AVX.
(md_show_usage): Add avx, aes, clmul, fma and -msse2avx.
(intel_e09): Support YMMWORD.
(intel_e11): Likewise.
(intel_get_token): Likewise.
gas/testsuite/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run aes, aes-intel, x86-64-aes,
x86-64-aes-intel, avx, avx-intel, inval-avx, x86-64-avx,
x86-64-avx-intel and x86-64-inval-avx.
* gas/cfi/cfi-i386.s: Add tests for AVX register maps.
* gas/cfi/cfi-x86_64.s: Likewise.
* gas/i386/aes.d: New.
* gas/i386/aes.s: Likewise.
* gas/i386/aes-intel.d: Likewise.
* gas/i386/avx.d: Likewise.
* gas/i386/avx.s: Likewise.
* gas/i386/avx-intel.d: Likewise.
* gas/i386/clmul.d: Likewise.
* gas/i386/clmul-intel.d: Likewise.
* gas/i386/clmul.s: Likewise.
* gas/i386/i386.exp: Likewise.
* gas/i386/inval-avx.l: Likewise.
* gas/i386/inval-avx.s: Likewise.
* gas/i386/sse2avx.d: Likewise.
* gas/i386/sse2avx.s: Likewise.
* gas/i386/x86-64-aes.d: Likewise.
* gas/i386/x86-64-aes.s: Likewise.
* gas/i386/x86-64-aes-intel.d: Likewise.
* gas/i386/x86-64-avx.d: Likewise.
* gas/i386/x86-64-avx.s: Likewise.
* gas/i386/x86-64-avx-intel.d: Likewise.
* gas/i386/x86-64-clmul.d: Likewise.
* gas/i386/x86-64-clmul-intel.d: Likewise.
* gas/i386/x86-64-clmul.s: Likewise.
* gas/i386/x86-64-inval-avx.l: Likewise.
* gas/i386/x86-64-inval-avx.s: Likewise.
* gas/i386/x86-64-sse2avx.d: Likewise.
* gas/i386/x86-64-sse2avx.s: Likewise.
* gas/i386/arch-10.s: Add tests for AVX, AES, CLMUL and FMA.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/rexw.s: Add AVX tests.
* gas/i386/x86-64-opcode-inval.s: Remove lds/les test.
* gas/cfi/cfi-i386.d: Updated.
* gas/cfi/cfi-x86_64.d: Likewise.
* gas/i386/arch-10.d: Likewise.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/rexw.d: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
* gas/i386/x86-64-opcode-inval.d: Likewise.
* gas/i386/x86-64-opcode-inval-intel.d: Likewise.
include/opcode/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (MAX_OPERANDS): Set to 5.
(MAX_MNEM_SIZE): Changed to 20.
opcodes/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (OP_E_register): New.
(OP_E_memory): Likewise.
(OP_VEX): Likewise.
(OP_EX_Vex): Likewise.
(OP_EX_VexW): Likewise.
(OP_XMM_Vex): Likewise.
(OP_XMM_VexW): Likewise.
(OP_REG_VexI4): Likewise.
(PCLMUL_Fixup): Likewise.
(VEXI4_Fixup): Likewise.
(VZERO_Fixup): Likewise.
(VCMP_Fixup): Likewise.
(VPERMIL2_Fixup): Likewise.
(rex_original): Likewise.
(rex_ignored): Likewise.
(Mxmm): Likewise.
(XMM): Likewise.
(EXxmm): Likewise.
(EXxmmq): Likewise.
(EXymmq): Likewise.
(Vex): Likewise.
(Vex128): Likewise.
(Vex256): Likewise.
(VexI4): Likewise.
(EXdVex): Likewise.
(EXqVex): Likewise.
(EXVexW): Likewise.
(EXdVexW): Likewise.
(EXqVexW): Likewise.
(XMVex): Likewise.
(XMVexW): Likewise.
(XMVexI4): Likewise.
(PCLMUL): Likewise.
(VZERO): Likewise.
(VCMP): Likewise.
(VPERMIL2): Likewise.
(xmm_mode): Likewise.
(xmmq_mode): Likewise.
(ymmq_mode): Likewise.
(vex_mode): Likewise.
(vex128_mode): Likewise.
(vex256_mode): Likewise.
(USE_VEX_C4_TABLE): Likewise.
(USE_VEX_C5_TABLE): Likewise.
(USE_VEX_LEN_TABLE): Likewise.
(VEX_C4_TABLE): Likewise.
(VEX_C5_TABLE): Likewise.
(VEX_LEN_TABLE): Likewise.
(REG_VEX_XX): Likewise.
(MOD_VEX_XXX): Likewise.
(PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
(PREFIX_0F3A44): Likewise.
(PREFIX_0F3ADF): Likewise.
(PREFIX_VEX_XXX): Likewise.
(VEX_OF): Likewise.
(VEX_OF38): Likewise.
(VEX_OF3A): Likewise.
(VEX_LEN_XXX): Likewise.
(vex): Likewise.
(need_vex): Likewise.
(need_vex_reg): Likewise.
(vex_i4_done): Likewise.
(vex_table): Likewise.
(vex_len_table): Likewise.
(OP_REG_VexI4): Likewise.
(vex_cmp_op): Likewise.
(pclmul_op): Likewise.
(vpermil2_op): Likewise.
(m_mode): Updated.
(es_reg): Likewise.
(PREFIX_0F38F0): Likewise.
(PREFIX_0F3A60): Likewise.
(reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
(prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
and PREFIX_VEX_XXX entries.
(x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
(three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
PREFIX_0F3ADF.
(mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
Add MOD_VEX_XXX entries.
(ckprefix): Initialize rex_original and rex_ignored. Store the
REX byte in rex_original.
(get_valid_dis386): Handle the implicit prefix in VEX prefix
bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
(print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
calling get_valid_dis386. Use rex_original and rex_ignored when
printing out REX.
(putop): Handle "XY".
(intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
ymmq_mode.
(OP_E_extended): Updated to use OP_E_register and
OP_E_memory.
(OP_XMM): Handle VEX.
(OP_EX): Likewise.
(XMM_Fixup): Likewise.
(CMP_Fixup): Use ARRAY_SIZE.
* i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
CPU_FMA_FLAGS and CPU_AVX_FLAGS.
(operand_type_init): Add OPERAND_TYPE_REGYMM and
OPERAND_TYPE_VEX_IMM4.
(cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
(opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
VexImmExt and SSE2AVX.
(operand_types): Add RegYMM, Ymmword and Vex_Imm4.
* i386-opc.h (CpuAVX): New.
(CpuAES): Likewise.
(CpuCLMUL): Likewise.
(CpuFMA): Likewise.
(Vex): Likewise.
(Vex256): Likewise.
(VexNDS): Likewise.
(VexNDD): Likewise.
(VexW0): Likewise.
(VexW1): Likewise.
(Vex0F): Likewise.
(Vex0F38): Likewise.
(Vex0F3A): Likewise.
(Vex3Sources): Likewise.
(VexImmExt): Likewise.
(SSE2AVX): Likewise.
(RegYMM): Likewise.
(Ymmword): Likewise.
(Vex_Imm4): Likewise.
(Implicit1stXmm0): Likewise.
(CpuXsave): Updated.
(CpuLM): Likewise.
(ByteOkIntel): Likewise.
(OldGcc): Likewise.
(Control): Likewise.
(Unspecified): Likewise.
(OTMax): Likewise.
(i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
(i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
vex3sources, veximmext and sse2avx.
(i386_operand_type): Add regymm, ymmword and vex_imm4.
* i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
* i386-reg.tbl: Add AVX registers, ymm0..ymm15.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2008-04-03 22:03:21 +08:00
|
|
|
BITFIELD (Vex),
|
2009-12-20 02:36:27 +08:00
|
|
|
BITFIELD (VexVVVV),
|
2009-12-16 10:10:45 +08:00
|
|
|
BITFIELD (VexW),
|
2020-10-14 10:28:58 +08:00
|
|
|
BITFIELD (OpcodePrefix),
|
2020-06-26 23:24:30 +08:00
|
|
|
BITFIELD (SIB),
|
binutils/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* dwarf.c (dwarf_regnames_i386): Add AVX registers.
(dwarf_regnames_x86_64): Likewise.
gas/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention AES, CLMUL, AVX/FMA and -msse2avx.
* doc/c-i386.texi: Add avx, aes, clmul and fma to -march=.
Document -msse2avx, .avx, .aes, .clmul and .fma.
* config/tc-i386.c (YMMWORD_MNEM_SUFFIX): New.
(vex_prefix): Likewise.
(sse2avx): Likewise.
(CPU_FLAGS_ARCH_MATCH): Likewise.
(CPU_FLAGS_64BIT_MATCH): Likewise.
(CPU_FLAGS_32BIT_MATCH): Likewise.
(CPU_FLAGS_PERFECT_MATCH): Likewise.
(regymm): Likewise.
(vex_imm4): Likewise.
(fits_in_imm4): Likewise.
(build_vex_prefix): Likewise.
(VEX_check_operands): Likewise.
(bad_implicit_operand): Likewise.
(OPTION_MSSE2AVX): Likewise.
(T_YMMWORD): Likewise.
(_i386_insn): Add vex.
(cpu_arch): Add .avx, .aes, .clmul and .fma.
(cpu_flags_match): Changed to take a pointer to const template.
Enable encoding SSE instructions with VEX prefix for -msse2avx.
(match_mem_size): Also check ymmword.
(operand_type_match): Clear ymmword.
(md_begin): Allow '_' in mnemonic.
(type_names): Add OPERAND_TYPE_VEX_IMM4.
(process_immext): Update assert.
(md_assemble): Don't call process_immext if sse2avx and immext
are true. Call build_vex_prefix if vex is true.
(parse_insn): Updated for cpu_flags_match.
(swap_operands): Handle 5 operands.
(match_template): Handle 5 operands. Updated for cpu_flags_match.
Check regymm. Call VEX_check_operands. Handle YMMWORD_MNEM_SUFFIX.
(process_suffix): Handle YMMWORD_MNEM_SUFFIX.
(check_byte_reg): Check regymm.
(process_operands): Duplicate the destination register for
-msse2avx if needed.
(build_modrm_byte): Updated for instructions with VEX encoding.
(output_insn): Output VEX prefix if needed.
(md_longopts): Add msse2avx.
(md_parse_option): Handle OPTION_MSSE2AVX.
(md_show_usage): Add avx, aes, clmul, fma and -msse2avx.
(intel_e09): Support YMMWORD.
(intel_e11): Likewise.
(intel_get_token): Likewise.
gas/testsuite/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run aes, aes-intel, x86-64-aes,
x86-64-aes-intel, avx, avx-intel, inval-avx, x86-64-avx,
x86-64-avx-intel and x86-64-inval-avx.
* gas/cfi/cfi-i386.s: Add tests for AVX register maps.
* gas/cfi/cfi-x86_64.s: Likewise.
* gas/i386/aes.d: New.
* gas/i386/aes.s: Likewise.
* gas/i386/aes-intel.d: Likewise.
* gas/i386/avx.d: Likewise.
* gas/i386/avx.s: Likewise.
* gas/i386/avx-intel.d: Likewise.
* gas/i386/clmul.d: Likewise.
* gas/i386/clmul-intel.d: Likewise.
* gas/i386/clmul.s: Likewise.
* gas/i386/i386.exp: Likewise.
* gas/i386/inval-avx.l: Likewise.
* gas/i386/inval-avx.s: Likewise.
* gas/i386/sse2avx.d: Likewise.
* gas/i386/sse2avx.s: Likewise.
* gas/i386/x86-64-aes.d: Likewise.
* gas/i386/x86-64-aes.s: Likewise.
* gas/i386/x86-64-aes-intel.d: Likewise.
* gas/i386/x86-64-avx.d: Likewise.
* gas/i386/x86-64-avx.s: Likewise.
* gas/i386/x86-64-avx-intel.d: Likewise.
* gas/i386/x86-64-clmul.d: Likewise.
* gas/i386/x86-64-clmul-intel.d: Likewise.
* gas/i386/x86-64-clmul.s: Likewise.
* gas/i386/x86-64-inval-avx.l: Likewise.
* gas/i386/x86-64-inval-avx.s: Likewise.
* gas/i386/x86-64-sse2avx.d: Likewise.
* gas/i386/x86-64-sse2avx.s: Likewise.
* gas/i386/arch-10.s: Add tests for AVX, AES, CLMUL and FMA.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/rexw.s: Add AVX tests.
* gas/i386/x86-64-opcode-inval.s: Remove lds/les test.
* gas/cfi/cfi-i386.d: Updated.
* gas/cfi/cfi-x86_64.d: Likewise.
* gas/i386/arch-10.d: Likewise.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/rexw.d: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
* gas/i386/x86-64-opcode-inval.d: Likewise.
* gas/i386/x86-64-opcode-inval-intel.d: Likewise.
include/opcode/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (MAX_OPERANDS): Set to 5.
(MAX_MNEM_SIZE): Changed to 20.
opcodes/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (OP_E_register): New.
(OP_E_memory): Likewise.
(OP_VEX): Likewise.
(OP_EX_Vex): Likewise.
(OP_EX_VexW): Likewise.
(OP_XMM_Vex): Likewise.
(OP_XMM_VexW): Likewise.
(OP_REG_VexI4): Likewise.
(PCLMUL_Fixup): Likewise.
(VEXI4_Fixup): Likewise.
(VZERO_Fixup): Likewise.
(VCMP_Fixup): Likewise.
(VPERMIL2_Fixup): Likewise.
(rex_original): Likewise.
(rex_ignored): Likewise.
(Mxmm): Likewise.
(XMM): Likewise.
(EXxmm): Likewise.
(EXxmmq): Likewise.
(EXymmq): Likewise.
(Vex): Likewise.
(Vex128): Likewise.
(Vex256): Likewise.
(VexI4): Likewise.
(EXdVex): Likewise.
(EXqVex): Likewise.
(EXVexW): Likewise.
(EXdVexW): Likewise.
(EXqVexW): Likewise.
(XMVex): Likewise.
(XMVexW): Likewise.
(XMVexI4): Likewise.
(PCLMUL): Likewise.
(VZERO): Likewise.
(VCMP): Likewise.
(VPERMIL2): Likewise.
(xmm_mode): Likewise.
(xmmq_mode): Likewise.
(ymmq_mode): Likewise.
(vex_mode): Likewise.
(vex128_mode): Likewise.
(vex256_mode): Likewise.
(USE_VEX_C4_TABLE): Likewise.
(USE_VEX_C5_TABLE): Likewise.
(USE_VEX_LEN_TABLE): Likewise.
(VEX_C4_TABLE): Likewise.
(VEX_C5_TABLE): Likewise.
(VEX_LEN_TABLE): Likewise.
(REG_VEX_XX): Likewise.
(MOD_VEX_XXX): Likewise.
(PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
(PREFIX_0F3A44): Likewise.
(PREFIX_0F3ADF): Likewise.
(PREFIX_VEX_XXX): Likewise.
(VEX_OF): Likewise.
(VEX_OF38): Likewise.
(VEX_OF3A): Likewise.
(VEX_LEN_XXX): Likewise.
(vex): Likewise.
(need_vex): Likewise.
(need_vex_reg): Likewise.
(vex_i4_done): Likewise.
(vex_table): Likewise.
(vex_len_table): Likewise.
(OP_REG_VexI4): Likewise.
(vex_cmp_op): Likewise.
(pclmul_op): Likewise.
(vpermil2_op): Likewise.
(m_mode): Updated.
(es_reg): Likewise.
(PREFIX_0F38F0): Likewise.
(PREFIX_0F3A60): Likewise.
(reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
(prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
and PREFIX_VEX_XXX entries.
(x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
(three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
PREFIX_0F3ADF.
(mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
Add MOD_VEX_XXX entries.
(ckprefix): Initialize rex_original and rex_ignored. Store the
REX byte in rex_original.
(get_valid_dis386): Handle the implicit prefix in VEX prefix
bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
(print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
calling get_valid_dis386. Use rex_original and rex_ignored when
printing out REX.
(putop): Handle "XY".
(intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
ymmq_mode.
(OP_E_extended): Updated to use OP_E_register and
OP_E_memory.
(OP_XMM): Handle VEX.
(OP_EX): Likewise.
(XMM_Fixup): Likewise.
(CMP_Fixup): Use ARRAY_SIZE.
* i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
CPU_FMA_FLAGS and CPU_AVX_FLAGS.
(operand_type_init): Add OPERAND_TYPE_REGYMM and
OPERAND_TYPE_VEX_IMM4.
(cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
(opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
VexImmExt and SSE2AVX.
(operand_types): Add RegYMM, Ymmword and Vex_Imm4.
* i386-opc.h (CpuAVX): New.
(CpuAES): Likewise.
(CpuCLMUL): Likewise.
(CpuFMA): Likewise.
(Vex): Likewise.
(Vex256): Likewise.
(VexNDS): Likewise.
(VexNDD): Likewise.
(VexW0): Likewise.
(VexW1): Likewise.
(Vex0F): Likewise.
(Vex0F38): Likewise.
(Vex0F3A): Likewise.
(Vex3Sources): Likewise.
(VexImmExt): Likewise.
(SSE2AVX): Likewise.
(RegYMM): Likewise.
(Ymmword): Likewise.
(Vex_Imm4): Likewise.
(Implicit1stXmm0): Likewise.
(CpuXsave): Updated.
(CpuLM): Likewise.
(ByteOkIntel): Likewise.
(OldGcc): Likewise.
(Control): Likewise.
(Unspecified): Likewise.
(OTMax): Likewise.
(i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
(i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
vex3sources, veximmext and sse2avx.
(i386_operand_type): Add regymm, ymmword and vex_imm4.
* i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
* i386-reg.tbl: Add AVX registers, ymm0..ymm15.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2008-04-03 22:03:21 +08:00
|
|
|
BITFIELD (SSE2AVX),
|
Add Intel AVX-512 support
binutils/
2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
Alexander Ivchenko <alexander.ivchenko@intel.com>
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Sergey Lega <sergey.s.lega@intel.com>
Anna Tikhonova <anna.tikhonova@intel.com>
Ilya Tocar <ilya.tocar@intel.com>
Andrey Turetskiy <andrey.turetskiy@intel.com>
Ilya Verbin <ilya.verbin@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and
numeration in comments.
(dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to
dwarf table.
gas/
2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
Alexander Ivchenko <alexander.ivchenko@intel.com>
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Sergey Lega <sergey.s.lega@intel.com>
Anna Tikhonova <anna.tikhonova@intel.com>
Ilya Tocar <ilya.tocar@intel.com>
Andrey Turetskiy <andrey.turetskiy@intel.com>
Ilya Verbin <ilya.verbin@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* config/tc-i386-intel.c (O_zmmword_ptr): New.
(i386_types): Add zmmword.
(i386_intel_simplify_register): Allow regzmm.
(i386_intel_simplify): Handle zmmwords.
(i386_intel_operand): Handle RC/SAE, vector operations and
zmmwords.
* config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New.
(struct RC_Operation): New.
(struct Mask_Operation): New.
(struct Broadcast_Operation): New.
(vex_prefix): Size of bytes increased to 4 to support EVEX
encoding.
(enum i386_error): Add new error codes: unsupported_broadcast,
broadcast_not_on_src_operand, broadcast_needed,
unsupported_masking, mask_not_on_destination, no_default_mask,
unsupported_rc_sae, rc_sae_operand_not_last_imm,
invalid_register_operand, try_vector_disp8.
(struct _i386_insn): Add new fields vrex, need_vrex, mask,
rounding, broadcast, memshift.
(struct RC_name): New.
(RC_NamesTable): New.
(evexlig): New.
(evexwig): New.
(extra_symbol_chars): Add '{'.
(cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF.
(i386_operand_type): Add regzmm, regmask and vec_disp8.
(match_mem_size): Handle zmmwords.
(operand_type_match): Handle zmm-registers.
(mode_from_disp_size): Handle vec_disp8.
(fits_in_vec_disp8): New.
(md_begin): Handle {} properly.
(type_names): Add "rZMM", "Mask reg" and "Vector d8".
(build_vex_prefix): Handle vrex.
(build_evex_prefix): New.
(process_immext): Adjust to properly handle EVEX.
(md_assemble): Add EVEX encoding support.
(swap_2_operands): Correctly handle operands with masking,
broadcasting or RC/SAE.
(check_VecOperands): Support EVEX features.
(VEX_check_operands): Properly handle 16 upper [xyz]mm registers.
(match_template): Support regzmm and handle new error codes.
(process_suffix): Handle zmmwords and zmm-registers.
(check_byte_reg): Extend to zmm-registers.
(process_operands): Extend to zmm-registers.
(build_modrm_byte): Handle EVEX.
(output_insn): Adjust to properly handle EVEX case.
(disp_size): Handle vec_disp8.
(output_disp): Support compressed disp8*N evex feature.
(output_imm): Handle RC/SAE immediates properly.
(check_VecOperations): New.
(i386_immediate): Handle EVEX features.
(i386_index_check): Handle zmmwords and zmm-registers.
(RC_SAE_immediate): New.
(i386_att_operand): Handle EVEX features.
(parse_real_register): Add a check for ZMM/Mask registers.
(OPTION_MEVEXLIG): New.
(OPTION_MEVEXWIG): New.
(md_longopts): Add mevexlig and mevexwig.
(md_parse_option): Handle mevexlig and mevexwig options.
(md_show_usage): Add description for mevexlig and mevexwig.
* doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd,
avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig.
gas/testsuite/
2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
Alexander Ivchenko <alexander.ivchenko@intel.com>
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Sergey Lega <sergey.s.lega@intel.com>
Anna Tikhonova <anna.tikhonova@intel.com>
Ilya Tocar <ilya.tocar@intel.com>
Andrey Turetskiy <andrey.turetskiy@intel.com>
Ilya Verbin <ilya.verbin@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* gas/cfi/cfi-i386.s: Add tests for k0-k7.
* gas/cfi/cfi-i386.d: Change to reflect above mentioned changes.
* gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7.
* gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes.
* gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto.
* gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers.
* gas/i386/intel-regs.d: Change correspondingly.
* gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1.
* gas/i386/prefetch.d: Ditto.
* gas/i386/x86-64-prefetch-intel.d: Ditto.
* gas/i386/x86-64-prefetch.d: Ditto.
* gas/i386/avx512f-intel.d: New.
* gas/i386/avx512f-nondef.d: New.
* gas/i386/avx512f-nondef.s: New.
* gas/i386/avx512f-opts-intel.d: New.
* gas/i386/avx512f-opts.d: New.
* gas/i386/avx512f-opts.s: New.
* gas/i386/avx512f.d: New.
* gas/i386/avx512f.s: New.
* gas/i386/avx512cd-intel.d: New.
* gas/i386/avx512cd.d: New.
* gas/i386/avx512cd.s: New.
* gas/i386/avx512er-intel.d: New.
* gas/i386/avx512er.d: New.
* gas/i386/avx512er.s: New.
* gas/i386/avx512pf-intel.d: New.
* gas/i386/avx512pf.d: New.
* gas/i386/avx512pf.s: New.
* gas/i386/evex-lig.s: New.
* gas/i386/evex-lig256-intel.d: New.
* gas/i386/evex-lig256.d: New.
* gas/i386/evex-lig512-intel.d: New.
* gas/i386/evex-lig512.d: New.
* gas/i386/evex-wig.s: New.
* gas/i386/evex-wig1-intel.d: New.
* gas/i386/evex-wig1.d: New.
* gas/i386/inval-avx512f.l: New.
* gas/i386/inval-avx512f.s: New.
* gas/i386/x86-64-avx512f-intel.d: New.
* gas/i386/x86-64-avx512f-nondef.d: New.
* gas/i386/x86-64-avx512f-nondef.s: New.
* gas/i386/x86-64-avx512f-opts-intel.d: New.
* gas/i386/x86-64-avx512f-opts.d: New.
* gas/i386/x86-64-avx512f-opts.s: New.
* gas/i386/x86-64-avx512f.d: New.
* gas/i386/x86-64-avx512f.s: New.
* gas/i386/x86-64-avx512cd-intel.d: New.
* gas/i386/x86-64-avx512cd.d: New.
* gas/i386/x86-64-avx512cd.s: New.
* gas/i386/x86-64-avx512er-intel.d: New.
* gas/i386/x86-64-avx512er.d: New.
* gas/i386/x86-64-avx512er.s: New.
* gas/i386/x86-64-avx512pf-intel.d: New.
* gas/i386/x86-64-avx512pf.d: New.
* gas/i386/x86-64-avx512pf.s: New.
* gas/i386/x86-64-evex-lig.s: New.
* gas/i386/x86-64-evex-lig256-intel.d: New.
* gas/i386/x86-64-evex-lig256.d: New.
* gas/i386/x86-64-evex-lig512-intel.d: New.
* gas/i386/x86-64-evex-lig512.d: New.
* gas/i386/x86-64-evex-wig.s: New.
* gas/i386/x86-64-evex-wig1-intel.d: New.
* gas/i386/x86-64-evex-wig1.d: New.
* gas/i386/x86-64-inval-avx512f.l: New.
* gas/i386/x86-64-inval-avx512f.s: New.
* gas/i386/i386.exp: Run new AVX-512 tests.
opcodes/
2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
Alexander Ivchenko <alexander.ivchenko@intel.com>
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Sergey Lega <sergey.s.lega@intel.com>
Anna Tikhonova <anna.tikhonova@intel.com>
Ilya Tocar <ilya.tocar@intel.com>
Andrey Turetskiy <andrey.turetskiy@intel.com>
Ilya Verbin <ilya.verbin@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* i386-dis-evex.h: New.
* i386-dis.c (OP_Rounding): New.
(VPCMP_Fixup): New.
(OP_Mask): New.
(Rdq): New.
(XMxmmq): New.
(EXdScalarS): New.
(EXymm): New.
(EXEvexHalfBcstXmmq): New.
(EXxmm_mdq): New.
(EXEvexXGscat): New.
(EXEvexXNoBcst): New.
(VPCMP): New.
(EXxEVexR): New.
(EXxEVexS): New.
(XMask): New.
(MaskG): New.
(MaskE): New.
(MaskR): New.
(MaskVex): New.
(modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
evex_rounding_mode, evex_sae_mode, mask_mode.
(USE_EVEX_TABLE): New.
(EVEX_TABLE): New.
(EVEX enum): New.
(REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
REG_EVEX_0F38C7.
(MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5,
MOD_EVEX_0F38C7_REG_6.
(PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
PREFIX_EVEX_0F3A55.
(VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
VEX_W_0F3A32_P_2_LEN_0.
(VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
(struct vex): Add fields evex, r, v, mask_register_specifier,
zeroing, ll, b.
(intel_names_xmm): Add upper 16 registers.
(att_names_xmm): Ditto.
(intel_names_ymm): Ditto.
(att_names_ymm): Ditto.
(names_zmm): New.
(intel_names_zmm): Ditto.
(att_names_zmm): Ditto.
(names_mask): Ditto.
(intel_names_mask): Ditto.
(att_names_mask): Ditto.
(names_rounding): Ditto.
(names_broadcast): Ditto.
(x86_64_table): Add escape to evex-table.
(reg_table): Include reg_table evex-entries from
i386-dis-evex.h. Fix prefetchwt1 instruction.
(prefix_table): Add entries for new instructions.
(vex_table): Ditto.
(vex_len_table): Ditto.
(vex_w_table): Ditto.
(mod_table): Ditto.
(get_valid_dis386): Properly handle new instructions.
(print_insn): Handle zmm and mask registers, print mask operand.
(intel_operand_size): Support EVEX, new modes and sizes.
(OP_E_register): Handle new modes.
(OP_E_memory): Ditto.
(OP_G): Ditto.
(OP_XMM): Ditto.
(OP_EX): Ditto.
(OP_VEX): Ditto.
* i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
(cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
CpuAVX512PF and CpuVREX.
(operand_type_init): Add OPERAND_TYPE_REGZMM,
OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
(opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
StaticRounding, SAE, Disp8MemShift, NoDefMask.
(operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
* i386-init.h: Regenerate.
* i386-opc.h (CpuAVX512F): New.
(CpuAVX512CD): New.
(CpuAVX512ER): New.
(CpuAVX512PF): New.
(CpuVREX): New.
(i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
cpuavx512pf and cpuvrex fields.
(VecSIB): Add VecSIB512.
(EVex): New.
(Masking): New.
(VecESize): New.
(Broadcast): New.
(StaticRounding): New.
(SAE): New.
(Disp8MemShift): New.
(NoDefMask): New.
(i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
staticrounding, sae, disp8memshift and nodefmask.
(RegZMM): New.
(Zmmword): Ditto.
(Vec_Disp8): Ditto.
(i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
fields.
(RegVRex): New.
* i386-opc.tbl: Add AVX512 instructions.
* i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
registers, mask registers.
* i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
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BITFIELD (EVex),
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BITFIELD (Masking),
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BITFIELD (Broadcast),
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BITFIELD (StaticRounding),
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BITFIELD (SAE),
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BITFIELD (Disp8MemShift),
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x86: Add -O[2|s] assembler command-line options
On x86, some instructions have alternate shorter encodings:
1. When the upper 32 bits of destination registers of
andq $imm31, %r64
testq $imm31, %r64
xorq %r64, %r64
subq %r64, %r64
known to be zero, we can encode them without the REX_W bit:
andl $imm31, %r32
testl $imm31, %r32
xorl %r32, %r32
subl %r32, %r32
This optimization is enabled with -O, -O2 and -Os.
2. Since 0xb0 mov with 32-bit destination registers zero-extends 32-bit
immediate to 64-bit destination register, we can use it to encode 64-bit
mov with 32-bit immediates. This optimization is enabled with -O, -O2
and -Os.
3. Since the upper bits of destination registers of VEX128 and EVEX128
instructions are extended to zero, if all bits of destination registers
of AVX256 or AVX512 instructions are zero, we can use VEX128 or EVEX128
encoding to encode AVX256 or AVX512 instructions. When 2 source
registers are identical, AVX256 and AVX512 andn and xor instructions:
VOP %reg, %reg, %dest_reg
can be encoded with
VOP128 %reg, %reg, %dest_reg
This optimization is enabled with -O2 and -Os.
4. 16-bit, 32-bit and 64-bit register tests with immediate may be
encoded as 8-bit register test with immediate. This optimization is
enabled with -Os.
This patch does:
1. Add {nooptimize} pseudo prefix to disable instruction size
optimization.
2. Add optimize to i386_opcode_modifier to tell assembler that encoding
of an instruction may be optimized.
gas/
PR gas/22871
* NEWS: Mention -O[2|s].
* config/tc-i386.c (_i386_insn): Add no_optimize.
(optimize): New.
(optimize_for_space): Likewise.
(fits_in_imm7): New function.
(fits_in_imm31): Likewise.
(optimize_encoding): Likewise.
(md_assemble): Call optimize_encoding to optimize encoding.
(parse_insn): Handle {nooptimize}.
(md_shortopts): Append "O::".
(md_parse_option): Handle -On.
* doc/c-i386.texi: Document -O0, -O, -O1, -O2 and -Os as well
as {nooptimize}.
* testsuite/gas/cfi/cfi-x86_64.d: Pass -O0 to assembler.
* testsuite/gas/i386/ilp32/cfi/cfi-x86_64.d: Likewise.
* testsuite/gas/i386/i386.exp: Run optimize-1, optimize-2,
optimize-3, x86-64-optimize-1, x86-64-optimize-2,
x86-64-optimize-3 and x86-64-optimize-4.
* testsuite/gas/i386/optimize-1.d: New file.
* testsuite/gas/i386/optimize-1.s: Likewise.
* testsuite/gas/i386/optimize-2.d: Likewise.
* testsuite/gas/i386/optimize-2.s: Likewise.
* testsuite/gas/i386/optimize-3.d: Likewise.
* testsuite/gas/i386/optimize-3.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-1.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-1.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-2.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-3.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-3.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-4.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-4.s: Likewise.
opcodes/
PR gas/22871
* i386-gen.c (opcode_modifiers): Add Optimize.
* i386-opc.h (Optimize): New enum.
(i386_opcode_modifier): Add optimize.
* i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
"sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
"and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
"movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
vpxord and vpxorq.
* i386-tbl.h: Regenerated.
2018-02-27 23:36:33 +08:00
|
|
|
BITFIELD (Optimize),
|
2023-12-15 19:05:11 +08:00
|
|
|
BITFIELD (Dialect),
|
2024-05-29 16:03:00 +08:00
|
|
|
BITFIELD (IntelSuffix),
|
2020-02-11 00:37:22 +08:00
|
|
|
BITFIELD (ISA64),
|
2023-12-28 09:06:39 +08:00
|
|
|
BITFIELD (NoEgpr),
|
Support APX GPR32 with extend evex prefix
This patch adds non-ND, non-NF forms of EVEX promotion insn.
EVEX extension of legacy instructions:
All promoted legacy instructions are placed in EVEX map 4, which is
currently reserved.
EVEX extension of EVEX instructions:
All existing EVEX instructions are extended by APX using the extended
EVEX prefix, so that they can access all 32 GPRs.
EVEX extension of VEX instructions:
Promoting a VEX instruction into the EVEX space does not change the map
id, the opcode, or the operand encoding of the VEX instruction.
Note: The promoted versions of MOVBE will be extended to include the “MOVBE
reg1, reg2”.
gas/ChangeLog:
2023-12-28 Lingling Kong <lingling.kong@intel.com>
H.J. Lu <hongjiu.lu@intel.com>
Lili Cui <lili.cui@intel.com>
Lin Hu <lin1.hu@intel.com>
* config/tc-i386.c (struct _i386_insn): Add has_egpr.
(need_evex_encoding): Adjusted for apx.
(cpu_flags_match): Ditto.
(install_template): Handled APX combines.
(is_apx_evex_encoding): Test apx evex encoding.
(build_apx_evex_prefix): Enabe APX evex prefix.
(md_assemble): Handle apx with evex encoding.
(process_suffix): Handle apx map4 prefix.
(check_register): Assign i.vec_encoding for APX evex instructions.
* testsuite/gas/i386/x86-64-evex.d: Adjust test cases.
* testsuite/gas/i386/x86-64.exp: Adjust x86-64-inval-movbe.
opcodes/ChangeLog:
* i386-dis-evex-len.h: Handle EVEX_LEN_0F38F2, EVEX_LEN_0F38F3.
* i386-dis-evex-prefix.h: Handle PREFIX_EVEX_0F38F2_L_0,
PREFIX_EVEX_0F38F3_L_0, PREFIX_EVEX_MAP4_D8,
PREFIX_EVEX_MAP4_DA, PREFIX_EVEX_MAP4_DB,
PREFIX_EVEX_MAP4_DC, PREFIX_EVEX_MAP4_DD,
PREFIX_EVEX_MAP4_DE, PREFIX_EVEX_MAP4_DF,
PREFIX_EVEX_MAP4_F0, PREFIX_EVEX_MAP4_F1,
PREFIX_EVEX_MAP4_F2, PREFIX_EVEX_MAP4_F8.
* i386-dis-evex-reg.h: Handle REG_EVEX_0F38F3_L_0_P_0.
* i386-dis-evex.h: Add EVEX_MAP4_ for legacy insn
promote to apx to use gpr32
* opcodes/i386-dis-evex-x86-64.h: Handle Add X86_64_EVEX_0F90,
X86_64_EVEX_0F92, X86_64_EVEX_0F93, X86_64_EVEX_0F38F2,
X86_64_EVEX_0F38F3, X86_64_EVEX_0F38F5, X86_64_EVEX_0F38F6,
X86_64_EVEX_0F38F7, X86_64_EVEX_0F3AF0, X86_64_EVEX_0F91.
* i386-dis.c
(struct instr_info): Deleted bool r.
(PREFIX_NP_OR_DATA): New.
(NO_PREFIX): New.
(putop): Ditto.
(X86_64_EVEX_FROM_VEX_TABLE): Diito.
(get_valid_dis386): Decode insn erex in extend evex prefix.
Handle EVEX_MAP4
(print_insn): Handle PREFIX_DATA_AND_NP_ONLY.
(print_register): Handle apx instructions decode.
(OP_E_memory): Diito.
(OP_G): Diito.
(OP_XMM): Diito.
(DistinctDest_Fixup): Diito.
* i386-gen.c (process_i386_opcode_modifier): Add EVEXMAP4.
* i386-opc.h (SPACE_EVEXMAP4): Add legacy insn
promote to evex.
* i386-opc.tbl: Handle some legacy and vex insns don't
support gpr32. And add some legacy insn (map2 / 3) promote
to evex.
2023-12-28 09:06:40 +08:00
|
|
|
BITFIELD (NF),
|
2024-01-15 17:00:23 +08:00
|
|
|
BITFIELD (Rex2),
|
2024-05-22 16:15:47 +08:00
|
|
|
BITFIELD (ZU),
|
2007-09-09 09:22:57 +08:00
|
|
|
};
|
|
|
|
|
2019-11-08 16:03:23 +08:00
|
|
|
#define CLASS(n) #n, n
|
|
|
|
|
|
|
|
static const struct {
|
|
|
|
const char *name;
|
|
|
|
enum operand_class value;
|
|
|
|
} operand_classes[] = {
|
|
|
|
CLASS (Reg),
|
2019-11-08 16:04:09 +08:00
|
|
|
CLASS (SReg),
|
2019-11-08 16:04:53 +08:00
|
|
|
CLASS (RegCR),
|
|
|
|
CLASS (RegDR),
|
|
|
|
CLASS (RegTR),
|
2019-11-08 16:05:36 +08:00
|
|
|
CLASS (RegMMX),
|
|
|
|
CLASS (RegSIMD),
|
2019-11-08 16:06:24 +08:00
|
|
|
CLASS (RegMask),
|
|
|
|
CLASS (RegBND),
|
2019-11-08 16:03:23 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
#undef CLASS
|
|
|
|
|
2019-11-12 16:07:34 +08:00
|
|
|
#define INSTANCE(n) #n, n
|
|
|
|
|
|
|
|
static const struct {
|
|
|
|
const char *name;
|
|
|
|
enum operand_instance value;
|
|
|
|
} operand_instances[] = {
|
|
|
|
INSTANCE (Accum),
|
|
|
|
INSTANCE (RegC),
|
|
|
|
INSTANCE (RegD),
|
2019-11-12 16:08:32 +08:00
|
|
|
INSTANCE (RegB),
|
2019-11-12 16:07:34 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
#undef INSTANCE
|
|
|
|
|
2007-09-09 09:22:57 +08:00
|
|
|
static bitfield operand_types[] =
|
|
|
|
{
|
2009-12-19 05:07:58 +08:00
|
|
|
BITFIELD (Imm1),
|
2007-09-09 09:22:57 +08:00
|
|
|
BITFIELD (Imm8),
|
|
|
|
BITFIELD (Imm8S),
|
|
|
|
BITFIELD (Imm16),
|
|
|
|
BITFIELD (Imm32),
|
|
|
|
BITFIELD (Imm32S),
|
|
|
|
BITFIELD (Imm64),
|
|
|
|
BITFIELD (BaseIndex),
|
|
|
|
BITFIELD (Disp8),
|
|
|
|
BITFIELD (Disp16),
|
|
|
|
BITFIELD (Disp32),
|
|
|
|
BITFIELD (Disp64),
|
gas/testsuite/
2008-01-12 H.J. Lu <hongjiu.lu@intel.com>
PR gas/5534
* gas/i386/i386.s: Add tests for fnstsw and fstsw.
* gas/i386/inval.s: Likewise.
* gas/i386/x86_64.s: Likewise.
* gas/i386/intel.s: Use word instead of dword on ss.
* gas/i386/x86-64-inval.s: Add tests for fnstsw, fstsw, in
and out.
* gas/i386/prefix.s: Remove invalid fstsw.
* gas/i386/inval.l: Updated.
* gas/i386/intelbad.l: Likewise.
* gas/i386/i386.d: Likewise.
* gas/i386/x86_64.d: Likewise.
* gas/i386/x86-64-inval.l: Likewise.
* gas/i386/prefix.d: Updated.
gas/
2008-01-12 H.J. Lu <hongjiu.lu@intel.com>
PR gas/5534
* config/tc-i386.c (_i386_insn): Update comment.
(operand_type_match): Also clear unspecified.
(operand_type_register_match): Likewise.
(parse_operands): Initialize unspecified.
(i386_intel_operand): Likewise.
(match_template): Check memory and accumulator operand size.
(i386_att_operand): Clear unspecified on register operand.
(intel_e11): Likewise.
(intel_e09): Set operand size and clean unspecified for
"XXX PTR".
opcodes/
2008-01-12 H.J. Lu <hongjiu.lu@intel.com>
PR gas/5534
* i386-gen.c (operand_type_init): Add Dword to
OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
(opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
Qword and Xmmword.
(operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
Xmmword, Unspecified and Anysize.
(set_bitfield): Make Mmword an alias of Qword. Make Oword
an alias of Xmmword.
* i386-opc.h (CheckSize): Removed.
(Byte): Updated.
(Word): Likewise.
(Dword): Likewise.
(Qword): Likewise.
(Xmmword): Likewise.
(FWait): Updated.
(OTMax): Likewise.
(i386_opcode_modifier): Remove checksize, byte, word, dword,
qword and xmmword.
(Fword): New.
(TBYTE): Likewise.
(Unspecified): Likewise.
(Anysize): Likewise.
(i386_operand_type): Add byte, word, dword, fword, qword,
tbyte xmmword, unspecified and anysize.
* i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
Tbyte, Xmmword, Unspecified and Anysize.
* i386-reg.tbl: Add size for accumulator.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2008-01-13 00:05:42 +08:00
|
|
|
BITFIELD (Byte),
|
|
|
|
BITFIELD (Word),
|
|
|
|
BITFIELD (Dword),
|
|
|
|
BITFIELD (Fword),
|
|
|
|
BITFIELD (Qword),
|
|
|
|
BITFIELD (Tbyte),
|
|
|
|
BITFIELD (Xmmword),
|
binutils/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* dwarf.c (dwarf_regnames_i386): Add AVX registers.
(dwarf_regnames_x86_64): Likewise.
gas/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention AES, CLMUL, AVX/FMA and -msse2avx.
* doc/c-i386.texi: Add avx, aes, clmul and fma to -march=.
Document -msse2avx, .avx, .aes, .clmul and .fma.
* config/tc-i386.c (YMMWORD_MNEM_SUFFIX): New.
(vex_prefix): Likewise.
(sse2avx): Likewise.
(CPU_FLAGS_ARCH_MATCH): Likewise.
(CPU_FLAGS_64BIT_MATCH): Likewise.
(CPU_FLAGS_32BIT_MATCH): Likewise.
(CPU_FLAGS_PERFECT_MATCH): Likewise.
(regymm): Likewise.
(vex_imm4): Likewise.
(fits_in_imm4): Likewise.
(build_vex_prefix): Likewise.
(VEX_check_operands): Likewise.
(bad_implicit_operand): Likewise.
(OPTION_MSSE2AVX): Likewise.
(T_YMMWORD): Likewise.
(_i386_insn): Add vex.
(cpu_arch): Add .avx, .aes, .clmul and .fma.
(cpu_flags_match): Changed to take a pointer to const template.
Enable encoding SSE instructions with VEX prefix for -msse2avx.
(match_mem_size): Also check ymmword.
(operand_type_match): Clear ymmword.
(md_begin): Allow '_' in mnemonic.
(type_names): Add OPERAND_TYPE_VEX_IMM4.
(process_immext): Update assert.
(md_assemble): Don't call process_immext if sse2avx and immext
are true. Call build_vex_prefix if vex is true.
(parse_insn): Updated for cpu_flags_match.
(swap_operands): Handle 5 operands.
(match_template): Handle 5 operands. Updated for cpu_flags_match.
Check regymm. Call VEX_check_operands. Handle YMMWORD_MNEM_SUFFIX.
(process_suffix): Handle YMMWORD_MNEM_SUFFIX.
(check_byte_reg): Check regymm.
(process_operands): Duplicate the destination register for
-msse2avx if needed.
(build_modrm_byte): Updated for instructions with VEX encoding.
(output_insn): Output VEX prefix if needed.
(md_longopts): Add msse2avx.
(md_parse_option): Handle OPTION_MSSE2AVX.
(md_show_usage): Add avx, aes, clmul, fma and -msse2avx.
(intel_e09): Support YMMWORD.
(intel_e11): Likewise.
(intel_get_token): Likewise.
gas/testsuite/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run aes, aes-intel, x86-64-aes,
x86-64-aes-intel, avx, avx-intel, inval-avx, x86-64-avx,
x86-64-avx-intel and x86-64-inval-avx.
* gas/cfi/cfi-i386.s: Add tests for AVX register maps.
* gas/cfi/cfi-x86_64.s: Likewise.
* gas/i386/aes.d: New.
* gas/i386/aes.s: Likewise.
* gas/i386/aes-intel.d: Likewise.
* gas/i386/avx.d: Likewise.
* gas/i386/avx.s: Likewise.
* gas/i386/avx-intel.d: Likewise.
* gas/i386/clmul.d: Likewise.
* gas/i386/clmul-intel.d: Likewise.
* gas/i386/clmul.s: Likewise.
* gas/i386/i386.exp: Likewise.
* gas/i386/inval-avx.l: Likewise.
* gas/i386/inval-avx.s: Likewise.
* gas/i386/sse2avx.d: Likewise.
* gas/i386/sse2avx.s: Likewise.
* gas/i386/x86-64-aes.d: Likewise.
* gas/i386/x86-64-aes.s: Likewise.
* gas/i386/x86-64-aes-intel.d: Likewise.
* gas/i386/x86-64-avx.d: Likewise.
* gas/i386/x86-64-avx.s: Likewise.
* gas/i386/x86-64-avx-intel.d: Likewise.
* gas/i386/x86-64-clmul.d: Likewise.
* gas/i386/x86-64-clmul-intel.d: Likewise.
* gas/i386/x86-64-clmul.s: Likewise.
* gas/i386/x86-64-inval-avx.l: Likewise.
* gas/i386/x86-64-inval-avx.s: Likewise.
* gas/i386/x86-64-sse2avx.d: Likewise.
* gas/i386/x86-64-sse2avx.s: Likewise.
* gas/i386/arch-10.s: Add tests for AVX, AES, CLMUL and FMA.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/rexw.s: Add AVX tests.
* gas/i386/x86-64-opcode-inval.s: Remove lds/les test.
* gas/cfi/cfi-i386.d: Updated.
* gas/cfi/cfi-x86_64.d: Likewise.
* gas/i386/arch-10.d: Likewise.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/rexw.d: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
* gas/i386/x86-64-opcode-inval.d: Likewise.
* gas/i386/x86-64-opcode-inval-intel.d: Likewise.
include/opcode/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (MAX_OPERANDS): Set to 5.
(MAX_MNEM_SIZE): Changed to 20.
opcodes/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (OP_E_register): New.
(OP_E_memory): Likewise.
(OP_VEX): Likewise.
(OP_EX_Vex): Likewise.
(OP_EX_VexW): Likewise.
(OP_XMM_Vex): Likewise.
(OP_XMM_VexW): Likewise.
(OP_REG_VexI4): Likewise.
(PCLMUL_Fixup): Likewise.
(VEXI4_Fixup): Likewise.
(VZERO_Fixup): Likewise.
(VCMP_Fixup): Likewise.
(VPERMIL2_Fixup): Likewise.
(rex_original): Likewise.
(rex_ignored): Likewise.
(Mxmm): Likewise.
(XMM): Likewise.
(EXxmm): Likewise.
(EXxmmq): Likewise.
(EXymmq): Likewise.
(Vex): Likewise.
(Vex128): Likewise.
(Vex256): Likewise.
(VexI4): Likewise.
(EXdVex): Likewise.
(EXqVex): Likewise.
(EXVexW): Likewise.
(EXdVexW): Likewise.
(EXqVexW): Likewise.
(XMVex): Likewise.
(XMVexW): Likewise.
(XMVexI4): Likewise.
(PCLMUL): Likewise.
(VZERO): Likewise.
(VCMP): Likewise.
(VPERMIL2): Likewise.
(xmm_mode): Likewise.
(xmmq_mode): Likewise.
(ymmq_mode): Likewise.
(vex_mode): Likewise.
(vex128_mode): Likewise.
(vex256_mode): Likewise.
(USE_VEX_C4_TABLE): Likewise.
(USE_VEX_C5_TABLE): Likewise.
(USE_VEX_LEN_TABLE): Likewise.
(VEX_C4_TABLE): Likewise.
(VEX_C5_TABLE): Likewise.
(VEX_LEN_TABLE): Likewise.
(REG_VEX_XX): Likewise.
(MOD_VEX_XXX): Likewise.
(PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
(PREFIX_0F3A44): Likewise.
(PREFIX_0F3ADF): Likewise.
(PREFIX_VEX_XXX): Likewise.
(VEX_OF): Likewise.
(VEX_OF38): Likewise.
(VEX_OF3A): Likewise.
(VEX_LEN_XXX): Likewise.
(vex): Likewise.
(need_vex): Likewise.
(need_vex_reg): Likewise.
(vex_i4_done): Likewise.
(vex_table): Likewise.
(vex_len_table): Likewise.
(OP_REG_VexI4): Likewise.
(vex_cmp_op): Likewise.
(pclmul_op): Likewise.
(vpermil2_op): Likewise.
(m_mode): Updated.
(es_reg): Likewise.
(PREFIX_0F38F0): Likewise.
(PREFIX_0F3A60): Likewise.
(reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
(prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
and PREFIX_VEX_XXX entries.
(x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
(three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
PREFIX_0F3ADF.
(mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
Add MOD_VEX_XXX entries.
(ckprefix): Initialize rex_original and rex_ignored. Store the
REX byte in rex_original.
(get_valid_dis386): Handle the implicit prefix in VEX prefix
bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
(print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
calling get_valid_dis386. Use rex_original and rex_ignored when
printing out REX.
(putop): Handle "XY".
(intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
ymmq_mode.
(OP_E_extended): Updated to use OP_E_register and
OP_E_memory.
(OP_XMM): Handle VEX.
(OP_EX): Likewise.
(XMM_Fixup): Likewise.
(CMP_Fixup): Use ARRAY_SIZE.
* i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
CPU_FMA_FLAGS and CPU_AVX_FLAGS.
(operand_type_init): Add OPERAND_TYPE_REGYMM and
OPERAND_TYPE_VEX_IMM4.
(cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
(opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
VexImmExt and SSE2AVX.
(operand_types): Add RegYMM, Ymmword and Vex_Imm4.
* i386-opc.h (CpuAVX): New.
(CpuAES): Likewise.
(CpuCLMUL): Likewise.
(CpuFMA): Likewise.
(Vex): Likewise.
(Vex256): Likewise.
(VexNDS): Likewise.
(VexNDD): Likewise.
(VexW0): Likewise.
(VexW1): Likewise.
(Vex0F): Likewise.
(Vex0F38): Likewise.
(Vex0F3A): Likewise.
(Vex3Sources): Likewise.
(VexImmExt): Likewise.
(SSE2AVX): Likewise.
(RegYMM): Likewise.
(Ymmword): Likewise.
(Vex_Imm4): Likewise.
(Implicit1stXmm0): Likewise.
(CpuXsave): Updated.
(CpuLM): Likewise.
(ByteOkIntel): Likewise.
(OldGcc): Likewise.
(Control): Likewise.
(Unspecified): Likewise.
(OTMax): Likewise.
(i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
(i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
vex3sources, veximmext and sse2avx.
(i386_operand_type): Add regymm, ymmword and vex_imm4.
* i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
* i386-reg.tbl: Add AVX registers, ymm0..ymm15.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2008-04-03 22:03:21 +08:00
|
|
|
BITFIELD (Ymmword),
|
Add Intel AVX-512 support
binutils/
2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
Alexander Ivchenko <alexander.ivchenko@intel.com>
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Sergey Lega <sergey.s.lega@intel.com>
Anna Tikhonova <anna.tikhonova@intel.com>
Ilya Tocar <ilya.tocar@intel.com>
Andrey Turetskiy <andrey.turetskiy@intel.com>
Ilya Verbin <ilya.verbin@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and
numeration in comments.
(dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to
dwarf table.
gas/
2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
Alexander Ivchenko <alexander.ivchenko@intel.com>
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Sergey Lega <sergey.s.lega@intel.com>
Anna Tikhonova <anna.tikhonova@intel.com>
Ilya Tocar <ilya.tocar@intel.com>
Andrey Turetskiy <andrey.turetskiy@intel.com>
Ilya Verbin <ilya.verbin@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* config/tc-i386-intel.c (O_zmmword_ptr): New.
(i386_types): Add zmmword.
(i386_intel_simplify_register): Allow regzmm.
(i386_intel_simplify): Handle zmmwords.
(i386_intel_operand): Handle RC/SAE, vector operations and
zmmwords.
* config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New.
(struct RC_Operation): New.
(struct Mask_Operation): New.
(struct Broadcast_Operation): New.
(vex_prefix): Size of bytes increased to 4 to support EVEX
encoding.
(enum i386_error): Add new error codes: unsupported_broadcast,
broadcast_not_on_src_operand, broadcast_needed,
unsupported_masking, mask_not_on_destination, no_default_mask,
unsupported_rc_sae, rc_sae_operand_not_last_imm,
invalid_register_operand, try_vector_disp8.
(struct _i386_insn): Add new fields vrex, need_vrex, mask,
rounding, broadcast, memshift.
(struct RC_name): New.
(RC_NamesTable): New.
(evexlig): New.
(evexwig): New.
(extra_symbol_chars): Add '{'.
(cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF.
(i386_operand_type): Add regzmm, regmask and vec_disp8.
(match_mem_size): Handle zmmwords.
(operand_type_match): Handle zmm-registers.
(mode_from_disp_size): Handle vec_disp8.
(fits_in_vec_disp8): New.
(md_begin): Handle {} properly.
(type_names): Add "rZMM", "Mask reg" and "Vector d8".
(build_vex_prefix): Handle vrex.
(build_evex_prefix): New.
(process_immext): Adjust to properly handle EVEX.
(md_assemble): Add EVEX encoding support.
(swap_2_operands): Correctly handle operands with masking,
broadcasting or RC/SAE.
(check_VecOperands): Support EVEX features.
(VEX_check_operands): Properly handle 16 upper [xyz]mm registers.
(match_template): Support regzmm and handle new error codes.
(process_suffix): Handle zmmwords and zmm-registers.
(check_byte_reg): Extend to zmm-registers.
(process_operands): Extend to zmm-registers.
(build_modrm_byte): Handle EVEX.
(output_insn): Adjust to properly handle EVEX case.
(disp_size): Handle vec_disp8.
(output_disp): Support compressed disp8*N evex feature.
(output_imm): Handle RC/SAE immediates properly.
(check_VecOperations): New.
(i386_immediate): Handle EVEX features.
(i386_index_check): Handle zmmwords and zmm-registers.
(RC_SAE_immediate): New.
(i386_att_operand): Handle EVEX features.
(parse_real_register): Add a check for ZMM/Mask registers.
(OPTION_MEVEXLIG): New.
(OPTION_MEVEXWIG): New.
(md_longopts): Add mevexlig and mevexwig.
(md_parse_option): Handle mevexlig and mevexwig options.
(md_show_usage): Add description for mevexlig and mevexwig.
* doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd,
avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig.
gas/testsuite/
2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
Alexander Ivchenko <alexander.ivchenko@intel.com>
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Sergey Lega <sergey.s.lega@intel.com>
Anna Tikhonova <anna.tikhonova@intel.com>
Ilya Tocar <ilya.tocar@intel.com>
Andrey Turetskiy <andrey.turetskiy@intel.com>
Ilya Verbin <ilya.verbin@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* gas/cfi/cfi-i386.s: Add tests for k0-k7.
* gas/cfi/cfi-i386.d: Change to reflect above mentioned changes.
* gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7.
* gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes.
* gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto.
* gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers.
* gas/i386/intel-regs.d: Change correspondingly.
* gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1.
* gas/i386/prefetch.d: Ditto.
* gas/i386/x86-64-prefetch-intel.d: Ditto.
* gas/i386/x86-64-prefetch.d: Ditto.
* gas/i386/avx512f-intel.d: New.
* gas/i386/avx512f-nondef.d: New.
* gas/i386/avx512f-nondef.s: New.
* gas/i386/avx512f-opts-intel.d: New.
* gas/i386/avx512f-opts.d: New.
* gas/i386/avx512f-opts.s: New.
* gas/i386/avx512f.d: New.
* gas/i386/avx512f.s: New.
* gas/i386/avx512cd-intel.d: New.
* gas/i386/avx512cd.d: New.
* gas/i386/avx512cd.s: New.
* gas/i386/avx512er-intel.d: New.
* gas/i386/avx512er.d: New.
* gas/i386/avx512er.s: New.
* gas/i386/avx512pf-intel.d: New.
* gas/i386/avx512pf.d: New.
* gas/i386/avx512pf.s: New.
* gas/i386/evex-lig.s: New.
* gas/i386/evex-lig256-intel.d: New.
* gas/i386/evex-lig256.d: New.
* gas/i386/evex-lig512-intel.d: New.
* gas/i386/evex-lig512.d: New.
* gas/i386/evex-wig.s: New.
* gas/i386/evex-wig1-intel.d: New.
* gas/i386/evex-wig1.d: New.
* gas/i386/inval-avx512f.l: New.
* gas/i386/inval-avx512f.s: New.
* gas/i386/x86-64-avx512f-intel.d: New.
* gas/i386/x86-64-avx512f-nondef.d: New.
* gas/i386/x86-64-avx512f-nondef.s: New.
* gas/i386/x86-64-avx512f-opts-intel.d: New.
* gas/i386/x86-64-avx512f-opts.d: New.
* gas/i386/x86-64-avx512f-opts.s: New.
* gas/i386/x86-64-avx512f.d: New.
* gas/i386/x86-64-avx512f.s: New.
* gas/i386/x86-64-avx512cd-intel.d: New.
* gas/i386/x86-64-avx512cd.d: New.
* gas/i386/x86-64-avx512cd.s: New.
* gas/i386/x86-64-avx512er-intel.d: New.
* gas/i386/x86-64-avx512er.d: New.
* gas/i386/x86-64-avx512er.s: New.
* gas/i386/x86-64-avx512pf-intel.d: New.
* gas/i386/x86-64-avx512pf.d: New.
* gas/i386/x86-64-avx512pf.s: New.
* gas/i386/x86-64-evex-lig.s: New.
* gas/i386/x86-64-evex-lig256-intel.d: New.
* gas/i386/x86-64-evex-lig256.d: New.
* gas/i386/x86-64-evex-lig512-intel.d: New.
* gas/i386/x86-64-evex-lig512.d: New.
* gas/i386/x86-64-evex-wig.s: New.
* gas/i386/x86-64-evex-wig1-intel.d: New.
* gas/i386/x86-64-evex-wig1.d: New.
* gas/i386/x86-64-inval-avx512f.l: New.
* gas/i386/x86-64-inval-avx512f.s: New.
* gas/i386/i386.exp: Run new AVX-512 tests.
opcodes/
2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
Alexander Ivchenko <alexander.ivchenko@intel.com>
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Sergey Lega <sergey.s.lega@intel.com>
Anna Tikhonova <anna.tikhonova@intel.com>
Ilya Tocar <ilya.tocar@intel.com>
Andrey Turetskiy <andrey.turetskiy@intel.com>
Ilya Verbin <ilya.verbin@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* i386-dis-evex.h: New.
* i386-dis.c (OP_Rounding): New.
(VPCMP_Fixup): New.
(OP_Mask): New.
(Rdq): New.
(XMxmmq): New.
(EXdScalarS): New.
(EXymm): New.
(EXEvexHalfBcstXmmq): New.
(EXxmm_mdq): New.
(EXEvexXGscat): New.
(EXEvexXNoBcst): New.
(VPCMP): New.
(EXxEVexR): New.
(EXxEVexS): New.
(XMask): New.
(MaskG): New.
(MaskE): New.
(MaskR): New.
(MaskVex): New.
(modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
evex_rounding_mode, evex_sae_mode, mask_mode.
(USE_EVEX_TABLE): New.
(EVEX_TABLE): New.
(EVEX enum): New.
(REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
REG_EVEX_0F38C7.
(MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5,
MOD_EVEX_0F38C7_REG_6.
(PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
PREFIX_EVEX_0F3A55.
(VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
VEX_W_0F3A32_P_2_LEN_0.
(VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
(struct vex): Add fields evex, r, v, mask_register_specifier,
zeroing, ll, b.
(intel_names_xmm): Add upper 16 registers.
(att_names_xmm): Ditto.
(intel_names_ymm): Ditto.
(att_names_ymm): Ditto.
(names_zmm): New.
(intel_names_zmm): Ditto.
(att_names_zmm): Ditto.
(names_mask): Ditto.
(intel_names_mask): Ditto.
(att_names_mask): Ditto.
(names_rounding): Ditto.
(names_broadcast): Ditto.
(x86_64_table): Add escape to evex-table.
(reg_table): Include reg_table evex-entries from
i386-dis-evex.h. Fix prefetchwt1 instruction.
(prefix_table): Add entries for new instructions.
(vex_table): Ditto.
(vex_len_table): Ditto.
(vex_w_table): Ditto.
(mod_table): Ditto.
(get_valid_dis386): Properly handle new instructions.
(print_insn): Handle zmm and mask registers, print mask operand.
(intel_operand_size): Support EVEX, new modes and sizes.
(OP_E_register): Handle new modes.
(OP_E_memory): Ditto.
(OP_G): Ditto.
(OP_XMM): Ditto.
(OP_EX): Ditto.
(OP_VEX): Ditto.
* i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
(cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
CpuAVX512PF and CpuVREX.
(operand_type_init): Add OPERAND_TYPE_REGZMM,
OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
(opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
StaticRounding, SAE, Disp8MemShift, NoDefMask.
(operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
* i386-init.h: Regenerate.
* i386-opc.h (CpuAVX512F): New.
(CpuAVX512CD): New.
(CpuAVX512ER): New.
(CpuAVX512PF): New.
(CpuVREX): New.
(i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
cpuavx512pf and cpuvrex fields.
(VecSIB): Add VecSIB512.
(EVex): New.
(Masking): New.
(VecESize): New.
(Broadcast): New.
(StaticRounding): New.
(SAE): New.
(Disp8MemShift): New.
(NoDefMask): New.
(i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
staticrounding, sae, disp8memshift and nodefmask.
(RegZMM): New.
(Zmmword): Ditto.
(Vec_Disp8): Ditto.
(i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
fields.
(RegVRex): New.
* i386-opc.tbl: Add AVX512 instructions.
* i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
registers, mask registers.
* i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
|
|
|
BITFIELD (Zmmword),
|
2020-07-10 20:17:29 +08:00
|
|
|
BITFIELD (Tmmword),
|
gas/testsuite/
2008-01-12 H.J. Lu <hongjiu.lu@intel.com>
PR gas/5534
* gas/i386/i386.s: Add tests for fnstsw and fstsw.
* gas/i386/inval.s: Likewise.
* gas/i386/x86_64.s: Likewise.
* gas/i386/intel.s: Use word instead of dword on ss.
* gas/i386/x86-64-inval.s: Add tests for fnstsw, fstsw, in
and out.
* gas/i386/prefix.s: Remove invalid fstsw.
* gas/i386/inval.l: Updated.
* gas/i386/intelbad.l: Likewise.
* gas/i386/i386.d: Likewise.
* gas/i386/x86_64.d: Likewise.
* gas/i386/x86-64-inval.l: Likewise.
* gas/i386/prefix.d: Updated.
gas/
2008-01-12 H.J. Lu <hongjiu.lu@intel.com>
PR gas/5534
* config/tc-i386.c (_i386_insn): Update comment.
(operand_type_match): Also clear unspecified.
(operand_type_register_match): Likewise.
(parse_operands): Initialize unspecified.
(i386_intel_operand): Likewise.
(match_template): Check memory and accumulator operand size.
(i386_att_operand): Clear unspecified on register operand.
(intel_e11): Likewise.
(intel_e09): Set operand size and clean unspecified for
"XXX PTR".
opcodes/
2008-01-12 H.J. Lu <hongjiu.lu@intel.com>
PR gas/5534
* i386-gen.c (operand_type_init): Add Dword to
OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
(opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
Qword and Xmmword.
(operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
Xmmword, Unspecified and Anysize.
(set_bitfield): Make Mmword an alias of Qword. Make Oword
an alias of Xmmword.
* i386-opc.h (CheckSize): Removed.
(Byte): Updated.
(Word): Likewise.
(Dword): Likewise.
(Qword): Likewise.
(Xmmword): Likewise.
(FWait): Updated.
(OTMax): Likewise.
(i386_opcode_modifier): Remove checksize, byte, word, dword,
qword and xmmword.
(Fword): New.
(TBYTE): Likewise.
(Unspecified): Likewise.
(Anysize): Likewise.
(i386_operand_type): Add byte, word, dword, fword, qword,
tbyte xmmword, unspecified and anysize.
* i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
Tbyte, Xmmword, Unspecified and Anysize.
* i386-reg.tbl: Add size for accumulator.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2008-01-13 00:05:42 +08:00
|
|
|
BITFIELD (Unspecified),
|
2007-09-09 09:22:57 +08:00
|
|
|
#ifdef OTUnused
|
|
|
|
BITFIELD (OTUnused),
|
|
|
|
#endif
|
|
|
|
};
|
|
|
|
|
2008-01-09 05:24:16 +08:00
|
|
|
static const char *filename;
|
2017-11-30 18:48:13 +08:00
|
|
|
static i386_cpu_flags active_cpu_flags;
|
|
|
|
static int active_isstring;
|
2008-01-09 05:24:16 +08:00
|
|
|
|
2020-03-09 17:12:14 +08:00
|
|
|
struct template_arg {
|
|
|
|
const struct template_arg *next;
|
|
|
|
const char *val;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct template_instance {
|
|
|
|
const struct template_instance *next;
|
|
|
|
const char *name;
|
|
|
|
const struct template_arg *args;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct template_param {
|
|
|
|
const struct template_param *next;
|
|
|
|
const char *name;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct template {
|
2022-08-16 15:14:39 +08:00
|
|
|
struct template *next;
|
2020-03-09 17:12:14 +08:00
|
|
|
const char *name;
|
|
|
|
const struct template_instance *instances;
|
|
|
|
const struct template_param *params;
|
|
|
|
};
|
|
|
|
|
2022-08-16 15:14:39 +08:00
|
|
|
static struct template *templates;
|
2020-03-09 17:12:14 +08:00
|
|
|
|
2007-09-09 09:22:57 +08:00
|
|
|
static int
|
|
|
|
compare (const void *x, const void *y)
|
|
|
|
{
|
|
|
|
const bitfield *xp = (const bitfield *) x;
|
|
|
|
const bitfield *yp = (const bitfield *) y;
|
|
|
|
return xp->position - yp->position;
|
|
|
|
}
|
|
|
|
|
2007-06-28 22:29:56 +08:00
|
|
|
static void
|
|
|
|
fail (const char *message, ...)
|
|
|
|
{
|
|
|
|
va_list args;
|
2012-06-23 00:42:08 +08:00
|
|
|
|
2007-06-28 22:29:56 +08:00
|
|
|
va_start (args, message);
|
2023-01-27 16:20:26 +08:00
|
|
|
fprintf (stderr, "%s: error: ", program_name);
|
2007-06-28 22:29:56 +08:00
|
|
|
vfprintf (stderr, message, args);
|
|
|
|
va_end (args);
|
|
|
|
xexit (1);
|
|
|
|
}
|
|
|
|
|
2007-09-07 06:08:08 +08:00
|
|
|
static void
|
|
|
|
process_copyright (FILE *fp)
|
|
|
|
{
|
|
|
|
fprintf (fp, "/* This file is automatically generated by i386-gen. Do not edit! */\n\
|
2024-01-04 19:52:08 +08:00
|
|
|
/* Copyright (C) 2007-2024 Free Software Foundation, Inc.\n\
|
2007-09-07 06:08:08 +08:00
|
|
|
\n\
|
|
|
|
This file is part of the GNU opcodes library.\n\
|
|
|
|
\n\
|
|
|
|
This library is free software; you can redistribute it and/or modify\n\
|
|
|
|
it under the terms of the GNU General Public License as published by\n\
|
|
|
|
the Free Software Foundation; either version 3, or (at your option)\n\
|
|
|
|
any later version.\n\
|
|
|
|
\n\
|
|
|
|
It is distributed in the hope that it will be useful, but WITHOUT\n\
|
|
|
|
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\n\
|
|
|
|
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public\n\
|
|
|
|
License for more details.\n\
|
|
|
|
\n\
|
|
|
|
You should have received a copy of the GNU General Public License\n\
|
|
|
|
along with this program; if not, write to the Free Software\n\
|
|
|
|
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,\n\
|
|
|
|
MA 02110-1301, USA. */\n");
|
|
|
|
}
|
|
|
|
|
2007-06-28 22:29:56 +08:00
|
|
|
/* Remove leading white spaces. */
|
|
|
|
|
|
|
|
static char *
|
|
|
|
remove_leading_whitespaces (char *str)
|
|
|
|
{
|
|
|
|
while (ISSPACE (*str))
|
|
|
|
str++;
|
|
|
|
return str;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Remove trailing white spaces. */
|
|
|
|
|
|
|
|
static void
|
|
|
|
remove_trailing_whitespaces (char *str)
|
|
|
|
{
|
|
|
|
size_t last = strlen (str);
|
|
|
|
|
|
|
|
if (last == 0)
|
|
|
|
return;
|
|
|
|
|
|
|
|
do
|
|
|
|
{
|
|
|
|
last--;
|
|
|
|
if (ISSPACE (str [last]))
|
|
|
|
str[last] = '\0';
|
|
|
|
else
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
while (last != 0);
|
|
|
|
}
|
|
|
|
|
2007-09-07 06:55:04 +08:00
|
|
|
/* Find next field separated by SEP and terminate it. Return a
|
2007-06-28 22:29:56 +08:00
|
|
|
pointer to the one after it. */
|
|
|
|
|
|
|
|
static char *
|
2008-10-01 03:47:14 +08:00
|
|
|
next_field (char *str, char sep, char **next, char *last)
|
2007-06-28 22:29:56 +08:00
|
|
|
{
|
|
|
|
char *p;
|
|
|
|
|
|
|
|
p = remove_leading_whitespaces (str);
|
2007-09-07 06:55:04 +08:00
|
|
|
for (str = p; *str != sep && *str != '\0'; str++);
|
2007-06-28 22:29:56 +08:00
|
|
|
|
|
|
|
*str = '\0';
|
|
|
|
remove_trailing_whitespaces (p);
|
|
|
|
|
2012-06-23 00:42:08 +08:00
|
|
|
*next = str + 1;
|
2007-06-28 22:29:56 +08:00
|
|
|
|
2008-10-01 03:47:14 +08:00
|
|
|
if (p >= last)
|
|
|
|
abort ();
|
|
|
|
|
2007-06-28 22:29:56 +08:00
|
|
|
return p;
|
|
|
|
}
|
|
|
|
|
Update x86 CPU_XXX_FLAGS handling
Support defining CPU_XXX_FLAGS with other CPU_XXX_FLAGS. Update
CPU_XXX_FLAGS to enable more bits like x87 and SYSCALL. Don't enable
MMX when enabling SSE, AVX or AVX512. Don't disable AVX nor AVX512 when
disabling SSE. Don't disable AVX512 when disabling AVX. Disable F16C,
FMA, FMA4 and XOP when disabling AVX. Add 87, no287, no387, no687,
nosse2, nosse3, nossse3, nosse4.1, nosse4.2, nosse4 and noavx2 directives
to x86 assembler.
TODO: Add more .noXXX, like .noavx512f, directives to x86 assembler.
gas/
PR gas/20145
* config/tc-i386.c (cpu_arch): Add 687.
(cpu_noarch): Add no287, no387, no687, nosse2, nosse3, nossse3,
nosse4.1, nosse4.2, nosse4 and noavx2.
(parse_real_register): Check cpuregmmx instead of cpummx for MMX
register. Check cpuregxmm instead of cpusse for XMM register.
Check cpuregymm instead of cpuavx for YMM register. Check
cpuregzmm/cpuregmask instead of cpuavx512f for ZMMM/mask register.
* doc/c-i386.texi: Mention 687, no287, no387, no687, nosse2,
nosse3, nossse3, nosse4.1, nosse4.2, nosse4 and noavx2.
* testsuite/gas/i386/arch-10-prefetchw.d (as): Add mmx.
* testsuite/gas/i386/arch-10.d (as): Likewise.
* testsuite/gas/i386/arch-11.s: Add ".arch .mmx".
* testsuite/gas/i386/i386.exp: Pass mmx to assembler for
arch-10-3 and arch-10-4. Run no87-3, nosse-4, nosse-5, noavx-3
and noavx-4.
* testsuite/gas/i386/no87-3.l: New file.
* testsuite/gas/i386/no87-3.s: Likewise.
* testsuite/gas/i386/noavx-3.l: Likewise.
* testsuite/gas/i386/noavx-3.s: Likewise.
* testsuite/gas/i386/noavx-4.d: Likewise.
* testsuite/gas/i386/noavx-4.s: Likewise.
* testsuite/gas/i386/nosse-4.l: Likewise.
* testsuite/gas/i386/nosse-4.s: Likewise.
* testsuite/gas/i386/nosse-5.d: Likewise.
* testsuite/gas/i386/nosse-5.s: Likewise.
opcodes/
PR gas/20145
* i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
CpuRegMask for AVX512.
(cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
and CpuRegMask.
(set_bitfield_from_cpu_flag_init): New function.
(set_bitfield): Remove const on f. Call
set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
* i386-opc.h (CpuRegMMX): New.
(CpuRegXMM): Likewise.
(CpuRegYMM): Likewise.
(CpuRegZMM): Likewise.
(CpuRegMask): Likewise.
(i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
and cpuregmask.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2016-05-28 01:05:39 +08:00
|
|
|
static void set_bitfield (char *, bitfield *, int, unsigned int, int);
|
|
|
|
|
2007-09-09 09:22:57 +08:00
|
|
|
static void
|
Update x86 CPU_XXX_FLAGS handling
Support defining CPU_XXX_FLAGS with other CPU_XXX_FLAGS. Update
CPU_XXX_FLAGS to enable more bits like x87 and SYSCALL. Don't enable
MMX when enabling SSE, AVX or AVX512. Don't disable AVX nor AVX512 when
disabling SSE. Don't disable AVX512 when disabling AVX. Disable F16C,
FMA, FMA4 and XOP when disabling AVX. Add 87, no287, no387, no687,
nosse2, nosse3, nossse3, nosse4.1, nosse4.2, nosse4 and noavx2 directives
to x86 assembler.
TODO: Add more .noXXX, like .noavx512f, directives to x86 assembler.
gas/
PR gas/20145
* config/tc-i386.c (cpu_arch): Add 687.
(cpu_noarch): Add no287, no387, no687, nosse2, nosse3, nossse3,
nosse4.1, nosse4.2, nosse4 and noavx2.
(parse_real_register): Check cpuregmmx instead of cpummx for MMX
register. Check cpuregxmm instead of cpusse for XMM register.
Check cpuregymm instead of cpuavx for YMM register. Check
cpuregzmm/cpuregmask instead of cpuavx512f for ZMMM/mask register.
* doc/c-i386.texi: Mention 687, no287, no387, no687, nosse2,
nosse3, nossse3, nosse4.1, nosse4.2, nosse4 and noavx2.
* testsuite/gas/i386/arch-10-prefetchw.d (as): Add mmx.
* testsuite/gas/i386/arch-10.d (as): Likewise.
* testsuite/gas/i386/arch-11.s: Add ".arch .mmx".
* testsuite/gas/i386/i386.exp: Pass mmx to assembler for
arch-10-3 and arch-10-4. Run no87-3, nosse-4, nosse-5, noavx-3
and noavx-4.
* testsuite/gas/i386/no87-3.l: New file.
* testsuite/gas/i386/no87-3.s: Likewise.
* testsuite/gas/i386/noavx-3.l: Likewise.
* testsuite/gas/i386/noavx-3.s: Likewise.
* testsuite/gas/i386/noavx-4.d: Likewise.
* testsuite/gas/i386/noavx-4.s: Likewise.
* testsuite/gas/i386/nosse-4.l: Likewise.
* testsuite/gas/i386/nosse-4.s: Likewise.
* testsuite/gas/i386/nosse-5.d: Likewise.
* testsuite/gas/i386/nosse-5.s: Likewise.
opcodes/
PR gas/20145
* i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
CpuRegMask for AVX512.
(cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
and CpuRegMask.
(set_bitfield_from_cpu_flag_init): New function.
(set_bitfield): Remove const on f. Call
set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
* i386-opc.h (CpuRegMMX): New.
(CpuRegXMM): Likewise.
(CpuRegYMM): Likewise.
(CpuRegZMM): Likewise.
(CpuRegMask): Likewise.
(i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
and cpuregmask.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2016-05-28 01:05:39 +08:00
|
|
|
set_bitfield (char *f, bitfield *array, int value,
|
2009-07-25 22:58:58 +08:00
|
|
|
unsigned int size, int lineno)
|
2007-09-09 09:22:57 +08:00
|
|
|
{
|
|
|
|
unsigned int i;
|
|
|
|
|
2020-03-09 17:13:04 +08:00
|
|
|
/* Ignore empty fields; they may result from template expansions. */
|
|
|
|
if (*f == '\0')
|
|
|
|
return;
|
|
|
|
|
2007-09-09 09:22:57 +08:00
|
|
|
for (i = 0; i < size; i++)
|
|
|
|
if (strcasecmp (array[i].name, f) == 0)
|
|
|
|
{
|
2009-07-25 22:58:58 +08:00
|
|
|
array[i].value = value;
|
2007-09-09 09:22:57 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2009-09-25 00:37:09 +08:00
|
|
|
if (value)
|
|
|
|
{
|
|
|
|
const char *v = strchr (f, '=');
|
|
|
|
|
|
|
|
if (v)
|
|
|
|
{
|
|
|
|
size_t n = v - f;
|
|
|
|
char *end;
|
|
|
|
|
|
|
|
for (i = 0; i < size; i++)
|
|
|
|
if (strncasecmp (array[i].name, f, n) == 0)
|
|
|
|
{
|
|
|
|
value = strtol (v + 1, &end, 0);
|
|
|
|
if (*end == '\0')
|
|
|
|
{
|
|
|
|
array[i].value = value;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
gas/
2009-01-10 H.J. Lu <hongjiu.lu@intel.com>
* gas/config/tc-i386.c (cpu_arch): Add corei7, .clflush and
.syscall.
(i386_align_code): Handle PROCESSOR_COREI7.
(md_show_usage): Add corei7, clflush and syscall.
(i386_target_format): Replace cpup4 with cpuclflush.
* gas/config/tc-i386.h (processor_type): Add PROCESSOR_COREI7.
* doc/c-i386.texi: Document corei7, clflush and syscall.
gas/testsuite/
2009-01-10 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/arch-10.s: Add clflush and syscall.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/arch-10.d: Updated.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
opcodes/
2009-01-10 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (cpu_flag_init): Replace CpuP4 and CpuK6 with
CpuClflush and CpuSYSCALL, respectively. Remove CpuK8. Add
CPU_COREI7_FLAGS, CPU_CLFLUSH_FLAGS and CPU_SYSCALL_FLAGS.
(cpu_flags): Remove CpuP4, CpuK6 and CpuK8. Add CpuClflush
and CpuSYSCALL.
(lineno): Removed.
(set_bitfield): Take an argument, lineno. Don't report lineno
on error if it is -1.
(process_i386_cpu_flag): Take an argument, lineno.
(process_i386_opcode_modifier): Likewise.
(process_i386_operand_type): Likewise.
(output_i386_opcode): Likewise.
(opcode_hash_entry): Add lineno.
(process_i386_opcodes): Updated.
(process_i386_registers): Likewise.
(process_i386_initializers): Likewise.
* i386-opc.h (CpuP4): Removed.
(CpuK6): Likewise.
(CpuK8): Likewise.
(CpuClflush): New.
(CpuSYSCALL): Likewise.
(CpuMMX): Updated.
(i386_cpu_flags): Remove cpup4, cpuk6 and cpuk8. Add
cpuclflush and cpusyscall.
* i386-opc.tbl: Update movnti, clflush, lfence, mfence, pause,
syscall and sysret.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2009-01-11 01:25:52 +08:00
|
|
|
if (lineno != -1)
|
2023-01-27 16:20:26 +08:00
|
|
|
fail ("%s: %d: unknown bitfield: %s\n", filename, lineno, f);
|
gas/
2009-01-10 H.J. Lu <hongjiu.lu@intel.com>
* gas/config/tc-i386.c (cpu_arch): Add corei7, .clflush and
.syscall.
(i386_align_code): Handle PROCESSOR_COREI7.
(md_show_usage): Add corei7, clflush and syscall.
(i386_target_format): Replace cpup4 with cpuclflush.
* gas/config/tc-i386.h (processor_type): Add PROCESSOR_COREI7.
* doc/c-i386.texi: Document corei7, clflush and syscall.
gas/testsuite/
2009-01-10 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/arch-10.s: Add clflush and syscall.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/arch-10.d: Updated.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
opcodes/
2009-01-10 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (cpu_flag_init): Replace CpuP4 and CpuK6 with
CpuClflush and CpuSYSCALL, respectively. Remove CpuK8. Add
CPU_COREI7_FLAGS, CPU_CLFLUSH_FLAGS and CPU_SYSCALL_FLAGS.
(cpu_flags): Remove CpuP4, CpuK6 and CpuK8. Add CpuClflush
and CpuSYSCALL.
(lineno): Removed.
(set_bitfield): Take an argument, lineno. Don't report lineno
on error if it is -1.
(process_i386_cpu_flag): Take an argument, lineno.
(process_i386_opcode_modifier): Likewise.
(process_i386_operand_type): Likewise.
(output_i386_opcode): Likewise.
(opcode_hash_entry): Add lineno.
(process_i386_opcodes): Updated.
(process_i386_registers): Likewise.
(process_i386_initializers): Likewise.
* i386-opc.h (CpuP4): Removed.
(CpuK6): Likewise.
(CpuK8): Likewise.
(CpuClflush): New.
(CpuSYSCALL): Likewise.
(CpuMMX): Updated.
(i386_cpu_flags): Remove cpup4, cpuk6 and cpuk8. Add
cpuclflush and cpusyscall.
* i386-opc.tbl: Update movnti, clflush, lfence, mfence, pause,
syscall and sysret.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2009-01-11 01:25:52 +08:00
|
|
|
else
|
2023-01-27 16:20:26 +08:00
|
|
|
fail ("unknown bitfield: %s\n", f);
|
2007-09-09 09:22:57 +08:00
|
|
|
}
|
|
|
|
|
2022-12-22 16:32:29 +08:00
|
|
|
static void
|
|
|
|
add_isa_dependencies (bitfield *flags, const char *f, int value,
|
|
|
|
unsigned int reverse)
|
|
|
|
{
|
|
|
|
unsigned int i;
|
|
|
|
char *str = NULL;
|
|
|
|
const char *isa = f;
|
2023-09-14 14:40:58 +08:00
|
|
|
static bool is_avx;
|
|
|
|
bool is_isa = false, orig_is_avx = is_avx;
|
2022-12-22 16:32:29 +08:00
|
|
|
|
|
|
|
/* Need to find base entry for references to auxiliary ones. */
|
|
|
|
if (strchr (f, ':'))
|
|
|
|
{
|
|
|
|
str = xstrdup (f);
|
|
|
|
*strchr (str, ':') = '\0';
|
|
|
|
isa = str;
|
|
|
|
}
|
2023-09-15 15:57:05 +08:00
|
|
|
/* isa_dependencies[] prefers "LM" over "64". */
|
|
|
|
else if (!strcmp (f, "LM"))
|
|
|
|
isa = "64";
|
|
|
|
for (i = 0; i < CpuMax; ++i)
|
2022-12-22 16:32:29 +08:00
|
|
|
if (strcasecmp (flags[i].name, isa) == 0)
|
|
|
|
{
|
|
|
|
flags[i].value = value;
|
|
|
|
if (reverse < ARRAY_SIZE (isa_reverse_deps[0])
|
|
|
|
/* Don't record the feature itself here. */
|
|
|
|
&& reverse != i
|
|
|
|
/* Don't record base architectures. */
|
|
|
|
&& reverse > Cpu686)
|
|
|
|
isa_reverse_deps[i][reverse] = 1;
|
|
|
|
is_isa = true;
|
2023-09-14 14:40:58 +08:00
|
|
|
if (i == CpuAVX || i == CpuXOP || i == CpuVAES || i == CpuVPCLMULQDQ)
|
2022-12-22 16:32:29 +08:00
|
|
|
is_avx = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
free (str);
|
|
|
|
|
|
|
|
/* Do not turn off dependencies. */
|
|
|
|
if (is_isa && !value)
|
2023-09-14 14:40:58 +08:00
|
|
|
{
|
|
|
|
is_avx = orig_is_avx;
|
|
|
|
return;
|
|
|
|
}
|
2022-12-22 16:32:29 +08:00
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE (isa_dependencies); ++i)
|
|
|
|
if (strcasecmp (isa_dependencies[i].name, f) == 0)
|
|
|
|
{
|
|
|
|
char *deps = xstrdup (isa_dependencies[i].deps);
|
|
|
|
char *next = deps;
|
|
|
|
char *last = deps + strlen (deps);
|
|
|
|
|
|
|
|
for (; next && next < last; )
|
|
|
|
{
|
|
|
|
char *str = next_field (next, '|', &next, last);
|
|
|
|
|
|
|
|
/* No AVX/XOP -> SSE reverse dependencies. */
|
|
|
|
if (is_avx && strncmp (str, "SSE", 3) == 0)
|
|
|
|
add_isa_dependencies (flags, str, value, CpuMax);
|
|
|
|
else
|
|
|
|
add_isa_dependencies (flags, str, value, reverse);
|
|
|
|
}
|
|
|
|
free (deps);
|
|
|
|
|
2023-11-09 19:54:23 +08:00
|
|
|
/* ISA extensions with dependencies need CPU_ANY_*_FLAGS emitted,
|
|
|
|
unless the sole dependency is the "64-bit mode only" one. */
|
|
|
|
if (reverse < ARRAY_SIZE (isa_reverse_deps[0])
|
|
|
|
&& strcmp (isa_dependencies[i].deps, "64"))
|
2022-12-22 16:32:29 +08:00
|
|
|
isa_reverse_deps[reverse][reverse] = 1;
|
|
|
|
|
2023-09-14 14:40:58 +08:00
|
|
|
is_avx = orig_is_avx;
|
2022-12-22 16:32:29 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!is_isa)
|
2023-01-27 16:20:26 +08:00
|
|
|
fail ("unknown bitfield: %s\n", f);
|
2023-09-14 14:40:58 +08:00
|
|
|
|
|
|
|
is_avx = orig_is_avx;
|
2022-12-22 16:32:29 +08:00
|
|
|
}
|
|
|
|
|
2007-09-09 09:22:57 +08:00
|
|
|
static void
|
|
|
|
output_cpu_flags (FILE *table, bitfield *flags, unsigned int size,
|
2023-11-09 19:54:58 +08:00
|
|
|
int mode, const char *comma, const char *indent, int lineno)
|
2007-09-09 09:22:57 +08:00
|
|
|
{
|
2023-08-11 16:04:49 +08:00
|
|
|
unsigned int i = 0, j = 0;
|
2007-09-09 09:22:57 +08:00
|
|
|
|
2023-11-09 19:54:58 +08:00
|
|
|
if (mode < 0)
|
|
|
|
memset (&active_cpu_flags, 0, sizeof(active_cpu_flags));
|
2017-11-30 18:48:13 +08:00
|
|
|
|
2007-09-09 09:22:57 +08:00
|
|
|
fprintf (table, "%s{ { ", indent);
|
|
|
|
|
2023-11-09 19:54:58 +08:00
|
|
|
if (mode <= 0)
|
2007-09-09 09:22:57 +08:00
|
|
|
{
|
2023-08-11 16:04:49 +08:00
|
|
|
for (j = ~0u; i < CpuAttrEnums; i++)
|
|
|
|
{
|
|
|
|
if (!flags[i].value)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (j < ~0u)
|
|
|
|
fail ("%s: %d: invalid combination of CPU identifiers\n",
|
|
|
|
filename, lineno);
|
|
|
|
j = i;
|
2023-11-09 19:54:58 +08:00
|
|
|
if (mode)
|
|
|
|
active_cpu_flags.array[i / 32] |= 1U << (i % 32);
|
2023-08-11 16:04:49 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Write 0 to indicate "no associated flag". */
|
|
|
|
fprintf (table, "%u, ", j + 1);
|
|
|
|
|
|
|
|
j = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (; i < size - 1; i++, j++)
|
|
|
|
{
|
|
|
|
if (((j + 1) % 20) != 0)
|
2014-02-20 04:53:27 +08:00
|
|
|
fprintf (table, "%d, ", flags[i].value);
|
|
|
|
else
|
|
|
|
fprintf (table, "%d,", flags[i].value);
|
2023-08-11 16:04:49 +08:00
|
|
|
if (((j + 1) % 20) == 0)
|
2007-09-09 09:22:57 +08:00
|
|
|
{
|
|
|
|
/* We need \\ for macro. */
|
2023-11-09 19:54:58 +08:00
|
|
|
if (mode > 0)
|
2007-09-09 09:22:57 +08:00
|
|
|
fprintf (table, " \\\n %s", indent);
|
|
|
|
else
|
|
|
|
fprintf (table, "\n %s", indent);
|
|
|
|
}
|
2023-11-09 19:54:58 +08:00
|
|
|
if (mode < 0 && flags[i].value)
|
2017-11-30 18:48:13 +08:00
|
|
|
active_cpu_flags.array[i / 32] |= 1U << (i % 32);
|
2007-09-09 09:22:57 +08:00
|
|
|
}
|
|
|
|
|
2024-01-05 15:20:23 +08:00
|
|
|
#if defined(CpuAttrUnused) != defined(CpuUnused)
|
|
|
|
if (mode <= 0)
|
|
|
|
# ifdef CpuUnused
|
|
|
|
fprintf (table, " } }%s\n", comma);
|
|
|
|
# else
|
|
|
|
fprintf (table, "%d, 0 } }%s\n", flags[i].value, comma);
|
|
|
|
# endif
|
|
|
|
else
|
|
|
|
#endif
|
|
|
|
fprintf (table, "%d } }%s\n", flags[i].value, comma);
|
2007-09-09 09:22:57 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2022-12-22 16:32:29 +08:00
|
|
|
process_i386_cpu_flag (FILE *table, char *flag,
|
|
|
|
const char *name,
|
gas/
2009-01-10 H.J. Lu <hongjiu.lu@intel.com>
* gas/config/tc-i386.c (cpu_arch): Add corei7, .clflush and
.syscall.
(i386_align_code): Handle PROCESSOR_COREI7.
(md_show_usage): Add corei7, clflush and syscall.
(i386_target_format): Replace cpup4 with cpuclflush.
* gas/config/tc-i386.h (processor_type): Add PROCESSOR_COREI7.
* doc/c-i386.texi: Document corei7, clflush and syscall.
gas/testsuite/
2009-01-10 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/arch-10.s: Add clflush and syscall.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/arch-10.d: Updated.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
opcodes/
2009-01-10 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (cpu_flag_init): Replace CpuP4 and CpuK6 with
CpuClflush and CpuSYSCALL, respectively. Remove CpuK8. Add
CPU_COREI7_FLAGS, CPU_CLFLUSH_FLAGS and CPU_SYSCALL_FLAGS.
(cpu_flags): Remove CpuP4, CpuK6 and CpuK8. Add CpuClflush
and CpuSYSCALL.
(lineno): Removed.
(set_bitfield): Take an argument, lineno. Don't report lineno
on error if it is -1.
(process_i386_cpu_flag): Take an argument, lineno.
(process_i386_opcode_modifier): Likewise.
(process_i386_operand_type): Likewise.
(output_i386_opcode): Likewise.
(opcode_hash_entry): Add lineno.
(process_i386_opcodes): Updated.
(process_i386_registers): Likewise.
(process_i386_initializers): Likewise.
* i386-opc.h (CpuP4): Removed.
(CpuK6): Likewise.
(CpuK8): Likewise.
(CpuClflush): New.
(CpuSYSCALL): Likewise.
(CpuMMX): Updated.
(i386_cpu_flags): Remove cpup4, cpuk6 and cpuk8. Add
cpuclflush and cpusyscall.
* i386-opc.tbl: Update movnti, clflush, lfence, mfence, pause,
syscall and sysret.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2009-01-11 01:25:52 +08:00
|
|
|
const char *comma, const char *indent,
|
2022-12-22 16:32:29 +08:00
|
|
|
int lineno, unsigned int reverse)
|
2007-09-09 09:22:57 +08:00
|
|
|
{
|
2022-03-17 18:04:41 +08:00
|
|
|
char *str, *next = flag, *last;
|
2009-07-25 22:58:58 +08:00
|
|
|
unsigned int i;
|
2022-03-17 18:04:41 +08:00
|
|
|
int value = 1;
|
2022-12-22 16:32:29 +08:00
|
|
|
bool is_isa = false;
|
2023-11-09 19:54:58 +08:00
|
|
|
bitfield all [ARRAY_SIZE (cpu_flags)];
|
|
|
|
bitfield any [ARRAY_SIZE (cpu_flags)];
|
2007-09-09 09:22:57 +08:00
|
|
|
|
|
|
|
/* Copy the default cpu flags. */
|
2023-11-09 19:54:58 +08:00
|
|
|
memcpy (all, cpu_flags, sizeof (cpu_flags));
|
|
|
|
memcpy (any, cpu_flags, sizeof (cpu_flags));
|
2007-09-09 09:22:57 +08:00
|
|
|
|
2022-12-22 16:32:29 +08:00
|
|
|
if (flag == NULL)
|
|
|
|
{
|
|
|
|
for (i = 0; i < ARRAY_SIZE (isa_reverse_deps[0]); ++i)
|
2023-11-09 19:54:58 +08:00
|
|
|
any[i].value = isa_reverse_deps[reverse][i];
|
2022-12-22 16:32:29 +08:00
|
|
|
goto output;
|
|
|
|
}
|
|
|
|
|
2022-03-17 18:04:41 +08:00
|
|
|
if (flag[0] == '~')
|
2009-07-25 22:58:58 +08:00
|
|
|
{
|
|
|
|
last = flag + strlen (flag);
|
|
|
|
|
|
|
|
if (flag[1] == '(')
|
|
|
|
{
|
|
|
|
last -= 1;
|
|
|
|
next = flag + 2;
|
|
|
|
if (*last != ')')
|
2023-01-27 16:20:26 +08:00
|
|
|
fail ("%s: %d: missing `)' in bitfield: %s\n", filename,
|
2009-07-25 22:58:58 +08:00
|
|
|
lineno, flag);
|
|
|
|
*last = '\0';
|
|
|
|
}
|
|
|
|
else
|
|
|
|
next = flag + 1;
|
|
|
|
|
2023-09-15 15:57:05 +08:00
|
|
|
/* First we turn on everything except for cpuno64 and - if
|
2022-03-17 18:05:11 +08:00
|
|
|
present - the padding field. */
|
2023-11-09 19:54:58 +08:00
|
|
|
for (i = 0; i < ARRAY_SIZE (any); i++)
|
|
|
|
if (any[i].position < CpuNo64)
|
|
|
|
any[i].value = 1;
|
2009-07-25 22:58:58 +08:00
|
|
|
|
|
|
|
/* Turn off selective bits. */
|
2022-03-17 18:04:41 +08:00
|
|
|
value = 0;
|
2007-09-09 09:22:57 +08:00
|
|
|
}
|
2022-03-17 18:04:41 +08:00
|
|
|
|
2022-12-22 16:32:29 +08:00
|
|
|
if (name != NULL && value != 0)
|
|
|
|
{
|
2023-11-09 19:54:58 +08:00
|
|
|
for (i = 0; i < ARRAY_SIZE (any); i++)
|
|
|
|
if (strcasecmp (any[i].name, name) == 0)
|
2022-12-22 16:32:29 +08:00
|
|
|
{
|
2023-11-09 19:54:58 +08:00
|
|
|
add_isa_dependencies (any, name, 1, reverse);
|
2022-12-22 16:32:29 +08:00
|
|
|
is_isa = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-03-17 18:04:41 +08:00
|
|
|
if (strcmp (flag, "0"))
|
2007-09-09 09:22:57 +08:00
|
|
|
{
|
2023-11-09 19:54:58 +08:00
|
|
|
bool combined = false;
|
|
|
|
|
2022-12-22 16:32:29 +08:00
|
|
|
if (is_isa)
|
|
|
|
return;
|
|
|
|
|
2022-03-17 18:04:41 +08:00
|
|
|
/* Turn on/off selective bits. */
|
2007-09-09 09:22:57 +08:00
|
|
|
last = flag + strlen (flag);
|
2023-11-09 19:54:58 +08:00
|
|
|
if (name == NULL && strchr (flag, '&'))
|
|
|
|
{
|
|
|
|
for (; next < last && *next != '('; )
|
|
|
|
{
|
|
|
|
str = next_field (next, '&', &next, last);
|
|
|
|
set_bitfield (str, all, value, ARRAY_SIZE (all), lineno);
|
|
|
|
}
|
|
|
|
if (*next == '(')
|
|
|
|
{
|
|
|
|
if (*--last != ')')
|
|
|
|
fail ("%s: %d: missing `)' in bitfield: %s\n", filename,
|
|
|
|
lineno, flag);
|
|
|
|
++next;
|
|
|
|
*last = '\0';
|
|
|
|
}
|
|
|
|
combined = true;
|
|
|
|
}
|
2022-03-17 18:04:41 +08:00
|
|
|
for (; next && next < last; )
|
2007-09-09 09:22:57 +08:00
|
|
|
{
|
2008-10-01 03:47:14 +08:00
|
|
|
str = next_field (next, '|', &next, last);
|
2023-11-09 19:54:58 +08:00
|
|
|
if (name)
|
|
|
|
add_isa_dependencies (any, str, value, reverse);
|
|
|
|
else if (combined || next < last)
|
|
|
|
set_bitfield (str, any, value, ARRAY_SIZE (any), lineno);
|
|
|
|
else /* Singular specifiers go into "all". */
|
|
|
|
set_bitfield (str, all, value, ARRAY_SIZE (all), lineno);
|
|
|
|
combined = true;
|
2007-09-09 09:22:57 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-12-22 16:32:29 +08:00
|
|
|
output:
|
|
|
|
if (name != NULL)
|
|
|
|
{
|
|
|
|
size_t len = strlen (name);
|
|
|
|
char *upper = xmalloc (len + 1);
|
|
|
|
|
2023-11-09 19:54:23 +08:00
|
|
|
/* Cpu64 is special: It specifies a mode dependency, not an ISA one. Zap
|
|
|
|
the flag from ISA initializer macros (and from CPU_ANY_64_FLAGS
|
|
|
|
itself we only care about tracking its dependents. Also don't emit the
|
|
|
|
(otherwise all zero) CPU_64_FLAGS. */
|
|
|
|
if (flag != NULL && reverse == Cpu64)
|
|
|
|
return;
|
|
|
|
if (is_isa || flag == NULL)
|
2023-11-09 19:54:58 +08:00
|
|
|
any[Cpu64].value = 0;
|
2023-11-09 19:54:23 +08:00
|
|
|
|
2022-12-22 16:32:29 +08:00
|
|
|
for (i = 0; i < len; ++i)
|
|
|
|
{
|
|
|
|
/* Don't emit #define-s for auxiliary entries. */
|
|
|
|
if (name[i] == ':')
|
|
|
|
return;
|
|
|
|
upper[i] = TOUPPER (name[i]);
|
|
|
|
}
|
|
|
|
upper[i] = '\0';
|
|
|
|
fprintf (table, "\n#define CPU_%s%s_FLAGS \\\n",
|
|
|
|
flag != NULL ? "": "ANY_", upper);
|
|
|
|
free (upper);
|
|
|
|
}
|
2023-11-09 19:54:23 +08:00
|
|
|
else
|
|
|
|
{
|
|
|
|
/* Synthesize "64-bit mode only" dependencies from the dependencies we
|
|
|
|
have accumulated. */
|
|
|
|
for (i = 0; i < ARRAY_SIZE (isa_reverse_deps[0]); ++i)
|
2023-11-09 19:54:58 +08:00
|
|
|
if (all[i].value && isa_reverse_deps[Cpu64][i])
|
|
|
|
all[Cpu64].value = 1;
|
|
|
|
|
|
|
|
output_cpu_flags(table, all, ARRAY_SIZE (all), -1, comma, indent, lineno);
|
2023-11-09 19:54:23 +08:00
|
|
|
}
|
2022-12-22 16:32:29 +08:00
|
|
|
|
2023-11-09 19:54:58 +08:00
|
|
|
output_cpu_flags (table, any, ARRAY_SIZE (any), name != NULL,
|
2023-08-11 16:04:49 +08:00
|
|
|
comma, indent, lineno);
|
2007-09-09 09:22:57 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
output_opcode_modifier (FILE *table, bitfield *modifier, unsigned int size)
|
|
|
|
{
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
fprintf (table, " { ");
|
|
|
|
|
|
|
|
for (i = 0; i < size - 1; i++)
|
|
|
|
{
|
2014-02-20 04:53:27 +08:00
|
|
|
if (((i + 1) % 20) != 0)
|
|
|
|
fprintf (table, "%d, ", modifier[i].value);
|
|
|
|
else
|
|
|
|
fprintf (table, "%d,", modifier[i].value);
|
2007-09-09 09:22:57 +08:00
|
|
|
if (((i + 1) % 20) == 0)
|
|
|
|
fprintf (table, "\n ");
|
|
|
|
}
|
|
|
|
|
|
|
|
fprintf (table, "%d },\n", modifier[i].value);
|
|
|
|
}
|
|
|
|
|
2022-08-16 15:11:59 +08:00
|
|
|
/* Returns LOG2 of element size. */
|
2018-07-26 06:28:07 +08:00
|
|
|
static int
|
2022-08-16 15:11:59 +08:00
|
|
|
get_element_size (char **opnd, int lineno)
|
2018-07-26 06:28:07 +08:00
|
|
|
{
|
|
|
|
char *str, *next, *last, *op;
|
2022-08-16 15:11:59 +08:00
|
|
|
const char *full = opnd[0];
|
|
|
|
int elem_size = INT_MAX;
|
2018-07-26 06:28:07 +08:00
|
|
|
|
2022-08-16 15:11:59 +08:00
|
|
|
/* Find the memory operand. */
|
|
|
|
while (full != NULL && strstr(full, "BaseIndex") == NULL)
|
|
|
|
full = *++opnd;
|
|
|
|
if (full == NULL)
|
2023-01-27 16:20:26 +08:00
|
|
|
fail ("%s: %d: no memory operand\n", filename, lineno);
|
2018-07-26 06:28:07 +08:00
|
|
|
|
2022-08-16 15:11:59 +08:00
|
|
|
op = xstrdup (full);
|
2018-07-26 06:28:07 +08:00
|
|
|
last = op + strlen (op);
|
|
|
|
for (next = op; next && next < last; )
|
|
|
|
{
|
|
|
|
str = next_field (next, '|', &next, last);
|
|
|
|
if (str)
|
|
|
|
{
|
|
|
|
if (strcasecmp(str, "Byte") == 0)
|
|
|
|
{
|
2022-08-16 15:11:59 +08:00
|
|
|
/* The smallest element size, no need to check
|
2018-07-26 06:28:07 +08:00
|
|
|
further. */
|
2022-08-16 15:11:59 +08:00
|
|
|
elem_size = 0;
|
2018-07-26 06:28:07 +08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
else if (strcasecmp(str, "Word") == 0)
|
|
|
|
{
|
2022-08-16 15:11:59 +08:00
|
|
|
if (elem_size > 1)
|
|
|
|
elem_size = 1;
|
2018-07-26 06:28:07 +08:00
|
|
|
}
|
|
|
|
else if (strcasecmp(str, "Dword") == 0)
|
|
|
|
{
|
2022-08-16 15:11:59 +08:00
|
|
|
if (elem_size > 2)
|
|
|
|
elem_size = 2;
|
2018-07-26 06:28:07 +08:00
|
|
|
}
|
|
|
|
else if (strcasecmp(str, "Qword") == 0)
|
|
|
|
{
|
2022-08-16 15:11:59 +08:00
|
|
|
if (elem_size > 3)
|
|
|
|
elem_size = 3;
|
2018-07-26 06:28:07 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
free (op);
|
|
|
|
|
2022-08-16 15:11:59 +08:00
|
|
|
if (elem_size == INT_MAX)
|
2023-01-27 16:20:26 +08:00
|
|
|
fail ("%s: %d: unknown element size: %s\n", filename, lineno, full);
|
2018-07-26 06:28:07 +08:00
|
|
|
|
2022-08-16 15:11:59 +08:00
|
|
|
return elem_size;
|
2018-07-26 06:28:07 +08:00
|
|
|
}
|
|
|
|
|
2023-12-28 09:06:39 +08:00
|
|
|
static bool
|
|
|
|
rex2_disallowed (const unsigned long long opcode, unsigned int length,
|
|
|
|
unsigned int space, const char *cpu_flags)
|
|
|
|
{
|
|
|
|
/* Some opcodes encode a ModR/M-like byte directly in the opcode. */
|
|
|
|
unsigned int base_opcode = opcode >> (8 * length - 8);
|
|
|
|
|
|
|
|
/* All opcodes listed map0 0x4*, 0x7*, 0xa*, 0xe* and map1 0x3*, 0x8*
|
|
|
|
are reserved under REX2 and triggers #UD when prefixed with REX2 */
|
|
|
|
if (space == 0)
|
|
|
|
switch (base_opcode >> 4)
|
|
|
|
{
|
|
|
|
case 0x4:
|
|
|
|
case 0x7:
|
|
|
|
case 0xA:
|
|
|
|
case 0xE:
|
|
|
|
return true;
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (space == SPACE_0F)
|
|
|
|
switch (base_opcode >> 4)
|
|
|
|
{
|
|
|
|
case 0x3:
|
|
|
|
case 0x8:
|
|
|
|
return true;
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2021-03-24 15:32:32 +08:00
|
|
|
static void
|
2021-03-29 18:02:50 +08:00
|
|
|
process_i386_opcode_modifier (FILE *table, char *mod, unsigned int space,
|
2023-02-10 15:10:38 +08:00
|
|
|
unsigned int prefix, const char *extension_opcode,
|
2023-12-28 09:06:39 +08:00
|
|
|
char **opnd, int lineno, bool rex2_disallowed)
|
2007-09-09 09:22:57 +08:00
|
|
|
{
|
|
|
|
char *str, *next, *last;
|
2024-05-03 15:24:48 +08:00
|
|
|
bool disp8_shift_derived = false;
|
2007-09-09 09:22:57 +08:00
|
|
|
bitfield modifiers [ARRAY_SIZE (opcode_modifiers)];
|
2023-02-10 15:10:38 +08:00
|
|
|
static const char *const spaces[] = {
|
|
|
|
#define SPACE(n) [SPACE_##n] = #n
|
|
|
|
SPACE(BASE),
|
|
|
|
SPACE(0F),
|
|
|
|
SPACE(0F38),
|
|
|
|
SPACE(0F3A),
|
Support APX GPR32 with extend evex prefix
This patch adds non-ND, non-NF forms of EVEX promotion insn.
EVEX extension of legacy instructions:
All promoted legacy instructions are placed in EVEX map 4, which is
currently reserved.
EVEX extension of EVEX instructions:
All existing EVEX instructions are extended by APX using the extended
EVEX prefix, so that they can access all 32 GPRs.
EVEX extension of VEX instructions:
Promoting a VEX instruction into the EVEX space does not change the map
id, the opcode, or the operand encoding of the VEX instruction.
Note: The promoted versions of MOVBE will be extended to include the “MOVBE
reg1, reg2”.
gas/ChangeLog:
2023-12-28 Lingling Kong <lingling.kong@intel.com>
H.J. Lu <hongjiu.lu@intel.com>
Lili Cui <lili.cui@intel.com>
Lin Hu <lin1.hu@intel.com>
* config/tc-i386.c (struct _i386_insn): Add has_egpr.
(need_evex_encoding): Adjusted for apx.
(cpu_flags_match): Ditto.
(install_template): Handled APX combines.
(is_apx_evex_encoding): Test apx evex encoding.
(build_apx_evex_prefix): Enabe APX evex prefix.
(md_assemble): Handle apx with evex encoding.
(process_suffix): Handle apx map4 prefix.
(check_register): Assign i.vec_encoding for APX evex instructions.
* testsuite/gas/i386/x86-64-evex.d: Adjust test cases.
* testsuite/gas/i386/x86-64.exp: Adjust x86-64-inval-movbe.
opcodes/ChangeLog:
* i386-dis-evex-len.h: Handle EVEX_LEN_0F38F2, EVEX_LEN_0F38F3.
* i386-dis-evex-prefix.h: Handle PREFIX_EVEX_0F38F2_L_0,
PREFIX_EVEX_0F38F3_L_0, PREFIX_EVEX_MAP4_D8,
PREFIX_EVEX_MAP4_DA, PREFIX_EVEX_MAP4_DB,
PREFIX_EVEX_MAP4_DC, PREFIX_EVEX_MAP4_DD,
PREFIX_EVEX_MAP4_DE, PREFIX_EVEX_MAP4_DF,
PREFIX_EVEX_MAP4_F0, PREFIX_EVEX_MAP4_F1,
PREFIX_EVEX_MAP4_F2, PREFIX_EVEX_MAP4_F8.
* i386-dis-evex-reg.h: Handle REG_EVEX_0F38F3_L_0_P_0.
* i386-dis-evex.h: Add EVEX_MAP4_ for legacy insn
promote to apx to use gpr32
* opcodes/i386-dis-evex-x86-64.h: Handle Add X86_64_EVEX_0F90,
X86_64_EVEX_0F92, X86_64_EVEX_0F93, X86_64_EVEX_0F38F2,
X86_64_EVEX_0F38F3, X86_64_EVEX_0F38F5, X86_64_EVEX_0F38F6,
X86_64_EVEX_0F38F7, X86_64_EVEX_0F3AF0, X86_64_EVEX_0F91.
* i386-dis.c
(struct instr_info): Deleted bool r.
(PREFIX_NP_OR_DATA): New.
(NO_PREFIX): New.
(putop): Ditto.
(X86_64_EVEX_FROM_VEX_TABLE): Diito.
(get_valid_dis386): Decode insn erex in extend evex prefix.
Handle EVEX_MAP4
(print_insn): Handle PREFIX_DATA_AND_NP_ONLY.
(print_register): Handle apx instructions decode.
(OP_E_memory): Diito.
(OP_G): Diito.
(OP_XMM): Diito.
(DistinctDest_Fixup): Diito.
* i386-gen.c (process_i386_opcode_modifier): Add EVEXMAP4.
* i386-opc.h (SPACE_EVEXMAP4): Add legacy insn
promote to evex.
* i386-opc.tbl: Handle some legacy and vex insns don't
support gpr32. And add some legacy insn (map2 / 3) promote
to evex.
2023-12-28 09:06:40 +08:00
|
|
|
SPACE(EVEXMAP4),
|
2023-02-10 15:10:38 +08:00
|
|
|
SPACE(EVEXMAP5),
|
|
|
|
SPACE(EVEXMAP6),
|
2023-10-31 16:23:53 +08:00
|
|
|
SPACE(VEXMAP7),
|
2023-02-10 15:10:38 +08:00
|
|
|
SPACE(XOP08),
|
|
|
|
SPACE(XOP09),
|
|
|
|
SPACE(XOP0A),
|
|
|
|
#undef SPACE
|
|
|
|
};
|
2007-09-09 09:22:57 +08:00
|
|
|
|
2017-11-30 18:48:13 +08:00
|
|
|
active_isstring = 0;
|
|
|
|
|
2007-09-09 09:22:57 +08:00
|
|
|
/* Copy the default opcode modifier. */
|
|
|
|
memcpy (modifiers, opcode_modifiers, sizeof (modifiers));
|
|
|
|
|
|
|
|
if (strcmp (mod, "0"))
|
|
|
|
{
|
2019-10-30 16:05:46 +08:00
|
|
|
unsigned int have_w = 0, bwlq_suf = 0xf;
|
|
|
|
|
2007-09-09 09:22:57 +08:00
|
|
|
last = mod + strlen (mod);
|
|
|
|
for (next = mod; next && next < last; )
|
|
|
|
{
|
2008-10-01 03:47:14 +08:00
|
|
|
str = next_field (next, '|', &next, last);
|
2007-09-09 09:22:57 +08:00
|
|
|
if (str)
|
2017-11-30 18:48:13 +08:00
|
|
|
{
|
2018-07-26 06:28:07 +08:00
|
|
|
int val = 1;
|
2023-02-10 15:10:38 +08:00
|
|
|
|
|
|
|
if (strncmp(str, "OpcodeSpace", 11) == 0)
|
|
|
|
{
|
|
|
|
char *end;
|
|
|
|
|
|
|
|
if (str[11] != '=')
|
|
|
|
fail ("%s:%d: Missing value for `OpcodeSpace'\n",
|
|
|
|
filename, lineno);
|
|
|
|
|
|
|
|
val = strtol (str + 12, &end, 0);
|
|
|
|
if (*end)
|
|
|
|
fail ("%s:%d: Bogus value `%s' for `OpcodeSpace'\n",
|
|
|
|
filename, lineno, end);
|
|
|
|
|
|
|
|
if (space)
|
|
|
|
{
|
|
|
|
if (val != space)
|
|
|
|
fail ("%s:%d: Conflicting opcode space specifications\n",
|
|
|
|
filename, lineno);
|
|
|
|
fprintf (stderr,
|
|
|
|
"%s:%d: Warning: redundant opcode space specification\n",
|
|
|
|
filename, lineno);
|
|
|
|
}
|
|
|
|
|
|
|
|
space = val;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2018-07-26 06:28:07 +08:00
|
|
|
if (strcasecmp(str, "Broadcast") == 0)
|
2022-08-16 15:11:59 +08:00
|
|
|
val = get_element_size (opnd, lineno) + BYTE_BROADCAST;
|
|
|
|
else if (strcasecmp(str, "Disp8MemShift") == 0)
|
2024-05-03 15:24:48 +08:00
|
|
|
{
|
|
|
|
val = get_element_size (opnd, lineno);
|
|
|
|
disp8_shift_derived = true;
|
|
|
|
}
|
2020-10-14 19:17:54 +08:00
|
|
|
|
2018-07-26 06:28:07 +08:00
|
|
|
set_bitfield (str, modifiers, val, ARRAY_SIZE (modifiers),
|
2020-10-14 19:17:54 +08:00
|
|
|
lineno);
|
2017-11-30 18:48:13 +08:00
|
|
|
if (strcasecmp(str, "IsString") == 0)
|
|
|
|
active_isstring = 1;
|
2019-10-30 16:05:46 +08:00
|
|
|
|
|
|
|
if (strcasecmp(str, "W") == 0)
|
|
|
|
have_w = 1;
|
|
|
|
|
|
|
|
if (strcasecmp(str, "No_bSuf") == 0)
|
|
|
|
bwlq_suf &= ~1;
|
|
|
|
if (strcasecmp(str, "No_wSuf") == 0)
|
|
|
|
bwlq_suf &= ~2;
|
|
|
|
if (strcasecmp(str, "No_lSuf") == 0)
|
|
|
|
bwlq_suf &= ~4;
|
|
|
|
if (strcasecmp(str, "No_qSuf") == 0)
|
|
|
|
bwlq_suf &= ~8;
|
2017-11-30 18:48:13 +08:00
|
|
|
}
|
2007-09-09 09:22:57 +08:00
|
|
|
}
|
2019-10-30 16:05:46 +08:00
|
|
|
|
2021-03-24 15:32:32 +08:00
|
|
|
if (prefix)
|
|
|
|
{
|
|
|
|
if (!modifiers[OpcodePrefix].value)
|
|
|
|
modifiers[OpcodePrefix].value = prefix;
|
|
|
|
else if (modifiers[OpcodePrefix].value != prefix)
|
2023-01-27 16:20:26 +08:00
|
|
|
fail ("%s:%d: Conflicting prefix specifications\n",
|
2021-03-24 15:32:32 +08:00
|
|
|
filename, lineno);
|
|
|
|
else
|
|
|
|
fprintf (stderr,
|
2023-01-27 16:20:26 +08:00
|
|
|
"%s:%d: Warning: redundant prefix specification\n",
|
2021-03-24 15:32:32 +08:00
|
|
|
filename, lineno);
|
|
|
|
}
|
|
|
|
|
2019-10-30 16:05:46 +08:00
|
|
|
if (have_w && !bwlq_suf)
|
|
|
|
fail ("%s: %d: stray W modifier\n", filename, lineno);
|
|
|
|
if (have_w && !(bwlq_suf & 1))
|
|
|
|
fprintf (stderr, "%s: %d: W modifier without Byte operand(s)\n",
|
|
|
|
filename, lineno);
|
|
|
|
if (have_w && !(bwlq_suf & ~1))
|
|
|
|
fprintf (stderr,
|
|
|
|
"%s: %d: W modifier without Word/Dword/Qword operand(s)\n",
|
|
|
|
filename, lineno);
|
2007-09-09 09:22:57 +08:00
|
|
|
}
|
2023-02-10 15:10:38 +08:00
|
|
|
|
|
|
|
if (space >= ARRAY_SIZE (spaces) || !spaces[space])
|
|
|
|
fail ("%s:%d: Unknown opcode space %u\n", filename, lineno, space);
|
|
|
|
|
|
|
|
fprintf (table, " SPACE_%s, %s,\n",
|
|
|
|
spaces[space], extension_opcode ? extension_opcode : "None");
|
|
|
|
|
2023-11-09 19:55:26 +08:00
|
|
|
/* Rather than evaluating multiple conditions at runtime to determine
|
|
|
|
whether an EVEX encoding is being dealt with, derive that information
|
2024-05-03 15:24:48 +08:00
|
|
|
right here. A missing EVex attribute means "dynamic". There's one
|
|
|
|
exception though: A value-less Disp8MemShift needs zapping rather than
|
|
|
|
respecting if no other attribute indicates EVEX encoding. This is for
|
|
|
|
certain SSE2AVX templatized templates to work reasonably. */
|
|
|
|
if (!modifiers[EVex].value)
|
|
|
|
{
|
|
|
|
if (modifiers[Broadcast].value
|
2023-11-09 19:55:26 +08:00
|
|
|
|| modifiers[Masking].value
|
2024-05-03 15:24:48 +08:00
|
|
|
|| modifiers[SAE].value)
|
|
|
|
modifiers[EVex].value = EVEXDYN;
|
|
|
|
else if (disp8_shift_derived)
|
|
|
|
modifiers[Disp8MemShift].value = 0;
|
|
|
|
else if (modifiers[Disp8MemShift].value)
|
|
|
|
modifiers[EVex].value = EVEXDYN;
|
|
|
|
}
|
2023-11-09 19:55:26 +08:00
|
|
|
|
2023-12-28 09:06:39 +08:00
|
|
|
/* Vex, legacy map2 and map3 and rex2_disallowed do not support EGPR.
|
|
|
|
For templates supporting both Vex and EVex allowing EGPR. */
|
|
|
|
if ((modifiers[Vex].value || space > SPACE_0F || rex2_disallowed)
|
|
|
|
&& !modifiers[EVex].value)
|
|
|
|
modifiers[NoEgpr].value = 1;
|
|
|
|
|
2007-09-09 09:22:57 +08:00
|
|
|
output_opcode_modifier (table, modifiers, ARRAY_SIZE (modifiers));
|
|
|
|
}
|
|
|
|
|
2017-11-30 18:48:13 +08:00
|
|
|
enum stage {
|
|
|
|
stage_macros,
|
|
|
|
stage_opcodes,
|
|
|
|
stage_registers,
|
|
|
|
};
|
|
|
|
|
2007-09-09 09:22:57 +08:00
|
|
|
static void
|
2019-11-08 16:03:23 +08:00
|
|
|
output_operand_type (FILE *table, enum operand_class class,
|
2019-11-12 16:07:34 +08:00
|
|
|
enum operand_instance instance,
|
2019-11-08 16:03:23 +08:00
|
|
|
const bitfield *types, unsigned int size,
|
2017-11-30 18:48:13 +08:00
|
|
|
enum stage stage, const char *indent)
|
2007-09-09 09:22:57 +08:00
|
|
|
{
|
|
|
|
unsigned int i;
|
|
|
|
|
2019-11-12 16:07:34 +08:00
|
|
|
fprintf (table, "{ { %d, %d, ", class, instance);
|
2007-09-09 09:22:57 +08:00
|
|
|
|
|
|
|
for (i = 0; i < size - 1; i++)
|
|
|
|
{
|
2019-11-12 16:07:34 +08:00
|
|
|
if (((i + 3) % 20) != 0)
|
2014-02-20 04:53:27 +08:00
|
|
|
fprintf (table, "%d, ", types[i].value);
|
|
|
|
else
|
|
|
|
fprintf (table, "%d,", types[i].value);
|
2019-11-12 16:07:34 +08:00
|
|
|
if (((i + 3) % 20) == 0)
|
2007-09-09 09:22:57 +08:00
|
|
|
{
|
|
|
|
/* We need \\ for macro. */
|
2017-11-30 18:48:13 +08:00
|
|
|
if (stage == stage_macros)
|
2014-02-20 04:53:27 +08:00
|
|
|
fprintf (table, " \\\n%s", indent);
|
2007-09-09 09:22:57 +08:00
|
|
|
else
|
|
|
|
fprintf (table, "\n%s", indent);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
fprintf (table, "%d } }", types[i].value);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2017-11-30 18:48:13 +08:00
|
|
|
process_i386_operand_type (FILE *table, char *op, enum stage stage,
|
gas/
2009-01-10 H.J. Lu <hongjiu.lu@intel.com>
* gas/config/tc-i386.c (cpu_arch): Add corei7, .clflush and
.syscall.
(i386_align_code): Handle PROCESSOR_COREI7.
(md_show_usage): Add corei7, clflush and syscall.
(i386_target_format): Replace cpup4 with cpuclflush.
* gas/config/tc-i386.h (processor_type): Add PROCESSOR_COREI7.
* doc/c-i386.texi: Document corei7, clflush and syscall.
gas/testsuite/
2009-01-10 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/arch-10.s: Add clflush and syscall.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/arch-10.d: Updated.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
opcodes/
2009-01-10 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (cpu_flag_init): Replace CpuP4 and CpuK6 with
CpuClflush and CpuSYSCALL, respectively. Remove CpuK8. Add
CPU_COREI7_FLAGS, CPU_CLFLUSH_FLAGS and CPU_SYSCALL_FLAGS.
(cpu_flags): Remove CpuP4, CpuK6 and CpuK8. Add CpuClflush
and CpuSYSCALL.
(lineno): Removed.
(set_bitfield): Take an argument, lineno. Don't report lineno
on error if it is -1.
(process_i386_cpu_flag): Take an argument, lineno.
(process_i386_opcode_modifier): Likewise.
(process_i386_operand_type): Likewise.
(output_i386_opcode): Likewise.
(opcode_hash_entry): Add lineno.
(process_i386_opcodes): Updated.
(process_i386_registers): Likewise.
(process_i386_initializers): Likewise.
* i386-opc.h (CpuP4): Removed.
(CpuK6): Likewise.
(CpuK8): Likewise.
(CpuClflush): New.
(CpuSYSCALL): Likewise.
(CpuMMX): Updated.
(i386_cpu_flags): Remove cpup4, cpuk6 and cpuk8. Add
cpuclflush and cpusyscall.
* i386-opc.tbl: Update movnti, clflush, lfence, mfence, pause,
syscall and sysret.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2009-01-11 01:25:52 +08:00
|
|
|
const char *indent, int lineno)
|
2007-09-09 09:22:57 +08:00
|
|
|
{
|
|
|
|
char *str, *next, *last;
|
2019-11-08 16:03:23 +08:00
|
|
|
enum operand_class class = ClassNone;
|
2019-11-12 16:07:34 +08:00
|
|
|
enum operand_instance instance = InstanceNone;
|
2007-09-09 09:22:57 +08:00
|
|
|
bitfield types [ARRAY_SIZE (operand_types)];
|
|
|
|
|
|
|
|
/* Copy the default operand type. */
|
|
|
|
memcpy (types, operand_types, sizeof (types));
|
|
|
|
|
|
|
|
if (strcmp (op, "0"))
|
|
|
|
{
|
2017-11-30 18:48:13 +08:00
|
|
|
int baseindex = 0;
|
|
|
|
|
2007-09-09 09:22:57 +08:00
|
|
|
last = op + strlen (op);
|
|
|
|
for (next = op; next && next < last; )
|
|
|
|
{
|
2008-10-01 03:47:14 +08:00
|
|
|
str = next_field (next, '|', &next, last);
|
2019-11-08 16:03:23 +08:00
|
|
|
if (str)
|
|
|
|
{
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
if (!strncmp(str, "Class=", 6))
|
|
|
|
{
|
|
|
|
for (i = 0; i < ARRAY_SIZE(operand_classes); ++i)
|
|
|
|
if (!strcmp(str + 6, operand_classes[i].name))
|
|
|
|
{
|
|
|
|
class = operand_classes[i].value;
|
|
|
|
str = NULL;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2019-11-12 16:07:34 +08:00
|
|
|
|
|
|
|
if (str && !strncmp(str, "Instance=", 9))
|
|
|
|
{
|
|
|
|
for (i = 0; i < ARRAY_SIZE(operand_instances); ++i)
|
|
|
|
if (!strcmp(str + 9, operand_instances[i].name))
|
|
|
|
{
|
|
|
|
instance = operand_instances[i].value;
|
|
|
|
str = NULL;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2019-11-08 16:03:23 +08:00
|
|
|
}
|
2007-09-09 09:22:57 +08:00
|
|
|
if (str)
|
2017-11-30 18:48:13 +08:00
|
|
|
{
|
|
|
|
set_bitfield (str, types, 1, ARRAY_SIZE (types), lineno);
|
|
|
|
if (strcasecmp(str, "BaseIndex") == 0)
|
|
|
|
baseindex = 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (stage == stage_opcodes && baseindex && !active_isstring)
|
|
|
|
{
|
|
|
|
set_bitfield("Disp8", types, 1, ARRAY_SIZE (types), lineno);
|
|
|
|
if (!active_cpu_flags.bitfield.cpu64
|
|
|
|
&& !active_cpu_flags.bitfield.cpumpx)
|
|
|
|
set_bitfield("Disp16", types, 1, ARRAY_SIZE (types), lineno);
|
2022-07-04 14:32:50 +08:00
|
|
|
set_bitfield("Disp32", types, 1, ARRAY_SIZE (types), lineno);
|
2007-09-09 09:22:57 +08:00
|
|
|
}
|
|
|
|
}
|
2019-11-12 16:07:34 +08:00
|
|
|
output_operand_type (table, class, instance, types, ARRAY_SIZE (types),
|
|
|
|
stage, indent);
|
2007-09-09 09:22:57 +08:00
|
|
|
}
|
|
|
|
|
2023-01-20 17:15:48 +08:00
|
|
|
static char *mkident (const char *mnem)
|
|
|
|
{
|
|
|
|
char *ident = xstrdup (mnem), *p = ident;
|
|
|
|
|
|
|
|
do
|
|
|
|
{
|
|
|
|
if (!ISALNUM (*p))
|
|
|
|
*p = '_';
|
|
|
|
}
|
|
|
|
while (*++p);
|
|
|
|
|
|
|
|
return ident;
|
|
|
|
}
|
|
|
|
|
2008-10-01 03:47:14 +08:00
|
|
|
static void
|
|
|
|
output_i386_opcode (FILE *table, const char *name, char *str,
|
gas/
2009-01-10 H.J. Lu <hongjiu.lu@intel.com>
* gas/config/tc-i386.c (cpu_arch): Add corei7, .clflush and
.syscall.
(i386_align_code): Handle PROCESSOR_COREI7.
(md_show_usage): Add corei7, clflush and syscall.
(i386_target_format): Replace cpup4 with cpuclflush.
* gas/config/tc-i386.h (processor_type): Add PROCESSOR_COREI7.
* doc/c-i386.texi: Document corei7, clflush and syscall.
gas/testsuite/
2009-01-10 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/arch-10.s: Add clflush and syscall.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/arch-10.d: Updated.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
opcodes/
2009-01-10 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (cpu_flag_init): Replace CpuP4 and CpuK6 with
CpuClflush and CpuSYSCALL, respectively. Remove CpuK8. Add
CPU_COREI7_FLAGS, CPU_CLFLUSH_FLAGS and CPU_SYSCALL_FLAGS.
(cpu_flags): Remove CpuP4, CpuK6 and CpuK8. Add CpuClflush
and CpuSYSCALL.
(lineno): Removed.
(set_bitfield): Take an argument, lineno. Don't report lineno
on error if it is -1.
(process_i386_cpu_flag): Take an argument, lineno.
(process_i386_opcode_modifier): Likewise.
(process_i386_operand_type): Likewise.
(output_i386_opcode): Likewise.
(opcode_hash_entry): Add lineno.
(process_i386_opcodes): Updated.
(process_i386_registers): Likewise.
(process_i386_initializers): Likewise.
* i386-opc.h (CpuP4): Removed.
(CpuK6): Likewise.
(CpuK8): Likewise.
(CpuClflush): New.
(CpuSYSCALL): Likewise.
(CpuMMX): Updated.
(i386_cpu_flags): Remove cpup4, cpuk6 and cpuk8. Add
cpuclflush and cpusyscall.
* i386-opc.tbl: Update movnti, clflush, lfence, mfence, pause,
syscall and sysret.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2009-01-11 01:25:52 +08:00
|
|
|
char *last, int lineno)
|
2008-10-01 03:47:14 +08:00
|
|
|
{
|
2021-03-29 18:02:50 +08:00
|
|
|
unsigned int i, length, prefix = 0, space = 0;
|
2023-01-20 17:15:48 +08:00
|
|
|
char *base_opcode, *extension_opcode, *end, *ident;
|
2008-10-01 03:47:14 +08:00
|
|
|
char *cpu_flags, *opcode_modifier, *operand_types [MAX_OPERANDS];
|
2021-03-29 18:04:03 +08:00
|
|
|
unsigned long long opcode;
|
2008-10-01 03:47:14 +08:00
|
|
|
|
|
|
|
/* Find base_opcode. */
|
|
|
|
base_opcode = next_field (str, ',', &str, last);
|
|
|
|
|
2022-12-16 16:00:23 +08:00
|
|
|
/* Find extension_opcode, if any. */
|
|
|
|
extension_opcode = strchr (base_opcode, '/');
|
|
|
|
if (extension_opcode)
|
|
|
|
*extension_opcode++ = '\0';
|
2008-10-01 03:47:14 +08:00
|
|
|
|
|
|
|
/* Find cpu_flags. */
|
|
|
|
cpu_flags = next_field (str, ',', &str, last);
|
|
|
|
|
|
|
|
/* Find opcode_modifier. */
|
|
|
|
opcode_modifier = next_field (str, ',', &str, last);
|
|
|
|
|
|
|
|
/* Remove the first {. */
|
|
|
|
str = remove_leading_whitespaces (str);
|
|
|
|
if (*str != '{')
|
|
|
|
abort ();
|
|
|
|
str = remove_leading_whitespaces (str + 1);
|
2021-03-03 19:57:08 +08:00
|
|
|
remove_trailing_whitespaces (str);
|
2008-10-01 03:47:14 +08:00
|
|
|
|
2021-03-03 19:57:08 +08:00
|
|
|
/* Remove } and trailing white space. */
|
2008-10-01 03:47:14 +08:00
|
|
|
i = strlen (str);
|
2021-03-03 19:57:08 +08:00
|
|
|
if (!i || str[i - 1] != '}')
|
2008-10-01 03:47:14 +08:00
|
|
|
abort ();
|
2021-03-03 19:57:08 +08:00
|
|
|
str[--i] = '\0';
|
|
|
|
remove_trailing_whitespaces (str);
|
2008-10-01 03:47:14 +08:00
|
|
|
|
2021-03-03 19:57:08 +08:00
|
|
|
if (!*str)
|
|
|
|
operand_types [i = 0] = NULL;
|
|
|
|
else
|
2008-10-01 03:47:14 +08:00
|
|
|
{
|
2021-03-03 19:57:08 +08:00
|
|
|
last = str + strlen (str);
|
2008-10-01 03:47:14 +08:00
|
|
|
|
2021-03-03 19:57:08 +08:00
|
|
|
/* Find operand_types. */
|
|
|
|
for (i = 0; i < ARRAY_SIZE (operand_types); i++)
|
2008-10-01 03:47:14 +08:00
|
|
|
{
|
2021-03-03 19:57:08 +08:00
|
|
|
if (str >= last)
|
|
|
|
{
|
|
|
|
operand_types [i] = NULL;
|
|
|
|
break;
|
|
|
|
}
|
2008-10-01 03:47:14 +08:00
|
|
|
|
2021-03-03 19:57:08 +08:00
|
|
|
operand_types [i] = next_field (str, ',', &str, last);
|
2008-10-01 03:47:14 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-03-29 18:04:03 +08:00
|
|
|
opcode = strtoull (base_opcode, &end, 0);
|
2008-10-01 03:47:14 +08:00
|
|
|
|
2021-03-24 15:33:33 +08:00
|
|
|
/* Determine opcode length. */
|
2021-03-29 18:04:03 +08:00
|
|
|
for (length = 1; length < 8; ++length)
|
2021-03-24 15:33:33 +08:00
|
|
|
if (!(opcode >> (8 * length)))
|
|
|
|
break;
|
|
|
|
|
2021-03-24 15:32:32 +08:00
|
|
|
/* Transform prefixes encoded in the opcode into opcode modifier
|
|
|
|
representation. */
|
2021-03-24 15:33:33 +08:00
|
|
|
if (length > 1)
|
2020-10-14 19:17:54 +08:00
|
|
|
{
|
2021-03-24 15:33:33 +08:00
|
|
|
switch (opcode >> (8 * length - 8))
|
2020-10-14 19:17:54 +08:00
|
|
|
{
|
2021-03-24 15:32:32 +08:00
|
|
|
case 0x66: prefix = PREFIX_0X66; break;
|
|
|
|
case 0xF3: prefix = PREFIX_0XF3; break;
|
|
|
|
case 0xF2: prefix = PREFIX_0XF2; break;
|
2020-10-14 19:17:54 +08:00
|
|
|
}
|
2021-03-24 15:32:32 +08:00
|
|
|
|
2021-03-24 15:33:33 +08:00
|
|
|
if (prefix)
|
2021-03-29 18:04:03 +08:00
|
|
|
opcode &= (1ULL << (8 * --length)) - 1;
|
2020-10-14 19:17:54 +08:00
|
|
|
}
|
2008-10-01 03:47:14 +08:00
|
|
|
|
2021-03-29 18:02:50 +08:00
|
|
|
/* Transform opcode space encoded in the opcode into opcode modifier
|
|
|
|
representation. */
|
|
|
|
if (length > 1 && (opcode >> (8 * length - 8)) == 0xf)
|
|
|
|
{
|
|
|
|
switch ((opcode >> (8 * length - 16)) & 0xff)
|
|
|
|
{
|
|
|
|
default: space = SPACE_0F; break;
|
|
|
|
case 0x38: space = SPACE_0F38; break;
|
|
|
|
case 0x3A: space = SPACE_0F3A; break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (space != SPACE_0F && --length == 1)
|
2023-01-27 16:20:26 +08:00
|
|
|
fail ("%s:%d: %s: unrecognized opcode encoding space\n",
|
2021-03-29 18:02:50 +08:00
|
|
|
filename, lineno, name);
|
2021-03-29 18:04:03 +08:00
|
|
|
opcode &= (1ULL << (8 * --length)) - 1;
|
2021-03-29 18:02:50 +08:00
|
|
|
}
|
|
|
|
|
2021-03-29 18:04:03 +08:00
|
|
|
if (length > 2)
|
2023-01-27 16:20:26 +08:00
|
|
|
fail ("%s:%d: %s: residual opcode (0x%0*llx) too large\n",
|
2021-03-29 18:04:03 +08:00
|
|
|
filename, lineno, name, 2 * length, opcode);
|
|
|
|
|
2023-01-20 17:15:48 +08:00
|
|
|
ident = mkident (name);
|
2023-02-10 15:10:38 +08:00
|
|
|
fprintf (table, " { MN_%s, 0x%0*llx%s, %u,",
|
|
|
|
ident, 2 * (int)length, opcode, end, i);
|
2023-01-20 17:15:48 +08:00
|
|
|
free (ident);
|
2021-03-24 15:32:32 +08:00
|
|
|
|
2021-03-29 18:02:50 +08:00
|
|
|
process_i386_opcode_modifier (table, opcode_modifier, space, prefix,
|
2023-12-28 09:06:39 +08:00
|
|
|
extension_opcode, operand_types, lineno,
|
|
|
|
rex2_disallowed (opcode, length, space,
|
|
|
|
cpu_flags));
|
2021-03-24 15:32:32 +08:00
|
|
|
|
2022-12-22 16:32:29 +08:00
|
|
|
process_i386_cpu_flag (table, cpu_flags, NULL, ",", " ", lineno, CpuMax);
|
2021-03-24 00:09:11 +08:00
|
|
|
|
2008-10-01 03:47:14 +08:00
|
|
|
fprintf (table, " { ");
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE (operand_types); i++)
|
|
|
|
{
|
2021-03-03 19:57:08 +08:00
|
|
|
if (!operand_types[i])
|
2008-10-01 03:47:14 +08:00
|
|
|
{
|
|
|
|
if (i == 0)
|
2017-11-30 18:48:13 +08:00
|
|
|
process_i386_operand_type (table, "0", stage_opcodes, "\t ",
|
|
|
|
lineno);
|
2008-10-01 03:47:14 +08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (i != 0)
|
|
|
|
fprintf (table, ",\n ");
|
|
|
|
|
2017-11-30 18:48:13 +08:00
|
|
|
process_i386_operand_type (table, operand_types[i], stage_opcodes,
|
gas/
2009-01-10 H.J. Lu <hongjiu.lu@intel.com>
* gas/config/tc-i386.c (cpu_arch): Add corei7, .clflush and
.syscall.
(i386_align_code): Handle PROCESSOR_COREI7.
(md_show_usage): Add corei7, clflush and syscall.
(i386_target_format): Replace cpup4 with cpuclflush.
* gas/config/tc-i386.h (processor_type): Add PROCESSOR_COREI7.
* doc/c-i386.texi: Document corei7, clflush and syscall.
gas/testsuite/
2009-01-10 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/arch-10.s: Add clflush and syscall.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/arch-10.d: Updated.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
opcodes/
2009-01-10 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (cpu_flag_init): Replace CpuP4 and CpuK6 with
CpuClflush and CpuSYSCALL, respectively. Remove CpuK8. Add
CPU_COREI7_FLAGS, CPU_CLFLUSH_FLAGS and CPU_SYSCALL_FLAGS.
(cpu_flags): Remove CpuP4, CpuK6 and CpuK8. Add CpuClflush
and CpuSYSCALL.
(lineno): Removed.
(set_bitfield): Take an argument, lineno. Don't report lineno
on error if it is -1.
(process_i386_cpu_flag): Take an argument, lineno.
(process_i386_opcode_modifier): Likewise.
(process_i386_operand_type): Likewise.
(output_i386_opcode): Likewise.
(opcode_hash_entry): Add lineno.
(process_i386_opcodes): Updated.
(process_i386_registers): Likewise.
(process_i386_initializers): Likewise.
* i386-opc.h (CpuP4): Removed.
(CpuK6): Likewise.
(CpuK8): Likewise.
(CpuClflush): New.
(CpuSYSCALL): Likewise.
(CpuMMX): Updated.
(i386_cpu_flags): Remove cpup4, cpuk6 and cpuk8. Add
cpuclflush and cpusyscall.
* i386-opc.tbl: Update movnti, clflush, lfence, mfence, pause,
syscall and sysret.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2009-01-11 01:25:52 +08:00
|
|
|
"\t ", lineno);
|
2008-10-01 03:47:14 +08:00
|
|
|
}
|
|
|
|
fprintf (table, " } },\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
struct opcode_hash_entry
|
|
|
|
{
|
2023-01-20 17:18:40 +08:00
|
|
|
const char *name;
|
|
|
|
struct opcode_entry
|
|
|
|
{
|
|
|
|
struct opcode_entry *next;
|
|
|
|
char *opcode;
|
|
|
|
int lineno;
|
|
|
|
} entry;
|
2008-10-01 03:47:14 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
/* Calculate the hash value of an opcode hash entry P. */
|
|
|
|
|
|
|
|
static hashval_t
|
|
|
|
opcode_hash_hash (const void *p)
|
|
|
|
{
|
|
|
|
struct opcode_hash_entry *entry = (struct opcode_hash_entry *) p;
|
|
|
|
return htab_hash_string (entry->name);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Compare a string Q against an opcode hash entry P. */
|
|
|
|
|
|
|
|
static int
|
|
|
|
opcode_hash_eq (const void *p, const void *q)
|
|
|
|
{
|
|
|
|
struct opcode_hash_entry *entry = (struct opcode_hash_entry *) p;
|
|
|
|
const char *name = (const char *) q;
|
|
|
|
return strcmp (name, entry->name) == 0;
|
|
|
|
}
|
|
|
|
|
2024-03-28 18:47:59 +08:00
|
|
|
static bool
|
2020-03-09 17:12:14 +08:00
|
|
|
parse_template (char *buf, int lineno)
|
|
|
|
{
|
2024-03-28 18:47:59 +08:00
|
|
|
char sep, *end, *ptr;
|
2022-08-16 15:14:39 +08:00
|
|
|
struct template *tmpl;
|
2020-03-09 17:12:14 +08:00
|
|
|
struct template_instance *last_inst = NULL;
|
|
|
|
|
|
|
|
buf = remove_leading_whitespaces (buf + 1);
|
|
|
|
end = strchr (buf, ':');
|
|
|
|
if (end == NULL)
|
2022-08-16 15:14:39 +08:00
|
|
|
{
|
|
|
|
struct template *prev = NULL;
|
|
|
|
|
|
|
|
end = strchr (buf, '>');
|
|
|
|
if (end == NULL)
|
|
|
|
fail ("%s: %d: missing ':' or '>'\n", filename, lineno);
|
|
|
|
if (*remove_leading_whitespaces (end + 1))
|
|
|
|
fail ("%s: %d: malformed template purge\n", filename, lineno);
|
|
|
|
*end = '\0';
|
|
|
|
remove_trailing_whitespaces (buf);
|
|
|
|
/* Don't bother freeing the various structures. */
|
|
|
|
for (tmpl = templates; tmpl != NULL; tmpl = (prev = tmpl)->next)
|
|
|
|
if (!strcmp (buf, tmpl->name))
|
|
|
|
break;
|
|
|
|
if (tmpl == NULL)
|
|
|
|
fail ("%s: %d: no template '%s'\n", filename, lineno, buf);
|
|
|
|
if (prev)
|
|
|
|
prev->next = tmpl->next;
|
|
|
|
else
|
|
|
|
templates = tmpl->next;
|
2024-03-28 18:47:59 +08:00
|
|
|
return true;
|
2022-08-16 15:14:39 +08:00
|
|
|
}
|
2024-03-28 18:47:59 +08:00
|
|
|
|
|
|
|
/* Check whether this actually is a reference to an existing template:
|
|
|
|
If there's '>' ahead of ':', it can't be a new template definition
|
|
|
|
(and template undefs have are dealt with above). */
|
|
|
|
ptr = strchr (buf, '>');
|
|
|
|
if (ptr != NULL && ptr < end)
|
|
|
|
return false;
|
|
|
|
|
2020-03-09 17:12:14 +08:00
|
|
|
*end++ = '\0';
|
|
|
|
remove_trailing_whitespaces (buf);
|
|
|
|
|
|
|
|
if (*buf == '\0')
|
|
|
|
fail ("%s: %d: missing template identifier\n", filename, lineno);
|
2022-08-16 15:14:39 +08:00
|
|
|
tmpl = xmalloc (sizeof (*tmpl));
|
2020-03-09 17:12:14 +08:00
|
|
|
tmpl->name = xstrdup (buf);
|
|
|
|
|
|
|
|
tmpl->params = NULL;
|
|
|
|
do {
|
|
|
|
struct template_param *param;
|
|
|
|
|
|
|
|
buf = remove_leading_whitespaces (end);
|
|
|
|
end = strpbrk (buf, ":,");
|
|
|
|
if (end == NULL)
|
|
|
|
fail ("%s: %d: missing ':' or ','\n", filename, lineno);
|
|
|
|
|
|
|
|
sep = *end;
|
|
|
|
*end++ = '\0';
|
|
|
|
remove_trailing_whitespaces (buf);
|
|
|
|
|
|
|
|
param = xmalloc (sizeof (*param));
|
|
|
|
param->name = xstrdup (buf);
|
|
|
|
param->next = tmpl->params;
|
|
|
|
tmpl->params = param;
|
|
|
|
} while (sep == ':');
|
|
|
|
|
|
|
|
tmpl->instances = NULL;
|
|
|
|
do {
|
|
|
|
struct template_instance *inst;
|
|
|
|
char *cur, *next;
|
|
|
|
const struct template_param *param;
|
|
|
|
|
|
|
|
buf = remove_leading_whitespaces (end);
|
|
|
|
end = strpbrk (buf, ",>");
|
|
|
|
if (end == NULL)
|
|
|
|
fail ("%s: %d: missing ',' or '>'\n", filename, lineno);
|
|
|
|
|
|
|
|
sep = *end;
|
|
|
|
*end++ = '\0';
|
|
|
|
|
|
|
|
inst = xmalloc (sizeof (*inst));
|
2021-01-26 09:50:23 +08:00
|
|
|
inst->next = NULL;
|
|
|
|
inst->args = NULL;
|
2020-03-09 17:12:14 +08:00
|
|
|
|
|
|
|
cur = next_field (buf, ':', &next, end);
|
x86: fold SSE2AVX and their base MMX/SSE templates
This way not only the overall (source) table size shrinks by quite a
bit and the risk of related templates going out of sync with one another
gets lowered, but also (dis)similarities between neighboring templates
become easier to spot.
Note that for certain SSE2AVX templates this results in benign attribute
changes:
- LDMXCSR and STMXCSR: NoAVX gets set,
- MOVMSKPS, PMOVMSKB, PEXTR{B,W} (register destination), and PINSR{B,W}
(register source): IgnoreSize and NoRex64 get set,
- CVT{DQ,PS}2PD, CVTSD2SS, MOVMSKPD, MOVDDUP, PMOV{S,Z}X{BW,WD,DQ}, and
ROUNDSD: NoRex64 gets set,
- CVTSS2SD, INSERTPS, PEXTRW (memory destination), PINSRW (memory
source), and PMOV{S,Z}X{BD,WQ,BQ}: IgnoreSize gets set.
Similarly the "normal" (non-SSE2AVX)
- non-64-bit CVTS{I,S}2SD forms get NoRex64 set,
- CMP{EQ,ORD,NEQ,UNORD}{P,S}{S,D} forms get C set,
all again in a benign way.
The remaining differences in the generated table are due to re-ordering
of entries in the course of being folded into templates.
2021-03-29 18:05:25 +08:00
|
|
|
inst->name = *cur != '$' ? xstrdup (cur) : "";
|
2020-03-09 17:12:14 +08:00
|
|
|
|
|
|
|
for (param = tmpl->params; param; param = param->next)
|
|
|
|
{
|
|
|
|
struct template_arg *arg = xmalloc (sizeof (*arg));
|
|
|
|
|
|
|
|
cur = next_field (next, ':', &next, end);
|
|
|
|
if (next > end)
|
|
|
|
fail ("%s: %d: missing argument for '%s'\n", filename, lineno, param->name);
|
|
|
|
arg->val = xstrdup (cur);
|
|
|
|
arg->next = inst->args;
|
|
|
|
inst->args = arg;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (tmpl->instances)
|
|
|
|
last_inst->next = inst;
|
|
|
|
else
|
|
|
|
tmpl->instances = inst;
|
|
|
|
last_inst = inst;
|
|
|
|
} while (sep == ',');
|
|
|
|
|
|
|
|
buf = remove_leading_whitespaces (end);
|
|
|
|
if (*buf)
|
|
|
|
fprintf(stderr, "%s: %d: excess characters '%s'\n",
|
|
|
|
filename, lineno, buf);
|
|
|
|
|
|
|
|
tmpl->next = templates;
|
|
|
|
templates = tmpl;
|
2024-03-28 18:47:59 +08:00
|
|
|
|
|
|
|
return true;
|
2020-03-09 17:12:14 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static unsigned int
|
|
|
|
expand_templates (char *name, const char *str, htab_t opcode_hash_table,
|
|
|
|
struct opcode_hash_entry ***opcode_array_p, int lineno)
|
|
|
|
{
|
|
|
|
static unsigned int idx, opcode_array_size;
|
|
|
|
struct opcode_hash_entry **opcode_array = *opcode_array_p;
|
2023-01-20 17:18:40 +08:00
|
|
|
struct opcode_hash_entry **hash_slot;
|
|
|
|
struct opcode_entry *entry;
|
2020-03-09 17:12:14 +08:00
|
|
|
char *ptr1 = strchr(name, '<'), *ptr2;
|
|
|
|
|
|
|
|
if (ptr1 == NULL)
|
|
|
|
{
|
|
|
|
/* Get the slot in hash table. */
|
|
|
|
hash_slot = (struct opcode_hash_entry **)
|
|
|
|
htab_find_slot_with_hash (opcode_hash_table, name,
|
|
|
|
htab_hash_string (name),
|
|
|
|
INSERT);
|
|
|
|
|
|
|
|
if (*hash_slot == NULL)
|
|
|
|
{
|
|
|
|
/* It is the new one. Put it on opcode array. */
|
|
|
|
if (idx >= opcode_array_size)
|
|
|
|
{
|
|
|
|
/* Grow the opcode array when needed. */
|
|
|
|
opcode_array_size += 1024;
|
|
|
|
opcode_array = (struct opcode_hash_entry **)
|
|
|
|
xrealloc (opcode_array,
|
|
|
|
sizeof (*opcode_array) * opcode_array_size);
|
|
|
|
*opcode_array_p = opcode_array;
|
|
|
|
}
|
|
|
|
|
|
|
|
opcode_array[idx] = (struct opcode_hash_entry *)
|
|
|
|
xmalloc (sizeof (struct opcode_hash_entry));
|
|
|
|
opcode_array[idx]->name = xstrdup (name);
|
|
|
|
*hash_slot = opcode_array[idx];
|
2023-01-20 17:18:40 +08:00
|
|
|
entry = &opcode_array[idx]->entry;
|
2020-03-09 17:12:14 +08:00
|
|
|
idx++;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* Append it to the existing one. */
|
2023-01-20 17:18:40 +08:00
|
|
|
struct opcode_entry **entryp = &(*hash_slot)->entry.next;
|
|
|
|
|
|
|
|
while (*entryp != NULL)
|
|
|
|
entryp = &(*entryp)->next;
|
|
|
|
entry = (struct opcode_entry *)xmalloc (sizeof (struct opcode_entry));
|
|
|
|
*entryp = entry;
|
2020-03-09 17:12:14 +08:00
|
|
|
}
|
2023-01-20 17:18:40 +08:00
|
|
|
|
|
|
|
entry->next = NULL;
|
|
|
|
entry->opcode = xstrdup (str);
|
|
|
|
entry->lineno = lineno;
|
2020-03-09 17:12:14 +08:00
|
|
|
}
|
|
|
|
else if ((ptr2 = strchr(ptr1 + 1, '>')) == NULL)
|
|
|
|
fail ("%s: %d: missing '>'\n", filename, lineno);
|
|
|
|
else
|
|
|
|
{
|
|
|
|
const struct template *tmpl;
|
|
|
|
const struct template_instance *inst;
|
|
|
|
|
|
|
|
*ptr1 = '\0';
|
|
|
|
ptr1 = remove_leading_whitespaces (ptr1 + 1);
|
|
|
|
remove_trailing_whitespaces (ptr1);
|
|
|
|
|
|
|
|
*ptr2++ = '\0';
|
|
|
|
|
|
|
|
for ( tmpl = templates; tmpl; tmpl = tmpl->next )
|
|
|
|
if (!strcmp(ptr1, tmpl->name))
|
|
|
|
break;
|
|
|
|
if (!tmpl)
|
|
|
|
fail ("reference to unknown template '%s'\n", ptr1);
|
|
|
|
|
|
|
|
for (inst = tmpl->instances; inst; inst = inst->next)
|
|
|
|
{
|
|
|
|
char *name2 = xmalloc(strlen(name) + strlen(inst->name) + strlen(ptr2) + 1);
|
|
|
|
char *str2 = xmalloc(2 * strlen(str));
|
|
|
|
const char *src;
|
|
|
|
|
|
|
|
strcpy (name2, name);
|
|
|
|
strcat (name2, inst->name);
|
|
|
|
strcat (name2, ptr2);
|
|
|
|
|
|
|
|
for (ptr1 = str2, src = str; *src; )
|
|
|
|
{
|
|
|
|
const char *ident = tmpl->name, *end;
|
|
|
|
const struct template_param *param;
|
|
|
|
const struct template_arg *arg;
|
|
|
|
|
|
|
|
if ((*ptr1 = *src++) != '<')
|
|
|
|
{
|
|
|
|
++ptr1;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
while (ISSPACE(*src))
|
|
|
|
++src;
|
|
|
|
while (*ident && *src == *ident)
|
|
|
|
++src, ++ident;
|
|
|
|
while (ISSPACE(*src))
|
|
|
|
++src;
|
|
|
|
if (*src != ':' || *ident != '\0')
|
|
|
|
{
|
|
|
|
memcpy (++ptr1, tmpl->name, ident - tmpl->name);
|
|
|
|
ptr1 += ident - tmpl->name;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
while (ISSPACE(*++src))
|
|
|
|
;
|
|
|
|
|
|
|
|
end = src;
|
|
|
|
while (*end != '\0' && !ISSPACE(*end) && *end != '>')
|
|
|
|
++end;
|
|
|
|
|
|
|
|
for (param = tmpl->params, arg = inst->args; param;
|
|
|
|
param = param->next, arg = arg->next)
|
|
|
|
{
|
|
|
|
if (end - src == strlen (param->name)
|
|
|
|
&& !memcmp (src, param->name, end - src))
|
|
|
|
{
|
|
|
|
src = end;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (param == NULL)
|
|
|
|
fail ("template '%s' has no parameter '%.*s'\n",
|
|
|
|
tmpl->name, (int)(end - src), src);
|
|
|
|
|
|
|
|
while (ISSPACE(*src))
|
|
|
|
++src;
|
|
|
|
if (*src != '>')
|
|
|
|
fail ("%s: %d: missing '>'\n", filename, lineno);
|
|
|
|
|
|
|
|
memcpy(ptr1, arg->val, strlen(arg->val));
|
|
|
|
ptr1 += strlen(arg->val);
|
|
|
|
++src;
|
|
|
|
}
|
|
|
|
|
|
|
|
*ptr1 = '\0';
|
|
|
|
|
|
|
|
expand_templates (name2, str2, opcode_hash_table, opcode_array_p,
|
|
|
|
lineno);
|
|
|
|
|
|
|
|
free (str2);
|
|
|
|
free (name2);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return idx;
|
|
|
|
}
|
|
|
|
|
2023-01-20 17:16:17 +08:00
|
|
|
static int mnemonic_cmp(const void *p1, const void *p2)
|
|
|
|
{
|
|
|
|
const struct opcode_hash_entry *const *e1 = p1, *const *e2 = p2;
|
|
|
|
const char *s1 = (*e1)->name, *s2 = (*e2)->name;
|
|
|
|
unsigned int i;
|
|
|
|
size_t l1 = strlen (s1), l2 = strlen (s2);
|
|
|
|
|
|
|
|
for (i = 1; i <= l1 && i <= l2; ++i)
|
|
|
|
{
|
|
|
|
if (s1[l1 - i] != s2[l2 - i])
|
|
|
|
return (unsigned char)s1[l1 - i] - (unsigned char)s2[l2 - i];
|
|
|
|
}
|
|
|
|
|
|
|
|
return (int)(l1 - l2);
|
|
|
|
}
|
|
|
|
|
2007-06-28 22:29:56 +08:00
|
|
|
static void
|
2007-09-07 06:08:08 +08:00
|
|
|
process_i386_opcodes (FILE *table)
|
2007-06-28 22:29:56 +08:00
|
|
|
{
|
2008-01-09 05:24:16 +08:00
|
|
|
FILE *fp;
|
2007-06-28 22:29:56 +08:00
|
|
|
char buf[2048];
|
2023-01-20 17:15:48 +08:00
|
|
|
unsigned int i, j, nr, offs;
|
2023-01-20 17:16:17 +08:00
|
|
|
size_t l;
|
2023-01-20 17:18:40 +08:00
|
|
|
char *str, *p, *last;
|
2008-10-01 03:47:14 +08:00
|
|
|
htab_t opcode_hash_table;
|
2020-03-09 17:12:14 +08:00
|
|
|
struct opcode_hash_entry **opcode_array = NULL;
|
2018-07-19 14:28:29 +08:00
|
|
|
int lineno = 0, marker = 0;
|
2007-06-28 22:29:56 +08:00
|
|
|
|
2008-01-09 05:24:16 +08:00
|
|
|
filename = "i386-opc.tbl";
|
2018-07-19 14:28:29 +08:00
|
|
|
fp = stdin;
|
2007-06-28 22:29:56 +08:00
|
|
|
|
2008-10-01 03:47:14 +08:00
|
|
|
i = 0;
|
|
|
|
opcode_hash_table = htab_create_alloc (16, opcode_hash_hash,
|
|
|
|
opcode_hash_eq, NULL,
|
|
|
|
xcalloc, free);
|
|
|
|
|
2023-01-20 17:15:48 +08:00
|
|
|
fprintf (table, "\n#include \"i386-mnem.h\"\n");
|
2007-09-07 05:31:55 +08:00
|
|
|
fprintf (table, "\n/* i386 opcode table. */\n\n");
|
2022-12-12 15:46:47 +08:00
|
|
|
fprintf (table, "static const insn_template i386_optab[] =\n{\n");
|
2007-06-28 22:29:56 +08:00
|
|
|
|
2008-10-01 03:47:14 +08:00
|
|
|
/* Put everything on opcode array. */
|
2007-06-28 22:29:56 +08:00
|
|
|
while (!feof (fp))
|
|
|
|
{
|
2023-01-20 17:18:40 +08:00
|
|
|
char *name;
|
|
|
|
|
2007-06-28 22:29:56 +08:00
|
|
|
if (fgets (buf, sizeof (buf), fp) == NULL)
|
|
|
|
break;
|
|
|
|
|
|
|
|
p = remove_leading_whitespaces (buf);
|
|
|
|
|
2022-08-16 15:11:18 +08:00
|
|
|
for ( ; ; )
|
|
|
|
{
|
|
|
|
lineno++;
|
|
|
|
|
|
|
|
/* Skip comments. */
|
|
|
|
str = strstr (p, "//");
|
|
|
|
if (str != NULL)
|
|
|
|
{
|
|
|
|
str[0] = '\0';
|
|
|
|
remove_trailing_whitespaces (p);
|
|
|
|
break;
|
|
|
|
}
|
2007-06-28 22:29:56 +08:00
|
|
|
|
2022-08-16 15:11:18 +08:00
|
|
|
/* Look for line continuation character. */
|
|
|
|
remove_trailing_whitespaces (p);
|
|
|
|
j = strlen (buf);
|
|
|
|
if (!j || buf[j - 1] != '+')
|
|
|
|
break;
|
|
|
|
if (j >= sizeof (buf) - 1)
|
2023-01-27 16:20:26 +08:00
|
|
|
fail ("%s: %d: (continued) line too long\n", filename, lineno);
|
2022-08-16 15:11:18 +08:00
|
|
|
|
|
|
|
if (fgets (buf + j - 1, sizeof (buf) - j + 1, fp) == NULL)
|
|
|
|
{
|
|
|
|
fprintf (stderr, "%s: Line continuation on last line?\n",
|
|
|
|
filename);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2007-06-28 22:29:56 +08:00
|
|
|
|
|
|
|
switch (p[0])
|
|
|
|
{
|
|
|
|
case '#':
|
2018-07-19 14:28:29 +08:00
|
|
|
if (!strcmp("### MARKER ###", buf))
|
|
|
|
marker = 1;
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* Since we ignore all included files (we only care about their
|
|
|
|
#define-s here), we don't need to monitor filenames. The final
|
|
|
|
line number directive is going to refer to the main source file
|
|
|
|
again. */
|
|
|
|
char *end;
|
|
|
|
unsigned long ln;
|
|
|
|
|
|
|
|
p = remove_leading_whitespaces (p + 1);
|
|
|
|
if (!strncmp(p, "line", 4))
|
|
|
|
p += 4;
|
|
|
|
ln = strtoul (p, &end, 10);
|
|
|
|
if (ln > 1 && ln < INT_MAX
|
|
|
|
&& *remove_leading_whitespaces (end) == '"')
|
|
|
|
lineno = ln - 1;
|
|
|
|
}
|
2008-10-01 03:47:14 +08:00
|
|
|
/* Ignore comments. */
|
2007-06-28 22:29:56 +08:00
|
|
|
case '\0':
|
|
|
|
continue;
|
2024-03-28 18:47:59 +08:00
|
|
|
|
2020-03-09 17:12:14 +08:00
|
|
|
case '<':
|
2024-03-28 18:47:59 +08:00
|
|
|
if (parse_template (p, lineno))
|
|
|
|
continue;
|
|
|
|
break;
|
|
|
|
|
2007-06-28 22:29:56 +08:00
|
|
|
default:
|
2018-07-19 14:28:29 +08:00
|
|
|
if (!marker)
|
|
|
|
continue;
|
2007-06-28 22:29:56 +08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
last = p + strlen (p);
|
|
|
|
|
|
|
|
/* Find name. */
|
2008-10-01 03:47:14 +08:00
|
|
|
name = next_field (p, ',', &str, last);
|
2007-06-28 22:29:56 +08:00
|
|
|
|
2020-03-09 17:12:14 +08:00
|
|
|
i = expand_templates (name, str, opcode_hash_table, &opcode_array,
|
|
|
|
lineno);
|
2008-10-01 03:47:14 +08:00
|
|
|
}
|
2007-06-28 22:29:56 +08:00
|
|
|
|
2008-10-01 03:47:14 +08:00
|
|
|
/* Process opcode array. */
|
|
|
|
for (j = 0; j < i; j++)
|
|
|
|
{
|
2023-01-20 17:18:40 +08:00
|
|
|
const char *name = opcode_array[j]->name;
|
|
|
|
struct opcode_entry *next;
|
2020-03-09 17:12:14 +08:00
|
|
|
|
2023-01-20 17:18:40 +08:00
|
|
|
for (next = &opcode_array[j]->entry; next; next = next->next)
|
2008-10-01 03:47:14 +08:00
|
|
|
{
|
|
|
|
str = next->opcode;
|
gas/
2009-01-10 H.J. Lu <hongjiu.lu@intel.com>
* gas/config/tc-i386.c (cpu_arch): Add corei7, .clflush and
.syscall.
(i386_align_code): Handle PROCESSOR_COREI7.
(md_show_usage): Add corei7, clflush and syscall.
(i386_target_format): Replace cpup4 with cpuclflush.
* gas/config/tc-i386.h (processor_type): Add PROCESSOR_COREI7.
* doc/c-i386.texi: Document corei7, clflush and syscall.
gas/testsuite/
2009-01-10 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/arch-10.s: Add clflush and syscall.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/arch-10.d: Updated.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
opcodes/
2009-01-10 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (cpu_flag_init): Replace CpuP4 and CpuK6 with
CpuClflush and CpuSYSCALL, respectively. Remove CpuK8. Add
CPU_COREI7_FLAGS, CPU_CLFLUSH_FLAGS and CPU_SYSCALL_FLAGS.
(cpu_flags): Remove CpuP4, CpuK6 and CpuK8. Add CpuClflush
and CpuSYSCALL.
(lineno): Removed.
(set_bitfield): Take an argument, lineno. Don't report lineno
on error if it is -1.
(process_i386_cpu_flag): Take an argument, lineno.
(process_i386_opcode_modifier): Likewise.
(process_i386_operand_type): Likewise.
(output_i386_opcode): Likewise.
(opcode_hash_entry): Add lineno.
(process_i386_opcodes): Updated.
(process_i386_registers): Likewise.
(process_i386_initializers): Likewise.
* i386-opc.h (CpuP4): Removed.
(CpuK6): Likewise.
(CpuK8): Likewise.
(CpuClflush): New.
(CpuSYSCALL): Likewise.
(CpuMMX): Updated.
(i386_cpu_flags): Remove cpup4, cpuk6 and cpuk8. Add
cpuclflush and cpusyscall.
* i386-opc.tbl: Update movnti, clflush, lfence, mfence, pause,
syscall and sysret.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2009-01-11 01:25:52 +08:00
|
|
|
lineno = next->lineno;
|
2008-10-01 03:47:14 +08:00
|
|
|
last = str + strlen (str);
|
gas/
2009-01-10 H.J. Lu <hongjiu.lu@intel.com>
* gas/config/tc-i386.c (cpu_arch): Add corei7, .clflush and
.syscall.
(i386_align_code): Handle PROCESSOR_COREI7.
(md_show_usage): Add corei7, clflush and syscall.
(i386_target_format): Replace cpup4 with cpuclflush.
* gas/config/tc-i386.h (processor_type): Add PROCESSOR_COREI7.
* doc/c-i386.texi: Document corei7, clflush and syscall.
gas/testsuite/
2009-01-10 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/arch-10.s: Add clflush and syscall.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/arch-10.d: Updated.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
opcodes/
2009-01-10 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (cpu_flag_init): Replace CpuP4 and CpuK6 with
CpuClflush and CpuSYSCALL, respectively. Remove CpuK8. Add
CPU_COREI7_FLAGS, CPU_CLFLUSH_FLAGS and CPU_SYSCALL_FLAGS.
(cpu_flags): Remove CpuP4, CpuK6 and CpuK8. Add CpuClflush
and CpuSYSCALL.
(lineno): Removed.
(set_bitfield): Take an argument, lineno. Don't report lineno
on error if it is -1.
(process_i386_cpu_flag): Take an argument, lineno.
(process_i386_opcode_modifier): Likewise.
(process_i386_operand_type): Likewise.
(output_i386_opcode): Likewise.
(opcode_hash_entry): Add lineno.
(process_i386_opcodes): Updated.
(process_i386_registers): Likewise.
(process_i386_initializers): Likewise.
* i386-opc.h (CpuP4): Removed.
(CpuK6): Likewise.
(CpuK8): Likewise.
(CpuClflush): New.
(CpuSYSCALL): Likewise.
(CpuMMX): Updated.
(i386_cpu_flags): Remove cpup4, cpuk6 and cpuk8. Add
cpuclflush and cpusyscall.
* i386-opc.tbl: Update movnti, clflush, lfence, mfence, pause,
syscall and sysret.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2009-01-11 01:25:52 +08:00
|
|
|
output_i386_opcode (table, name, str, last, lineno);
|
2007-06-28 22:29:56 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-09-07 05:31:55 +08:00
|
|
|
fclose (fp);
|
|
|
|
|
|
|
|
fprintf (table, "};\n");
|
2022-12-12 15:49:26 +08:00
|
|
|
|
|
|
|
/* Generate opcode sets array. */
|
|
|
|
fprintf (table, "\n/* i386 opcode sets table. */\n\n");
|
2023-11-24 16:55:51 +08:00
|
|
|
fprintf (table, "typedef unsigned short i386_op_off_t;\n");
|
|
|
|
fprintf (table, "static const i386_op_off_t i386_op_sets[] =\n{\n ");
|
2022-12-12 15:49:26 +08:00
|
|
|
|
|
|
|
for (nr = j = 0; j < i; j++)
|
|
|
|
{
|
2023-01-20 17:18:40 +08:00
|
|
|
struct opcode_entry *next = &opcode_array[j]->entry;
|
2022-12-12 15:49:26 +08:00
|
|
|
|
2023-11-24 16:55:51 +08:00
|
|
|
if ((j + 1) % 8 != 0)
|
|
|
|
fprintf (table, "%5u,", nr);
|
|
|
|
else
|
|
|
|
fprintf (table, "%5u,\n ", nr);
|
2022-12-12 15:49:26 +08:00
|
|
|
do
|
|
|
|
{
|
|
|
|
++nr;
|
|
|
|
next = next->next;
|
|
|
|
}
|
|
|
|
while (next);
|
|
|
|
}
|
|
|
|
|
2023-11-24 16:55:51 +08:00
|
|
|
fprintf (table, "%5u\n};\n", nr);
|
2023-01-20 17:15:48 +08:00
|
|
|
|
|
|
|
/* Emit mnemonics and associated #define-s. */
|
2023-01-20 17:16:17 +08:00
|
|
|
qsort (opcode_array, i, sizeof (*opcode_array), mnemonic_cmp);
|
|
|
|
|
2023-01-20 17:15:48 +08:00
|
|
|
fp = fopen ("i386-mnem.h", "w");
|
|
|
|
if (fp == NULL)
|
2023-01-27 16:20:26 +08:00
|
|
|
fail ("can't create i386-mnem.h, errno = %s\n",
|
2023-01-20 17:15:48 +08:00
|
|
|
xstrerror (errno));
|
|
|
|
|
|
|
|
process_copyright (fp);
|
|
|
|
|
|
|
|
fprintf (table, "\n/* i386 mnemonics table. */\n\n");
|
|
|
|
fprintf (table, "const char i386_mnemonics[] =\n");
|
|
|
|
fprintf (fp, "\nextern const char i386_mnemonics[];\n\n");
|
|
|
|
|
2023-01-20 17:16:56 +08:00
|
|
|
str = NULL;
|
2023-01-20 17:16:17 +08:00
|
|
|
for (l = strlen (opcode_array[offs = j = 0]->name); j < i; j++)
|
2023-01-20 17:15:48 +08:00
|
|
|
{
|
2023-01-20 17:18:40 +08:00
|
|
|
const char *name = opcode_array[j]->name;
|
2023-01-20 17:16:17 +08:00
|
|
|
const char *next = NULL;
|
|
|
|
size_t l1 = j + 1 < i ? strlen(next = opcode_array[j + 1]->name) : 0;
|
|
|
|
|
2023-01-20 17:16:56 +08:00
|
|
|
if (str == NULL)
|
|
|
|
str = mkident (name);
|
2023-01-20 17:16:17 +08:00
|
|
|
if (l < l1 && !strcmp(name, next + l1 - l))
|
|
|
|
{
|
|
|
|
fprintf (fp, "#define MN_%s ", str);
|
|
|
|
free (str);
|
|
|
|
str = mkident (next);
|
2023-08-26 09:47:47 +08:00
|
|
|
fprintf (fp, "(MN_%s + %zu)\n", str, l1 - l);
|
2023-01-20 17:16:17 +08:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
fprintf (table, " \"\\0\"\"%s\"\n", name);
|
|
|
|
fprintf (fp, "#define MN_%s %#x\n", str, offs + 1);
|
|
|
|
offs += strlen (name) + 1;
|
2023-01-20 17:16:56 +08:00
|
|
|
free (str);
|
|
|
|
str = NULL;
|
2023-01-20 17:16:17 +08:00
|
|
|
}
|
|
|
|
l = l1;
|
2023-01-20 17:15:48 +08:00
|
|
|
}
|
|
|
|
|
2023-03-31 14:18:58 +08:00
|
|
|
fprintf (table, " \"\\0\"\".insn\"\n");
|
|
|
|
fprintf (fp, "#define MN__insn %#x\n", offs + 1);
|
|
|
|
|
2023-01-20 17:15:48 +08:00
|
|
|
fprintf (table, ";\n");
|
|
|
|
|
|
|
|
fclose (fp);
|
2007-06-28 22:29:56 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2007-09-07 06:08:08 +08:00
|
|
|
process_i386_registers (FILE *table)
|
2007-06-28 22:29:56 +08:00
|
|
|
{
|
2008-01-09 05:24:16 +08:00
|
|
|
FILE *fp;
|
2007-06-28 22:29:56 +08:00
|
|
|
char buf[2048];
|
|
|
|
char *str, *p, *last;
|
|
|
|
char *reg_name, *reg_type, *reg_flags, *reg_num;
|
2008-02-13 18:14:40 +08:00
|
|
|
char *dw2_32_num, *dw2_64_num;
|
gas/
2009-01-10 H.J. Lu <hongjiu.lu@intel.com>
* gas/config/tc-i386.c (cpu_arch): Add corei7, .clflush and
.syscall.
(i386_align_code): Handle PROCESSOR_COREI7.
(md_show_usage): Add corei7, clflush and syscall.
(i386_target_format): Replace cpup4 with cpuclflush.
* gas/config/tc-i386.h (processor_type): Add PROCESSOR_COREI7.
* doc/c-i386.texi: Document corei7, clflush and syscall.
gas/testsuite/
2009-01-10 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/arch-10.s: Add clflush and syscall.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/arch-10.d: Updated.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
opcodes/
2009-01-10 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (cpu_flag_init): Replace CpuP4 and CpuK6 with
CpuClflush and CpuSYSCALL, respectively. Remove CpuK8. Add
CPU_COREI7_FLAGS, CPU_CLFLUSH_FLAGS and CPU_SYSCALL_FLAGS.
(cpu_flags): Remove CpuP4, CpuK6 and CpuK8. Add CpuClflush
and CpuSYSCALL.
(lineno): Removed.
(set_bitfield): Take an argument, lineno. Don't report lineno
on error if it is -1.
(process_i386_cpu_flag): Take an argument, lineno.
(process_i386_opcode_modifier): Likewise.
(process_i386_operand_type): Likewise.
(output_i386_opcode): Likewise.
(opcode_hash_entry): Add lineno.
(process_i386_opcodes): Updated.
(process_i386_registers): Likewise.
(process_i386_initializers): Likewise.
* i386-opc.h (CpuP4): Removed.
(CpuK6): Likewise.
(CpuK8): Likewise.
(CpuClflush): New.
(CpuSYSCALL): Likewise.
(CpuMMX): Updated.
(i386_cpu_flags): Remove cpup4, cpuk6 and cpuk8. Add
cpuclflush and cpusyscall.
* i386-opc.tbl: Update movnti, clflush, lfence, mfence, pause,
syscall and sysret.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2009-01-11 01:25:52 +08:00
|
|
|
int lineno = 0;
|
2007-06-28 22:29:56 +08:00
|
|
|
|
2008-01-09 05:24:16 +08:00
|
|
|
filename = "i386-reg.tbl";
|
|
|
|
fp = fopen (filename, "r");
|
2007-06-28 22:29:56 +08:00
|
|
|
if (fp == NULL)
|
2023-01-27 16:20:26 +08:00
|
|
|
fail ("can't find i386-reg.tbl for reading, errno = %s\n",
|
2007-09-09 09:22:57 +08:00
|
|
|
xstrerror (errno));
|
2007-06-28 22:29:56 +08:00
|
|
|
|
2007-09-07 05:31:55 +08:00
|
|
|
fprintf (table, "\n/* i386 register table. */\n\n");
|
2022-12-12 15:46:47 +08:00
|
|
|
fprintf (table, "static const reg_entry i386_regtab[] =\n{\n");
|
2007-06-28 22:29:56 +08:00
|
|
|
|
|
|
|
while (!feof (fp))
|
|
|
|
{
|
|
|
|
if (fgets (buf, sizeof (buf), fp) == NULL)
|
|
|
|
break;
|
|
|
|
|
2008-01-09 05:24:16 +08:00
|
|
|
lineno++;
|
|
|
|
|
2007-06-28 22:29:56 +08:00
|
|
|
p = remove_leading_whitespaces (buf);
|
|
|
|
|
|
|
|
/* Skip comments. */
|
|
|
|
str = strstr (p, "//");
|
|
|
|
if (str != NULL)
|
|
|
|
str[0] = '\0';
|
|
|
|
|
|
|
|
/* Remove trailing white spaces. */
|
|
|
|
remove_trailing_whitespaces (p);
|
|
|
|
|
|
|
|
switch (p[0])
|
|
|
|
{
|
|
|
|
case '#':
|
2007-09-07 05:31:55 +08:00
|
|
|
fprintf (table, "%s\n", p);
|
2007-06-28 22:29:56 +08:00
|
|
|
case '\0':
|
|
|
|
continue;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
last = p + strlen (p);
|
|
|
|
|
|
|
|
/* Find reg_name. */
|
2008-10-01 03:47:14 +08:00
|
|
|
reg_name = next_field (p, ',', &str, last);
|
2007-06-28 22:29:56 +08:00
|
|
|
|
|
|
|
/* Find reg_type. */
|
2008-10-01 03:47:14 +08:00
|
|
|
reg_type = next_field (str, ',', &str, last);
|
2007-06-28 22:29:56 +08:00
|
|
|
|
|
|
|
/* Find reg_flags. */
|
2008-10-01 03:47:14 +08:00
|
|
|
reg_flags = next_field (str, ',', &str, last);
|
2007-06-28 22:29:56 +08:00
|
|
|
|
|
|
|
/* Find reg_num. */
|
2008-10-01 03:47:14 +08:00
|
|
|
reg_num = next_field (str, ',', &str, last);
|
2008-02-13 18:14:40 +08:00
|
|
|
|
2007-09-09 09:22:57 +08:00
|
|
|
fprintf (table, " { \"%s\",\n ", reg_name);
|
|
|
|
|
2017-11-30 18:48:13 +08:00
|
|
|
process_i386_operand_type (table, reg_type, stage_registers, "\t",
|
|
|
|
lineno);
|
2007-09-09 09:22:57 +08:00
|
|
|
|
2008-02-13 18:14:40 +08:00
|
|
|
/* Find 32-bit Dwarf2 register number. */
|
2008-10-01 03:47:14 +08:00
|
|
|
dw2_32_num = next_field (str, ',', &str, last);
|
2008-02-13 18:14:40 +08:00
|
|
|
|
|
|
|
/* Find 64-bit Dwarf2 register number. */
|
2008-10-01 03:47:14 +08:00
|
|
|
dw2_64_num = next_field (str, ',', &str, last);
|
2008-02-13 18:14:40 +08:00
|
|
|
|
|
|
|
fprintf (table, ",\n %s, %s, { %s, %s } },\n",
|
|
|
|
reg_flags, reg_num, dw2_32_num, dw2_64_num);
|
2007-06-28 22:29:56 +08:00
|
|
|
}
|
|
|
|
|
2007-09-07 05:31:55 +08:00
|
|
|
fclose (fp);
|
|
|
|
|
|
|
|
fprintf (table, "};\n");
|
2007-06-28 22:29:56 +08:00
|
|
|
|
2022-12-12 15:46:47 +08:00
|
|
|
fprintf (table, "\nstatic const unsigned int i386_regtab_size = ARRAY_SIZE (i386_regtab);\n");
|
2007-06-28 22:29:56 +08:00
|
|
|
}
|
|
|
|
|
2007-09-09 09:22:57 +08:00
|
|
|
static void
|
|
|
|
process_i386_initializers (void)
|
|
|
|
{
|
|
|
|
unsigned int i;
|
|
|
|
FILE *fp = fopen ("i386-init.h", "w");
|
|
|
|
|
|
|
|
if (fp == NULL)
|
2023-01-27 16:20:26 +08:00
|
|
|
fail ("can't create i386-init.h, errno = %s\n",
|
2007-09-09 09:22:57 +08:00
|
|
|
xstrerror (errno));
|
|
|
|
|
|
|
|
process_copyright (fp);
|
|
|
|
|
2023-09-15 15:57:05 +08:00
|
|
|
for (i = 0; i < CpuMax; i++)
|
2022-12-22 16:32:29 +08:00
|
|
|
process_i386_cpu_flag (fp, "0", cpu_flags[i].name, "", " ", -1, i);
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE (isa_dependencies); i++)
|
|
|
|
{
|
|
|
|
char *deps = xstrdup (isa_dependencies[i].deps);
|
|
|
|
|
|
|
|
process_i386_cpu_flag (fp, deps, isa_dependencies[i].name,
|
|
|
|
"", " ", -1, CpuMax);
|
|
|
|
free (deps);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Early x87 is somewhat special: Both 287 and 387 not only add new insns
|
|
|
|
but also remove some. Hence 8087 isn't a prereq to 287, and 287 isn't
|
|
|
|
one to 387. We want the reverse to be true though: Disabling 8087 also
|
|
|
|
is to disable 287+ and later; disabling 287 also means disabling 387+. */
|
|
|
|
memcpy (isa_reverse_deps[Cpu287], isa_reverse_deps[Cpu387],
|
|
|
|
sizeof (isa_reverse_deps[0]));
|
|
|
|
isa_reverse_deps[Cpu287][Cpu387] = 1;
|
|
|
|
memcpy (isa_reverse_deps[Cpu8087], isa_reverse_deps[Cpu287],
|
|
|
|
sizeof (isa_reverse_deps[0]));
|
|
|
|
isa_reverse_deps[Cpu8087][Cpu287] = 1;
|
|
|
|
|
|
|
|
/* While we treat POPCNT as a prereq to SSE4.2, its disabling should not
|
|
|
|
lead to disabling of anything else. */
|
|
|
|
memset (isa_reverse_deps[CpuPOPCNT], 0, sizeof (isa_reverse_deps[0]));
|
|
|
|
|
|
|
|
for (i = Cpu686 + 1; i < ARRAY_SIZE (isa_reverse_deps); i++)
|
2007-09-09 09:22:57 +08:00
|
|
|
{
|
2022-12-22 16:32:29 +08:00
|
|
|
size_t len;
|
|
|
|
char *upper;
|
|
|
|
|
|
|
|
if (memchr(isa_reverse_deps[i], 1,
|
|
|
|
ARRAY_SIZE (isa_reverse_deps[0])) == NULL)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
isa_reverse_deps[i][i] = 1;
|
|
|
|
process_i386_cpu_flag (fp, NULL, cpu_flags[i].name, "", " ", -1, i);
|
2007-09-09 09:22:57 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
fprintf (fp, "\n");
|
|
|
|
|
|
|
|
fclose (fp);
|
|
|
|
}
|
|
|
|
|
2007-06-28 22:29:56 +08:00
|
|
|
/* Program options. */
|
|
|
|
#define OPTION_SRCDIR 200
|
|
|
|
|
2012-06-23 00:42:08 +08:00
|
|
|
struct option long_options[] =
|
2007-06-28 22:29:56 +08:00
|
|
|
{
|
|
|
|
{"srcdir", required_argument, NULL, OPTION_SRCDIR},
|
|
|
|
{"debug", no_argument, NULL, 'd'},
|
|
|
|
{"version", no_argument, NULL, 'V'},
|
|
|
|
{"help", no_argument, NULL, 'h'},
|
|
|
|
{0, no_argument, NULL, 0}
|
|
|
|
};
|
|
|
|
|
|
|
|
static void
|
|
|
|
print_version (void)
|
|
|
|
{
|
|
|
|
printf ("%s: version 1.0\n", program_name);
|
|
|
|
xexit (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
usage (FILE * stream, int status)
|
|
|
|
{
|
|
|
|
fprintf (stream, "Usage: %s [-V | --version] [-d | --debug] [--srcdir=dirname] [--help]\n",
|
|
|
|
program_name);
|
|
|
|
xexit (status);
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
main (int argc, char **argv)
|
|
|
|
{
|
|
|
|
extern int chdir (char *);
|
|
|
|
char *srcdir = NULL;
|
2007-09-10 00:02:17 +08:00
|
|
|
int c;
|
2016-05-27 23:02:56 +08:00
|
|
|
unsigned int i, cpumax;
|
2007-09-07 06:08:08 +08:00
|
|
|
FILE *table;
|
2012-06-23 00:42:08 +08:00
|
|
|
|
2007-06-28 22:29:56 +08:00
|
|
|
program_name = *argv;
|
|
|
|
xmalloc_set_program_name (program_name);
|
|
|
|
|
|
|
|
while ((c = getopt_long (argc, argv, "vVdh", long_options, 0)) != EOF)
|
|
|
|
switch (c)
|
|
|
|
{
|
|
|
|
case OPTION_SRCDIR:
|
|
|
|
srcdir = optarg;
|
|
|
|
break;
|
|
|
|
case 'V':
|
|
|
|
case 'v':
|
|
|
|
print_version ();
|
|
|
|
break;
|
|
|
|
case 'd':
|
|
|
|
debug = 1;
|
|
|
|
break;
|
|
|
|
case 'h':
|
|
|
|
case '?':
|
|
|
|
usage (stderr, 0);
|
|
|
|
default:
|
|
|
|
case 0:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (optind != argc)
|
|
|
|
usage (stdout, 1);
|
|
|
|
|
2012-06-23 00:42:08 +08:00
|
|
|
if (srcdir != NULL)
|
2007-06-28 22:29:56 +08:00
|
|
|
if (chdir (srcdir) != 0)
|
2023-01-27 16:20:26 +08:00
|
|
|
fail ("unable to change directory to \"%s\", errno = %s\n",
|
2007-09-09 09:22:57 +08:00
|
|
|
srcdir, xstrerror (errno));
|
|
|
|
|
2016-05-27 23:02:56 +08:00
|
|
|
/* cpu_flags isn't sorted by position. */
|
|
|
|
cpumax = 0;
|
|
|
|
for (i = 0; i < ARRAY_SIZE (cpu_flags); i++)
|
|
|
|
if (cpu_flags[i].position > cpumax)
|
|
|
|
cpumax = cpu_flags[i].position;
|
|
|
|
|
2007-09-09 09:22:57 +08:00
|
|
|
/* Check the unused bitfield in i386_cpu_flags. */
|
2016-05-27 21:55:42 +08:00
|
|
|
#ifdef CpuUnused
|
2019-07-17 15:15:49 +08:00
|
|
|
static_assert (ARRAY_SIZE (cpu_flags) == CpuMax + 2);
|
|
|
|
|
2016-05-27 23:02:56 +08:00
|
|
|
if ((cpumax - 1) != CpuMax)
|
2023-01-27 16:20:26 +08:00
|
|
|
fail ("CpuMax != %d!\n", cpumax);
|
2016-05-27 21:55:42 +08:00
|
|
|
#else
|
2019-07-17 15:15:49 +08:00
|
|
|
static_assert (ARRAY_SIZE (cpu_flags) == CpuMax + 1);
|
|
|
|
|
2016-05-27 23:02:56 +08:00
|
|
|
if (cpumax != CpuMax)
|
2023-01-27 16:20:26 +08:00
|
|
|
fail ("CpuMax != %d!\n", cpumax);
|
2016-05-27 21:55:42 +08:00
|
|
|
|
2007-09-10 00:02:17 +08:00
|
|
|
c = CpuNumOfBits - CpuMax - 1;
|
|
|
|
if (c)
|
2023-01-27 16:20:26 +08:00
|
|
|
fail ("%d unused bits in i386_cpu_flags.\n", c);
|
2023-08-11 16:04:49 +08:00
|
|
|
#endif
|
|
|
|
|
|
|
|
/* If this triggers, CpuIsaBits needs to be increased. */
|
|
|
|
static_assert (CpuAttrEnums <= (1u << CpuIsaBits));
|
|
|
|
|
|
|
|
/* Check the unused bitfield in i386_cpu_attr. */
|
|
|
|
#ifndef CpuAttrUnused
|
|
|
|
c = CpuAttrNumOfBits - (CpuIsaBits + CpuMax + 1 - CpuAttrEnums);
|
|
|
|
if (c)
|
|
|
|
fail ("%d unused bits in i386_cpu_attr.\n", c);
|
2007-09-09 09:22:57 +08:00
|
|
|
#endif
|
|
|
|
|
2019-07-17 15:15:49 +08:00
|
|
|
static_assert (ARRAY_SIZE (opcode_modifiers) == Opcode_Modifier_Num);
|
|
|
|
|
2007-09-09 09:22:57 +08:00
|
|
|
/* Check the unused bitfield in i386_operand_type. */
|
2019-07-17 15:15:49 +08:00
|
|
|
#ifdef OTUnused
|
2019-11-12 16:07:34 +08:00
|
|
|
static_assert (ARRAY_SIZE (operand_types) + CLASS_WIDTH + INSTANCE_WIDTH
|
|
|
|
== OTNum + 1);
|
2019-07-17 15:15:49 +08:00
|
|
|
#else
|
2019-11-12 16:07:34 +08:00
|
|
|
static_assert (ARRAY_SIZE (operand_types) + CLASS_WIDTH + INSTANCE_WIDTH
|
|
|
|
== OTNum);
|
2019-07-17 15:15:49 +08:00
|
|
|
|
2019-11-12 16:09:31 +08:00
|
|
|
c = OTNumOfBits - OTNum;
|
2007-09-10 00:02:17 +08:00
|
|
|
if (c)
|
2023-01-27 16:20:26 +08:00
|
|
|
fail ("%d unused bits in i386_operand_type.\n", c);
|
2007-09-09 09:22:57 +08:00
|
|
|
#endif
|
|
|
|
|
|
|
|
qsort (cpu_flags, ARRAY_SIZE (cpu_flags), sizeof (cpu_flags [0]),
|
|
|
|
compare);
|
|
|
|
|
|
|
|
qsort (opcode_modifiers, ARRAY_SIZE (opcode_modifiers),
|
|
|
|
sizeof (opcode_modifiers [0]), compare);
|
|
|
|
|
|
|
|
qsort (operand_types, ARRAY_SIZE (operand_types),
|
|
|
|
sizeof (operand_types [0]), compare);
|
2007-06-28 22:29:56 +08:00
|
|
|
|
2023-11-09 19:54:23 +08:00
|
|
|
process_i386_initializers ();
|
|
|
|
|
2007-09-07 05:31:55 +08:00
|
|
|
table = fopen ("i386-tbl.h", "w");
|
|
|
|
if (table == NULL)
|
2023-01-27 16:20:26 +08:00
|
|
|
fail ("can't create i386-tbl.h, errno = %s\n",
|
2007-09-09 09:22:57 +08:00
|
|
|
xstrerror (errno));
|
2007-09-07 05:31:55 +08:00
|
|
|
|
2007-09-07 06:08:08 +08:00
|
|
|
process_copyright (table);
|
2007-06-28 22:29:56 +08:00
|
|
|
|
2007-09-07 06:08:08 +08:00
|
|
|
process_i386_opcodes (table);
|
|
|
|
process_i386_registers (table);
|
2007-06-28 22:29:56 +08:00
|
|
|
|
2007-09-07 05:31:55 +08:00
|
|
|
fclose (table);
|
|
|
|
|
2007-06-28 22:29:56 +08:00
|
|
|
exit (0);
|
|
|
|
}
|