2018-09-06 11:21:51 +08:00
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2018-09-05 Simon Marchi <simon.marchi@ericsson.com>
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* diagnostics.h (DIAGNOSTIC_IGNORE_FORMAT_NONLITERAL): New macro.
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PowerPC64 higher REL16 relocations
There are occasions where someone might want to build a 64-bit
pc-relative offset from 16-bit pieces. This adds the necessary REL16
relocs corresponding to existing ADDR16 relocs that can be used to
build 64-bit absolute values.
include/
* elf/ppc64.h (R_PPC64_REL16_HIGH, R_PPC64_REL16_HIGHA),
(R_PPC64_REL16_HIGHER, R_PPC64_REL16_HIGHERA),
(R_PPC64_REL16_HIGHEST, R_PPC64_REL16_HIGHESTA): Define.
(R_PPC64_LO_DS_OPT, R_PPC64_16DX_HA): Bump value.
bfd/
* reloc.c (BFD_RELOC_PPC64_REL16_HIGH, BFD_RELOC_PPC64_REL16_HIGHA),
(BFD_RELOC_PPC64_REL16_HIGHER, BFD_RELOC_PPC64_REL16_HIGHERA),
(BFD_RELOC_PPC64_REL16_HIGHEST, BFD_RELOC_PPC64_REL16_HIGHESTA):
Define.
* elf64-ppc.c (ppc64_elf_howto_raw): Add new REL16 howtos.
(ppc64_elf_reloc_type_lookup): Translate new REL16 relocs.
(ppc64_elf_check_relocs, ppc64_elf_relocate_section): Handle them.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
gas/
* config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): Allow ADDR16
HIGH, HIGHA, HIGHER, HIGHERA, HIGHEST, and HIGHESTA relocs.
Group 16-bit relocs.
* config/tc-ppc.c (md_apply_fix): Translate those ADDR16 relocs
to REL16 when pcrel. Sort relocs.
2018-08-29 11:58:21 +08:00
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2018-08-31 Alan Modra <amodra@gmail.com>
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* elf/ppc64.h (R_PPC64_REL16_HIGH, R_PPC64_REL16_HIGHA),
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(R_PPC64_REL16_HIGHER, R_PPC64_REL16_HIGHERA),
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(R_PPC64_REL16_HIGHEST, R_PPC64_REL16_HIGHESTA): Define.
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(R_PPC64_LO_DS_OPT, R_PPC64_16DX_HA): Bump value.
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2018-08-31 04:23:12 +08:00
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2018-08-30 Kito Cheng <kito@andestech.com>
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* opcode/riscv.h (MAX_SUBSET_NUM): New.
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(riscv_opcode): Add xlen_requirement field and change type of
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subset.
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2018-08-29 20:36:23 +08:00
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2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
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2018-08-29 20:55:25 +08:00
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* elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS264E.
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* opcode/mips.h (CPU_XXX): New CPU_GS264E.
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2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
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2018-08-29 20:36:23 +08:00
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* elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS464E.
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* opcode/mips.h (CPU_XXX): New CPU_GS464E.
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2018-08-29 20:13:00 +08:00
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2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
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* elf/mips.h (E_MIPS_MACH_XXX): Rename E_MIPS_MACH_LS3A to
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E_MIPS_MACH_GS464.
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(AFL_EXT_XXX): Delete AFL_EXT_LOONGSON_3A.
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* opcode/mips.h (INSN_XXX): Delete INSN_LOONGSON_3A.
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(CPU_XXX): Rename CPU_LOONGSON_3A to CPU_GS464.
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* opcode/mips.h (mips_isa_table): Delete CPU_LOONGSON_3A case.
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2018-08-29 20:08:58 +08:00
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2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
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* elf/mips.h (AFL_ASE_LOONGSON_EXT2): New macro.
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(AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_EXT2.
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* opcode/mips.h (ASE_LOONGSON_EXT2): New macro.
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2018-08-29 19:57:39 +08:00
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2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
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* elf/mips.h (AFL_ASE_LOONGSON_EXT): New macro.
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(AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_EXT.
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* opcode/mips.h (ASE_LOONGSON_EXT): New macro.
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2018-08-29 17:39:33 +08:00
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2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
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* elf/mips.h (AFL_ASE_LOONGSON_CAM): New macro.
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(AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_CAM.
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* opcode/mips.h (ASE_LOONGSON_CAM): New macro.
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x86: Update GNU_PROPERTY_X86_XXX macros
This patch updates GNU_PROPERTY_X86_XXX macros:
1. GNU_PROPERTY_X86_UINT32_AND_XXX: A 4-byte unsigned integer property.
A bit is set if it is set in all relocatable inputs:
#define GNU_PROPERTY_X86_UINT32_AND_LO 0xc0000002
#define GNU_PROPERTY_X86_UINT32_AND_HI 0xc0007fff
2. GNU_PROPERTY_X86_UINT32_OR_XXX: A 4-byte unsigned integer property.
A bit is set if it is set in any relocatable inputs:
#define GNU_PROPERTY_X86_UINT32_OR_LO 0xc0008000
#define GNU_PROPERTY_X86_UINT32_OR_HI 0xc000ffff
3. GNU_PROPERTY_X86_UINT32_OR_AND_XXX: A 4-byte unsigned integer property.
A bit is set if it is set in any relocatable inputs and the property is
present in all relocatable inputs:
#define GNU_PROPERTY_X86_UINT32_OR_AND_LO 0xc0010000
#define GNU_PROPERTY_X86_UINT32_OR_AND_HI 0xc0017fff
4. GNU_PROPERTY_X86_FEATURE_2_NEEDED, GNU_PROPERTY_X86_FEATURE_2_USED
and GNU_PROPERTY_X86_FEATURE_2_XXX bits.
GNU_PROPERTY_X86_FEATURE_1_AND is unchanged. GNU_PROPERTY_X86_ISA_1_USED
and GNU_PROPERTY_X86_ISA_1_NEEDED are updated to better support targeted
processors since GNU_PROPERTY_X86_ISA_1_?86 aren't isn't very useful.
A new set of GNU_PROPERTY_X86_ISA_1_XXX bits are defined. The previous
GNU_PROPERTY_X86_ISA_1_XXX macros are deprecated and renamed to
GNU_PROPERTY_X86_COMPAT_ISA_1_XXX.
bfd/
* elfxx-x86.c (_bfd_x86_elf_parse_gnu_properties): Handle
X86_COMPAT_ISA_1_USED, X86_COMPAT_ISA_1_NEEDED,
X86_UINT32_AND_LO, X86_UINT32_AND_HI, X86_UINT32_OR_LO,
X86_UINT32_OR_HI, X86_UINT32_OR_AND_LO and X86_UINT32_OR_AND_HI
instead of X86_ISA_1_USED, X86_ISA_1_NEEDED and X86_FEATURE_1_AND.
(_bfd_x86_elf_merge_gnu_properties): Likewise.
(_bfd_x86_elf_link_setup_gnu_properties): Add X86_FEATURE_2_NEEDED
instead of X86_ISA_1_NEEDED.
(_bfd_x86_elf_link_fixup_gnu_properties): Handle
X86_COMPAT_ISA_1_USED, X86_COMPAT_ISA_1_NEEDED, X86_UINT32_AND_LO,
X86_UINT32_AND_HI, X86_UINT32_OR_LO, X86_UINT32_OR_HI,
X86_UINT32_OR_AND_LO and X86_UINT32_OR_AND_HI instead of
X86_ISA_1_USED, X86_ISA_1_NEEDED and X86_FEATURE_1_AND.
binutils/
* readelf.c (decode_x86_compat_isa): New function.
(decode_x86_feature_2): Likewise.
(decode_x86_isa): Updated for new X86_ISA_1_XXX bits.
(decode_x86_feature): Renamed to ...
(decode_x86_feature_1): This. Remove the type argument.
(print_gnu_property_note): Handle X86_COMPAT_ISA_1_USED,
X86_COMPAT_ISA_1_NEEDED, X86_UINT32_AND_LO, X86_UINT32_AND_HI,
X86_UINT32_OR_LO, X86_UINT32_OR_HI, X86_UINT32_OR_AND_LO and
X86_UINT32_OR_AND_HI instead of X86_ISA_1_USED, X86_ISA_1_NEEDED
and X86_FEATURE_1_AND.
* testsuite/binutils-all/i386/pr21231b.s: Updated to the current
GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_ISA_1_NEEDED
values.
* testsuite/binutils-all/x86-64/pr21231b.s: Likewise.
* testsuite/binutils-all/x86-64/pr23494a.s: Likewise.
* testsuite/binutils-all/x86-64/pr23494b.s: Likewise.
* testsuite/binutils-all/x86-64/pr23494c.s: Likewise.
* testsuite/binutils-all/i386/pr21231b.d: Updated.
* testsuite/binutils-all/x86-64/pr21231b.d: Likewise.
* testsuite/binutils-all/x86-64/pr23494a-x32.d: Likewise.
* testsuite/binutils-all/x86-64/pr23494a.d: Likewise.
* testsuite/binutils-all/x86-64/pr23494c-x32.d: Likewise.
* testsuite/binutils-all/x86-64/pr23494c.d: Likewise.
* testsuite/binutils-all/x86-64/pr23494d-x32.d: Likewise.
* testsuite/binutils-all/x86-64/pr23494d.d: Likewise.
* testsuite/binutils-all/x86-64/pr23494e-x32.d: Likewise.
* testsuite/binutils-all/x86-64/pr23494e.d: Likewise.
include/
* elf/common.h (GNU_PROPERTY_X86_ISA_1_USED): Renamed to ...
(GNU_PROPERTY_X86_COMPAT_ISA_1_USED): This.
(GNU_PROPERTY_X86_ISA_1_NEEDED): Renamed to ...
(GNU_PROPERTY_X86_COMPAT_ISA_1_NEEDED): This.
(GNU_PROPERTY_X86_ISA_1_XXX): Renamed to ...
(GNU_PROPERTY_X86_COMPAT_ISA_1_XXX): This.
(GNU_PROPERTY_X86_UINT32_AND_LO): New.
(GNU_PROPERTY_X86_UINT32_AND_HI): Likewise.
(GNU_PROPERTY_X86_UINT32_OR_LO): Likewise.
(GNU_PROPERTY_X86_UINT32_OR_HI): Likewise.
(GNU_PROPERTY_X86_UINT32_OR_AND_LO): Likewise.
(GNU_PROPERTY_X86_UINT32_OR_AND_HI): Likewise.
(GNU_PROPERTY_X86_ISA_1_CMOV): Likewise.
(GNU_PROPERTY_X86_ISA_1_SSE): Likewise.
(GNU_PROPERTY_X86_ISA_1_SSE2): Likewise.
(GNU_PROPERTY_X86_ISA_1_SSE3): Likewise.
(GNU_PROPERTY_X86_ISA_1_SSSE3): Likewise.
(GNU_PROPERTY_X86_ISA_1_SSE4_1): Likewise.
(GNU_PROPERTY_X86_ISA_1_SSE4_2): Likewise.
(GNU_PROPERTY_X86_ISA_1_AVX): Likewise.
(GNU_PROPERTY_X86_ISA_1_AVX2): Likewise.
(GNU_PROPERTY_X86_ISA_1_FMA): Likewise.
(GNU_PROPERTY_X86_ISA_1_AVX512F): Likewise.
(GNU_PROPERTY_X86_ISA_1_AVX512CD): Likewise.
(GNU_PROPERTY_X86_ISA_1_AVX512ER): Likewise.
(GNU_PROPERTY_X86_ISA_1_AVX512PF): Likewise.
(GNU_PROPERTY_X86_ISA_1_AVX512VL): Likewise.
(GNU_PROPERTY_X86_ISA_1_AVX512DQ): Likewise.
(GNU_PROPERTY_X86_ISA_1_AVX512BW): Likewise.
(GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS): Likewise.
(GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW): Likewise.
(GNU_PROPERTY_X86_ISA_1_AVX512_BITALG): Likewise.
(GNU_PROPERTY_X86_ISA_1_AVX512_IFMA): Likewise.
(GNU_PROPERTY_X86_ISA_1_AVX512_VBMI): Likewise.
(GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2): Likewise.
(GNU_PROPERTY_X86_ISA_1_AVX512_VNNI): Likewise.
(GNU_PROPERTY_X86_FEATURE_2_X86): Likewise.
(GNU_PROPERTY_X86_FEATURE_2_X87): Likewise.
(GNU_PROPERTY_X86_FEATURE_2_MMX): Likewise.
(GNU_PROPERTY_X86_FEATURE_2_XMM): Likewise.
(GNU_PROPERTY_X86_FEATURE_2_YMM): Likewise.
(GNU_PROPERTY_X86_FEATURE_2_ZMM): Likewise.
(GNU_PROPERTY_X86_FEATURE_2_FXSR): Likewise.
(GNU_PROPERTY_X86_FEATURE_2_XSAVE): Likewise.
(GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT): Likewise.
(GNU_PROPERTY_X86_FEATURE_2_XSAVEC): Likewise.
(GNU_PROPERTY_X86_FEATURE_1_AND): Updated to
(GNU_PROPERTY_X86_UINT32_AND_LO + 0).
(GNU_PROPERTY_X86_ISA_1_NEEDED): Defined to
(GNU_PROPERTY_X86_UINT32_OR_LO + 0).
(GNU_PROPERTY_X86_FEATURE_2_NEEDED): New. Defined to
(GNU_PROPERTY_X86_UINT32_OR_LO + 1).
(GNU_PROPERTY_X86_ISA_1_USED): Defined to
(GNU_PROPERTY_X86_UINT32_OR_AND_LO + 0).
(GNU_PROPERTY_X86_FEATURE_2_USED): New. Defined to
(GNU_PROPERTY_X86_UINT32_OR_AND_LO + 1).
ld/
* testsuite/ld-i386/i386.exp: Run pr23372c, pr23372d, pr23486c
and pr23486d.
* testsuite/ld-i386/pr23372a.s: Update comments.
* testsuite/ld-i386/pr23372b.s: Likewise.
* testsuite/ld-i386/pr23372c.s: Likewise.
* testsuite/ld-x86-64/pr23372a.s: Likewise.
* testsuite/ld-x86-64/pr23372b.s: Likewise.
* testsuite/ld-x86-64/pr23372c.s: Likewise.
* testsuite/ld-x86-64/pr23486a.s: Likewise.
* testsuite/ld-x86-64/pr23486b.s: Likewise.
* testsuite/ld-i386/pr23372c.d: New file.
* testsuite/ld-i386/pr23372d.d: Likewise.
* testsuite/ld-i386/pr23486c.d: Likewise.
* testsuite/ld-i386/pr23486d.d: Likewise.
* testsuite/ld-x86-64/pr23372c-x32.d: Likewise.
* testsuite/ld-x86-64/pr23372c.d: Likewise.
* testsuite/ld-x86-64/pr23372d-x32.d: Likewise.
* testsuite/ld-x86-64/pr23372d.d: Likewise.
* testsuite/ld-x86-64/pr23372d.s: Likewise.
* testsuite/ld-x86-64/pr23372e.s: Likewise.
* testsuite/ld-x86-64/pr23372f.s: Likewise.
* testsuite/ld-x86-64/pr23486c-x32.d: Likewise.
* testsuite/ld-x86-64/pr23486c.d: Likewise.
* testsuite/ld-x86-64/pr23486c.s: Likewise.
* testsuite/ld-x86-64/pr23486d-x32.d: Likewise.
* testsuite/ld-x86-64/pr23486d.d: Likewise.
* testsuite/ld-x86-64/pr23486d.s: Likewise.
* testsuite/ld-i386/property-3.r: Updated.
* testsuite/ld-i386/property-4.r: Likewise.
* testsuite/ld-i386/property-5.r: Likewise.
* testsuite/ld-i386/property-x86-3.d: Likewise.
* testsuite/ld-i386/property-x86-ibt3a.d: Likewise.
* testsuite/ld-i386/property-x86-shstk3a.d: Likewise.
* testsuite/ld-i386/property-x86-shstk3b.d: Likewise.
* testsuite/ld-x86-64/property-3.r: Likewise.
* testsuite/ld-x86-64/property-4.r: Likewise.
* testsuite/ld-x86-64/property-5.r: Likewise.
* testsuite/ld-x86-64/property-x86-3-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-3.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt3a-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt3a.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt3b-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-ibt3b.d: Likewise.
* testsuite/ld-x86-64/property-x86-shstk3a-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-shstk3a.d: Likewise.
* testsuite/ld-x86-64/property-x86-shstk3b-x32.d: Likewise.
* testsuite/ld-x86-64/property-x86-shstk3b.d: Likewise.
* testsuite/ld-i386/property-x86-1.S: Updated to the current
GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_ISA_1_NEEDED
values.
* testsuite/ld-i386/property-x86-2.S: Likewise.
* testsuite/ld-i386/property-x86-3.s: Likewise.
* testsuite/ld-x86-64/property-x86-1.S: Likewise.
* testsuite/ld-x86-64/property-x86-2.S: Likewise.
* testsuite/ld-x86-64/property-x86-3.s: Likewise.
* ld/testsuite/ld-x86-64/x86-64.exp: Run pr23372c, pr23372c-x32,
pr23372d, pr23372d-x32, pr23486c, pr23486c-x32, pr23486d and
pr23486d-x32.
2018-08-24 19:41:50 +08:00
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2018-08-24 H.J. Lu <hongjiu.lu@intel.com>
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* elf/common.h (GNU_PROPERTY_X86_ISA_1_USED): Renamed to ...
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(GNU_PROPERTY_X86_COMPAT_ISA_1_USED): This.
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(GNU_PROPERTY_X86_ISA_1_NEEDED): Renamed to ...
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(GNU_PROPERTY_X86_COMPAT_ISA_1_NEEDED): This.
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(GNU_PROPERTY_X86_ISA_1_XXX): Renamed to ...
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(GNU_PROPERTY_X86_COMPAT_ISA_1_XXX): This.
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(GNU_PROPERTY_X86_UINT32_AND_LO): New.
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(GNU_PROPERTY_X86_UINT32_AND_HI): Likewise.
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(GNU_PROPERTY_X86_UINT32_OR_LO): Likewise.
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(GNU_PROPERTY_X86_UINT32_OR_HI): Likewise.
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(GNU_PROPERTY_X86_UINT32_OR_AND_LO): Likewise.
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(GNU_PROPERTY_X86_UINT32_OR_AND_HI): Likewise.
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(GNU_PROPERTY_X86_ISA_1_CMOV): Likewise.
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(GNU_PROPERTY_X86_ISA_1_SSE): Likewise.
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(GNU_PROPERTY_X86_ISA_1_SSE2): Likewise.
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(GNU_PROPERTY_X86_ISA_1_SSE3): Likewise.
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(GNU_PROPERTY_X86_ISA_1_SSSE3): Likewise.
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(GNU_PROPERTY_X86_ISA_1_SSE4_1): Likewise.
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(GNU_PROPERTY_X86_ISA_1_SSE4_2): Likewise.
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(GNU_PROPERTY_X86_ISA_1_AVX): Likewise.
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(GNU_PROPERTY_X86_ISA_1_AVX2): Likewise.
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(GNU_PROPERTY_X86_ISA_1_FMA): Likewise.
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(GNU_PROPERTY_X86_ISA_1_AVX512F): Likewise.
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(GNU_PROPERTY_X86_ISA_1_AVX512CD): Likewise.
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(GNU_PROPERTY_X86_ISA_1_AVX512ER): Likewise.
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(GNU_PROPERTY_X86_ISA_1_AVX512PF): Likewise.
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(GNU_PROPERTY_X86_ISA_1_AVX512VL): Likewise.
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(GNU_PROPERTY_X86_ISA_1_AVX512DQ): Likewise.
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(GNU_PROPERTY_X86_ISA_1_AVX512BW): Likewise.
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(GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS): Likewise.
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(GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW): Likewise.
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(GNU_PROPERTY_X86_ISA_1_AVX512_BITALG): Likewise.
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(GNU_PROPERTY_X86_ISA_1_AVX512_IFMA): Likewise.
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(GNU_PROPERTY_X86_ISA_1_AVX512_VBMI): Likewise.
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(GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2): Likewise.
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(GNU_PROPERTY_X86_ISA_1_AVX512_VNNI): Likewise.
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(GNU_PROPERTY_X86_FEATURE_2_X86): Likewise.
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(GNU_PROPERTY_X86_FEATURE_2_X87): Likewise.
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(GNU_PROPERTY_X86_FEATURE_2_MMX): Likewise.
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|
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(GNU_PROPERTY_X86_FEATURE_2_XMM): Likewise.
|
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(GNU_PROPERTY_X86_FEATURE_2_YMM): Likewise.
|
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(GNU_PROPERTY_X86_FEATURE_2_ZMM): Likewise.
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(GNU_PROPERTY_X86_FEATURE_2_FXSR): Likewise.
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(GNU_PROPERTY_X86_FEATURE_2_XSAVE): Likewise.
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(GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT): Likewise.
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(GNU_PROPERTY_X86_FEATURE_2_XSAVEC): Likewise.
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(GNU_PROPERTY_X86_FEATURE_1_AND): Updated to
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(GNU_PROPERTY_X86_UINT32_AND_LO + 0).
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(GNU_PROPERTY_X86_ISA_1_NEEDED): Defined to
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(GNU_PROPERTY_X86_UINT32_OR_LO + 0).
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(GNU_PROPERTY_X86_FEATURE_2_NEEDED): New. Defined to
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(GNU_PROPERTY_X86_UINT32_OR_LO + 1).
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(GNU_PROPERTY_X86_ISA_1_USED): Defined to
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(GNU_PROPERTY_X86_UINT32_OR_AND_LO + 0).
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(GNU_PROPERTY_X86_FEATURE_2_USED): New. Defined to
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(GNU_PROPERTY_X86_UINT32_OR_AND_LO + 1).
|
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2018-08-24 19:37:45 +08:00
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2018-08-24 H.J. Lu <hongjiu.lu@intel.com>
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* elf/common.h (GNU_PROPERTY_X86_UINT32_VALID): New.
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2018-08-22 15:07:56 +08:00
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2018-08-21 John Darrington <john@darrington.wattle.id.au>
|
2018-06-17 13:04:11 +08:00
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* elf/s12z.h: Rename R_S12Z_UKNWN_3 to R_S12Z_EXT18.
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|
|
Use operand->extract to provide defaults for optional PowerPC operands
Most optional operands to powerpc instructions use a default value of
zero, but there are a few exceptions. Those have been handled by
PPC_OPERAND_OPTIONAL_VALUE and an entry in the powerpc_operands table
for the default value, smuggled in the shift field. This patch
changes that to using the operand extract function to provide non-zero
defaults.
I've also moved the code determining whether optional operands are
provided or omitted, to the point the first optional operand is seen,
and allowed for the possibility of optional base register operands
in a future patch.
The patch does change the error you get on invalid assembly like
ld 3,4
You'll now see "missing operand" rather than
"syntax error; end of line, expected `('".
gas/
* config/tc-ppc.c (md_assemble): Delay counting of optional
operands until one is encountered. Allow for the possibility
of optional base regs, ie. PPC_OPERAND_PARENS. Call
ppc_optional_operand_value with extra args.
include/
* opcode/ppc.h (struct powerpc_operand): Correct "insert" comment.
Mention use of "extract" function to provide default value.
(PPC_OPERAND_OPTIONAL_VALUE): Delete.
(ppc_optional_operand_value): Rewrite to use extract function.
opcodes/
* ppc-dis.c (operand_value_powerpc): Init "invalid".
(skip_optional_operands): Count optional operands, and update
ppc_optional_operand_value call.
* ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
(extract_vlensi): Likewise.
(extract_fxm): Return default value for missing optional operand.
(extract_ls, extract_raq, extract_tbr): Likewise.
(insert_sxl, extract_sxl): New functions.
(insert_esync, extract_esync): Remove Power9 handling and simplify.
(powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
flag and extra entry.
(powerpc_operands <SXL>): Likewise, and use insert_sxl and
extract_sxl.
2018-08-16 14:44:12 +08:00
|
|
|
|
2018-08-21 Alan Modra <amodra@gmail.com>
|
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|
|
* opcode/ppc.h (struct powerpc_operand): Correct "insert" comment.
|
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|
|
Mention use of "extract" function to provide default value.
|
|
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|
|
(PPC_OPERAND_OPTIONAL_VALUE): Delete.
|
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|
|
(ppc_optional_operand_value): Rewrite to use extract function.
|
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|
2018-08-20 16:46:34 +08:00
|
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|
|
2018-08-18 John Darrington <john@darrington.wattle.id.au>
|
2018-07-11 16:42:01 +08:00
|
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|
|
2018-08-20 07:52:28 +08:00
|
|
|
|
* opcode/s12z.h: New file.
|
2018-07-11 16:42:01 +08:00
|
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|
2018-08-09 23:51:09 +08:00
|
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|
|
2018-08-09 Richard Earnshaw <rearnsha@arm.com>
|
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|
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* elf/arm.h: Updated comments for e_flags definitions.
|
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|
2018-08-06 21:41:32 +08:00
|
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|
2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
|
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* elf/arc.h (Tag_ARC_ATR_version): New tag.
|
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|
2018-08-06 21:41:32 +08:00
|
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|
|
2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
|
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|
|
* opcode/arc.h (ARC_OPCODE_ARCV1): Define.
|
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|
2018-07-26 20:13:14 +08:00
|
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|
|
2018-08-01 Richard Earnshaw <rearnsha@arm.com>
|
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Copy over from GCC
|
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|
|
2018-07-26 Martin Liska <mliska@suse.cz>
|
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|
|
2018-08-20 07:52:28 +08:00
|
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|
|
PR lto/86548
|
2018-07-26 20:13:14 +08:00
|
|
|
|
* libiberty.h (make_temp_file_with_prefix): New function.
|
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|
2018-07-31 04:55:41 +08:00
|
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|
|
2018-07-30 Jim Wilson <jimw@sifive.com>
|
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|
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* opcode/riscv.h (INSN_TYPE, INSN_BRANCH, INSN_CONDBRANCH, INSN_JSR)
|
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|
|
(INSN_DREF, INSN_DATA_SIZE, INSN_DATA_SIZE_SHIFT, INSN_1_BYTE)
|
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|
(INSN_2_BYTE, INSN_4_BYTE, INSN_8_BYTE, INSN_16_BYTE): New.
|
|
|
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|
|
Add support for the C_SKY series of processors.
This patch series is a new binutils port for C-SKY processors, including support for both the V1 and V2 processor variants. V1 is derived from the MCore architecture while V2 is substantially different, with mixed 16- and 32-bit instructions, a larger register set, a different (but overlapping) ABI, etc. There is support for bare-metal ELF targets and Linux with both glibc and uClibc.
This code is being contributed jointly by C-SKY Microsystems and Mentor Graphics. C-SKY is responsible for the technical content and has proposed Lifang Xia and Yunhai Shang as port maintainers. (Note that C-SKY does have a corporate copyright assignment on file with the FSF.) Mentor Graphics' role has been cleaning up the code, adding documentation and additional test cases, etc, to address issues we anticipated reviewers would complain about.
bfd * Makefile.am (ALL_MACHINES, ALL_MACHINES_CFILES): Add C-SKY.
(BFD32_BACKENDS, BFD_BACKENDS_CFILES): Likewise.
* Makefile.in: Regenerated.
* archures.c (enum bfd_architecture): Add bfd_arch_csky and
related bfd_mach defines.
(bfd_csky_arch): Declare.
(bfd_archures_list): Add C-SKY.
* bfd-in.h (elf32_csky_build_stubs): Declare.
(elf32_csky_size_stubs): Declare.
(elf32_csky_next_input_section: Declare.
(elf32_csky_setup_section_lists): Declare.
* bfd-in2.h: Regenerated.
* config.bfd: Add C-SKY.
* configure.ac: Likewise.
* configure: Regenerated.
* cpu-csky.c: New file.
* elf-bfd.h (enum elf_target_id): Add C-SKY.
* elf32-csky.c: New file.
* libbfd.h: Regenerated.
* reloc.c: Add C-SKY relocations.
* targets.c (csky_elf32_be_vec, csky_elf32_le_vec): Declare.
(_bfd_target_vector): Add C-SKY target vector entries.
binutils* readelf.c: Include elf/csky.h.
(guess_is_rela): Handle EM_CSKY.
(dump_relocations): Likewise.
(get_machine_name): Likewise.
(is_32bit_abs_reloc): Likewise.
include * dis-asm.h (csky_symbol_is_valid): Declare.
* opcode/csky.h: New file.
opcodes * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
* Makefile.in: Regenerated.
* configure.ac: Add C-SKY.
* configure: Regenerated.
* csky-dis.c: New file.
* csky-opc.h: New file.
* disassemble.c (ARCH_csky): Define.
(disassembler, disassemble_init_for_target): Add case for ARCH_csky.
* disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
gas * Makefile.am (TARGET_CPU_CFILES): Add entry for C-SKY.
(TARGET_CPU_HFILES, TARGET_ENV_HFILES): Likewise.
* Makefile.in: Regenerated.
* config/tc-csky.c: New file.
* config/tc-csky.h: New file.
* config/te-csky_abiv1.h: New file.
* config/te-csky_abiv1_linux.h: New file.
* config/te-csky_abiv2.h: New file.
* config/te-csky_abiv2_linux.h: New file.
* configure.tgt: Add C-SKY.
* doc/Makefile.am (CPU_DOCS): Add entry for C-SKY.
* doc/Makefile.in: Regenerated.
* doc/all.texi: Set CSKY feature.
* doc/as.texi (Overview): Add C-SKY options.
(Machine Dependencies): Likewise.
* doc/c-csky.texi: New file.
* testsuite/gas/csky/*: New test cases.
ld * Makefile.am (ALL_EMULATION_SOURCES): Add C-SKY emulations.
(ecskyelf.c, ecskyelf_linux.c): New rules.
* Makefile.in: Regenerated.
* configure.tgt: Add C-SKY.
* emulparams/cskyelf.sh: New file.
* emulparams/cskyelf_linux.sh: New file.
* emultempl/cskyelf.em: New file.
* gen-doc.texi: Add C-SKY.
* ld.texi: Likewise.
(Options specific to C-SKY targets): New section.
* testsuite/ld-csky/*: New tests.
2018-07-30 19:24:14 +08:00
|
|
|
|
2018-07-30 Andrew Jenner <andrew@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* elf/common.h (EM_CSKY, EM_CSKY_OLD): Define.
|
|
|
|
|
|
* elf/csky.h: New file.
|
|
|
|
|
|
|
2018-07-27 08:12:43 +08:00
|
|
|
|
2018-07-27 Chenghua Xu <paul.hua.gm@gmail.com>
|
|
|
|
|
|
Maciej W. Rozycki <macro@linux-mips.org>
|
|
|
|
|
|
|
|
|
|
|
|
* elf/mips.h (AFL_ASE_MASK): Correct typo.
|
|
|
|
|
|
|
2018-07-24 07:51:44 +08:00
|
|
|
|
2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/ppc.h (PPC_OPCODE_750): Adjust comment.
|
|
|
|
|
|
|
2018-07-26 10:41:11 +08:00
|
|
|
|
2018-07-26 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* elf/ppc64.h: Specify byte offset to local entry for values
|
|
|
|
|
|
of two to six in STO_PPC64_LOCAL_MASK. Clarify r2 return
|
|
|
|
|
|
value for such functions when entering via global entry point.
|
|
|
|
|
|
Specify meaning of a value of one in STO_PPC64_LOCAL_MASK.
|
|
|
|
|
|
|
2018-07-24 15:05:52 +08:00
|
|
|
|
2018-07-24 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 23430
|
|
|
|
|
|
* elf/common.h (SHT_SYMTAB_SHNDX): Fix comment typo.
|
|
|
|
|
|
|
2018-07-20 20:21:33 +08:00
|
|
|
|
2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
|
|
|
|
|
|
Maciej W. Rozycki <macro@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* elf/mips.h (AFL_ASE_MMI): New macro.
|
|
|
|
|
|
(AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_MMI.
|
|
|
|
|
|
* opcode/mips.h (ASE_LOONGSON_MMI): New macro.
|
|
|
|
|
|
|
2018-07-18 03:04:53 +08:00
|
|
|
|
2018-07-17 Maciej W. Rozycki <macro@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* bfdlink.h (bfd_link_hash_entry): Add `rel_from_abs' member.
|
|
|
|
|
|
|
2018-07-06 13:37:08 +08:00
|
|
|
|
2018-07-06 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* diagnostics.h: Comment on macro usage.
|
|
|
|
|
|
|
2018-07-06 09:50:12 +08:00
|
|
|
|
2018-07-05 Simon Marchi <simon.marchi@polymtl.ca>
|
|
|
|
|
|
|
|
|
|
|
|
* diagnostics.h (DIAGNOSTIC_IGNORE_DEPRECATED_DECLARATIONS):
|
|
|
|
|
|
Define for clang.
|
|
|
|
|
|
|
GDB PR tdep/8282: MIPS: Wire in `set disassembler-options'
Implement MIPS target support for passing options to the disassembler,
complementing commit 65b48a81404c ("GDB: Add support for the new
set/show disassembler-options commands.").
This includes options that expect an argument, so adjust the generic
code and data structures used so as to handle such options. So as to
give backends syntax flexibility no specific delimiter has been defined
to separate options from their respective arguments, so it has to be
included as the last character of the option name. Completion code
however has not been adjusted and consequently option arguments cannot
be completed at this time.
Also the MIPS target has non-empty defaults for the options, so that ABI
names for the general-purpose registers respect our `set mips abi ...'
setting rather than always being determined from the ELF headers of the
binary file selected. Handle these defaults as implicit options, never
shown to the user and always prepended to the user-specified options, so
that the latters can override the defaults.
The resulting output for the MIPS target is as follows:
(gdb) show disassembler-options
The current disassembler options are ''
The following disassembler options are supported for use with the
'set disassembler-options <option>[,<option>...]' command:
no-aliases Use canonical instruction forms.
msa Recognize MSA instructions.
virt Recognize the virtualization ASE instructions.
xpa Recognize the eXtended Physical Address (XPA) ASE
instructions.
ginv Recognize the Global INValidate (GINV) ASE instructions.
gpr-names=ABI Print GPR names according to specified ABI.
Default: based on binary being disassembled.
fpr-names=ABI Print FPR names according to specified ABI.
Default: numeric.
cp0-names=ARCH Print CP0 register names according to specified architecture.
Default: based on binary being disassembled.
hwr-names=ARCH Print HWR names according to specified architecture.
Default: based on binary being disassembled.
reg-names=ABI Print GPR and FPR names according to specified ABI.
reg-names=ARCH Print CP0 register and HWR names according to specified
architecture.
For the options above, the following values are supported for "ABI":
numeric 32 n32 64
For the options above, the following values are supported for "ARCH":
numeric r3000 r3900 r4000 r4010 vr4100 vr4111 vr4120 r4300 r4400 r4600
r4650 r5000 vr5400 vr5500 r5900 r6000 rm7000 rm9000 r8000 r10000 r12000
r14000 r16000 mips5 mips32 mips32r2 mips32r3 mips32r5 mips32r6 mips64
mips64r2 mips64r3 mips64r5 mips64r6 interaptiv-mr2 sb1 loongson2e
loongson2f loongson3a octeon octeon+ octeon2 octeon3 xlr xlp
(gdb)
which corresponds to what `objdump --help' used to print for the MIPS
target, with minor formatting changes, most notably option argument
lists being wrapped, but also the amount of white space separating
options from the respective descriptions. The relevant part the new
code is now also used by `objdump --help', which means these formatting
changes apply to both outputs, except for argument list wrapping, which
is GDB-specific.
This also adds a separating new line between the heading and option
lists where descriptions are provided, hence:
(gdb) set architecture s390:31-bit
(gdb) show disassembler-options
The current disassembler options are ''
The following disassembler options are supported for use with the
'set disassembler-options <option>[,<option>...]' command:
esa Disassemble in ESA architecture mode
zarch Disassemble in z/Architecture mode
insnlength Print unknown instructions according to length from first two bits
(gdb)
but:
(gdb) set architecture powerpc:common
(gdb) show disassembler-options
The current disassembler options are ''
The following disassembler options are supported for use with the
'set disassembler-options <option>[,<option>...]' command:
403, 405, 440, 464, 476, 601, 603, 604, 620, 7400, 7410, 7450, 7455, 750cl,
821, 850, 860, a2, altivec, any, booke, booke32, cell, com, e200z4, e300,
e500, e500mc, e500mc64, e5500, e6500, e500x2, efs, efs2, power4, power5,
power6, power7, power8, power9, ppc, ppc32, 32, ppc64, 64, ppc64bridge,
ppcps, pwr, pwr2, pwr4, pwr5, pwr5x, pwr6, pwr7, pwr8, pwr9, pwrx, raw, spe,
spe2, titan, vle, vsx
(gdb)
Existing affected target backends have been adjusted accordingly.
This has been verified manually with:
(gdb) set architecture arm
(gdb) set architecture powerpc:common
(gdb) set architecture s390:31-bit
to cause no issues with the `show disassembler-options' and `set
disassembler-options' commands. A test case for the MIPS target has
also been provided, covering the default settings with ABI overrides as
well as disassembler option overrides.
2018-07-02 Maciej W. Rozycki <macro@mips.com>
Simon Marchi <simon.marchi@polymtl.ca>
include/
PR tdep/8282
* dis-asm.h (disasm_option_arg_t): New typedef.
(disasm_options_and_args_t): Likewise.
(disasm_options_t): Add `arg' member, document members.
(disassembler_options_mips): New prototype.
(disassembler_options_arm, disassembler_options_powerpc)
(disassembler_options_s390): Update prototypes.
opcodes/
PR tdep/8282
* mips-dis.c (mips_option_arg_t): New enumeration.
(mips_options): New variable.
(disassembler_options_mips): New function.
(print_mips_disassembler_options): Reimplement in terms of
`disassembler_options_mips'.
* arm-dis.c (disassembler_options_arm): Adapt to using the
`disasm_options_and_args_t' structure.
* ppc-dis.c (disassembler_options_powerpc): Likewise.
* s390-dis.c (disassembler_options_s390): Likewise.
gdb/
PR tdep/8282
* disasm.h (gdb_disassembler): Add
`m_disassembler_options_holder'. member
* disasm.c (get_all_disassembler_options): New function.
(gdb_disassembler::gdb_disassembler): Use it.
(gdb_buffered_insn_length_init_dis): Likewise.
(gdb_buffered_insn_length): Adjust accordingly.
(set_disassembler_options): Handle options with arguments.
(show_disassembler_options_sfunc): Likewise. Add a leading new
line if showing options with descriptions.
(disassembler_options_completer): Adapt to using the
`disasm_options_and_args_t' structure.
* mips-tdep.c (mips_disassembler_options): New variable.
(mips_disassembler_options_o32): Likewise.
(mips_disassembler_options_n32): Likewise.
(mips_disassembler_options_n64): Likewise.
(gdb_print_insn_mips): Don't set `disassembler_options'.
(gdb_print_insn_mips_n32, gdb_print_insn_mips_n64): Remove
functions.
(mips_gdbarch_init): Always set `gdbarch_print_insn' to
`gdb_print_insn_mips'. Set `gdbarch_disassembler_options',
`gdbarch_disassembler_options_implicit' and
`gdbarch_valid_disassembler_options'.
* arm-tdep.c (_initialize_arm_tdep): Adapt to using the
`disasm_options_and_args_t' structure.
* gdbarch.sh (disassembler_options_implicit): New `gdbarch'
method.
(valid_disassembler_options): Switch from `disasm_options_t' to
the `disasm_options_and_args_t' structure.
* NEWS: Document `set disassembler-options' support for the MIPS
target.
* gdbarch.h: Regenerate.
* gdbarch.c: Regenerate.
gdb/doc/
PR tdep/8282
* gdb.texinfo (Source and Machine Code): Document `set
disassembler-options' support for the MIPS target.
gdb/testsuite/
PR tdep/8282
* gdb.arch/mips-disassembler-options.exp: New test.
* gdb.arch/mips-disassembler-options.s: New test source.
2018-07-03 06:57:21 +08:00
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2018-07-02 Maciej W. Rozycki <macro@mips.com>
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PR tdep/8282
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* dis-asm.h (disasm_option_arg_t): New typedef.
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(disasm_options_and_args_t): Likewise.
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(disasm_options_t): Add `arg' member, document members.
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(disassembler_options_mips): New prototype.
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(disassembler_options_arm, disassembler_options_powerpc)
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(disassembler_options_s390): Update prototypes.
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Fix AArch64 encodings for by element instructions.
Some instructions in Armv8-a place a limitation on FP16 registers that can be
used as the register from which to select an element from.
e.g. fmla restricts Rm to 4 bits when using an FP16 register. This restriction
does not apply for all instructions, e.g. fcmla does not have this restriction
as it gets an extra bit from the M field.
Unfortunately, this restriction to S_H was added for all _Em operands before,
meaning for a large number of instructions you couldn't use the full register
file.
This fixes the issue by introducing a new operand _Em16 which applies this
restriction only when paired with S_H and leaves the _Em and the other
qualifiers for _Em16 unbounded (i.e. using the full 5 bit range).
Also the patch updates all instructions that should be affected by this.
opcodes/
PR binutils/23192
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Likewise.
* aarch64-opc-2.c: Likewise.
* aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
* aarch64-opc.c (operand_general_constraint_met_p,
aarch64_print_operand): Likewise.
* aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
fmlal2, fmlsl2.
(AARCH64_OPERANDS): Add Em2.
gas/
PR binutils/23192
* config/tc-aarch64.c (process_omitted_operand, parse_operands): Add
AARCH64_OPND_Em16
* testsuite/gas/aarch64/advsimd-armv8_3.s: Expand tests to cover upper
16 registers.
* testsuite/gas/aarch64/advsimd-armv8_3.d: Likewise.
* testsuite/gas/aarch64/advsimd-compnum.s: Likewise.
* testsuite/gas/aarch64/advsimd-compnum.d: Likewise.
* testsuite/gas/aarch64/sve.d: Likewise.
include/
PR binutils/23192
*opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_Em16.
2018-06-29 19:12:27 +08:00
|
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2018-06-29 Tamar Christina <tamar.christina@arm.com>
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|
PR binutils/23192
|
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|
|
*opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_Em16.
|
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|
2018-06-21 21:49:41 +08:00
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|
2018-06-26 Alan Modra <amodra@gmail.com>
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|
* elf/internal.h (ELF_SECTION_IN_SEGMENT): Revert last change.
|
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|
2018-06-25 01:36:15 +08:00
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|
2018-06-24 Nick Clifton <nickc@redhat.com>
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|
2.31 branch created.
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2018-06-21 16:37:58 +08:00
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|
2018-06-21 Alan Hayward <alan.hayward@arm.com>
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* elf/internal.h (ELF_SECTION_IN_SEGMENT): Don’t check addresses
|
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for non SHT_NOBITS.
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2018-06-18 23:31:15 +08:00
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2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
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Sync with GCC
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2018-05-24 Tom Rix <trix@juniper.net>
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* dwarf2.def (DW_FORM_strx*, DW_FORM_addrx*): New.
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2017-11-20 Kito Cheng <kito.cheng@gmail.com>
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* longlong.h [__riscv] (__umulsidi3): Define.
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[__riscv] (umul_ppmm): Likewise.
|
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[__riscv] (__muluw3): Likewise.
|
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MIPS: Add Global INValidate ASE support
Add support for the Global INValidate Application Specific Extension
for Release 6 of the MIPS Architecture.
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 187-191
bfd/
* elfxx-mips.c (print_mips_ases): Add GINV extension.
binutils/
* readelf.c (print_mips_ases): Add GINV extension.
gas/
* NEWS: Mention MIPS Global INValidate ASE support.
* config/tc-mips.c (options): Add OPTION_GINV and OPTION_NO_GINV.
(md_longopts): Likewise.
(mips_ases): Define availability for GINV.
(mips_convert_ase_flags): Map ASE_GINV to AFL_ASE_GINV.
(md_show_usage): Add help for -mginv and -mno-ginv.
* doc/as.texinfo: Document -mginv, -mno-ginv.
* doc/c-mips.texi: Document -mginv, -mno-ginv, .set ginv and
.set noginv.
* testsuite/gas/mips/ase-errors-1.s: Add error checks for GINV
ASE.
* testsuite/gas/mips/ase-errors-2.s: Likewise.
* testsuite/gas/mips/ase-errors-1.l: Likewise.
* testsuite/gas/mips/ase-errors-2.l: Likewise.
* testsuite/gas/mips/ginv.d: New test.
* testsuite/gas/mips/ginv-err.d: New test.
* testsuite/gas/mips/ginv-err.l: New test stderr output.
* testsuite/gas/mips/ginv.s: New test source.
* testsuite/gas/mips/ginv-err.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
include/
* elf/mips.h (AFL_ASE_GINV, AFL_ASE_RESERVED1): New macros.
(AFL_ASE_MASK): Update to include AFL_ASE_GINV.
* opcode/mips.h: Document "+\" operand format.
(ASE_GINV): New macro.
opcodes/
* mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
mips64r6 descriptors.
(parse_mips_ase_option): Handle -Mginv option.
(print_mips_disassembler_options): Document -Mginv.
* mips-opc.c (decode_mips_operand) <+\>: New operand format.
(GINV): New macro.
(mips_opcodes): Define ginvi and ginvt.
2018-06-15 04:34:49 +08:00
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2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
|
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|
|
* elf/mips.h (AFL_ASE_GINV, AFL_ASE_RESERVED1): New macros.
|
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|
|
(AFL_ASE_MASK): Update to include AFL_ASE_GINV.
|
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|
|
* opcode/mips.h: Document "+\" operand format.
|
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|
|
(ASE_GINV): New macro.
|
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|
MIPS: Add CRC ASE support
Add support for the CRC Application Specific Extension for Release 6 of
the MIPS Architecture.
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 143-148
[2] "MIPS Architecture for Programmers Volume II-A: The MIPS64
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00087, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 165-170
ChangeLog:
bfd/
2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
Faraz Shahbazker <Faraz.Shahbazker@mips.com>
* elfxx-mips.c (print_mips_ases): Add CRC.
binutils/
2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
Faraz Shahbazker <Faraz.Shahbazker@mips.com>
* readelf.c (print_mips_ases): Add CRC.
gas/
2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
Faraz Shahbazker <Faraz.Shahbazker@mips.com>
Maciej W. Rozycki <macro@mips.com>
* config/tc-mips.c (options): Add OPTION_CRC and OPTION_NO_CRC.
(md_longopts): Likewise.
(md_show_usage): Add help for -mcrc and -mno-crc.
(mips_ases): Define availability for CRC and CRC64.
(mips_convert_ase_flags): Map ASE_CRC to AFL_ASE_CRC.
* doc/as.texinfo: Document -mcrc, -mno-crc.
* doc/c-mips.texi: Document -mcrc, -mno-crc, .set crc and
.set no-crc.
* testsuite/gas/mips/ase-errors-1.l: Add error checks for CRC
ASE.
* testsuite/gas/mips/ase-errors-2.l: Likewise.
* testsuite/gas/mips/ase-errors-1.s: Likewise.
* testsuite/gas/mips/ase-errors-2.s: Likewise.
* testsuite/gas/mips/crc.d: New test.
* testsuite/gas/mips/crc64.d: New test.
* testsuite/gas/mips/crc-err.d: New test.
* testsuite/gas/mips/crc64-err.d: New test.
* testsuite/gas/mips/crc-err.l: New test stderr output.
* testsuite/gas/mips/crc64-err.l: New test stderr output.
* testsuite/gas/mips/crc.s: New test source.
* testsuite/gas/mips/crc64.s: New test source.
* testsuite/gas/mips/crc-err.s: New test source.
* testsuite/gas/mips/crc64-err.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
include/
2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
Faraz Shahbazker <Faraz.Shahbazker@mips.com>
* elf/mips.h (AFL_ASE_CRC): New macro.
(AFL_ASE_MASK): Update to include AFL_ASE_CRC.
* opcode/mips.h (ASE_CRC): New macro.
* opcode/mips.h (ASE_CRC64): Likewise.
opcodes/
2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
Faraz Shahbazker <Faraz.Shahbazker@mips.com>
* mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
* mips-opc.c (CRC, CRC64): New macros.
(mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
crc32cd for CRC64.
2018-06-13 22:39:05 +08:00
|
|
|
|
2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
|
|
|
|
|
|
Faraz Shahbazker <Faraz.Shahbazker@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* elf/mips.h (AFL_ASE_CRC): New macro.
|
|
|
|
|
|
(AFL_ASE_MASK): Update to include AFL_ASE_CRC.
|
|
|
|
|
|
* opcode/mips.h (ASE_CRC): New macro.
|
|
|
|
|
|
* opcode/mips.h (ASE_CRC64): Likewise.
|
|
|
|
|
|
|
2018-05-25 02:22:14 +08:00
|
|
|
|
2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
|
|
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|
|
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|
|
|
|
|
|
* elf/xtensa.h (xtensa_read_table_entries)
|
|
|
|
|
|
(xtensa_compute_fill_extra_space): New declarations.
|
|
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|
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|
|
2018-06-05 01:01:34 +08:00
|
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|
|
2018-06-04 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
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|
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|
|
|
* diagnostics.h (DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION): Always
|
|
|
|
|
|
define for GCC.
|
|
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|
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|
|
2018-06-04 21:33:07 +08:00
|
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|
|
2018-06-04 H.J. Lu <hongjiu.lu@intel.com>
|
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|
|
|
|
|
|
* diagnostics.h (DIAGNOSTIC_STRINGIFY_1): New.
|
|
|
|
|
|
(DIAGNOSTIC_STRINGIFY): Likewise.
|
|
|
|
|
|
(DIAGNOSTIC_IGNORE): Replace STRINGIFY with DIAGNOSTIC_STRINGIFY.
|
|
|
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|
|
(DIAGNOSTIC_IGNORE_SELF_MOVE): Define empty if not defined.
|
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|
|
|
|
(DIAGNOSTIC_IGNORE_DEPRECATED_REGISTER): Likewise.
|
|
|
|
|
|
(DIAGNOSTIC_IGNORE_UNUSED_FUNCTION): Likewise.
|
|
|
|
|
|
(DIAGNOSTIC_IGNORE_SWITCH_DIFFERENT_ENUM_TYPES): Likewise.
|
|
|
|
|
|
(DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION): New.
|
|
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|
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|
|
2018-06-02 00:38:22 +08:00
|
|
|
|
2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
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|
|
|
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|
|
* diagnostics.h: Moved from ../gdb/common/diagnostics.h.
|
|
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|
|
2018-05-29 02:21:23 +08:00
|
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|
|
2018-05-28 Bernd Edlinger <bernd.edlinger@hotmail.de>
|
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|
|
* splay-tree.h (splay_tree_compare_strings,
|
|
|
|
|
|
splay_tree_delete_pointers): Declare new utility functions.
|
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|
|
Remove fake operand handling for extended mnemonics.
opcodes/
* ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
(insert_bab, extract_bab, insert_btab, extract_btab,
insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
(BAT, BBA VBA RBS XB6S): Delete macros.
(BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
(BB, BD, RBX, XC6): Update for new macros.
(powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
* ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
include/
* opcode/ppc.h (PPC_OPERAND_FAKE): Delete macro.
gas/
* config/tc-ppc.c (md_assemble): Delete handling of fake operands.
* testsuite/gas/ppc/common.s (crmove, cror, or., or, nor., nor): Add
test of extended mnemonics.
* testsuite/gas/ppc/common.d: Likewise. Don't match instruction offset.
* testsuite/gas/ppc/spe.s (evor, evnor): Add test of extended mnemonics.
* testsuite/gas/ppc/spe.d: Likewise. Don't match instruction offset.
2018-05-22 06:31:07 +08:00
|
|
|
|
2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
|
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|
|
|
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|
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|
|
|
* opcode/ppc.h (PPC_OPERAND_FAKE): Delete macro.
|
|
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|
|
2018-05-19 05:03:18 +08:00
|
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|
|
2018-05-18 Kito Cheng <kito.cheng@gmail.com>
|
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|
|
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|
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|
|
* elf/riscv.h (EF_RISCV_RVE): New define.
|
|
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|
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|
|
2018-05-18 22:26:18 +08:00
|
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|
|
2018-05-18 John Darrington <john@darrington.wattle.id.au>
|
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|
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|
|
|
|
|
|
|
|
* elf/s12z.h: New header.
|
|
|
|
|
|
|
Implement Read/Write constraints on system registers on AArch64
This patch adds constraints for read and write only system registers with the
msr and mrs instructions. The code will treat having both flags set and none
set as the same. These flags add constraints that must be matched up. e.g. a
system register with a READ only flag set, can only be used with mrs. If The
constraint fails a warning is emitted.
Examples of the warnings generated:
test.s: Assembler messages:
test.s:5: Warning: specified register cannot be written to at operand 1 -- `msr dbgdtrrx_el0,x3'
test.s:7: Warning: specified register cannot be read from at operand 2 -- `mrs x3,dbgdtrtx_el0'
test.s:8: Warning: specified register cannot be written to at operand 1 -- `msr midr_el1,x3'
and disassembly notes:
0000000000000000 <main>:
0: d5130503 msr dbgdtrtx_el0, x3
4: d5130503 msr dbgdtrtx_el0, x3
8: d5330503 mrs x3, dbgdtrrx_el0
c: d5330503 mrs x3, dbgdtrrx_el0
10: d5180003 msr midr_el1, x3 ; note: writing to a read-only register.
Note that because dbgdtrrx_el0 and dbgdtrtx_el0 have the same encoding, during
disassembly the constraints are use to disambiguate between the two. An exact
constraint match is always prefered over partial ones if available.
As always the warnings can be suppressed with -w and also be made errors using
warnings as errors.
binutils/
PR binutils/21446
* doc/binutils.texi (-M): Document AArch64 options.
gas/
PR binutils/21446
* testsuite/gas/aarch64/illegal-sysreg-2.s: Fix pmbidr_el1 test.
* testsuite/gas/aarch64/illegal-sysreg-2.l: Likewise.
* testsuite/gas/aarch64/illegal-sysreg-2.d: Likewise.
* testsuite/gas/aarch64/sysreg-diagnostic.s: New.
* testsuite/gas/aarch64/sysreg-diagnostic.l: New.
* testsuite/gas/aarch64/sysreg-diagnostic.d: New.
include/
PR binutils/21446
* opcode/aarch64.h (F_SYS_READ, F_SYS_WRITE): New.
opcodes/
PR binutils/21446
* aarch64-asm.c (opintl.h): Include.
(aarch64_ins_sysreg): Enforce read/write constraints.
* aarch64-dis.c (aarch64_ext_sysreg): Likewise.
* aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
(F_REG_READ, F_REG_WRITE): New.
* aarch64-opc.c (aarch64_print_operand): Generate notes for
AARCH64_OPND_SYSREG.
(F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
(aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
* aarch64-tbl.h (aarch64_opcode_table): Add constraints to
msr (F_SYS_WRITE), mrs (F_SYS_READ).
2018-05-15 23:37:20 +08:00
|
|
|
|
2018-05-15 Tamar Christina <tamar.christina@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/21446
|
|
|
|
|
|
* opcode/aarch64.h (F_SYS_READ, F_SYS_WRITE): New.
|
|
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|
|
|
|
2018-05-15 23:34:54 +08:00
|
|
|
|
2018-05-15 Tamar Christina <tamar.christina@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/21446
|
|
|
|
|
|
* opcode/aarch64.h (aarch64_operand_error): Add non_fatal.
|
|
|
|
|
|
(aarch64_print_operand): Support notes.
|
|
|
|
|
|
|
Modify AArch64 Assembly and disassembly functions to be able to fail and report why.
This patch if the first patch in a series to add the ability to add constraints
to system registers that an instruction must adhere to in order for the register
to be usable with that instruction.
These constraints can also be used to disambiguate between registers with the
same encoding during disassembly.
This patch adds a new flags entry in the sysreg structures and ensures it is
filled in and read out during assembly/disassembly. It also adds the ability for
the assemble and disassemble functions to be able to gracefully fail and re-use
the existing error reporting infrastructure.
The return type of these functions are changed to a boolean to denote success or
failure and the error structure is passed around to them. This requires
aarch64-gen changes so a lot of the changes here are just mechanical.
gas/
PR binutils/21446
* config/tc-aarch64.c (parse_sys_reg): Return register flags.
(parse_operands): Fill in register flags.
gdb/
PR binutils/21446
* aarch64-tdep.c (aarch64_analyze_prologue,
aarch64_software_single_step, aarch64_displaced_step_copy_insn):
Indicate not interested in errors.
include/
PR binutils/21446
* opcode/aarch64.h (aarch64_opnd_info): Change sysreg to struct.
(aarch64_decode_insn): Accept error struct.
opcodes/
PR binutils/21446
* aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
and take error struct.
* aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
aarch64_ins_reglist, aarch64_ins_ldst_reglist,
aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
* aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
* aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
aarch64_ext_reglist, aarch64_ext_ldst_reglist,
aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
(determine_disassembling_preference, aarch64_decode_insn,
print_insn_aarch64_word, print_insn_data): Take errors struct.
(print_insn_aarch64): Use errors.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-gen.c (print_operand_inserter): Use errors and change type to
boolean in aarch64_insert_operan.
(print_operand_extractor): Likewise.
* aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
2018-05-15 23:11:42 +08:00
|
|
|
|
2018-05-15 Tamar Christina <tamar.christina@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/21446
|
|
|
|
|
|
* opcode/aarch64.h (aarch64_opnd_info): Change sysreg to struct.
|
|
|
|
|
|
(aarch64_decode_insn): Accept error struct.
|
|
|
|
|
|
|
2018-05-15 20:28:06 +08:00
|
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|
|
2018-05-15 Francois H. Theron <francois.theron@netronome.com>
|
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|
|
|
|
|
|
|
|
|
|
* opcode/nfp.h: Use uint64_t instead of bfd_vma.
|
|
|
|
|
|
|
2018-05-10 19:51:42 +08:00
|
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|
|
2018-05-10 John Darrington <john@darrington.wattle.id.au>
|
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|
|
|
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|
|
|
|
* elf/common.h (EM_S12Z): New macro.
|
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|
|
2018-05-09 14:20:29 +08:00
|
|
|
|
2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
|
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|
|
|
|
|
|
|
|
|
|
* mach-o/unwind.h (MACH_O_UNWIND_X86_64_RBP_FRAME_REGISTERS):
|
|
|
|
|
|
Rename from MACH_O_UNWIND_X86_64_RBP_FRAME_REGSITERS.
|
|
|
|
|
|
(MACH_O_UNWIND_X86_EBP_FRAME_REGISTERS): Rename from
|
|
|
|
|
|
MACH_O_UNWIND_X86_EBP_FRAME_REGSITERS.
|
|
|
|
|
|
|
RISC-V: Add missing hint instructions from RV128I.
gas/
* testsuite/gas/riscv/c-zero-imm.d: Add more tests.
* testsuite/gas/riscv/c-zero-imm.s: Likewise.
* testsuite/gas/riscv/c-zero-reg.d: Fix typo in test. Add disabled
future test for RV128 support.
* testsuite/gas/riscv/c-zero-reg.s: Likewise.
include/
* opcode/riscv-opc.h (MATCH_C_SRLI64, MASK_C_SRLI64): New.
(MATCH_C_SRAI64, MASK_C_SRAI64): New.
(MATCH_C_SLLI64, MASK_C_SLLI64): New.
opcodes/
* riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
(match_c_slli64, match_srxi_as_c_srxi): New.
(riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
<srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
<c.slli, c.srli, c.srai>: Use match_s_slli.
<c.slli64, c.srli64, c.srai64>: New.
2018-05-09 06:46:19 +08:00
|
|
|
|
2018-05-08 Jim Wilson <jimw@sifive.com>
|
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|
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|
|
|
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|
|
* opcode/riscv-opc.h (MATCH_C_SRLI64, MASK_C_SRLI64): New.
|
|
|
|
|
|
(MATCH_C_SRAI64, MASK_C_SRAI64): New.
|
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|
|
|
|
(MATCH_C_SLLI64, MASK_C_SLLI64): New.
|
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|
|
|
|
|
2018-05-07 22:40:59 +08:00
|
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|
|
2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
|
|
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|
|
|
|
|
|
|
|
|
* opcode/ppc.h (powerpc_num_opcodes): Change type to unsigned.
|
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|
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|
|
(vle_num_opcodes): Likewise.
|
|
|
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|
|
(spe2_num_opcodes): Likewise.
|
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|
|
|
|
2018-04-27 08:12:11 +08:00
|
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|
|
2018-05-04 Alan Modra <amodra@gmail.com>
|
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|
|
* ansidecl.h: Import from gcc.
|
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|
|
|
|
* coff/internal.h (struct internal_scnhdr): Add ATTRIBUTE_NONSTRING
|
|
|
|
|
|
to s_name.
|
|
|
|
|
|
(struct internal_syment): Add ATTRIBUTE_NONSTRING to _n_name.
|
|
|
|
|
|
|
2018-05-01 00:02:59 +08:00
|
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|
|
2018-04-30 Francois H. Theron <francois.theron@netronome.com>
|
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|
|
|
|
|
|
|
|
|
|
* dis-asm.h: Added print_nfp_disassembler_options prototype.
|
|
|
|
|
|
* elf/common.h: Added EM_NFP, officially assigned. See Google Group
|
|
|
|
|
|
Generic System V Application Binary Interface.
|
|
|
|
|
|
* elf/nfp.h: New, for NFP support.
|
|
|
|
|
|
* opcode/nfp.h: New, for NFP support.
|
|
|
|
|
|
|
[ARM] Add TLS relocations for FDPIC.
Define and handle TLS relocations for FDPIC in BFD and gas.
In gas, the new relocations are rejected if the --fdpic option was not
specified.
We also define the __tdata_start symbol to mark the start of the
.tdata section. This allows FDPIC static binaries to find the start of
.tdata section, since phdr->p_vaddr of TLS segment is not a valid
value for FDPIC.
2018-04-25 Christophe Lyon <christophe.lyon@st.com>
Mickaël Guêné <mickael.guene@st.com>
bfd/:
* bfd-in2.h (BFD_RELOC_ARM_TLS_GD32_FDPIC)
(BFD_RELOC_ARM_TLS_LDM32_FDPIC, BFD_RELOC_ARM_TLS_IE32_FDPIC): New
relocations.
* elf32-arm.c (elf32_arm_howto_table_2): Add R_ARM_TLS_GD32_FDPIC,
R_ARM_TLS_LDM32_FDPIC, R_ARM_TLS_IE32_FDPIC relocations.
(elf32_arm_reloc_map): Add R_ARM_TLS_GD32_FDPIC,
R_ARM_TLS_LDM32_FDPIC, R_ARM_TLS_IE32_FDPIC.
(struct elf32_arm_link_hash_table): Update comment.
(elf32_arm_final_link_relocate): Handle TLS FDPIC relocations.
(IS_ARM_TLS_RELOC): Likewise.
(elf32_arm_check_relocs): Likewise.
(allocate_dynrelocs_for_symbol): Likewise.
(elf32_arm_size_dynamic_sections): Update comment.
* reloc.c: Add BFD_RELOC_ARM_TLS_GD32_FDPIC,
BFD_RELOC_ARM_TLS_LDM32_FDPIC, BFD_RELOC_ARM_TLS_IE32_FDPIC.
gas/
* config/tc-arm.c (reloc_names): Add TLSGD_FDPIC, TLSLDM_FDPIC,
GOTTPOFF_FDIC relocations.
(md_apply_fix): Handle the new TLS FDPIC relocations.
(tc_gen_reloc): Likewise.
(arm_fix_adjustable): Likewise.
include/
* elf/arm.h: Add R_ARM_TLS_GD32_FDPIC, R_ARM_TLS_LDM32_FDPIC,
R_ARM_TLS_IE32_FDPIC.
ld/
* scripttempl/elf.sc: Define __tdata_start for .tdata section.
2018-03-20 17:55:29 +08:00
|
|
|
|
2018-04-25 Christophe Lyon <christophe.lyon@st.com>
|
|
|
|
|
|
Mickaël Guêné <mickael.guene@st.com>
|
|
|
|
|
|
|
|
|
|
|
|
* elf/arm.h: Add R_ARM_TLS_GD32_FDPIC, R_ARM_TLS_LDM32_FDPIC,
|
|
|
|
|
|
R_ARM_TLS_IE32_FDPIC.
|
|
|
|
|
|
|
[ARM] Add FDPIC relocations definitions
Add FDPIC relocation definitions in BFD and gas.
Gas rejects them if the --fdpic option was not specified.
2018-04-25 Christophe Lyon <christophe.lyon@st.com>
Mickaël Guêné <mickael.guene@st.com>
bfd/
* bfd-in2.c (BFD_RELOC_ARM_GOTFUNCDESC)
(BFD_RELOC_ARM_GOTOFFFUNCDESC, BFD_RELOC_ARM_FUNCDESC)
(BFD_RELOC_ARM_FUNCDESC_VALUE): New.
* elf32-arm.c (elf32_arm_howto_table_2): Add R_ARM_GOTFUNCDESC,
R_ARM_GOTOFFFUNCDESC, R_ARM_FUNCDESC, R_ARM_FUNCDESC_VALUE.
(elf32_arm_howto_from_type): Take new members of
elf32_arm_howto_table_2 into account.
(elf32_arm_reloc_map): Add BFD_RELOC_ARM_GOTFUNCDESC,
BFD_RELOC_ARM_GOTOFFFUNCDESC, BFD_RELOC_ARM_FUNCDESC,
BFD_RELOC_ARM_FUNCDESC_VALUE.
* reloc.c: Add BFD_RELOC_ARM_GOTFUNCDESC,
BFD_RELOC_ARM_GOTOFFFUNCDESC, BFD_RELOC_ARM_FUNCDESC,
BFD_RELOC_ARM_FUNCDESC_VALUE.
gas/
* config/tc-arm.c (reloc_names): Add gotfuncdesc, gotofffuncdesc,
funcdesc.
(md_apply_fix): Support the new relocations.
(tc_gen_reloc): Likewise.
* testsuite/gas/arm/reloc-fdpic.d: New.
* testsuite/gas/arm/reloc-fdpic.s: New.
include/
* elf/arm.h (R_ARM_GOTFUNCDESC, R_ARM_GOTOFFFUNCDESC)
(R_ARM_FUNCDESC)
(R_ARM_FUNCDESC_VALUE): Define new relocations.
2018-03-20 17:54:59 +08:00
|
|
|
|
2018-04-25 Christophe Lyon <christophe.lyon@st.com>
|
|
|
|
|
|
Mickaël Guêné <mickael.guene@st.com>
|
|
|
|
|
|
|
|
|
|
|
|
* elf/arm.h (R_ARM_GOTFUNCDESC, R_ARM_GOTOFFFUNCDESC)
|
|
|
|
|
|
(R_ARM_FUNCDESC)
|
|
|
|
|
|
(R_ARM_FUNCDESC_VALUE): Define new relocations.
|
|
|
|
|
|
|
2018-03-20 17:54:50 +08:00
|
|
|
|
2018-04-25 Christophe Lyon <christophe.lyon@st.com>
|
|
|
|
|
|
Mickaël Guêné <mickael.guene@st.com>
|
|
|
|
|
|
|
|
|
|
|
|
* elf/arm.h (EF_ARM_FDPIC): New.
|
|
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|
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|
|
2018-04-18 14:09:34 +08:00
|
|
|
|
2018-04-18 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* coff/mipspe.h: Delete.
|
|
|
|
|
|
|
2018-04-16 20:44:01 +08:00
|
|
|
|
2018-04-18 Alan Modra <amodra@gmail.com>
|
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|
|
|
|
|
|
|
|
|
* aout/dynix3.h: Delete.
|
|
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|
|
|
|
2018-04-18 08:00:17 +08:00
|
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|
|
2018-04-17 Andrew Sadek <andrew.sadek.se@gmail.com>
|
2018-04-18 05:47:13 +08:00
|
|
|
|
|
|
|
|
|
|
Microblaze Target: PIC data text relative
|
|
|
|
|
|
|
|
|
|
|
|
* bfdlink.h (Add flag): Add new flag @ 'bfd_link_info' struct.
|
|
|
|
|
|
* elf/microblaze.h (Add 3 new relocations):
|
|
|
|
|
|
R_MICROBLAZE_TEXTPCREL_64, R_MICROBLAZE_TEXTREL_64
|
|
|
|
|
|
and R_MICROBLAZE_TEXTREL_32_LO for relax function.
|
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|
|
2018-04-17 07:30:57 +08:00
|
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|
|
2018-04-17 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* elf/i370.h: Revert removal.
|
|
|
|
|
|
* elf/i860.h: Likewise.
|
|
|
|
|
|
* elf/i960.h: Likewise.
|
|
|
|
|
|
|
2018-04-16 18:55:42 +08:00
|
|
|
|
2018-04-16 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* coff/sparc.h: Delete.
|
|
|
|
|
|
|
2018-04-16 14:01:36 +08:00
|
|
|
|
2018-04-16 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aout/host.h: Remove m68k-aout and m68k-coff support.
|
|
|
|
|
|
* aout/hp300hpux.h: Delete.
|
|
|
|
|
|
* coff/apollo.h: Delete.
|
|
|
|
|
|
* coff/aux-coff.h: Delete.
|
|
|
|
|
|
* coff/m68k.h: Delete.
|
|
|
|
|
|
|
2018-04-16 13:59:39 +08:00
|
|
|
|
2018-04-16 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* dis-asm.h: Remove sh5 and sh64 support.
|
|
|
|
|
|
|
2018-04-16 13:56:05 +08:00
|
|
|
|
2018-04-16 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
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|
|
* coff/internal.h: Remove w65 support.
|
|
|
|
|
|
* coff/w65.h: Delete.
|
|
|
|
|
|
|
2018-04-16 13:54:43 +08:00
|
|
|
|
2018-04-16 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* coff/we32k.h: Delete.
|
|
|
|
|
|
|
2018-04-16 13:53:38 +08:00
|
|
|
|
2018-04-16 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* coff/internal.h: Remove m88k support.
|
|
|
|
|
|
* coff/m88k.h: Delete.
|
|
|
|
|
|
* opcode/m88k.h: Delete.
|
|
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|
|
|
|
2018-04-16 13:51:56 +08:00
|
|
|
|
2018-04-16 Alan Modra <amodra@gmail.com>
|
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|
* elf/i370.h: Delete.
|
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|
* opcode/i370.h: Delete.
|
|
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|
|
2018-04-16 13:49:41 +08:00
|
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|
|
2018-04-16 Alan Modra <amodra@gmail.com>
|
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|
|
* coff/h8500.h: Delete.
|
|
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|
|
|
* coff/internal.h: Remove h8500 support.
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2018-04-16 13:47:57 +08:00
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|
2018-04-16 Alan Modra <amodra@gmail.com>
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* coff/h8300.h: Delete.
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2018-04-16 13:46:00 +08:00
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2018-04-16 Alan Modra <amodra@gmail.com>
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* ieee.h: Delete.
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2018-04-16 13:43:07 +08:00
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2018-04-16 Alan Modra <amodra@gmail.com>
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* aout/host.h: Remove newsos3 support.
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2018-04-16 13:41:22 +08:00
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|
2018-04-16 Alan Modra <amodra@gmail.com>
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* nlm/ChangeLog-9315: Delete.
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* nlm/alpha-ext.h: Delete.
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* nlm/common.h: Delete.
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* nlm/external.h: Delete.
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* nlm/i386-ext.h: Delete.
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* nlm/internal.h: Delete.
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* nlm/ppc-ext.h: Delete.
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* nlm/sparc32-ext.h: Delete.
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2018-04-16 13:38:40 +08:00
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|
2018-04-16 Alan Modra <amodra@gmail.com>
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* opcode/tahoe.h: Delete.
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|
Remove i860, i960, bout and aout-adobe targets
Plus remove a few leftovers from the 29k support.
include/
* aout/adobe.h: Delete.
* aout/reloc.h: Delete.
* coff/i860.h: Delete.
* coff/i960.h: Delete.
* elf/i860.h: Delete.
* elf/i960.h: Delete.
* opcode/i860.h: Delete.
* opcode/i960.h: Delete.
* aout/aout64.h (enum reloc_type): Trim off 29k and other unused values.
* aout/ar.h (ARMAGB): Remove.
* coff/internal.h (struct internal_aouthdr, struct internal_scnhdr,
union internal_auxent): Remove i960 support.
bfd/
* aout-adobe.c: Delete.
* bout.c: Delete.
* coff-i860.c: Delete.
* coff-i960.c: Delete.
* cpu-i860.c: Delete.
* cpu-i960.c: Delete.
* elf32-i860.c: Delete.
* elf32-i960.c: Delete.
* hosts/i860mach3.h: Delete.
* Makefile.am: Remove i860, i960, bout, and adobe support.
* archures.c: Remove i860 and i960 support.
* coffcode.h: Likewise.
* reloc.c: Likewise.
* aoutx.h: Comment updates.
* archive.c: Remove BOUT and i960 support.
* bfd.c: Remove BOUT support.
* coffswap.h: Remove i960 support.
* config.bfd: Remove i860, i960 and adobe targets.
* configure.ac: Remove adode, bout, i860, i960, icoff targets.
* targets.c: Likewise.
* ieee.c: Remove i960 support.
* mach-o.c: Remove i860 support.
* Makefile.in: Regenerate.
* bfd-in2.h: Regenerate.
* configure: Regenerate.
* libbfd.h: Regenerate.
* po/SRC-POTFILES.in: Regenerate.
opcodes/
* opcodes/i860-dis.c: Delete.
* opcodes/i960-dis.c: Delete.
* Makefile.am: Remove i860 and i960 support.
* configure.ac: Likewise.
* disassemble.c: Likewise.
* disassemble.h: Likewise.
* Makefile.in: Regenerate.
* configure: Regenerate.
* po/POTFILES.in: Regenerate.
binutils/
* ieee.c: Remove i960 support.
* od-macho.c: Remove i860 support.
* readelf.c: Remove i860 and i960 support.
* testsuite/binutils-all/objcopy.exp: Likewise.
* testsuite/binutils-all/objdump.exp: Likewise.
* testsuite/lib/binutils-common.exp: Likewise.
gas/
* config/aout_gnu.h: Delete.
* config/tc-i860.c: Delete.
* config/tc-i860.h: Delete.
* config/tc-i960.c: Delete.
* config/tc-i960.h: Delete.
* doc/c-i860.texi: Delete.
* doc/c-i960.texi: Delete.
* testsuite/gas/i860/README.i860: Delete.
* testsuite/gas/i860/bitwise.d: Delete.
* testsuite/gas/i860/bitwise.s: Delete.
* testsuite/gas/i860/branch.d: Delete.
* testsuite/gas/i860/branch.s: Delete.
* testsuite/gas/i860/bte.d: Delete.
* testsuite/gas/i860/bte.s: Delete.
* testsuite/gas/i860/dir-align01.d: Delete.
* testsuite/gas/i860/dir-align01.s: Delete.
* testsuite/gas/i860/dir-intel01.d: Delete.
* testsuite/gas/i860/dir-intel01.s: Delete.
* testsuite/gas/i860/dir-intel02.d: Delete.
* testsuite/gas/i860/dir-intel02.s: Delete.
* testsuite/gas/i860/dir-intel03-err.l: Delete.
* testsuite/gas/i860/dir-intel03-err.s: Delete.
* testsuite/gas/i860/dual01.d: Delete.
* testsuite/gas/i860/dual01.s: Delete.
* testsuite/gas/i860/dual02-err.l: Delete.
* testsuite/gas/i860/dual02-err.s: Delete.
* testsuite/gas/i860/dual03.d: Delete.
* testsuite/gas/i860/dual03.s: Delete.
* testsuite/gas/i860/fldst01.d: Delete.
* testsuite/gas/i860/fldst01.s: Delete.
* testsuite/gas/i860/fldst02.d: Delete.
* testsuite/gas/i860/fldst02.s: Delete.
* testsuite/gas/i860/fldst03.d: Delete.
* testsuite/gas/i860/fldst03.s: Delete.
* testsuite/gas/i860/fldst04.d: Delete.
* testsuite/gas/i860/fldst04.s: Delete.
* testsuite/gas/i860/fldst05.d: Delete.
* testsuite/gas/i860/fldst05.s: Delete.
* testsuite/gas/i860/fldst06.d: Delete.
* testsuite/gas/i860/fldst06.s: Delete.
* testsuite/gas/i860/fldst07.d: Delete.
* testsuite/gas/i860/fldst07.s: Delete.
* testsuite/gas/i860/fldst08.d: Delete.
* testsuite/gas/i860/fldst08.s: Delete.
* testsuite/gas/i860/float01.d: Delete.
* testsuite/gas/i860/float01.s: Delete.
* testsuite/gas/i860/float02.d: Delete.
* testsuite/gas/i860/float02.s: Delete.
* testsuite/gas/i860/float03.d: Delete.
* testsuite/gas/i860/float03.s: Delete.
* testsuite/gas/i860/float04.d: Delete.
* testsuite/gas/i860/float04.s: Delete.
* testsuite/gas/i860/form.d: Delete.
* testsuite/gas/i860/form.s: Delete.
* testsuite/gas/i860/i860.exp: Delete.
* testsuite/gas/i860/iarith.d: Delete.
* testsuite/gas/i860/iarith.s: Delete.
* testsuite/gas/i860/ldst01.d: Delete.
* testsuite/gas/i860/ldst01.s: Delete.
* testsuite/gas/i860/ldst02.d: Delete.
* testsuite/gas/i860/ldst02.s: Delete.
* testsuite/gas/i860/ldst03.d: Delete.
* testsuite/gas/i860/ldst03.s: Delete.
* testsuite/gas/i860/ldst04.d: Delete.
* testsuite/gas/i860/ldst04.s: Delete.
* testsuite/gas/i860/ldst05.d: Delete.
* testsuite/gas/i860/ldst05.s: Delete.
* testsuite/gas/i860/ldst06.d: Delete.
* testsuite/gas/i860/ldst06.s: Delete.
* testsuite/gas/i860/pfam.d: Delete.
* testsuite/gas/i860/pfam.s: Delete.
* testsuite/gas/i860/pfmam.d: Delete.
* testsuite/gas/i860/pfmam.s: Delete.
* testsuite/gas/i860/pfmsm.d: Delete.
* testsuite/gas/i860/pfmsm.s: Delete.
* testsuite/gas/i860/pfsm.d: Delete.
* testsuite/gas/i860/pfsm.s: Delete.
* testsuite/gas/i860/pseudo-ops01.d: Delete.
* testsuite/gas/i860/pseudo-ops01.s: Delete.
* testsuite/gas/i860/regress01.d: Delete.
* testsuite/gas/i860/regress01.s: Delete.
* testsuite/gas/i860/shift.d: Delete.
* testsuite/gas/i860/shift.s: Delete.
* testsuite/gas/i860/simd.d: Delete.
* testsuite/gas/i860/simd.s: Delete.
* testsuite/gas/i860/system.d: Delete.
* testsuite/gas/i860/system.s: Delete.
* testsuite/gas/i860/xp.d: Delete.
* testsuite/gas/i860/xp.s: Delete.
* Makefile.am: Remove i860 and i960 support.
* configure.tgt: Likewise.
* doc/Makefile.am: Likewise.
* doc/all.texi: Likewise.
* testsuite/gas/all/gas.exp
* config/obj-coff.h: Remove i960 support.
* doc/internals.texi: Likewise.
* expr.c: Likewise.
* read.c: Likewise.
* write.c: Likewise.
* write.h: Likewise.
* testsuite/gas/lns/lns.exp: Likewise.
* testsuite/gas/symver/symver.exp: Likewise.
* config/tc-m68k.c: Remove BOUT support.
* config/tc-score.c: Likewise.
* config/tc-score7.c: Likewise.
* config/tc-sparc.c: Likewise.
* symbols.c: Likewise.
* doc/h8.texi: Likewise.
* configure.ac: Remove BOUT and i860 support.
* doc/as.texinfo: Remove BOUT, i860 and i960 support
* Makefile.in: Regenerate.
* config.in: Regenerate.
* configure: Regenerate.
* doc/Makefile.in: Regenerate.
* po/POTFILES.in: Regenerate.
ld/
* emulparams/coff_i860.sh: Delete.
* emulparams/elf32_i860.sh: Delete.
* emulparams/elf32_i960.sh: Delete.
* emulparams/gld960.sh: Delete.
* emulparams/gld960coff.sh: Delete.
* emulparams/lnk960.sh: Delete.
* emultempl/gld960.em: Delete.
* emultempl/gld960c.em: Delete.
* emultempl/lnk960.em: Delete.
* scripttempl/i860coff.sc: Delete.
* scripttempl/i960.sc: Delete.
* ld.texinfo: Remove i960 support.
* Makefile.am: Remove i860 and i960 support.
* configure.tgt: Likewise.
* testsuite/ld-discard/extern.d: Likewise.
* testsuite/ld-discard/start.d: Likewise.
* testsuite/ld-discard/static.d: Likewise.
* testsuite/ld-elf/compressed1d.d: Likewise.
* testsuite/ld-elf/group1.d: Likewise.
* testsuite/ld-elf/group3b.d: Likewise.
* testsuite/ld-elf/group8a.d: Likewise.
* testsuite/ld-elf/group8b.d: Likewise.
* testsuite/ld-elf/group9a.d: Likewise.
* testsuite/ld-elf/group9b.d: Likewise.
* testsuite/ld-elf/linkonce2.d: Likewise.
* testsuite/ld-elf/merge.d: Likewise.
* testsuite/ld-elf/merge2.d: Likewise.
* testsuite/ld-elf/merge3.d: Likewise.
* testsuite/ld-elf/orphan-10.d: Likewise.
* testsuite/ld-elf/orphan-11.d: Likewise.
* testsuite/ld-elf/orphan-12.d: Likewise.
* testsuite/ld-elf/orphan-9.d: Likewise.
* testsuite/ld-elf/orphan-region.d: Likewise.
* testsuite/ld-elf/orphan.d: Likewise.
* testsuite/ld-elf/orphan3.d: Likewise.
* testsuite/ld-elf/pr12851.d: Likewise.
* testsuite/ld-elf/pr12975.d: Likewise.
* testsuite/ld-elf/pr13177.d: Likewise.
* testsuite/ld-elf/pr13195.d: Likewise.
* testsuite/ld-elf/pr17550a.d: Likewise.
* testsuite/ld-elf/pr17550b.d: Likewise.
* testsuite/ld-elf/pr17550c.d: Likewise.
* testsuite/ld-elf/pr17550d.d: Likewise.
* testsuite/ld-elf/pr17615.d: Likewise.
* testsuite/ld-elf/pr20528a.d: Likewise.
* testsuite/ld-elf/pr20528b.d: Likewise.
* testsuite/ld-elf/pr21562a.d: Likewise.
* testsuite/ld-elf/pr21562b.d: Likewise.
* testsuite/ld-elf/pr21562c.d: Likewise.
* testsuite/ld-elf/pr21562d.d: Likewise.
* testsuite/ld-elf/pr21562i.d: Likewise.
* testsuite/ld-elf/pr21562j.d: Likewise.
* testsuite/ld-elf/pr21562k.d: Likewise.
* testsuite/ld-elf/pr21562l.d: Likewise.
* testsuite/ld-elf/pr21562m.d: Likewise.
* testsuite/ld-elf/pr21562n.d: Likewise.
* testsuite/ld-elf/pr22677.d: Likewise.
* testsuite/ld-elf/pr22836-1a.d: Likewise.
* testsuite/ld-elf/pr22836-1b.d: Likewise.
* testsuite/ld-elf/pr349.d: Likewise.
* testsuite/ld-elf/sec-to-seg.exp: Likewise.
* testsuite/ld-elf/sec64k.exp: Likewise.
* testsuite/ld-elf/warn1.d: Likewise.
* testsuite/ld-elf/warn2.d: Likewise.
* testsuite/ld-elf/warn3.d: Likewise.
* testsuite/lib/ld-lib.exp: Likewise.
* Makefile.in: Regenerate.
* po/BLD-POTFILES.in: Regenerate.
2018-04-11 17:16:05 +08:00
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|
|
2018-04-11 Alan Modra <amodra@gmail.com>
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* aout/adobe.h: Delete.
|
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* aout/reloc.h: Delete.
|
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* coff/i860.h: Delete.
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* coff/i960.h: Delete.
|
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|
* elf/i860.h: Delete.
|
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* elf/i960.h: Delete.
|
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|
* opcode/i860.h: Delete.
|
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|
|
|
* opcode/i960.h: Delete.
|
|
|
|
|
|
* aout/aout64.h (enum reloc_type): Trim off 29k and other unused values.
|
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|
|
|
* aout/ar.h (ARMAGB): Remove.
|
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|
|
* coff/internal.h (struct internal_aouthdr, struct internal_scnhdr,
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|
|
|
|
union internal_auxent): Remove i960 support.
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|
PowerPC inline PLT call support
In addition to the existing relocs we need two more to mark all
instructions in the call sequence, PLTCALL on the call itself (plus
the toc restore insn for ppc64), and PLTSEQ on others. All
relocations in a particular sequence have the same symbol.
Example ppc64 ELFv2 assembly:
.reloc .,R_PPC64_PLTSEQ,puts
std 2,24(1)
addis 12,2,puts@plt@ha # .reloc .,R_PPC64_PLT16_HA,puts
ld 12,puts@plt@l(12) # .reloc .,R_PPC64_PLT16_LO_DS,puts
.reloc .,R_PPC64_PLTSEQ,puts
mtctr 12
.reloc .,R_PPC64_PLTCALL,puts
bctrl
ld 2,24(1)
Example ppc32 -fPIC assembly:
addis 12,30,puts+32768@plt@ha # .reloc .,R_PPC_PLT16_HA,puts+0x8000
lwz 12,12,puts+32768@plt@l # .reloc .,R_PPC_PLT16_LO,puts+0x8000
.reloc .,R_PPC_PLTSEQ,puts+32768
mtctr 12
.reloc .,R_PPC_PLTCALL,puts+32768
bctrl
Marking sequences like this allows the linker to convert them to nops
and a direct call if the target symbol turns out to be local.
When the call is __tls_get_addr, each relocation shown above is paired
with an R_PPC*_TLSLD or R_PPC*_TLSGD reloc to additionally mark the
sequence for possible TLS optimization. The TLSLD or TLSGD relocs are
emitted first.
include/
* elf/ppc.h (R_PPC_PLTSEQ, R_PPC_PLTCALL): Define.
* elf/ppc64.h (R_PPC64_PLTSEQ, R_PPC64_PLTCALL): Define.
bfd/
* elf32-ppc.c (ppc_elf_howto_raw): Add PLTSEQ and PLTCALL howtos.
(is_plt_seq_reloc): New function.
(ppc_elf_check_relocs): Handle PLTSEQ and PLTCALL relocs.
(ppc_elf_tls_optimize): Handle inline plt call sequence.
(ppc_elf_relax_section): Handle PLTCALL reloc.
(ppc_elf_relocate_section): Nop out inline plt call sequence when
resolving locally.
* elf64-ppc.c (ppc64_elf_howto_raw): Add R_PPC64_PLTSEQ and
R_PPC64_PLTCALL entries. Comment R_PPC64_TOCSAVE.
(has_tls_get_addr_call): Correct comment.
(is_branch_reloc): Add PLTCALL.
(is_plt_seq_reloc): New function.
(ppc64_elf_check_relocs): Handle PLT16_LO_DS reloc. Set
has_tls_reloc for R_PPC64_TLSGD and R_PPC64_TLSLD. Create plt
entry for R_PPC64_PLTCALL.
(ppc64_elf_tls_optimize): Handle inline plt call sequence.
(ppc_type_of_stub): Handle PLTCALL reloc.
(toc_adjusting_stub_needed): Likewise.
(ppc64_elf_relocate_section): Set "can_plt_call" for PLTCALL
reloc insn. Nop out inline plt call sequence when resolving
locally. Handle __tls_get_addr inline plt call optimization.
elfcpp/
* powerpc.h (R_POWERPC_PLTSEQ, R_POWERPC_PLTCALL): Define.
gold/
* powerpc.cc (Target_powerpc::Track_tls::maybe_skip_tls_get_addr_call):
Handle inline plt sequence relocs.
(Stub_table::Plt_stub_key::Plt_stub_key): Likewise.
(Target_powerpc::Scan::reloc_needs_plt_for_ifunc): Likewise.
(Target_powerpc::Relocate::relocate): Likewise.
2018-04-09 07:55:10 +08:00
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|
2018-04-09 Alan Modra <amodra@gmail.com>
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* elf/ppc.h (R_PPC_PLTSEQ, R_PPC_PLTCALL): Define.
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|
* elf/ppc64.h (R_PPC64_PLTSEQ, R_PPC64_PLTCALL): Define.
|
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|
2018-03-29 01:03:55 +08:00
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|
2018-03-28 Renlin Li <renlin.li@arm.com>
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PR ld/22970
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* elf/aarch64.h: Add relocation number for
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|
R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12,
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R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12_NC,
|
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R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12,
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R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12_NC,
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R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12,
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R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12_NC,
|
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R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12,
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R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12_NC.
|
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|
2018-03-28 16:44:45 +08:00
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|
2018-03-28 Nick Clifton <nickc@redhat.com>
|
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|
PR 22988
|
|
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|
|
* opcode/aarch64.h (enum aarch64_opnd): Add
|
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|
|
AARCH64_OPND_SVE_ADDR_R.
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2018-03-22 03:55:40 +08:00
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2018-03-21 H.J. Lu <hongjiu.lu@intel.com>
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|
* elf/common.h (DF_1_KMOD): New.
|
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|
(DF_1_WEAKFILTER): Likewise.
|
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|
(DF_1_NOCOMMON): Likewise.
|
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|
2018-03-15 07:04:03 +08:00
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|
2018-03-14 Kito Cheng <kito.cheng@gmail.com>
|
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|
* opcode/riscv.h (OP_MASK_FUNCT3): New.
|
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|
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|
|
(OP_SH_FUNCT3): Likewise.
|
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|
(OP_MASK_FUNCT7): Likewise.
|
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|
(OP_SH_FUNCT7): Likewise.
|
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|
(OP_MASK_OP2): Likewise.
|
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|
|
(OP_SH_OP2): Likewise.
|
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|
(OP_MASK_CFUNCT4): Likewise.
|
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|
(OP_SH_CFUNCT4): Likewise.
|
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|
(OP_MASK_CFUNCT3): Likewise.
|
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|
(OP_SH_CFUNCT3): Likewise.
|
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|
|
(riscv_insn_types): Likewise.
|
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|
2018-03-13 22:02:52 +08:00
|
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|
|
2018-03-13 Nick Clifton <nickc@redhat.com>
|
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|
|
PR 22113
|
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|
* coff/pe.h (struct pex64_unwind_info): Add a rawUnwindCodesEnd
|
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field.
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2018-03-08 22:31:32 +08:00
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2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
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* opcode/i386 (OLDGCC_COMPAT): Removed.
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2018-02-28 00:40:45 +08:00
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2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
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* opcode/arm.h (ARM_FEATURE_COPY): Remove macro definition.
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2018-02-21 04:51:36 +08:00
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2018-02-20 Maciej W. Rozycki <macro@mips.com>
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* opcode/mips.h: Remove `M' operand code.
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2018-02-12 21:12:45 +08:00
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2018-02-12 Zebediah Figura <z.figura12@gmail.com>
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* coff/msdos.h: New header.
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* coff/pe.h: Move common defines to msdos.h.
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* coff/powerpc.h: Likewise.
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2018-01-13 21:26:38 +08:00
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2018-01-13 Nick Clifton <nickc@redhat.com>
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2.30 branch created.
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2018-01-12 11:01:39 +08:00
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2018-01-11 H.J. Lu <hongjiu.lu@intel.com>
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PR ld/22393
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* bfdlink.h (bfd_link_info): Add separate_code.
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2018-01-05 06:17:53 +08:00
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2018-01-04 Jim Wilson <jimw@sifive.com>
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* opcode/riscv-opc.h (CSR_SBADADDR): Rename to CSR_STVAL. Rename
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DECLARE_CSR entry. Add alias to map sbadaddr to CSR_STVAL.
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(CSR_MBADADDR): Rename to CSR_MTVAL. Rename DECLARE_CSR entry.
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Add alias to map mbadaddr to CSR_MTVAL.
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2018-01-03 13:17:27 +08:00
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2018-01-03 Alan Modra <amodra@gmail.com>
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Update year range in copyright notice of all files.
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2018-01-03 13:15:17 +08:00
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For older changes see ChangeLog-2017
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2016-01-01 18:44:31 +08:00
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2018-01-03 13:15:17 +08:00
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Copyright (C) 2018 Free Software Foundation, Inc.
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2016-01-01 18:44:31 +08:00
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved.
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Local Variables:
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mode: change-log
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left-margin: 8
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fill-column: 74
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version-control: never
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End:
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