2015-04-27 16:29:16 +08:00
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2015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
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* s390-opc.c: New instruction type VV0UU2.
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* s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
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and WFC.
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x86: disambiguate disassembly of certain AVX512 insns
Certain conversion operations as well as vfpclassp{d,s} are ambiguous
when the input operand is in memory and no broadcast is being used.
While in Intel mode this gets resolved by printing suitable operand
size modifiers, AT&T mode need mnemonic suffixes to be added.
gas/testsuite/
2015-04-23 Jan Beulich <jbeulich@suse.com>
* gas/i386/avx512dq.d: Add 'z' suffix to vfpclassp{d,s} non-
register, non-broadcast cases.
* gas/i386/x86-64-avx512dq.d: Likewise.
* gas/i386/avx512dq_vl.d: Add 'x' and 'y' suffixes to
vcvt{,u}qq2ps and vfpclassp{d,s} non-register, non-broadcast
cases.
* gas/i386/x86-64-avx512dq_vl.d: Likewise.
* gas/i386/avx512f_vl.d: Add 'x' and 'y' suffixes to
vcvt{,t}pd2{,u}dq and vcvtpd2ps non-register, non-broadcast
cases.
* gas/i386/x86-64-avx512f_vl.d: Likewise.
opcodes/
2015-04-23 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
* i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
(vfpclasspd, vfpclassps): Add %XZ.
2015-04-23 22:42:40 +08:00
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2015-04-23 Jan Beulich <jbeulich@suse.com>
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* i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
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* i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
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vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
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(vfpclasspd, vfpclassps): Add %XZ.
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2015-04-16 06:58:45 +08:00
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2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (PREFIX_UD_SHIFT): Removed.
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(PREFIX_UD_REPZ): Likewise.
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(PREFIX_UD_REPNZ): Likewise.
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(PREFIX_UD_DATA): Likewise.
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(PREFIX_UD_ADDR): Likewise.
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(PREFIX_UD_LOCK): Likewise.
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2015-04-16 02:28:16 +08:00
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2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (prefix_requirement): Removed.
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(print_insn): Don't set prefix_requirement. Check
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dp->prefix_requirement instead of prefix_requirement.
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2015-04-16 00:53:13 +08:00
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2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
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PR binutils/17898
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* i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
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(PREFIX_MOD_0_0FC7_REG_6): This.
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(PREFIX_MOD_3_0FC7_REG_6): New.
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(PREFIX_MOD_3_0FC7_REG_7): Likewise.
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(prefix_table): Replace PREFIX_0FC7_REG_6 with
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PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
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PREFIX_MOD_3_0FC7_REG_7.
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(mod_table): Replace PREFIX_0FC7_REG_6 with
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PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
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PREFIX_MOD_3_0FC7_REG_7.
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2015-04-16 00:24:45 +08:00
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2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
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(PREFIX_MANDATORY_REPNZ): Likewise.
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(PREFIX_MANDATORY_DATA): Likewise.
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(PREFIX_MANDATORY_ADDR): Likewise.
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(PREFIX_MANDATORY_LOCK): Likewise.
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(PREFIX_MANDATORY): Likewise.
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(PREFIX_UD_SHIFT): Set to 8
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(PREFIX_UD_REPZ): Updated.
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(PREFIX_UD_REPNZ): Likewise.
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(PREFIX_UD_DATA): Likewise.
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(PREFIX_UD_ADDR): Likewise.
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(PREFIX_UD_LOCK): Likewise.
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(PREFIX_IGNORED_SHIFT): New.
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(PREFIX_IGNORED_REPZ): Likewise.
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(PREFIX_IGNORED_REPNZ): Likewise.
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(PREFIX_IGNORED_DATA): Likewise.
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(PREFIX_IGNORED_ADDR): Likewise.
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(PREFIX_IGNORED_LOCK): Likewise.
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(PREFIX_OPCODE): Likewise.
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(PREFIX_IGNORED): Likewise.
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(Bad_Opcode): Replace PREFIX_MANDATORY with 0.
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(dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
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(three_byte_table): Likewise.
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(mod_table): Likewise.
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(mandatory_prefix): Renamed to ...
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(prefix_requirement): This.
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(prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
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Update PREFIX_90 entry.
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(get_valid_dis386): Check prefix_requirement to see if a prefix
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should be ignored.
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(print_insn): Replace mandatory_prefix with prefix_requirement.
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2015-04-16 00:44:03 +08:00
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2015-04-15 Renlin Li <renlin.li@arm.com>
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* arm-dis.c (thumb32_opcodes): Define 'D' format control code,
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use it for ssat and ssat16.
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(print_insn_thumb32): Add handle case for 'D' control code.
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x86: Use individual prefix control for each opcode.
2015-04-06 Ilya Tocar <ilya.tocar@intel.com>
H.J. Lu <hongjiu.lu@intel.com>
* i386-dis-evex.h (evex_table): Fill prefix_requirement field.
* i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_OPTIONAL, PREFIX_MANDATORY):
Define.
(Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
Fill prefix_requirement field.
(struct dis386): Add prefix_requirement field.
(dis386): Fill prefix_requirement field.
(dis386_twobyte): Ditto.
(twobyte_has_mandatory_prefix_: Remove.
(reg_table): Fill prefix_requirement field.
(prefix_table): Ditto.
(x86_64_table): Ditto.
(three_byte_table): Ditto.
(xop_table): Ditto.
(vex_table): Ditto.
(vex_len_table): Ditto.
(vex_w_table): Ditto.
(mod_table): Ditto.
(bad_opcode): Ditto.
(print_insn): Use prefix_requirement.
(FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
(float_reg): Ditto.
2015-04-07 00:33:01 +08:00
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2015-04-06 Ilya Tocar <ilya.tocar@intel.com>
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H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis-evex.h (evex_table): Fill prefix_requirement field.
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* i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
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PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
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PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
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PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
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(Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
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Fill prefix_requirement field.
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(struct dis386): Add prefix_requirement field.
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(dis386): Fill prefix_requirement field.
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(dis386_twobyte): Ditto.
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(twobyte_has_mandatory_prefix_: Remove.
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(reg_table): Fill prefix_requirement field.
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(prefix_table): Ditto.
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(x86_64_table): Ditto.
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(three_byte_table): Ditto.
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(xop_table): Ditto.
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(vex_table): Ditto.
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(vex_len_table): Ditto.
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(vex_w_table): Ditto.
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(mod_table): Ditto.
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(bad_opcode): Ditto.
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(print_insn): Use prefix_requirement.
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(FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
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FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
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(float_reg): Ditto.
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2015-03-30 13:40:09 +08:00
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2015-03-30 Mike Frysinger <vapier@gentoo.org>
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* d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
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2015-03-29 22:46:30 +08:00
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2015-03-29 H.J. Lu <hongjiu.lu@intel.com>
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* Makefile.in: Regenerated.
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2015-03-25 10:44:28 +08:00
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2015-03-25 Anton Blanchard <anton@samba.org>
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* ppc-dis.c (disassemble_init_powerpc): Only initialise
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powerpc_opcd_indices and vle_opcd_indices once.
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2015-03-25 10:43:18 +08:00
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2015-03-25 Anton Blanchard <anton@samba.org>
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* ppc-opc.c (powerpc_opcodes): Add slbfee.
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2015-03-24 14:08:08 +08:00
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2015-03-24 Terry Guo <terry.guo@arm.com>
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* arm-dis.c (opcode32): Updated to use new arm feature struct.
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(opcode16): Likewise.
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(coprocessor_opcodes): Replace bit with feature struct.
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(neon_opcodes): Likewise.
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(arm_opcodes): Likewise.
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(thumb_opcodes): Likewise.
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(thumb32_opcodes): Likewise.
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(print_insn_coprocessor): Likewise.
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(print_insn_arm): Likewise.
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(select_arm_features): Follow new feature struct.
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2015-03-18 00:19:15 +08:00
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2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
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* i386-dis.c (rm_table): Add clzero.
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* i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
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Add CPU_CLZERO_FLAGS.
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(cpu_flags): Add CpuCLZERO.
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* i386-opc.h: Add CpuCLZERO.
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* i386-opc.tbl: Add clzero.
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* i386-init.h: Re-generated.
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* i386-tbl.h: Re-generated.
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2015-03-14 06:42:55 +08:00
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2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
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* mips-opc.c (decode_mips_operand): Fix constraint issues
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with u and y operands.
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2015-03-14 06:02:16 +08:00
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2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
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* mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
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2015-03-10 19:44:54 +08:00
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2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
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* s390-opc.c: Add new IBM z13 instructions.
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* s390-opc.txt: Likewise.
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2015-03-10 19:27:56 +08:00
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2015-03-10 Renlin Li <renlin.li@arm.com>
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* aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
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stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
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related alias.
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* aarch64-asm-2.c: Regenerate.
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* aarch64-dis-2.c: Likewise.
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* aarch64-opc-2.c: Likewise.
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2015-03-03 23:00:59 +08:00
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2015-03-03 Jiong Wang <jiong.wang@arm.com>
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* arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
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2015-02-26 04:22:54 +08:00
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2015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
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* sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
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arch_sh_up.
|
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|
|
(pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
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arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
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|
2015-02-24 01:16:30 +08:00
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|
2015-02-23 Vinay <Vinay.G@kpit.com>
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* rl78-decode.opc (MOV): Added space between two operands for
|
|
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|
|
'mov' instruction in index addressing mode.
|
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|
|
* rl78-decode.c: Regenerate.
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|
2015-02-12 17:59:03 +08:00
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|
2015-02-19 Pedro Alves <palves@redhat.com>
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* microblaze-dis.h [__cplusplus]: Wrap in extern "C".
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|
|
opcodes/microblaze: Rename 'or', 'and', 'xor' to avoid C++ conflict
Building GDB as a C++ program, we see:
In file included from gdb/microblaze-tdep.c:37:0:
gdb/../opcodes/../opcodes/microblaze-opcm.h: At global scope:
gdb/../opcodes/../opcodes/microblaze-opcm.h:32:51: error: expected identifier before ‘or’ token
ncget, ncput, muli, bslli, bsrai, bsrli, mului, or, and, xor,
^
gdb/../opcodes/../opcodes/microblaze-opcm.h:32:51: error: expected ‘}’ before ‘or’ token
gdb/../opcodes/../opcodes/microblaze-opcm.h:32:51: error: expected unqualified-id before ‘or’ token
gdb/../opcodes/../opcodes/microblaze-opcm.h:60:1: error: expected declaration before ‘}’ token
};
^
opcodes/ChangeLog:
2015-02-10 Pedro Alves <palves@redhat.com>
Tom Tromey <tromey@redhat.com>
* microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
microblaze_and, microblaze_xor.
* microblaze-opc.h (opcodes): Adjust.
2015-02-11 02:09:39 +08:00
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|
2015-02-10 Pedro Alves <palves@redhat.com>
|
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|
|
Tom Tromey <tromey@redhat.com>
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|
|
* microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
|
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|
|
microblaze_and, microblaze_xor.
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|
|
* microblaze-opc.h (opcodes): Adjust.
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|
|
2015-01-28 13:06:43 +08:00
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2015-01-28 James Bowman <james.bowman@ftdichip.com>
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* Makefile.am: Add FT32 files.
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* configure.ac: Handle FT32.
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* disassemble.c (disassembler): Call print_insn_ft32.
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* ft32-dis.c: New file.
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* ft32-opc.c: New file.
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* Makefile.in: Regenerate.
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* configure: Regenerate.
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* po/POTFILES.in: Regenerate.
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2015-01-28 09:12:59 +08:00
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2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
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* nds32-asm.c (keyword_sr): Add new system registers.
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2015-01-16 19:19:21 +08:00
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2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
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* s390-dis.c (s390_extract_operand): Support vector register
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operands.
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(s390_print_insn_with_opcode): Support new operands types and add
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new handling of optional operands.
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* s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
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and include opcode/s390.h instead.
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(struct op_struct): New field `flags'.
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(insertOpcode, insertExpandedMnemonic): New parameter `flags'.
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(dumpTable): Dump flags.
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(main): Parse flags from the s390-opc.txt file. Add z13 as cpu
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string.
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* s390-opc.c: Add new operands types, instruction formats, and
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instruction masks.
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(s390_opformats): Add new formats for .insn.
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* s390-opc.txt: Add new instructions.
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2015-01-01 22:15:26 +08:00
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2015-01-01 Alan Modra <amodra@gmail.com>
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2014-12-27 23:57:04 +08:00
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2015-01-01 22:15:26 +08:00
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Update year range in copyright notice of all files.
|
2014-12-27 23:57:04 +08:00
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2015-01-01 22:15:26 +08:00
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For older changes see ChangeLog-2014
|
1999-05-03 15:29:11 +08:00
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2015-01-01 22:15:26 +08:00
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Copyright (C) 2015 Free Software Foundation, Inc.
|
2012-12-10 20:48:03 +08:00
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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|
notice and this notice are preserved.
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1999-05-03 15:29:11 +08:00
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Local Variables:
|
2001-01-12 03:01:42 +08:00
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mode: change-log
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left-margin: 8
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fill-column: 74
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1999-05-03 15:29:11 +08:00
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version-control: never
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End:
|
