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66 lines
1.3 KiB
ArmAsm
66 lines
1.3 KiB
ArmAsm
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//Original:/testcases/core/c_dsp32shiftim_ahh_s/c_dsp32shiftim_ahh_s.dsp
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# mach: bfin
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.include "testutils.inc"
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start
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// Spec Reference: dsp32shiftimm ashift: ashift / ashift saturated
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imm32 r0, 0x01230abc;
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imm32 r1, 0x12345678;
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imm32 r2, 0x23456789;
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imm32 r3, 0x3456789a;
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imm32 r4, 0x456789ab;
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imm32 r5, 0x56789abc;
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imm32 r6, 0x6789abcd;
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imm32 r7, 0x789abcde;
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R0 = R0 << 0 (V , S);
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R1 = R1 << 3 (V , S);
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R2 = R2 << 5 (V , S);
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R3 = R3 << 8 (V , S);
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R4 = R4 << 9 (V , S);
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R5 = R5 << 15 (V , S);
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R6 = R6 << 7 (V , S);
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R7 = R7 << 13 (V , S);
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CHECKREG r0, 0x01230ABC;
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CHECKREG r1, 0x7FFF7FFF;
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CHECKREG r2, 0x7FFF7FFF;
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CHECKREG r3, 0x7FFF7FFF;
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CHECKREG r4, 0x7FFF8000;
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CHECKREG r5, 0x7FFF8000;
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CHECKREG r6, 0x7FFF8000;
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CHECKREG r7, 0x7FFF8000;
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imm32 r0, 0x01230000;
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imm32 r1, 0x12345678;
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imm32 r2, 0x23456789;
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imm32 r3, 0x3456789a;
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imm32 r4, 0x456789ab;
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imm32 r5, 0x56789abc;
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imm32 r6, 0x6789abcd;
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imm32 r7, 0x789abcde;
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R7 = R0 >>> 1 (V, S);
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R0 = R1 >>> 8 (V, S);
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R1 = R2 >>> 14 (V, S);
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R2 = R3 >>> 15 (V, S);
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R3 = R4 >>> 11 (V, S);
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R4 = R5 >>> 4 (V, S);
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R5 = R6 >>> 9 (V, S);
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R6 = R7 >>> 6 (V, S);
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CHECKREG r0, 0x00120056;
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CHECKREG r1, 0x00000001;
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CHECKREG r2, 0x00000000;
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CHECKREG r3, 0x0008FFF1;
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CHECKREG r4, 0x0567F9AB;
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CHECKREG r5, 0x0033FFD5;
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CHECKREG r6, 0x00020000;
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CHECKREG r7, 0x00910000;
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pass
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