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binutils-gdb/opcodes/i386-dis-evex.h

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Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
static const struct dis386 evex_table[][256] = {
/* EVEX_0F */
{
/* 00 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 08 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 10 */
Revert "2.41 Release sources" This reverts commit 675b9d612cc59446e84e2c6d89b45500cb603a8d. See https://sourceware.org/pipermail/binutils/2023-August/128761.html.
2023-08-02 19:06:23 +08:00
{ PREFIX_TABLE (PREFIX_0F10) },
{ PREFIX_TABLE (PREFIX_0F11) },
x86: share yet more VEX table entries with EVEX decoding On top of prior similar work more opportunities have appeared in the meantime. Note that this also happens to address the prior lack of decoding of EVEX.L'L for VMOV{L,H}P{S,D} and VMOV{LH,HL}PS.
2022-01-14 17:56:06 +08:00
{ PREFIX_TABLE (PREFIX_VEX_0F12) },
Revert "2.41 Release sources" This reverts commit 675b9d612cc59446e84e2c6d89b45500cb603a8d. See https://sourceware.org/pipermail/binutils/2023-August/128761.html.
2023-08-02 19:06:23 +08:00
{ VEX_LEN_TABLE (VEX_LEN_0F13) },
x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns When no AVX512-specific functionality is in use, the disassembly of AVX512VL insns is indistinguishable from their AVX counterparts (if such exist). Emit the {evex} pseudo-prefix in such cases. Where applicable drop stray uses of PREFIX_OPCODE from table entries.
2022-10-24 15:30:58 +08:00
{ "%XEvunpcklpX", { XM, Vex, EXx }, PREFIX_OPCODE },
{ "%XEvunpckhpX", { XM, Vex, EXx }, PREFIX_OPCODE },
x86: share yet more VEX table entries with EVEX decoding On top of prior similar work more opportunities have appeared in the meantime. Note that this also happens to address the prior lack of decoding of EVEX.L'L for VMOV{L,H}P{S,D} and VMOV{LH,HL}PS.
2022-01-14 17:56:06 +08:00
{ PREFIX_TABLE (PREFIX_VEX_0F16) },
Revert "2.41 Release sources" This reverts commit 675b9d612cc59446e84e2c6d89b45500cb603a8d. See https://sourceware.org/pipermail/binutils/2023-August/128761.html.
2023-08-02 19:06:23 +08:00
{ VEX_LEN_TABLE (VEX_LEN_0F17) },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
/* 18 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 20 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 28 */
x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns When no AVX512-specific functionality is in use, the disassembly of AVX512VL insns is indistinguishable from their AVX counterparts (if such exist). Emit the {evex} pseudo-prefix in such cases. Where applicable drop stray uses of PREFIX_OPCODE from table entries.
2022-10-24 15:30:58 +08:00
{ "%XEvmovapX", { XM, EXx }, PREFIX_OPCODE },
{ "%XEvmovapX", { EXxS, XM }, PREFIX_OPCODE },
x86: share yet more VEX table entries with EVEX decoding On top of prior similar work more opportunities have appeared in the meantime. Note that this also happens to address the prior lack of decoding of EVEX.L'L for VMOV{L,H}P{S,D} and VMOV{LH,HL}PS.
2022-01-14 17:56:06 +08:00
{ PREFIX_TABLE (PREFIX_VEX_0F2A) },
Revert "2.41 Release sources" This reverts commit 675b9d612cc59446e84e2c6d89b45500cb603a8d. See https://sourceware.org/pipermail/binutils/2023-August/128761.html.
2023-08-02 19:06:23 +08:00
{ "%XEvmovntpX", { Mx, XM }, PREFIX_OPCODE },
x86: drop further EVEX table entries that can be served by VEX ones A few cases were missed by 6df22cf64c93 ("x86: drop EVEX table entries that can be served by VEX ones").
2020-07-14 16:32:51 +08:00
{ PREFIX_TABLE (PREFIX_VEX_0F2C) },
{ PREFIX_TABLE (PREFIX_VEX_0F2D) },
Revert "2.41 Release sources" This reverts commit 675b9d612cc59446e84e2c6d89b45500cb603a8d. See https://sourceware.org/pipermail/binutils/2023-August/128761.html.
2023-08-02 19:06:23 +08:00
{ PREFIX_TABLE (PREFIX_0F2E) },
{ PREFIX_TABLE (PREFIX_0F2F) },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
/* 30 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 38 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 40 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 48 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 50 */
{ Bad_Opcode },
Revert "2.41 Release sources" This reverts commit 675b9d612cc59446e84e2c6d89b45500cb603a8d. See https://sourceware.org/pipermail/binutils/2023-August/128761.html.
2023-08-02 19:06:23 +08:00
{ PREFIX_TABLE (PREFIX_0F51) },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ Bad_Opcode },
{ Bad_Opcode },
x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns When no AVX512-specific functionality is in use, the disassembly of AVX512VL insns is indistinguishable from their AVX counterparts (if such exist). Emit the {evex} pseudo-prefix in such cases. Where applicable drop stray uses of PREFIX_OPCODE from table entries.
2022-10-24 15:30:58 +08:00
{ "%XEvandpX", { XM, Vex, EXx }, PREFIX_OPCODE },
{ "%XEvandnpX", { XM, Vex, EXx }, PREFIX_OPCODE },
{ "%XEvorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
{ "%XEvxorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
/* 58 */
Revert "2.41 Release sources" This reverts commit 675b9d612cc59446e84e2c6d89b45500cb603a8d. See https://sourceware.org/pipermail/binutils/2023-August/128761.html.
2023-08-02 19:06:23 +08:00
{ PREFIX_TABLE (PREFIX_0F58) },
{ PREFIX_TABLE (PREFIX_0F59) },
{ PREFIX_TABLE (PREFIX_0F5A) },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ PREFIX_TABLE (PREFIX_EVEX_0F5B) },
Revert "2.41 Release sources" This reverts commit 675b9d612cc59446e84e2c6d89b45500cb603a8d. See https://sourceware.org/pipermail/binutils/2023-August/128761.html.
2023-08-02 19:06:23 +08:00
{ PREFIX_TABLE (PREFIX_0F5C) },
{ PREFIX_TABLE (PREFIX_0F5D) },
{ PREFIX_TABLE (PREFIX_0F5E) },
{ PREFIX_TABLE (PREFIX_0F5F) },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
/* 60 */
x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns When no AVX512-specific functionality is in use, the disassembly of AVX512VL insns is indistinguishable from their AVX counterparts (if such exist). Emit the {evex} pseudo-prefix in such cases. Where applicable drop stray uses of PREFIX_OPCODE from table entries.
2022-10-24 15:30:58 +08:00
{ "%XEvpunpcklbw", { XM, Vex, EXx }, PREFIX_DATA },
{ "%XEvpunpcklwd", { XM, Vex, EXx }, PREFIX_DATA },
x86: drop EVEX table entries that can be made served by VEX ones By doing the EVEX.W decode first, in various cases VEX table entries can be re-used.
2020-07-06 19:42:33 +08:00
{ VEX_W_TABLE (EVEX_W_0F62) },
x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns When no AVX512-specific functionality is in use, the disassembly of AVX512VL insns is indistinguishable from their AVX counterparts (if such exist). Emit the {evex} pseudo-prefix in such cases. Where applicable drop stray uses of PREFIX_OPCODE from table entries.
2022-10-24 15:30:58 +08:00
{ "%XEvpacksswb", { XM, Vex, EXx }, PREFIX_DATA },
x86: drop OP_Mask() By moving its vex.r check there it becomes fully redundant with OP_G().
2021-07-22 19:01:09 +08:00
{ "vpcmpgtb", { MaskG, Vex, EXx }, PREFIX_DATA },
{ "vpcmpgtw", { MaskG, Vex, EXx }, PREFIX_DATA },
x86: simplify decode of opcodes valid with (embedded) 66 prefix only The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14 16:33:40 +08:00
{ VEX_W_TABLE (EVEX_W_0F66) },
x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns When no AVX512-specific functionality is in use, the disassembly of AVX512VL insns is indistinguishable from their AVX counterparts (if such exist). Emit the {evex} pseudo-prefix in such cases. Where applicable drop stray uses of PREFIX_OPCODE from table entries.
2022-10-24 15:30:58 +08:00
{ "%XEvpackuswb", { XM, Vex, EXx }, PREFIX_DATA },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
/* 68 */
x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns When no AVX512-specific functionality is in use, the disassembly of AVX512VL insns is indistinguishable from their AVX counterparts (if such exist). Emit the {evex} pseudo-prefix in such cases. Where applicable drop stray uses of PREFIX_OPCODE from table entries.
2022-10-24 15:30:58 +08:00
{ "%XEvpunpckhbw", { XM, Vex, EXx }, PREFIX_DATA },
{ "%XEvpunpckhwd", { XM, Vex, EXx }, PREFIX_DATA },
x86: drop EVEX table entries that can be made served by VEX ones By doing the EVEX.W decode first, in various cases VEX table entries can be re-used.
2020-07-06 19:42:33 +08:00
{ VEX_W_TABLE (EVEX_W_0F6A) },
{ VEX_W_TABLE (EVEX_W_0F6B) },
{ VEX_W_TABLE (EVEX_W_0F6C) },
{ VEX_W_TABLE (EVEX_W_0F6D) },
x86: reuse further VEX entries for EVEX When the VEX.L=1 decode matches that of both EVEX.L'L=1 and EVEX.L'L=2 (typically when all three are invalid) the (smaller) VEX table entry can be reused by EVEX, instead of duplicating data. (Note that XM and XMM as well as EXxmm_md and EXd are equivalent at least for the purposes here.)
2021-03-10 15:19:11 +08:00
{ VEX_LEN_TABLE (VEX_LEN_0F6E) },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ PREFIX_TABLE (PREFIX_EVEX_0F6F) },
/* 70 */
{ PREFIX_TABLE (PREFIX_EVEX_0F70) },
Add support for AVX512BW instructions and their AVX512VL versions. gas/ * config/tc-i386.c (cpu_arch): Add .avx512bw, CPU_AVX512BW_FLAGS. * doc/c-i386.texi: Document avx512bw/.avx512bw. gas/testsuite/ * gas/i386/avx512bw-intel.d: New. * gas/i386/avx512bw-opts-intel.d: New. * gas/i386/avx512bw-opts.d: New. * gas/i386/avx512bw-opts.s: New. * gas/i386/avx512bw-wig.s: New. * gas/i386/avx512bw-wig1-intel.d: New. * gas/i386/avx512bw-wig1.d: New. * gas/i386/avx512bw.d: New. * gas/i386/avx512bw.s: New. * gas/i386/avx512bw_vl-intel.d: New. * gas/i386/avx512bw_vl-opts-intel.d: New. * gas/i386/avx512bw_vl-opts.d: New. * gas/i386/avx512bw_vl-opts.s: New. * gas/i386/avx512bw_vl-wig.s: New. * gas/i386/avx512bw_vl-wig1-intel.d: New. * gas/i386/avx512bw_vl-wig1.d: New. * gas/i386/avx512bw_vl.d: New. * gas/i386/avx512bw_vl.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. * gas/i386/x86-64-avx512bw-intel.d: New. * gas/i386/x86-64-avx512bw-opts-intel.d: New. * gas/i386/x86-64-avx512bw-opts.d: New. * gas/i386/x86-64-avx512bw-opts.s: New. * gas/i386/x86-64-avx512bw-wig.s: New. * gas/i386/x86-64-avx512bw-wig1-intel.d: New. * gas/i386/x86-64-avx512bw-wig1.d: New. * gas/i386/x86-64-avx512bw.d: New. * gas/i386/x86-64-avx512bw.s: New. * gas/i386/x86-64-avx512bw_vl-intel.d: New. * gas/i386/x86-64-avx512bw_vl-opts-intel.d: New. * gas/i386/x86-64-avx512bw_vl-opts.d: New. * gas/i386/x86-64-avx512bw_vl-opts.s: New. * gas/i386/x86-64-avx512bw_vl-wig.s: New. * gas/i386/x86-64-avx512bw_vl-wig1-intel.d: New. * gas/i386/x86-64-avx512bw_vl-wig1.d: New. * gas/i386/x86-64-avx512bw_vl.d: New. * gas/i386/x86-64-avx512bw_vl.s: New. opcodes/ * i386-dis-evex.h: Add new instructions (prefixes bellow). * i386-dis.c (fetch_data): Add EdqwS, Edb, Edw, MaskBDE. (enum): Add dqw_swap_mode, db_mode, dw_mode, mask_bd_mode, REG_EVEX_0F71. (PREFIX enum): Add PREFIX_VEX_0F4A, PREFIX_VEX_0F99, PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A33, PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, PREFIX_EVEX_0F63, PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68, PREFIX_EVEX_0F69, PREFIX_EVEX_0F6B, PREFIX_EVEX_0F71_REG_2, PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE, PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC, PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1, PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B, PREFIX_EVEX_0F3810, PREFIX_EVEX_0F381C, PREFIX_EVEX_0F381D, PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3826, PREFIX_EVEX_0F382B, PREFIX_EVEX_0F3830, PREFIX_EVEX_0F3838, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, PREFIX_EVEX_0F387A, PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387D, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3A0F, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15, PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42. (VEX_LEN enum): Add VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0, VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_2, VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A33_P_2, VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1, VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_3_LEN_0, VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0, VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F6B_P_2, EVEX_W_0F6F_P_3, EVEX_W_0F7F_P_3, EVEX_W_0F3810_P_1, EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_2, EVEX_W_0F3820_P_1, EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2, EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F382B_P_2, EVEX_W_0F3830_P_1, EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F387A_P_2, EVEX_W_0F387B_P_2, EVEX_W_0F387D_P_2, EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2, EVEX_W_0F3A42_P_2. (prefix_table): Add entries for new instructions. (vex_table) : Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (intel_operand_size): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling. (OP_E_register): Add dqw_swap_mode, dw_mode, db_mode, mask_bd_mode handling. (OP_E_memory): Add dqw_mode, dw_mode, dqw_swap_mode, dqb_mode, db_mode handling. (OP_G): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling. (OP_EX): Add dqw_swap_mode handling. (OP_VEX): Add mask_bd_mode handling. (OP_Mask): Add mask_bd_mode handling. * i386-gen.c (cpu_flag_init): Add CPU_AVX512BW_FLAGS. (cpu_flags): Add CpuAVX512BW. * i386-init.h: Regenerated. * i386-opc.h (CpuAVX512BW): New. (i386_cpu_flags): Add cpuavx512bw. * i386-opc.tbl: Add AVX512BW instructions. * i386-tbl.h: Regenerate.
2014-07-11 20:32:29 +08:00
{ REG_TABLE (REG_EVEX_0F71) },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ REG_TABLE (REG_EVEX_0F72) },
{ REG_TABLE (REG_EVEX_0F73) },
x86: drop OP_Mask() By moving its vex.r check there it becomes fully redundant with OP_G().
2021-07-22 19:01:09 +08:00
{ "vpcmpeqb", { MaskG, Vex, EXx }, PREFIX_DATA },
{ "vpcmpeqw", { MaskG, Vex, EXx }, PREFIX_DATA },
x86: simplify decode of opcodes valid with (embedded) 66 prefix only The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14 16:33:40 +08:00
{ VEX_W_TABLE (EVEX_W_0F76) },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ Bad_Opcode },
/* 78 */
{ PREFIX_TABLE (PREFIX_EVEX_0F78) },
{ PREFIX_TABLE (PREFIX_EVEX_0F79) },
{ PREFIX_TABLE (PREFIX_EVEX_0F7A) },
{ PREFIX_TABLE (PREFIX_EVEX_0F7B) },
{ Bad_Opcode },
{ Bad_Opcode },
{ PREFIX_TABLE (PREFIX_EVEX_0F7E) },
{ PREFIX_TABLE (PREFIX_EVEX_0F7F) },
/* 80 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 88 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 90 */
x86/APX: no need to have decode go through x86_64_table[] As suggested during review already, all such entries have their first slot as Bad_Opcode, so by adding two more enumerators we can avoid doing that decode step altogether.
2024-01-26 17:34:24 +08:00
{ X86_64_EVEX_W_TABLE (VEX_W_0F90_L_0) },
{ X86_64_EVEX_W_TABLE (VEX_W_0F91_L_0) },
{ X86_64_EVEX_W_TABLE (VEX_W_0F92_L_0) },
{ X86_64_EVEX_W_TABLE (VEX_W_0F93_L_0) },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 98 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* A0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* A8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* B0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* B8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* C0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ PREFIX_TABLE (PREFIX_EVEX_0FC2) },
{ Bad_Opcode },
x86: reuse further VEX entries for EVEX When the VEX.L=1 decode matches that of both EVEX.L'L=1 and EVEX.L'L=2 (typically when all three are invalid) the (smaller) VEX table entry can be reused by EVEX, instead of duplicating data. (Note that XM and XMM as well as EXxmm_md and EXd are equivalent at least for the purposes here.)
2021-03-10 15:19:11 +08:00
{ VEX_LEN_TABLE (VEX_LEN_0FC4) },
Revert "2.41 Release sources" This reverts commit 675b9d612cc59446e84e2c6d89b45500cb603a8d. See https://sourceware.org/pipermail/binutils/2023-August/128761.html.
2023-08-02 19:06:23 +08:00
{ "%XEvpextrw", { Gd, Uxmm, Ib }, PREFIX_DATA },
x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns When no AVX512-specific functionality is in use, the disassembly of AVX512VL insns is indistinguishable from their AVX counterparts (if such exist). Emit the {evex} pseudo-prefix in such cases. Where applicable drop stray uses of PREFIX_OPCODE from table entries.
2022-10-24 15:30:58 +08:00
{ "%XEvshufpX", { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ Bad_Opcode },
/* C8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* D0 */
{ Bad_Opcode },
x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns When no AVX512-specific functionality is in use, the disassembly of AVX512VL insns is indistinguishable from their AVX counterparts (if such exist). Emit the {evex} pseudo-prefix in such cases. Where applicable drop stray uses of PREFIX_OPCODE from table entries.
2022-10-24 15:30:58 +08:00
{ "%XEvpsrlw", { XM, Vex, EXxmm }, PREFIX_DATA },
x86: drop EVEX table entries that can be made served by VEX ones By doing the EVEX.W decode first, in various cases VEX table entries can be re-used.
2020-07-06 19:42:33 +08:00
{ VEX_W_TABLE (EVEX_W_0FD2) },
{ VEX_W_TABLE (EVEX_W_0FD3) },
{ VEX_W_TABLE (EVEX_W_0FD4) },
x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns When no AVX512-specific functionality is in use, the disassembly of AVX512VL insns is indistinguishable from their AVX counterparts (if such exist). Emit the {evex} pseudo-prefix in such cases. Where applicable drop stray uses of PREFIX_OPCODE from table entries.
2022-10-24 15:30:58 +08:00
{ "%XEvpmullw", { XM, Vex, EXx }, PREFIX_DATA },
x86: reuse further VEX entries for EVEX When the VEX.L=1 decode matches that of both EVEX.L'L=1 and EVEX.L'L=2 (typically when all three are invalid) the (smaller) VEX table entry can be reused by EVEX, instead of duplicating data. (Note that XM and XMM as well as EXxmm_md and EXd are equivalent at least for the purposes here.)
2021-03-10 15:19:11 +08:00
{ VEX_W_TABLE (EVEX_W_0FD6) },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ Bad_Opcode },
/* D8 */
x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns When no AVX512-specific functionality is in use, the disassembly of AVX512VL insns is indistinguishable from their AVX counterparts (if such exist). Emit the {evex} pseudo-prefix in such cases. Where applicable drop stray uses of PREFIX_OPCODE from table entries.
2022-10-24 15:30:58 +08:00
{ "%XEvpsubusb", { XM, Vex, EXx }, PREFIX_DATA },
{ "%XEvpsubusw", { XM, Vex, EXx }, PREFIX_DATA },
{ "%XEvpminub", { XM, Vex, EXx }, PREFIX_DATA },
x86: simplify decode of opcodes valid with (embedded) 66 prefix only The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14 16:33:40 +08:00
{ "vpand%DQ", { XM, Vex, EXx }, PREFIX_DATA },
x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns When no AVX512-specific functionality is in use, the disassembly of AVX512VL insns is indistinguishable from their AVX counterparts (if such exist). Emit the {evex} pseudo-prefix in such cases. Where applicable drop stray uses of PREFIX_OPCODE from table entries.
2022-10-24 15:30:58 +08:00
{ "%XEvpaddusb", { XM, Vex, EXx }, PREFIX_DATA },
{ "%XEvpaddusw", { XM, Vex, EXx }, PREFIX_DATA },
{ "%XEvpmaxub", { XM, Vex, EXx }, PREFIX_DATA },
x86: simplify decode of opcodes valid with (embedded) 66 prefix only The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14 16:33:40 +08:00
{ "vpandn%DQ", { XM, Vex, EXx }, PREFIX_DATA },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
/* E0 */
x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns When no AVX512-specific functionality is in use, the disassembly of AVX512VL insns is indistinguishable from their AVX counterparts (if such exist). Emit the {evex} pseudo-prefix in such cases. Where applicable drop stray uses of PREFIX_OPCODE from table entries.
2022-10-24 15:30:58 +08:00
{ "%XEvpavgb", { XM, Vex, EXx }, PREFIX_DATA },
{ "%XEvpsraw", { XM, Vex, EXxmm }, PREFIX_DATA },
{ "%XEvpsra%DQ", { XM, Vex, EXxmm }, PREFIX_DATA },
{ "%XEvpavgw", { XM, Vex, EXx }, PREFIX_DATA },
{ "%XEvpmulhuw", { XM, Vex, EXx }, PREFIX_DATA },
{ "%XEvpmulhw", { XM, Vex, EXx }, PREFIX_DATA },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ PREFIX_TABLE (PREFIX_EVEX_0FE6) },
x86: simplify decode of opcodes valid with (embedded) 66 prefix only The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14 16:33:40 +08:00
{ VEX_W_TABLE (EVEX_W_0FE7) },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
/* E8 */
x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns When no AVX512-specific functionality is in use, the disassembly of AVX512VL insns is indistinguishable from their AVX counterparts (if such exist). Emit the {evex} pseudo-prefix in such cases. Where applicable drop stray uses of PREFIX_OPCODE from table entries.
2022-10-24 15:30:58 +08:00
{ "%XEvpsubsb", { XM, Vex, EXx }, PREFIX_DATA },
{ "%XEvpsubsw", { XM, Vex, EXx }, PREFIX_DATA },
{ "%XEvpminsw", { XM, Vex, EXx }, PREFIX_DATA },
x86: simplify decode of opcodes valid with (embedded) 66 prefix only The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14 16:33:40 +08:00
{ "vpor%DQ", { XM, Vex, EXx }, PREFIX_DATA },
x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns When no AVX512-specific functionality is in use, the disassembly of AVX512VL insns is indistinguishable from their AVX counterparts (if such exist). Emit the {evex} pseudo-prefix in such cases. Where applicable drop stray uses of PREFIX_OPCODE from table entries.
2022-10-24 15:30:58 +08:00
{ "%XEvpaddsb", { XM, Vex, EXx }, PREFIX_DATA },
{ "%XEvpaddsw", { XM, Vex, EXx }, PREFIX_DATA },
{ "%XEvpmaxsw", { XM, Vex, EXx }, PREFIX_DATA },
x86: simplify decode of opcodes valid with (embedded) 66 prefix only The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14 16:33:40 +08:00
{ "vpxor%DQ", { XM, Vex, EXx }, PREFIX_DATA },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
/* F0 */
{ Bad_Opcode },
x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns When no AVX512-specific functionality is in use, the disassembly of AVX512VL insns is indistinguishable from their AVX counterparts (if such exist). Emit the {evex} pseudo-prefix in such cases. Where applicable drop stray uses of PREFIX_OPCODE from table entries.
2022-10-24 15:30:58 +08:00
{ "%XEvpsllw", { XM, Vex, EXxmm }, PREFIX_DATA },
x86: drop EVEX table entries that can be made served by VEX ones By doing the EVEX.W decode first, in various cases VEX table entries can be re-used.
2020-07-06 19:42:33 +08:00
{ VEX_W_TABLE (EVEX_W_0FF2) },
{ VEX_W_TABLE (EVEX_W_0FF3) },
{ VEX_W_TABLE (EVEX_W_0FF4) },
x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns When no AVX512-specific functionality is in use, the disassembly of AVX512VL insns is indistinguishable from their AVX counterparts (if such exist). Emit the {evex} pseudo-prefix in such cases. Where applicable drop stray uses of PREFIX_OPCODE from table entries.
2022-10-24 15:30:58 +08:00
{ "%XEvpmaddwd", { XM, Vex, EXx }, PREFIX_DATA },
Revert "2.41 Release sources" This reverts commit 675b9d612cc59446e84e2c6d89b45500cb603a8d. See https://sourceware.org/pipermail/binutils/2023-August/128761.html.
2023-08-02 19:06:23 +08:00
{ "%XEvpsadbwY", { XM, Vex, EXx }, PREFIX_DATA },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ Bad_Opcode },
/* F8 */
x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns When no AVX512-specific functionality is in use, the disassembly of AVX512VL insns is indistinguishable from their AVX counterparts (if such exist). Emit the {evex} pseudo-prefix in such cases. Where applicable drop stray uses of PREFIX_OPCODE from table entries.
2022-10-24 15:30:58 +08:00
{ "%XEvpsubb", { XM, Vex, EXx }, PREFIX_DATA },
{ "%XEvpsubw", { XM, Vex, EXx }, PREFIX_DATA },
x86: drop EVEX table entries that can be made served by VEX ones By doing the EVEX.W decode first, in various cases VEX table entries can be re-used.
2020-07-06 19:42:33 +08:00
{ VEX_W_TABLE (EVEX_W_0FFA) },
{ VEX_W_TABLE (EVEX_W_0FFB) },
x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns When no AVX512-specific functionality is in use, the disassembly of AVX512VL insns is indistinguishable from their AVX counterparts (if such exist). Emit the {evex} pseudo-prefix in such cases. Where applicable drop stray uses of PREFIX_OPCODE from table entries.
2022-10-24 15:30:58 +08:00
{ "%XEvpaddb", { XM, Vex, EXx }, PREFIX_DATA },
{ "%XEvpaddw", { XM, Vex, EXx }, PREFIX_DATA },
x86: drop EVEX table entries that can be made served by VEX ones By doing the EVEX.W decode first, in various cases VEX table entries can be re-used.
2020-07-06 19:42:33 +08:00
{ VEX_W_TABLE (EVEX_W_0FFE) },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ Bad_Opcode },
},
/* EVEX_0F38 */
{
/* 00 */
x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns When no AVX512-specific functionality is in use, the disassembly of AVX512VL insns is indistinguishable from their AVX counterparts (if such exist). Emit the {evex} pseudo-prefix in such cases. Where applicable drop stray uses of PREFIX_OPCODE from table entries.
2022-10-24 15:30:58 +08:00
{ "%XEvpshufb", { XM, Vex, EXx }, PREFIX_DATA },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns When no AVX512-specific functionality is in use, the disassembly of AVX512VL insns is indistinguishable from their AVX counterparts (if such exist). Emit the {evex} pseudo-prefix in such cases. Where applicable drop stray uses of PREFIX_OPCODE from table entries.
2022-10-24 15:30:58 +08:00
{ "%XEvpmaddubsw", { XM, Vex, EXx }, PREFIX_DATA },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 08 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns When no AVX512-specific functionality is in use, the disassembly of AVX512VL insns is indistinguishable from their AVX counterparts (if such exist). Emit the {evex} pseudo-prefix in such cases. Where applicable drop stray uses of PREFIX_OPCODE from table entries.
2022-10-24 15:30:58 +08:00
{ "%XEvpmulhrsw", { XM, Vex, EXx }, PREFIX_DATA },
x86: simplify decode of opcodes valid with (embedded) 66 prefix only The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14 16:33:40 +08:00
{ VEX_W_TABLE (VEX_W_0F380C) },
x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns When no AVX512-specific functionality is in use, the disassembly of AVX512VL insns is indistinguishable from their AVX counterparts (if such exist). Emit the {evex} pseudo-prefix in such cases. Where applicable drop stray uses of PREFIX_OPCODE from table entries.
2022-10-24 15:30:58 +08:00
{ "%XEvpermilp%XD", { XM, Vex, EXx }, PREFIX_DATA },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ Bad_Opcode },
{ Bad_Opcode },
/* 10 */
Add support for AVX512BW instructions and their AVX512VL versions. gas/ * config/tc-i386.c (cpu_arch): Add .avx512bw, CPU_AVX512BW_FLAGS. * doc/c-i386.texi: Document avx512bw/.avx512bw. gas/testsuite/ * gas/i386/avx512bw-intel.d: New. * gas/i386/avx512bw-opts-intel.d: New. * gas/i386/avx512bw-opts.d: New. * gas/i386/avx512bw-opts.s: New. * gas/i386/avx512bw-wig.s: New. * gas/i386/avx512bw-wig1-intel.d: New. * gas/i386/avx512bw-wig1.d: New. * gas/i386/avx512bw.d: New. * gas/i386/avx512bw.s: New. * gas/i386/avx512bw_vl-intel.d: New. * gas/i386/avx512bw_vl-opts-intel.d: New. * gas/i386/avx512bw_vl-opts.d: New. * gas/i386/avx512bw_vl-opts.s: New. * gas/i386/avx512bw_vl-wig.s: New. * gas/i386/avx512bw_vl-wig1-intel.d: New. * gas/i386/avx512bw_vl-wig1.d: New. * gas/i386/avx512bw_vl.d: New. * gas/i386/avx512bw_vl.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. * gas/i386/x86-64-avx512bw-intel.d: New. * gas/i386/x86-64-avx512bw-opts-intel.d: New. * gas/i386/x86-64-avx512bw-opts.d: New. * gas/i386/x86-64-avx512bw-opts.s: New. * gas/i386/x86-64-avx512bw-wig.s: New. * gas/i386/x86-64-avx512bw-wig1-intel.d: New. * gas/i386/x86-64-avx512bw-wig1.d: New. * gas/i386/x86-64-avx512bw.d: New. * gas/i386/x86-64-avx512bw.s: New. * gas/i386/x86-64-avx512bw_vl-intel.d: New. * gas/i386/x86-64-avx512bw_vl-opts-intel.d: New. * gas/i386/x86-64-avx512bw_vl-opts.d: New. * gas/i386/x86-64-avx512bw_vl-opts.s: New. * gas/i386/x86-64-avx512bw_vl-wig.s: New. * gas/i386/x86-64-avx512bw_vl-wig1-intel.d: New. * gas/i386/x86-64-avx512bw_vl-wig1.d: New. * gas/i386/x86-64-avx512bw_vl.d: New. * gas/i386/x86-64-avx512bw_vl.s: New. opcodes/ * i386-dis-evex.h: Add new instructions (prefixes bellow). * i386-dis.c (fetch_data): Add EdqwS, Edb, Edw, MaskBDE. (enum): Add dqw_swap_mode, db_mode, dw_mode, mask_bd_mode, REG_EVEX_0F71. (PREFIX enum): Add PREFIX_VEX_0F4A, PREFIX_VEX_0F99, PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A33, PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, PREFIX_EVEX_0F63, PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68, PREFIX_EVEX_0F69, PREFIX_EVEX_0F6B, PREFIX_EVEX_0F71_REG_2, PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE, PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC, PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1, PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B, PREFIX_EVEX_0F3810, PREFIX_EVEX_0F381C, PREFIX_EVEX_0F381D, PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3826, PREFIX_EVEX_0F382B, PREFIX_EVEX_0F3830, PREFIX_EVEX_0F3838, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, PREFIX_EVEX_0F387A, PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387D, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3A0F, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15, PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42. (VEX_LEN enum): Add VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0, VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_2, VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A33_P_2, VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1, VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_3_LEN_0, VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0, VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F6B_P_2, EVEX_W_0F6F_P_3, EVEX_W_0F7F_P_3, EVEX_W_0F3810_P_1, EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_2, EVEX_W_0F3820_P_1, EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2, EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F382B_P_2, EVEX_W_0F3830_P_1, EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F387A_P_2, EVEX_W_0F387B_P_2, EVEX_W_0F387D_P_2, EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2, EVEX_W_0F3A42_P_2. (prefix_table): Add entries for new instructions. (vex_table) : Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (intel_operand_size): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling. (OP_E_register): Add dqw_swap_mode, dw_mode, db_mode, mask_bd_mode handling. (OP_E_memory): Add dqw_mode, dw_mode, dqw_swap_mode, dqb_mode, db_mode handling. (OP_G): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling. (OP_EX): Add dqw_swap_mode handling. (OP_VEX): Add mask_bd_mode handling. (OP_Mask): Add mask_bd_mode handling. * i386-gen.c (cpu_flag_init): Add CPU_AVX512BW_FLAGS. (cpu_flags): Add CpuAVX512BW. * i386-init.h: Regenerated. * i386-opc.h (CpuAVX512BW): New. (i386_cpu_flags): Add cpuavx512bw. * i386-opc.tbl: Add AVX512BW instructions. * i386-tbl.h: Regenerate.
2014-07-11 20:32:29 +08:00
{ PREFIX_TABLE (PREFIX_EVEX_0F3810) },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ PREFIX_TABLE (PREFIX_EVEX_0F3811) },
{ PREFIX_TABLE (PREFIX_EVEX_0F3812) },
{ PREFIX_TABLE (PREFIX_EVEX_0F3813) },
{ PREFIX_TABLE (PREFIX_EVEX_0F3814) },
{ PREFIX_TABLE (PREFIX_EVEX_0F3815) },
x86: simplify decode of opcodes valid with (embedded) 66 prefix only The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14 16:33:40 +08:00
{ EVEX_LEN_TABLE (EVEX_LEN_0F3816) },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ Bad_Opcode },
/* 18 */
x86: simplify decode of opcodes valid with (embedded) 66 prefix only The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14 16:33:40 +08:00
{ VEX_W_TABLE (VEX_W_0F3818) },
x86: re-arrange order of decode for various EVEX opcodes The order of decodes influences the overall number of table entries. Reduce table size quite a bit by first decoding few-alternatives attributes common to all valid leaves. This also adds a PREFIX_DATA 7531c61332db ("x86: simplify decode of opcodes valid with (embedded) 66 prefix only") missed to apply to vbroadcastf64x4.
2021-03-10 15:16:54 +08:00
{ EVEX_LEN_TABLE (EVEX_LEN_0F3819) },
Revert "2.41 Release sources" This reverts commit 675b9d612cc59446e84e2c6d89b45500cb603a8d. See https://sourceware.org/pipermail/binutils/2023-August/128761.html.
2023-08-02 19:06:23 +08:00
{ EVEX_LEN_TABLE (EVEX_LEN_0F381A) },
{ EVEX_LEN_TABLE (EVEX_LEN_0F381B) },
x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns When no AVX512-specific functionality is in use, the disassembly of AVX512VL insns is indistinguishable from their AVX counterparts (if such exist). Emit the {evex} pseudo-prefix in such cases. Where applicable drop stray uses of PREFIX_OPCODE from table entries.
2022-10-24 15:30:58 +08:00
{ "%XEvpabsb", { XM, EXx }, PREFIX_DATA },
{ "%XEvpabsw", { XM, EXx }, PREFIX_DATA },
x86: simplify decode of opcodes valid with (embedded) 66 prefix only The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14 16:33:40 +08:00
{ VEX_W_TABLE (EVEX_W_0F381E) },
{ VEX_W_TABLE (EVEX_W_0F381F) },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
/* 20 */
Add support for AVX512BW instructions and their AVX512VL versions. gas/ * config/tc-i386.c (cpu_arch): Add .avx512bw, CPU_AVX512BW_FLAGS. * doc/c-i386.texi: Document avx512bw/.avx512bw. gas/testsuite/ * gas/i386/avx512bw-intel.d: New. * gas/i386/avx512bw-opts-intel.d: New. * gas/i386/avx512bw-opts.d: New. * gas/i386/avx512bw-opts.s: New. * gas/i386/avx512bw-wig.s: New. * gas/i386/avx512bw-wig1-intel.d: New. * gas/i386/avx512bw-wig1.d: New. * gas/i386/avx512bw.d: New. * gas/i386/avx512bw.s: New. * gas/i386/avx512bw_vl-intel.d: New. * gas/i386/avx512bw_vl-opts-intel.d: New. * gas/i386/avx512bw_vl-opts.d: New. * gas/i386/avx512bw_vl-opts.s: New. * gas/i386/avx512bw_vl-wig.s: New. * gas/i386/avx512bw_vl-wig1-intel.d: New. * gas/i386/avx512bw_vl-wig1.d: New. * gas/i386/avx512bw_vl.d: New. * gas/i386/avx512bw_vl.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. * gas/i386/x86-64-avx512bw-intel.d: New. * gas/i386/x86-64-avx512bw-opts-intel.d: New. * gas/i386/x86-64-avx512bw-opts.d: New. * gas/i386/x86-64-avx512bw-opts.s: New. * gas/i386/x86-64-avx512bw-wig.s: New. * gas/i386/x86-64-avx512bw-wig1-intel.d: New. * gas/i386/x86-64-avx512bw-wig1.d: New. * gas/i386/x86-64-avx512bw.d: New. * gas/i386/x86-64-avx512bw.s: New. * gas/i386/x86-64-avx512bw_vl-intel.d: New. * gas/i386/x86-64-avx512bw_vl-opts-intel.d: New. * gas/i386/x86-64-avx512bw_vl-opts.d: New. * gas/i386/x86-64-avx512bw_vl-opts.s: New. * gas/i386/x86-64-avx512bw_vl-wig.s: New. * gas/i386/x86-64-avx512bw_vl-wig1-intel.d: New. * gas/i386/x86-64-avx512bw_vl-wig1.d: New. * gas/i386/x86-64-avx512bw_vl.d: New. * gas/i386/x86-64-avx512bw_vl.s: New. opcodes/ * i386-dis-evex.h: Add new instructions (prefixes bellow). * i386-dis.c (fetch_data): Add EdqwS, Edb, Edw, MaskBDE. (enum): Add dqw_swap_mode, db_mode, dw_mode, mask_bd_mode, REG_EVEX_0F71. (PREFIX enum): Add PREFIX_VEX_0F4A, PREFIX_VEX_0F99, PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A33, PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, PREFIX_EVEX_0F63, PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68, PREFIX_EVEX_0F69, PREFIX_EVEX_0F6B, PREFIX_EVEX_0F71_REG_2, PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE, PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC, PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1, PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B, PREFIX_EVEX_0F3810, PREFIX_EVEX_0F381C, PREFIX_EVEX_0F381D, PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3826, PREFIX_EVEX_0F382B, PREFIX_EVEX_0F3830, PREFIX_EVEX_0F3838, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, PREFIX_EVEX_0F387A, PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387D, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3A0F, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15, PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42. (VEX_LEN enum): Add VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0, VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_2, VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A33_P_2, VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1, VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_3_LEN_0, VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0, VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F6B_P_2, EVEX_W_0F6F_P_3, EVEX_W_0F7F_P_3, EVEX_W_0F3810_P_1, EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_2, EVEX_W_0F3820_P_1, EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2, EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F382B_P_2, EVEX_W_0F3830_P_1, EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F387A_P_2, EVEX_W_0F387B_P_2, EVEX_W_0F387D_P_2, EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2, EVEX_W_0F3A42_P_2. (prefix_table): Add entries for new instructions. (vex_table) : Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (intel_operand_size): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling. (OP_E_register): Add dqw_swap_mode, dw_mode, db_mode, mask_bd_mode handling. (OP_E_memory): Add dqw_mode, dw_mode, dqw_swap_mode, dqb_mode, db_mode handling. (OP_G): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling. (OP_EX): Add dqw_swap_mode handling. (OP_VEX): Add mask_bd_mode handling. (OP_Mask): Add mask_bd_mode handling. * i386-gen.c (cpu_flag_init): Add CPU_AVX512BW_FLAGS. (cpu_flags): Add CpuAVX512BW. * i386-init.h: Regenerated. * i386-opc.h (CpuAVX512BW): New. (i386_cpu_flags): Add cpuavx512bw. * i386-opc.tbl: Add AVX512BW instructions. * i386-tbl.h: Regenerate.
2014-07-11 20:32:29 +08:00
{ PREFIX_TABLE (PREFIX_EVEX_0F3820) },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ PREFIX_TABLE (PREFIX_EVEX_0F3821) },
{ PREFIX_TABLE (PREFIX_EVEX_0F3822) },
{ PREFIX_TABLE (PREFIX_EVEX_0F3823) },
{ PREFIX_TABLE (PREFIX_EVEX_0F3824) },
{ PREFIX_TABLE (PREFIX_EVEX_0F3825) },
Add support for AVX512BW instructions and their AVX512VL versions. gas/ * config/tc-i386.c (cpu_arch): Add .avx512bw, CPU_AVX512BW_FLAGS. * doc/c-i386.texi: Document avx512bw/.avx512bw. gas/testsuite/ * gas/i386/avx512bw-intel.d: New. * gas/i386/avx512bw-opts-intel.d: New. * gas/i386/avx512bw-opts.d: New. * gas/i386/avx512bw-opts.s: New. * gas/i386/avx512bw-wig.s: New. * gas/i386/avx512bw-wig1-intel.d: New. * gas/i386/avx512bw-wig1.d: New. * gas/i386/avx512bw.d: New. * gas/i386/avx512bw.s: New. * gas/i386/avx512bw_vl-intel.d: New. * gas/i386/avx512bw_vl-opts-intel.d: New. * gas/i386/avx512bw_vl-opts.d: New. * gas/i386/avx512bw_vl-opts.s: New. * gas/i386/avx512bw_vl-wig.s: New. * gas/i386/avx512bw_vl-wig1-intel.d: New. * gas/i386/avx512bw_vl-wig1.d: New. * gas/i386/avx512bw_vl.d: New. * gas/i386/avx512bw_vl.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. * gas/i386/x86-64-avx512bw-intel.d: New. * gas/i386/x86-64-avx512bw-opts-intel.d: New. * gas/i386/x86-64-avx512bw-opts.d: New. * gas/i386/x86-64-avx512bw-opts.s: New. * gas/i386/x86-64-avx512bw-wig.s: New. * gas/i386/x86-64-avx512bw-wig1-intel.d: New. * gas/i386/x86-64-avx512bw-wig1.d: New. * gas/i386/x86-64-avx512bw.d: New. * gas/i386/x86-64-avx512bw.s: New. * gas/i386/x86-64-avx512bw_vl-intel.d: New. * gas/i386/x86-64-avx512bw_vl-opts-intel.d: New. * gas/i386/x86-64-avx512bw_vl-opts.d: New. * gas/i386/x86-64-avx512bw_vl-opts.s: New. * gas/i386/x86-64-avx512bw_vl-wig.s: New. * gas/i386/x86-64-avx512bw_vl-wig1-intel.d: New. * gas/i386/x86-64-avx512bw_vl-wig1.d: New. * gas/i386/x86-64-avx512bw_vl.d: New. * gas/i386/x86-64-avx512bw_vl.s: New. opcodes/ * i386-dis-evex.h: Add new instructions (prefixes bellow). * i386-dis.c (fetch_data): Add EdqwS, Edb, Edw, MaskBDE. (enum): Add dqw_swap_mode, db_mode, dw_mode, mask_bd_mode, REG_EVEX_0F71. (PREFIX enum): Add PREFIX_VEX_0F4A, PREFIX_VEX_0F99, PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A33, PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, PREFIX_EVEX_0F63, PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68, PREFIX_EVEX_0F69, PREFIX_EVEX_0F6B, PREFIX_EVEX_0F71_REG_2, PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE, PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC, PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1, PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B, PREFIX_EVEX_0F3810, PREFIX_EVEX_0F381C, PREFIX_EVEX_0F381D, PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3826, PREFIX_EVEX_0F382B, PREFIX_EVEX_0F3830, PREFIX_EVEX_0F3838, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, PREFIX_EVEX_0F387A, PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387D, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3A0F, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15, PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42. (VEX_LEN enum): Add VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0, VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_2, VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A33_P_2, VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1, VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_3_LEN_0, VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0, VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F6B_P_2, EVEX_W_0F6F_P_3, EVEX_W_0F7F_P_3, EVEX_W_0F3810_P_1, EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_2, EVEX_W_0F3820_P_1, EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2, EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F382B_P_2, EVEX_W_0F3830_P_1, EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F387A_P_2, EVEX_W_0F387B_P_2, EVEX_W_0F387D_P_2, EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2, EVEX_W_0F3A42_P_2. (prefix_table): Add entries for new instructions. (vex_table) : Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (intel_operand_size): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling. (OP_E_register): Add dqw_swap_mode, dw_mode, db_mode, mask_bd_mode handling. (OP_E_memory): Add dqw_mode, dw_mode, dqw_swap_mode, dqb_mode, db_mode handling. (OP_G): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling. (OP_EX): Add dqw_swap_mode handling. (OP_VEX): Add mask_bd_mode handling. (OP_Mask): Add mask_bd_mode handling. * i386-gen.c (cpu_flag_init): Add CPU_AVX512BW_FLAGS. (cpu_flags): Add CpuAVX512BW. * i386-init.h: Regenerated. * i386-opc.h (CpuAVX512BW): New. (i386_cpu_flags): Add cpuavx512bw. * i386-opc.tbl: Add AVX512BW instructions. * i386-tbl.h: Regenerate.
2014-07-11 20:32:29 +08:00
{ PREFIX_TABLE (PREFIX_EVEX_0F3826) },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ PREFIX_TABLE (PREFIX_EVEX_0F3827) },
/* 28 */
{ PREFIX_TABLE (PREFIX_EVEX_0F3828) },
{ PREFIX_TABLE (PREFIX_EVEX_0F3829) },
{ PREFIX_TABLE (PREFIX_EVEX_0F382A) },
x86: drop EVEX table entries that can be made served by VEX ones By doing the EVEX.W decode first, in various cases VEX table entries can be re-used.
2020-07-06 19:42:33 +08:00
{ VEX_W_TABLE (EVEX_W_0F382B) },
x86: simplify decode of opcodes valid with (embedded) 66 prefix only The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14 16:33:40 +08:00
{ "vscalefp%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
x86: drop vex_scalar_w_dq_mode It has only a single use and can easily be represented by dq_mode instead. Plus its handling in intel_operand_size() was duplicating that of vex_vsib_{d,q}_w_dq_mode anyway.
2021-07-22 19:09:03 +08:00
{ "vscalefs%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ Bad_Opcode },
{ Bad_Opcode },
/* 30 */
Add support for AVX512BW instructions and their AVX512VL versions. gas/ * config/tc-i386.c (cpu_arch): Add .avx512bw, CPU_AVX512BW_FLAGS. * doc/c-i386.texi: Document avx512bw/.avx512bw. gas/testsuite/ * gas/i386/avx512bw-intel.d: New. * gas/i386/avx512bw-opts-intel.d: New. * gas/i386/avx512bw-opts.d: New. * gas/i386/avx512bw-opts.s: New. * gas/i386/avx512bw-wig.s: New. * gas/i386/avx512bw-wig1-intel.d: New. * gas/i386/avx512bw-wig1.d: New. * gas/i386/avx512bw.d: New. * gas/i386/avx512bw.s: New. * gas/i386/avx512bw_vl-intel.d: New. * gas/i386/avx512bw_vl-opts-intel.d: New. * gas/i386/avx512bw_vl-opts.d: New. * gas/i386/avx512bw_vl-opts.s: New. * gas/i386/avx512bw_vl-wig.s: New. * gas/i386/avx512bw_vl-wig1-intel.d: New. * gas/i386/avx512bw_vl-wig1.d: New. * gas/i386/avx512bw_vl.d: New. * gas/i386/avx512bw_vl.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. * gas/i386/x86-64-avx512bw-intel.d: New. * gas/i386/x86-64-avx512bw-opts-intel.d: New. * gas/i386/x86-64-avx512bw-opts.d: New. * gas/i386/x86-64-avx512bw-opts.s: New. * gas/i386/x86-64-avx512bw-wig.s: New. * gas/i386/x86-64-avx512bw-wig1-intel.d: New. * gas/i386/x86-64-avx512bw-wig1.d: New. * gas/i386/x86-64-avx512bw.d: New. * gas/i386/x86-64-avx512bw.s: New. * gas/i386/x86-64-avx512bw_vl-intel.d: New. * gas/i386/x86-64-avx512bw_vl-opts-intel.d: New. * gas/i386/x86-64-avx512bw_vl-opts.d: New. * gas/i386/x86-64-avx512bw_vl-opts.s: New. * gas/i386/x86-64-avx512bw_vl-wig.s: New. * gas/i386/x86-64-avx512bw_vl-wig1-intel.d: New. * gas/i386/x86-64-avx512bw_vl-wig1.d: New. * gas/i386/x86-64-avx512bw_vl.d: New. * gas/i386/x86-64-avx512bw_vl.s: New. opcodes/ * i386-dis-evex.h: Add new instructions (prefixes bellow). * i386-dis.c (fetch_data): Add EdqwS, Edb, Edw, MaskBDE. (enum): Add dqw_swap_mode, db_mode, dw_mode, mask_bd_mode, REG_EVEX_0F71. (PREFIX enum): Add PREFIX_VEX_0F4A, PREFIX_VEX_0F99, PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A33, PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, PREFIX_EVEX_0F63, PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68, PREFIX_EVEX_0F69, PREFIX_EVEX_0F6B, PREFIX_EVEX_0F71_REG_2, PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE, PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC, PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1, PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B, PREFIX_EVEX_0F3810, PREFIX_EVEX_0F381C, PREFIX_EVEX_0F381D, PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3826, PREFIX_EVEX_0F382B, PREFIX_EVEX_0F3830, PREFIX_EVEX_0F3838, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, PREFIX_EVEX_0F387A, PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387D, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3A0F, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15, PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42. (VEX_LEN enum): Add VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0, VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_2, VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A33_P_2, VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1, VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_3_LEN_0, VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0, VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F6B_P_2, EVEX_W_0F6F_P_3, EVEX_W_0F7F_P_3, EVEX_W_0F3810_P_1, EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_2, EVEX_W_0F3820_P_1, EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2, EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F382B_P_2, EVEX_W_0F3830_P_1, EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F387A_P_2, EVEX_W_0F387B_P_2, EVEX_W_0F387D_P_2, EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2, EVEX_W_0F3A42_P_2. (prefix_table): Add entries for new instructions. (vex_table) : Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (intel_operand_size): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling. (OP_E_register): Add dqw_swap_mode, dw_mode, db_mode, mask_bd_mode handling. (OP_E_memory): Add dqw_mode, dw_mode, dqw_swap_mode, dqb_mode, db_mode handling. (OP_G): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling. (OP_EX): Add dqw_swap_mode handling. (OP_VEX): Add mask_bd_mode handling. (OP_Mask): Add mask_bd_mode handling. * i386-gen.c (cpu_flag_init): Add CPU_AVX512BW_FLAGS. (cpu_flags): Add CpuAVX512BW. * i386-init.h: Regenerated. * i386-opc.h (CpuAVX512BW): New. (i386_cpu_flags): Add cpuavx512bw. * i386-opc.tbl: Add AVX512BW instructions. * i386-tbl.h: Regenerate.
2014-07-11 20:32:29 +08:00
{ PREFIX_TABLE (PREFIX_EVEX_0F3830) },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ PREFIX_TABLE (PREFIX_EVEX_0F3831) },
{ PREFIX_TABLE (PREFIX_EVEX_0F3832) },
{ PREFIX_TABLE (PREFIX_EVEX_0F3833) },
{ PREFIX_TABLE (PREFIX_EVEX_0F3834) },
{ PREFIX_TABLE (PREFIX_EVEX_0F3835) },
x86: simplify decode of opcodes valid with (embedded) 66 prefix only The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14 16:33:40 +08:00
{ EVEX_LEN_TABLE (EVEX_LEN_0F3836) },
{ VEX_W_TABLE (EVEX_W_0F3837) },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
/* 38 */
Add support for AVX512BW instructions and their AVX512VL versions. gas/ * config/tc-i386.c (cpu_arch): Add .avx512bw, CPU_AVX512BW_FLAGS. * doc/c-i386.texi: Document avx512bw/.avx512bw. gas/testsuite/ * gas/i386/avx512bw-intel.d: New. * gas/i386/avx512bw-opts-intel.d: New. * gas/i386/avx512bw-opts.d: New. * gas/i386/avx512bw-opts.s: New. * gas/i386/avx512bw-wig.s: New. * gas/i386/avx512bw-wig1-intel.d: New. * gas/i386/avx512bw-wig1.d: New. * gas/i386/avx512bw.d: New. * gas/i386/avx512bw.s: New. * gas/i386/avx512bw_vl-intel.d: New. * gas/i386/avx512bw_vl-opts-intel.d: New. * gas/i386/avx512bw_vl-opts.d: New. * gas/i386/avx512bw_vl-opts.s: New. * gas/i386/avx512bw_vl-wig.s: New. * gas/i386/avx512bw_vl-wig1-intel.d: New. * gas/i386/avx512bw_vl-wig1.d: New. * gas/i386/avx512bw_vl.d: New. * gas/i386/avx512bw_vl.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. * gas/i386/x86-64-avx512bw-intel.d: New. * gas/i386/x86-64-avx512bw-opts-intel.d: New. * gas/i386/x86-64-avx512bw-opts.d: New. * gas/i386/x86-64-avx512bw-opts.s: New. * gas/i386/x86-64-avx512bw-wig.s: New. * gas/i386/x86-64-avx512bw-wig1-intel.d: New. * gas/i386/x86-64-avx512bw-wig1.d: New. * gas/i386/x86-64-avx512bw.d: New. * gas/i386/x86-64-avx512bw.s: New. * gas/i386/x86-64-avx512bw_vl-intel.d: New. * gas/i386/x86-64-avx512bw_vl-opts-intel.d: New. * gas/i386/x86-64-avx512bw_vl-opts.d: New. * gas/i386/x86-64-avx512bw_vl-opts.s: New. * gas/i386/x86-64-avx512bw_vl-wig.s: New. * gas/i386/x86-64-avx512bw_vl-wig1-intel.d: New. * gas/i386/x86-64-avx512bw_vl-wig1.d: New. * gas/i386/x86-64-avx512bw_vl.d: New. * gas/i386/x86-64-avx512bw_vl.s: New. opcodes/ * i386-dis-evex.h: Add new instructions (prefixes bellow). * i386-dis.c (fetch_data): Add EdqwS, Edb, Edw, MaskBDE. (enum): Add dqw_swap_mode, db_mode, dw_mode, mask_bd_mode, REG_EVEX_0F71. (PREFIX enum): Add PREFIX_VEX_0F4A, PREFIX_VEX_0F99, PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A33, PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, PREFIX_EVEX_0F63, PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68, PREFIX_EVEX_0F69, PREFIX_EVEX_0F6B, PREFIX_EVEX_0F71_REG_2, PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE, PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC, PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1, PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B, PREFIX_EVEX_0F3810, PREFIX_EVEX_0F381C, PREFIX_EVEX_0F381D, PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3826, PREFIX_EVEX_0F382B, PREFIX_EVEX_0F3830, PREFIX_EVEX_0F3838, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, PREFIX_EVEX_0F387A, PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387D, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3A0F, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15, PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42. (VEX_LEN enum): Add VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0, VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_2, VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A33_P_2, VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1, VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_3_LEN_0, VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0, VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F6B_P_2, EVEX_W_0F6F_P_3, EVEX_W_0F7F_P_3, EVEX_W_0F3810_P_1, EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_2, EVEX_W_0F3820_P_1, EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2, EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F382B_P_2, EVEX_W_0F3830_P_1, EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F387A_P_2, EVEX_W_0F387B_P_2, EVEX_W_0F387D_P_2, EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2, EVEX_W_0F3A42_P_2. (prefix_table): Add entries for new instructions. (vex_table) : Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (intel_operand_size): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling. (OP_E_register): Add dqw_swap_mode, dw_mode, db_mode, mask_bd_mode handling. (OP_E_memory): Add dqw_mode, dw_mode, dqw_swap_mode, dqb_mode, db_mode handling. (OP_G): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling. (OP_EX): Add dqw_swap_mode handling. (OP_VEX): Add mask_bd_mode handling. (OP_Mask): Add mask_bd_mode handling. * i386-gen.c (cpu_flag_init): Add CPU_AVX512BW_FLAGS. (cpu_flags): Add CpuAVX512BW. * i386-init.h: Regenerated. * i386-opc.h (CpuAVX512BW): New. (i386_cpu_flags): Add cpuavx512bw. * i386-opc.tbl: Add AVX512BW instructions. * i386-tbl.h: Regenerate.
2014-07-11 20:32:29 +08:00
{ PREFIX_TABLE (PREFIX_EVEX_0F3838) },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ PREFIX_TABLE (PREFIX_EVEX_0F3839) },
{ PREFIX_TABLE (PREFIX_EVEX_0F383A) },
x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns When no AVX512-specific functionality is in use, the disassembly of AVX512VL insns is indistinguishable from their AVX counterparts (if such exist). Emit the {evex} pseudo-prefix in such cases. Where applicable drop stray uses of PREFIX_OPCODE from table entries.
2022-10-24 15:30:58 +08:00
{ "%XEvpminu%DQ", { XM, Vex, EXx }, PREFIX_DATA },
{ "%XEvpmaxsb", { XM, Vex, EXx }, PREFIX_DATA },
{ "%XEvpmaxs%DQ", { XM, Vex, EXx }, PREFIX_DATA },
{ "%XEvpmaxuw", { XM, Vex, EXx }, PREFIX_DATA },
{ "%XEvpmaxu%DQ", { XM, Vex, EXx }, PREFIX_DATA },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
/* 40 */
x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns When no AVX512-specific functionality is in use, the disassembly of AVX512VL insns is indistinguishable from their AVX counterparts (if such exist). Emit the {evex} pseudo-prefix in such cases. Where applicable drop stray uses of PREFIX_OPCODE from table entries.
2022-10-24 15:30:58 +08:00
{ "%XEvpmull%DQ", { XM, Vex, EXx }, PREFIX_DATA },
x86: simplify decode of opcodes valid with (embedded) 66 prefix only The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14 16:33:40 +08:00
{ Bad_Opcode },
{ "vgetexpp%XW", { XM, EXx, EXxEVexS }, PREFIX_DATA },
x86: drop vex_scalar_w_dq_mode It has only a single use and can easily be represented by dq_mode instead. Plus its handling in intel_operand_size() was duplicating that of vex_vsib_{d,q}_w_dq_mode anyway.
2021-07-22 19:09:03 +08:00
{ "vgetexps%XW", { XMScalar, VexScalar, EXdq, EXxEVexS }, PREFIX_DATA },
x86: simplify decode of opcodes valid with (embedded) 66 prefix only The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14 16:33:40 +08:00
{ "vplzcnt%DQ", { XM, EXx }, PREFIX_DATA },
{ "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
{ "vpsrav%DQ", { XM, Vex, EXx }, PREFIX_DATA },
{ "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
/* 48 */
{ Bad_Opcode },
x86/APX: TILE{RELEASE,ZERO} have no EVEX encodings Re-using the entire VEX decode hierarchy for the respective major opcode has led to those two also being decoded as-if valid. Follow the earlier USE_X86_64_EVEX_{PFX,W}_TABLE approach to avoid this happening.
2024-01-26 17:34:48 +08:00
{ X86_64_EVEX_MEM_W_TABLE (VEX_W_0F3849_X86_64_L_0) },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ Bad_Opcode },
x86/APX: TILE{RELEASE,ZERO} have no EVEX encodings Re-using the entire VEX decode hierarchy for the respective major opcode has led to those two also being decoded as-if valid. Follow the earlier USE_X86_64_EVEX_{PFX,W}_TABLE approach to avoid this happening.
2024-01-26 17:34:48 +08:00
{ X86_64_EVEX_MEM_W_TABLE (VEX_W_0F384B_X86_64_L_0) },
x86: simplify decode of opcodes valid with (embedded) 66 prefix only The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14 16:33:40 +08:00
{ "vrcp14p%XW", { XM, EXx }, PREFIX_DATA },
x86: drop vex_scalar_w_dq_mode It has only a single use and can easily be represented by dq_mode instead. Plus its handling in intel_operand_size() was duplicating that of vex_vsib_{d,q}_w_dq_mode anyway.
2021-07-22 19:09:03 +08:00
{ "vrcp14s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
x86: simplify decode of opcodes valid with (embedded) 66 prefix only The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14 16:33:40 +08:00
{ "vrsqrt14p%XW", { XM, EXx }, 0 },
x86: drop vex_scalar_w_dq_mode It has only a single use and can easily be represented by dq_mode instead. Plus its handling in intel_operand_size() was duplicating that of vex_vsib_{d,q}_w_dq_mode anyway.
2021-07-22 19:09:03 +08:00
{ "vrsqrt14s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
/* 50 */
x86: fold AVX512-VNNI disassembler entries with AVX-VNNI ones Make %XV also print the separating blank in the VEX case, while making it do nothing for EVEX-encoded insns. This way the AVX-VNNI entries can be re-used for AVX512-VNNI, at the same time fixing the lack of EVEX.W decoding. For the AVX-VNNI ones further make sure only VEX.66 forms are actually decoded.
2022-10-17 14:27:03 +08:00
{ VEX_W_TABLE (VEX_W_0F3850) },
{ VEX_W_TABLE (VEX_W_0F3851) },
Enable Intel AVX512_4VNNIW instructions gas/ * config/tc-i386.c: (cpu_arch) Add .avx512_4vnniw. (cpu_noarch): Add noavx512_4vnniw. * doc/c-i386.texi: Document avx512_4vnniw, noavx512_4vnniw. * testsuite/gas/i386/i386.exp: Run AVX512_4VNNIW tests. * testsuite/gas/i386/avx512_4vnniwd_vl-intel.d: New test. * testsuite/gas/i386/avx512_4vnniwd_vl.d: Ditto. * testsuite/gas/i386/avx512_4vnniwd_vl.s: Ditto. * testsuite/gas/i386/avx512_4vnniwd-intel.d: Ditto. * testsuite/gas/i386/avx512_4vnniwd.d: Ditto. * testsuite/gas/i386/avx512_4vnniwd.s: Ditto. * testsuite/gas/i386/x86-64-avx512_4vnniwd_vl-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512_4vnniwd_vl.d: Ditto. * testsuite/gas/i386/x86-64-avx512_4vnniwd_vl.s: Ditto. * testsuite/gas/i386/x86-64-avx512_4vnniwd-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx512_4vnniwd.d: Ditto. * testsuite/gas/i386/x86-64-avx512_4vnniwd.s: Ditto. opcodes/ * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853. * i386-dis-evex.h (evex_table): Updated. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS, CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS. (cpu_flags): Add CpuAVX512_4VNNIW. * i386-opc.h (enum): (AVX512_4VNNIW): New. (i386_cpu_flags): Add cpuavx512_4vnniw. * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions. * i386-init.h: Regenerate. * i386-tbl.h: Ditto.
2016-11-03 03:31:25 +08:00
{ PREFIX_TABLE (PREFIX_EVEX_0F3852) },
{ PREFIX_TABLE (PREFIX_EVEX_0F3853) },
x86: simplify decode of opcodes valid with (embedded) 66 prefix only The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14 16:33:40 +08:00
{ "vpopcnt%BW", { XM, EXx }, PREFIX_DATA },
{ "vpopcnt%DQ", { XM, EXx }, PREFIX_DATA },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ Bad_Opcode },
{ Bad_Opcode },
/* 58 */
x86: simplify decode of opcodes valid with (embedded) 66 prefix only The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14 16:33:40 +08:00
{ VEX_W_TABLE (VEX_W_0F3858) },
{ VEX_W_TABLE (EVEX_W_0F3859) },
Revert "2.41 Release sources" This reverts commit 675b9d612cc59446e84e2c6d89b45500cb603a8d. See https://sourceware.org/pipermail/binutils/2023-August/128761.html.
2023-08-02 19:06:23 +08:00
{ EVEX_LEN_TABLE (EVEX_LEN_0F385A) },
{ EVEX_LEN_TABLE (EVEX_LEN_0F385B) },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 60 */
{ Bad_Opcode },
{ Bad_Opcode },
[PATCH 1/2] Enable Intel AVX512_FP16 instructions Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32 in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx). There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8 operands predated our current conventions; those instructions moved to map 3. FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3 is very sparsely populated. Most of the FP16 instructions share opcodes and prefix (EVEX.pp) bits with the related FP32 operations. Intel AVX512 FP16 instructions has new displacements scaling rules, please refer to the public software developer manual for detail information. gas/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (struct Broadcast_Operation): Adjust comment. (cpu_arch): Add .avx512_fp16. (cpu_noarch): Add noavx512_fp16. (pte): Add evexmap5 and evexmap6. (build_evex_prefix): Handle EVEXMAP5 and EVEXMAP6. (check_VecOperations): Handle {1to32}. (check_VecOperands): Handle CheckRegNumb. (check_word_reg): Handle Toqword. (i386_error): Add invalid_dest_and_src_register_set. (match_template): Handle invalid_dest_and_src_register_set. * doc/c-i386.texi: Document avx512_fp16, noavx512_fp16. opcodes/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (EXwScalarS): New. (EXxh): Ditto. (EXxhc): Ditto. (EXxmmqh): Ditto. (EXxmmqdh): Ditto. (EXEvexXwb): Ditto. (DistinctDest_Fixup): Ditto. (enum): Add xh_mode, evex_half_bcst_xmmqh_mode, evex_half_bcst_xmmqdh_mode and w_swap_mode. (enum): Add PREFIX_EVEX_0F3A08_W_0, PREFIX_EVEX_0F3A0A_W_0, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3AC2, PREFIX_EVEX_MAP5_10, PREFIX_EVEX_MAP5_11, PREFIX_EVEX_MAP5_1D, PREFIX_EVEX_MAP5_2A, PREFIX_EVEX_MAP5_2C, PREFIX_EVEX_MAP5_2D, PREFIX_EVEX_MAP5_2E, PREFIX_EVEX_MAP5_2F, PREFIX_EVEX_MAP5_51, PREFIX_EVEX_MAP5_58, PREFIX_EVEX_MAP5_59, PREFIX_EVEX_MAP5_5A_W_0, PREFIX_EVEX_MAP5_5A_W_1, PREFIX_EVEX_MAP5_5B_W_0, PREFIX_EVEX_MAP5_5B_W_1, PREFIX_EVEX_MAP5_5C, PREFIX_EVEX_MAP5_5D, PREFIX_EVEX_MAP5_5E, PREFIX_EVEX_MAP5_5F, PREFIX_EVEX_MAP5_78, PREFIX_EVEX_MAP5_79, PREFIX_EVEX_MAP5_7A, PREFIX_EVEX_MAP5_7B, PREFIX_EVEX_MAP5_7C, PREFIX_EVEX_MAP5_7D_W_0, PREFIX_EVEX_MAP6_13, PREFIX_EVEX_MAP6_56, PREFIX_EVEX_MAP6_57, PREFIX_EVEX_MAP6_D6, PREFIX_EVEX_MAP6_D7 (enum): Add EVEX_MAP5 and EVEX_MAP6. (enum): Add EVEX_W_MAP5_5A, EVEX_W_MAP5_5B, EVEX_W_MAP5_78_P_0, EVEX_W_MAP5_78_P_2, EVEX_W_MAP5_79_P_0, EVEX_W_MAP5_79_P_2, EVEX_W_MAP5_7A_P_2, EVEX_W_MAP5_7A_P_3, EVEX_W_MAP5_7B_P_2, EVEX_W_MAP5_7C_P_0, EVEX_W_MAP5_7C_P_2, EVEX_W_MAP5_7D, EVEX_W_MAP6_13_P_0, EVEX_W_MAP6_13_P_2, (get_valid_dis386): Properly handle new instructions. (intel_operand_size): Handle new modes. (OP_E_memory): Ditto. (OP_EX): Ditto. * i386-dis-evex.h: Updated for AVX512_FP16. * i386-dis-evex-mod.h: Updated for AVX512_FP16. * i386-dis-evex-prefix.h: Updated for AVX512_FP16. * i386-dis-evex-reg.h : Updated for AVX512_FP16. * i386-dis-evex-w.h : Updated for AVX512_FP16. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_FP16_FLAGS, and CPU_ANY_AVX512_FP16_FLAGS. Update CPU_ANY_AVX512F_FLAGS and CPU_ANY_AVX512BW_FLAGS. (cpu_flags): Add CpuAVX512_FP16. (opcode_modifiers): Add DistinctDest. * i386-opc.h (enum): (AVX512_FP16): New. (i386_opcode_modifier): Add reqdistinctreg. (i386_cpu_flags): Add cpuavx512_fp16. (EVEXMAP5): Defined as a macro. (EVEXMAP6): Ditto. * i386-opc.tbl: Add Intel AVX512_FP16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Ditto.
2021-06-14 11:05:05 +08:00
{ "vpexpand%BW", { XM, EXbwUnit }, PREFIX_DATA },
{ "vpcompress%BW", { EXbwUnit, XM }, PREFIX_DATA },
x86: simplify decode of opcodes valid with (embedded) 66 prefix only The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14 16:33:40 +08:00
{ "vpblendm%DQ", { XM, Vex, EXx }, PREFIX_DATA },
{ "vblendmp%XW", { XM, Vex, EXx }, PREFIX_DATA },
{ "vpblendm%BW", { XM, Vex, EXx }, PREFIX_DATA },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ Bad_Opcode },
/* 68 */
Enable Intel AVX512_VP2INTERSECT insn This patch enables support for VP2INTERSECT in binutils. Please refer to https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf for VP2INTERSECT details. Make check-gas is ok. gas/ 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (cpu_arch): Add .avx512_vp2intersect. (cpu_noarch): Likewise. * doc/c-i386.texi: Document avx512_vp2intersect. * testsuite/gas/i386/i386.exp: Run vp2intersect tests. * testsuite/gas/i386/vp2intersect-intel.d: New test. * testsuite/gas/i386/vp2intersect.d: Likewise. * testsuite/gas/i386/vp2intersect.s: Likewise. * testsuite/gas/i386/vp2intersect-inval-bcast.l: Likewise. * testsuite/gas/i386/vp2intersect-inval-bcast.s: Likewise. * testsuite/gas/i386/x86-64-vp2intersect-intel.d: Likewise. * testsuite/gas/i386/x86-64-vp2intersect.d: Likewise. * testsuite/gas/i386/x86-64-vp2intersect.s: Likewise. * testsuite/gas/i386/x86-64-vp2intersect-inval-bcast.l: Likewise. * testsuite/gas/i386/x86-64-vp2intersect-inval-bcast.s: Likewise. opcodes/ 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3. * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT instructions. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS, CPU_ANY_AVX512_VP2INTERSECT_FLAGS. (cpu_flags): Add CpuAVX512_VP2INTERSECT. * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT. (i386_cpu_flags): Add cpuavx512_vp2intersect. * i386-opc.tbl: Add AVX512_VP2INTERSECT insns. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2019-06-04 23:58:21 +08:00
{ PREFIX_TABLE (PREFIX_EVEX_0F3868) },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 70 */
x86: simplify decode of opcodes valid with (embedded) 66 prefix only The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14 16:33:40 +08:00
{ VEX_W_TABLE (EVEX_W_0F3870) },
{ "vpshldv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
Enable Intel AVX512_VBMI2 instructions. Intel has disclosed a set of new instructions. The spec is https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf gas/ * config/tc-i386.c (cpu_arch): Add .avx512_vbmi2. (cpu_noarch): noavx512_vbmi2. * doc/c-i386.texi: Document .avx512_vbmi2, noavx512_vbmi2. * testsuite/gas/i386/i386.exp: Add AVX512_VBMI2 tests. * testsuite/gas/i386/avx512vbmi2-intel.d: New test. * testsuite/gas/i386/avx512vbmi2.d: Likewise. * testsuite/gas/i386/avx512vbmi2.s: Likewise. * testsuite/gas/i386/avx512vbmi2_vl-intel.d: Likewise. * testsuite/gas/i386/avx512vbmi2_vl.d: Likewise. * testsuite/gas/i386/avx512vbmi2_vl.s: Likewise. * testsuite/gas/i386/x86-64-avx512vbmi2-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512vbmi2.d: Likewise. * testsuite/gas/i386/x86-64-avx512vbmi2.s: Likewise. * testsuite/gas/i386/x86-64-avx512vbmi2_vl-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx512vbmi2_vl.d: Likewise. * testsuite/gas/i386/x86-64-avx512vbmi2_vl.s: Likewise. opcodes/ * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode. Define EXbScalar and EXwScalar for OP_EX. (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71, PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73. (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2, EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2, EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2, EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2. (intel_operand_size): Handle b_scalar_mode and w_scalar_mode. (OP_E_memory): Likewise. * i386-dis-evex.h: Updated. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2, CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS. (cpu_flags): Add CpuAVX512_VBMI2. * i386-opc.h (enum): Add CpuAVX512_VBMI2. (i386_cpu_flags): Add cpuavx512_vbmi2. * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions. * i386-init.h: Regenerate. * i386-tbl.h: Likewise.
2017-10-21 03:52:59 +08:00
{ PREFIX_TABLE (PREFIX_EVEX_0F3872) },
x86: simplify decode of opcodes valid with (embedded) 66 prefix only The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14 16:33:40 +08:00
{ "vpshrdv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ Bad_Opcode },
x86: simplify decode of opcodes valid with (embedded) 66 prefix only The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14 16:33:40 +08:00
{ "vpermi2%BW", { XM, Vex, EXx }, PREFIX_DATA },
{ "vpermi2%DQ", { XM, Vex, EXx }, PREFIX_DATA },
{ "vpermi2p%XW", { XM, Vex, EXx }, PREFIX_DATA },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
/* 78 */
x86: simplify decode of opcodes valid with (embedded) 66 prefix only The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14 16:33:40 +08:00
{ VEX_W_TABLE (VEX_W_0F3878) },
{ VEX_W_TABLE (VEX_W_0F3879) },
{ VEX_W_TABLE (EVEX_W_0F387A) },
{ VEX_W_TABLE (EVEX_W_0F387B) },
Revert "2.41 Release sources" This reverts commit 675b9d612cc59446e84e2c6d89b45500cb603a8d. See https://sourceware.org/pipermail/binutils/2023-August/128761.html.
2023-08-02 19:06:23 +08:00
{ "vpbroadcastK", { XM, Rdq }, PREFIX_DATA },
x86: simplify decode of opcodes valid with (embedded) 66 prefix only The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14 16:33:40 +08:00
{ "vpermt2%BW", { XM, Vex, EXx }, PREFIX_DATA },
{ "vpermt2%DQ", { XM, Vex, EXx }, PREFIX_DATA },
{ "vpermt2p%XW", { XM, Vex, EXx }, PREFIX_DATA },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
/* 80 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
x86: simplify decode of opcodes valid with (embedded) 66 prefix only The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14 16:33:40 +08:00
{ VEX_W_TABLE (EVEX_W_0F3883) },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 88 */
x86: simplify decode of opcodes valid with (embedded) 66 prefix only The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14 16:33:40 +08:00
{ "vexpandp%XW", { XM, EXEvexXGscat }, PREFIX_DATA },
{ "vpexpand%DQ", { XM, EXEvexXGscat }, PREFIX_DATA },
{ "vcompressp%XW", { EXEvexXGscat, XM }, PREFIX_DATA },
{ "vpcompress%DQ", { EXEvexXGscat, XM }, PREFIX_DATA },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ Bad_Opcode },
x86: simplify decode of opcodes valid with (embedded) 66 prefix only The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14 16:33:40 +08:00
{ "vperm%BW", { XM, Vex, EXx }, PREFIX_DATA },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ Bad_Opcode },
[PATCH 1/2] Enable Intel AVX512_FP16 instructions Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32 in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx). There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8 operands predated our current conventions; those instructions moved to map 3. FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3 is very sparsely populated. Most of the FP16 instructions share opcodes and prefix (EVEX.pp) bits with the related FP32 operations. Intel AVX512 FP16 instructions has new displacements scaling rules, please refer to the public software developer manual for detail information. gas/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (struct Broadcast_Operation): Adjust comment. (cpu_arch): Add .avx512_fp16. (cpu_noarch): Add noavx512_fp16. (pte): Add evexmap5 and evexmap6. (build_evex_prefix): Handle EVEXMAP5 and EVEXMAP6. (check_VecOperations): Handle {1to32}. (check_VecOperands): Handle CheckRegNumb. (check_word_reg): Handle Toqword. (i386_error): Add invalid_dest_and_src_register_set. (match_template): Handle invalid_dest_and_src_register_set. * doc/c-i386.texi: Document avx512_fp16, noavx512_fp16. opcodes/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (EXwScalarS): New. (EXxh): Ditto. (EXxhc): Ditto. (EXxmmqh): Ditto. (EXxmmqdh): Ditto. (EXEvexXwb): Ditto. (DistinctDest_Fixup): Ditto. (enum): Add xh_mode, evex_half_bcst_xmmqh_mode, evex_half_bcst_xmmqdh_mode and w_swap_mode. (enum): Add PREFIX_EVEX_0F3A08_W_0, PREFIX_EVEX_0F3A0A_W_0, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3AC2, PREFIX_EVEX_MAP5_10, PREFIX_EVEX_MAP5_11, PREFIX_EVEX_MAP5_1D, PREFIX_EVEX_MAP5_2A, PREFIX_EVEX_MAP5_2C, PREFIX_EVEX_MAP5_2D, PREFIX_EVEX_MAP5_2E, PREFIX_EVEX_MAP5_2F, PREFIX_EVEX_MAP5_51, PREFIX_EVEX_MAP5_58, PREFIX_EVEX_MAP5_59, PREFIX_EVEX_MAP5_5A_W_0, PREFIX_EVEX_MAP5_5A_W_1, PREFIX_EVEX_MAP5_5B_W_0, PREFIX_EVEX_MAP5_5B_W_1, PREFIX_EVEX_MAP5_5C, PREFIX_EVEX_MAP5_5D, PREFIX_EVEX_MAP5_5E, PREFIX_EVEX_MAP5_5F, PREFIX_EVEX_MAP5_78, PREFIX_EVEX_MAP5_79, PREFIX_EVEX_MAP5_7A, PREFIX_EVEX_MAP5_7B, PREFIX_EVEX_MAP5_7C, PREFIX_EVEX_MAP5_7D_W_0, PREFIX_EVEX_MAP6_13, PREFIX_EVEX_MAP6_56, PREFIX_EVEX_MAP6_57, PREFIX_EVEX_MAP6_D6, PREFIX_EVEX_MAP6_D7 (enum): Add EVEX_MAP5 and EVEX_MAP6. (enum): Add EVEX_W_MAP5_5A, EVEX_W_MAP5_5B, EVEX_W_MAP5_78_P_0, EVEX_W_MAP5_78_P_2, EVEX_W_MAP5_79_P_0, EVEX_W_MAP5_79_P_2, EVEX_W_MAP5_7A_P_2, EVEX_W_MAP5_7A_P_3, EVEX_W_MAP5_7B_P_2, EVEX_W_MAP5_7C_P_0, EVEX_W_MAP5_7C_P_2, EVEX_W_MAP5_7D, EVEX_W_MAP6_13_P_0, EVEX_W_MAP6_13_P_2, (get_valid_dis386): Properly handle new instructions. (intel_operand_size): Handle new modes. (OP_E_memory): Ditto. (OP_EX): Ditto. * i386-dis-evex.h: Updated for AVX512_FP16. * i386-dis-evex-mod.h: Updated for AVX512_FP16. * i386-dis-evex-prefix.h: Updated for AVX512_FP16. * i386-dis-evex-reg.h : Updated for AVX512_FP16. * i386-dis-evex-w.h : Updated for AVX512_FP16. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_FP16_FLAGS, and CPU_ANY_AVX512_FP16_FLAGS. Update CPU_ANY_AVX512F_FLAGS and CPU_ANY_AVX512BW_FLAGS. (cpu_flags): Add CpuAVX512_FP16. (opcode_modifiers): Add DistinctDest. * i386-opc.h (enum): (AVX512_FP16): New. (i386_opcode_modifier): Add reqdistinctreg. (i386_cpu_flags): Add cpuavx512_fp16. (EVEXMAP5): Defined as a macro. (EVEXMAP6): Ditto. * i386-opc.tbl: Add Intel AVX512_FP16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Ditto.
2021-06-14 11:05:05 +08:00
{ "vpshufbitqmb", { MaskG, Vex, EXx }, PREFIX_DATA },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
/* 90 */
x86: flag bad S/G insn operand combinations For VEX-encoded ones, all three involved vector registers have to be distinct. For EVEX-encoded ones an actual mask register has to be in use and zeroing-masking cannot be used (violation of either will #UD). Additionally both involved vector registers have to be distinct for EVEX-encoded gathers.
2021-03-25 15:20:19 +08:00
{ "vpgatherd%DQ", { XMGatherD, MVexVSIBDWpX }, PREFIX_DATA },
x86/Intel: correct AVX512 S/G disassembly Commit 6ff00b5e12e7 ("x86/Intel: correct permitted operand sizes for AVX512 scatter/gather") brought the assembler side of AVX512 S/G insn handling in line with AVX2's, but the disassembler side was forgotten. This has the benefit of - allowing to fold a number of table entries, - rendering a few #define-s and enumerators unused.
2021-03-10 15:20:29 +08:00
{ "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX }, PREFIX_DATA },
x86: flag bad S/G insn operand combinations For VEX-encoded ones, all three involved vector registers have to be distinct. For EVEX-encoded ones an actual mask register has to be in use and zeroing-masking cannot be used (violation of either will #UD). Additionally both involved vector registers have to be distinct for EVEX-encoded gathers.
2021-03-25 15:20:19 +08:00
{ "vgatherdp%XW", { XMGatherD, MVexVSIBDWpX }, PREFIX_DATA },
x86/Intel: correct AVX512 S/G disassembly Commit 6ff00b5e12e7 ("x86/Intel: correct permitted operand sizes for AVX512 scatter/gather") brought the assembler side of AVX512 S/G insn handling in line with AVX2's, but the disassembler side was forgotten. This has the benefit of - allowing to fold a number of table entries, - rendering a few #define-s and enumerators unused.
2021-03-10 15:20:29 +08:00
{ "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX }, PREFIX_DATA },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ Bad_Opcode },
{ Bad_Opcode },
x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns When no AVX512-specific functionality is in use, the disassembly of AVX512VL insns is indistinguishable from their AVX counterparts (if such exist). Emit the {evex} pseudo-prefix in such cases. Where applicable drop stray uses of PREFIX_OPCODE from table entries.
2022-10-24 15:30:58 +08:00
{ "%XEvfmaddsub132p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
{ "%XEvfmsubadd132p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
/* 98 */
x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns When no AVX512-specific functionality is in use, the disassembly of AVX512VL insns is indistinguishable from their AVX counterparts (if such exist). Emit the {evex} pseudo-prefix in such cases. Where applicable drop stray uses of PREFIX_OPCODE from table entries.
2022-10-24 15:30:58 +08:00
{ "%XEvfmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
{ "%XEvfmadd132s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ PREFIX_TABLE (PREFIX_EVEX_0F389A) },
{ PREFIX_TABLE (PREFIX_EVEX_0F389B) },
x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns When no AVX512-specific functionality is in use, the disassembly of AVX512VL insns is indistinguishable from their AVX counterparts (if such exist). Emit the {evex} pseudo-prefix in such cases. Where applicable drop stray uses of PREFIX_OPCODE from table entries.
2022-10-24 15:30:58 +08:00
{ "%XEvfnmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
{ "%XEvfnmadd132s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
{ "%XEvfnmsub132p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
{ "%XEvfnmsub132s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
/* A0 */
x86: simplify decode of opcodes valid with (embedded) 66 prefix only The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14 16:33:40 +08:00
{ "vpscatterd%DQ", { MVexVSIBDWpX, XM }, PREFIX_DATA },
x86/Intel: correct AVX512 S/G disassembly Commit 6ff00b5e12e7 ("x86/Intel: correct permitted operand sizes for AVX512 scatter/gather") brought the assembler side of AVX512 S/G insn handling in line with AVX2's, but the disassembler side was forgotten. This has the benefit of - allowing to fold a number of table entries, - rendering a few #define-s and enumerators unused.
2021-03-10 15:20:29 +08:00
{ "vpscatterq%DQ", { MVexVSIBQWpX, XMGatherQ }, PREFIX_DATA },
x86: simplify decode of opcodes valid with (embedded) 66 prefix only The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14 16:33:40 +08:00
{ "vscatterdp%XW", { MVexVSIBDWpX, XM }, PREFIX_DATA },
x86/Intel: correct AVX512 S/G disassembly Commit 6ff00b5e12e7 ("x86/Intel: correct permitted operand sizes for AVX512 scatter/gather") brought the assembler side of AVX512 S/G insn handling in line with AVX2's, but the disassembler side was forgotten. This has the benefit of - allowing to fold a number of table entries, - rendering a few #define-s and enumerators unused.
2021-03-10 15:20:29 +08:00
{ "vscatterqp%XW", { MVexVSIBQWpX, XMGatherQ }, PREFIX_DATA },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ Bad_Opcode },
{ Bad_Opcode },
x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns When no AVX512-specific functionality is in use, the disassembly of AVX512VL insns is indistinguishable from their AVX counterparts (if such exist). Emit the {evex} pseudo-prefix in such cases. Where applicable drop stray uses of PREFIX_OPCODE from table entries.
2022-10-24 15:30:58 +08:00
{ "%XEvfmaddsub213p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
{ "%XEvfmsubadd213p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
/* A8 */
x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns When no AVX512-specific functionality is in use, the disassembly of AVX512VL insns is indistinguishable from their AVX counterparts (if such exist). Emit the {evex} pseudo-prefix in such cases. Where applicable drop stray uses of PREFIX_OPCODE from table entries.
2022-10-24 15:30:58 +08:00
{ "%XEvfmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
{ "%XEvfmadd213s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ PREFIX_TABLE (PREFIX_EVEX_0F38AA) },
{ PREFIX_TABLE (PREFIX_EVEX_0F38AB) },
x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns When no AVX512-specific functionality is in use, the disassembly of AVX512VL insns is indistinguishable from their AVX counterparts (if such exist). Emit the {evex} pseudo-prefix in such cases. Where applicable drop stray uses of PREFIX_OPCODE from table entries.
2022-10-24 15:30:58 +08:00
{ "%XEvfnmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
{ "%XEvfnmadd213s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
{ "%XEvfnmsub213p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
{ "%XEvfnmsub213s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
/* B0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
Support Intel AVX-IFMA x86: Support Intel AVX-IFMA Intel AVX IFMA instructions are marked with CpuVEX_PREFIX, which is cleared by default. Without {vex} pseudo prefix, Intel IFMA instructions are encoded with EVEX prefix. {vex} pseudo prefix will turn on VEX encoding for Intel IFMA instructions. gas/ * NEWS: Support Intel AVX-IFMA. * config/tc-i386.c (cpu_arch): Add avx_ifma. * doc/c-i386.texi: Document .avx_ifma. * testsuite/gas/i386/avx-ifma.d: New file. * testsuite/gas/i386/avx-ifma-intel.d: Likewise. * testsuite/gas/i386/avx-ifma.s: Likewise. * testsuite/gas/i386/x86-64-avx-ifma.d: Likewise. * testsuite/gas/i386/x86-64-avx-ifma-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx-ifma.s: Likewise. * testsuite/gas/i386/i386.exp: Run AVX IFMA tests. opcodes/ * i386-dis.c (PREFIX_VEX_0F38B4): New. (PREFIX_VEX_0F38B5): Likewise. (VEX_W_0F38B4_P_2): Likewise. (VEX_W_0F38B5_P_2): Likewise. (prefix_table): Add PREFIX_VEX_0F38B4 and PREFIX_VEX_0F38B5. (vex_table): Add VEX_W_0F38B4_P_2 and VEX_W_0F38B5_P_2. * i386-dis-evex.h: Fold AVX512IFMA entries to AVX-IFMA. * i386-gen.c (cpu_flag_init): Clear the CpuAVX_IFMA bit in CPU_UNKNOWN_FLAGS. Add CPU_AVX_IFMA_FLGAS and CPU_ANY_AVX_IFMA_FLAGS. Add CpuAVX_IFMA to CPU_AVX2_FLAGS. (cpu_flags): Add CpuAVX_IFMA. * i386-opc.h (CpuAVX_IFMA): New. (i386_cpu_flags): Add cpuavx_ifma. * i386-opc.tbl: Add Intel AVX IFMA instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise. Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
2022-11-01 10:49:29 +08:00
{ VEX_W_TABLE (VEX_W_0F38B4) },
{ VEX_W_TABLE (VEX_W_0F38B5) },
x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns When no AVX512-specific functionality is in use, the disassembly of AVX512VL insns is indistinguishable from their AVX counterparts (if such exist). Emit the {evex} pseudo-prefix in such cases. Where applicable drop stray uses of PREFIX_OPCODE from table entries.
2022-10-24 15:30:58 +08:00
{ "%XEvfmaddsub231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
{ "%XEvfmsubadd231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
/* B8 */
x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns When no AVX512-specific functionality is in use, the disassembly of AVX512VL insns is indistinguishable from their AVX counterparts (if such exist). Emit the {evex} pseudo-prefix in such cases. Where applicable drop stray uses of PREFIX_OPCODE from table entries.
2022-10-24 15:30:58 +08:00
{ "%XEvfmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
{ "%XEvfmadd231s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
{ "%XEvfmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
{ "%XEvfmsub231s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
{ "%XEvfnmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
{ "%XEvfnmadd231s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
{ "%XEvfnmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
{ "%XEvfnmsub231s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
/* C0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
x86: simplify decode of opcodes valid with (embedded) 66 prefix only The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14 16:33:40 +08:00
{ "vpconflict%DQ", { XM, EXx }, PREFIX_DATA },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ Bad_Opcode },
Revert "2.41 Release sources" This reverts commit 675b9d612cc59446e84e2c6d89b45500cb603a8d. See https://sourceware.org/pipermail/binutils/2023-August/128761.html.
2023-08-02 19:06:23 +08:00
{ EVEX_LEN_TABLE (EVEX_LEN_0F38C6) },
{ EVEX_LEN_TABLE (EVEX_LEN_0F38C7) },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
/* C8 */
[PATCH 1/2] Enable Intel AVX512_FP16 instructions Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32 in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx). There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8 operands predated our current conventions; those instructions moved to map 3. FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3 is very sparsely populated. Most of the FP16 instructions share opcodes and prefix (EVEX.pp) bits with the related FP32 operations. Intel AVX512 FP16 instructions has new displacements scaling rules, please refer to the public software developer manual for detail information. gas/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (struct Broadcast_Operation): Adjust comment. (cpu_arch): Add .avx512_fp16. (cpu_noarch): Add noavx512_fp16. (pte): Add evexmap5 and evexmap6. (build_evex_prefix): Handle EVEXMAP5 and EVEXMAP6. (check_VecOperations): Handle {1to32}. (check_VecOperands): Handle CheckRegNumb. (check_word_reg): Handle Toqword. (i386_error): Add invalid_dest_and_src_register_set. (match_template): Handle invalid_dest_and_src_register_set. * doc/c-i386.texi: Document avx512_fp16, noavx512_fp16. opcodes/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (EXwScalarS): New. (EXxh): Ditto. (EXxhc): Ditto. (EXxmmqh): Ditto. (EXxmmqdh): Ditto. (EXEvexXwb): Ditto. (DistinctDest_Fixup): Ditto. (enum): Add xh_mode, evex_half_bcst_xmmqh_mode, evex_half_bcst_xmmqdh_mode and w_swap_mode. (enum): Add PREFIX_EVEX_0F3A08_W_0, PREFIX_EVEX_0F3A0A_W_0, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3AC2, PREFIX_EVEX_MAP5_10, PREFIX_EVEX_MAP5_11, PREFIX_EVEX_MAP5_1D, PREFIX_EVEX_MAP5_2A, PREFIX_EVEX_MAP5_2C, PREFIX_EVEX_MAP5_2D, PREFIX_EVEX_MAP5_2E, PREFIX_EVEX_MAP5_2F, PREFIX_EVEX_MAP5_51, PREFIX_EVEX_MAP5_58, PREFIX_EVEX_MAP5_59, PREFIX_EVEX_MAP5_5A_W_0, PREFIX_EVEX_MAP5_5A_W_1, PREFIX_EVEX_MAP5_5B_W_0, PREFIX_EVEX_MAP5_5B_W_1, PREFIX_EVEX_MAP5_5C, PREFIX_EVEX_MAP5_5D, PREFIX_EVEX_MAP5_5E, PREFIX_EVEX_MAP5_5F, PREFIX_EVEX_MAP5_78, PREFIX_EVEX_MAP5_79, PREFIX_EVEX_MAP5_7A, PREFIX_EVEX_MAP5_7B, PREFIX_EVEX_MAP5_7C, PREFIX_EVEX_MAP5_7D_W_0, PREFIX_EVEX_MAP6_13, PREFIX_EVEX_MAP6_56, PREFIX_EVEX_MAP6_57, PREFIX_EVEX_MAP6_D6, PREFIX_EVEX_MAP6_D7 (enum): Add EVEX_MAP5 and EVEX_MAP6. (enum): Add EVEX_W_MAP5_5A, EVEX_W_MAP5_5B, EVEX_W_MAP5_78_P_0, EVEX_W_MAP5_78_P_2, EVEX_W_MAP5_79_P_0, EVEX_W_MAP5_79_P_2, EVEX_W_MAP5_7A_P_2, EVEX_W_MAP5_7A_P_3, EVEX_W_MAP5_7B_P_2, EVEX_W_MAP5_7C_P_0, EVEX_W_MAP5_7C_P_2, EVEX_W_MAP5_7D, EVEX_W_MAP6_13_P_0, EVEX_W_MAP6_13_P_2, (get_valid_dis386): Properly handle new instructions. (intel_operand_size): Handle new modes. (OP_E_memory): Ditto. (OP_EX): Ditto. * i386-dis-evex.h: Updated for AVX512_FP16. * i386-dis-evex-mod.h: Updated for AVX512_FP16. * i386-dis-evex-prefix.h: Updated for AVX512_FP16. * i386-dis-evex-reg.h : Updated for AVX512_FP16. * i386-dis-evex-w.h : Updated for AVX512_FP16. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_FP16_FLAGS, and CPU_ANY_AVX512_FP16_FLAGS. Update CPU_ANY_AVX512F_FLAGS and CPU_ANY_AVX512BW_FLAGS. (cpu_flags): Add CpuAVX512_FP16. (opcode_modifiers): Add DistinctDest. * i386-opc.h (enum): (AVX512_FP16): New. (i386_opcode_modifier): Add reqdistinctreg. (i386_cpu_flags): Add cpuavx512_fp16. (EVEXMAP5): Defined as a macro. (EVEXMAP6): Ditto. * i386-opc.tbl: Add Intel AVX512_FP16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Ditto.
2021-06-14 11:05:05 +08:00
{ "vexp2p%XW", { XM, EXx, EXxEVexS }, PREFIX_DATA },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ Bad_Opcode },
[PATCH 1/2] Enable Intel AVX512_FP16 instructions Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32 in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx). There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8 operands predated our current conventions; those instructions moved to map 3. FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3 is very sparsely populated. Most of the FP16 instructions share opcodes and prefix (EVEX.pp) bits with the related FP32 operations. Intel AVX512 FP16 instructions has new displacements scaling rules, please refer to the public software developer manual for detail information. gas/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (struct Broadcast_Operation): Adjust comment. (cpu_arch): Add .avx512_fp16. (cpu_noarch): Add noavx512_fp16. (pte): Add evexmap5 and evexmap6. (build_evex_prefix): Handle EVEXMAP5 and EVEXMAP6. (check_VecOperations): Handle {1to32}. (check_VecOperands): Handle CheckRegNumb. (check_word_reg): Handle Toqword. (i386_error): Add invalid_dest_and_src_register_set. (match_template): Handle invalid_dest_and_src_register_set. * doc/c-i386.texi: Document avx512_fp16, noavx512_fp16. opcodes/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (EXwScalarS): New. (EXxh): Ditto. (EXxhc): Ditto. (EXxmmqh): Ditto. (EXxmmqdh): Ditto. (EXEvexXwb): Ditto. (DistinctDest_Fixup): Ditto. (enum): Add xh_mode, evex_half_bcst_xmmqh_mode, evex_half_bcst_xmmqdh_mode and w_swap_mode. (enum): Add PREFIX_EVEX_0F3A08_W_0, PREFIX_EVEX_0F3A0A_W_0, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3AC2, PREFIX_EVEX_MAP5_10, PREFIX_EVEX_MAP5_11, PREFIX_EVEX_MAP5_1D, PREFIX_EVEX_MAP5_2A, PREFIX_EVEX_MAP5_2C, PREFIX_EVEX_MAP5_2D, PREFIX_EVEX_MAP5_2E, PREFIX_EVEX_MAP5_2F, PREFIX_EVEX_MAP5_51, PREFIX_EVEX_MAP5_58, PREFIX_EVEX_MAP5_59, PREFIX_EVEX_MAP5_5A_W_0, PREFIX_EVEX_MAP5_5A_W_1, PREFIX_EVEX_MAP5_5B_W_0, PREFIX_EVEX_MAP5_5B_W_1, PREFIX_EVEX_MAP5_5C, PREFIX_EVEX_MAP5_5D, PREFIX_EVEX_MAP5_5E, PREFIX_EVEX_MAP5_5F, PREFIX_EVEX_MAP5_78, PREFIX_EVEX_MAP5_79, PREFIX_EVEX_MAP5_7A, PREFIX_EVEX_MAP5_7B, PREFIX_EVEX_MAP5_7C, PREFIX_EVEX_MAP5_7D_W_0, PREFIX_EVEX_MAP6_13, PREFIX_EVEX_MAP6_56, PREFIX_EVEX_MAP6_57, PREFIX_EVEX_MAP6_D6, PREFIX_EVEX_MAP6_D7 (enum): Add EVEX_MAP5 and EVEX_MAP6. (enum): Add EVEX_W_MAP5_5A, EVEX_W_MAP5_5B, EVEX_W_MAP5_78_P_0, EVEX_W_MAP5_78_P_2, EVEX_W_MAP5_79_P_0, EVEX_W_MAP5_79_P_2, EVEX_W_MAP5_7A_P_2, EVEX_W_MAP5_7A_P_3, EVEX_W_MAP5_7B_P_2, EVEX_W_MAP5_7C_P_0, EVEX_W_MAP5_7C_P_2, EVEX_W_MAP5_7D, EVEX_W_MAP6_13_P_0, EVEX_W_MAP6_13_P_2, (get_valid_dis386): Properly handle new instructions. (intel_operand_size): Handle new modes. (OP_E_memory): Ditto. (OP_EX): Ditto. * i386-dis-evex.h: Updated for AVX512_FP16. * i386-dis-evex-mod.h: Updated for AVX512_FP16. * i386-dis-evex-prefix.h: Updated for AVX512_FP16. * i386-dis-evex-reg.h : Updated for AVX512_FP16. * i386-dis-evex-w.h : Updated for AVX512_FP16. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_FP16_FLAGS, and CPU_ANY_AVX512_FP16_FLAGS. Update CPU_ANY_AVX512F_FLAGS and CPU_ANY_AVX512BW_FLAGS. (cpu_flags): Add CpuAVX512_FP16. (opcode_modifiers): Add DistinctDest. * i386-opc.h (enum): (AVX512_FP16): New. (i386_opcode_modifier): Add reqdistinctreg. (i386_cpu_flags): Add cpuavx512_fp16. (EVEXMAP5): Defined as a macro. (EVEXMAP6): Ditto. * i386-opc.tbl: Add Intel AVX512_FP16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Ditto.
2021-06-14 11:05:05 +08:00
{ "vrcp28p%XW", { XM, EXx, EXxEVexS }, PREFIX_DATA },
x86: drop vex_scalar_w_dq_mode It has only a single use and can easily be represented by dq_mode instead. Plus its handling in intel_operand_size() was duplicating that of vex_vsib_{d,q}_w_dq_mode anyway.
2021-07-22 19:09:03 +08:00
{ "vrcp28s%XW", { XMScalar, VexScalar, EXdq, EXxEVexS }, PREFIX_DATA },
[PATCH 1/2] Enable Intel AVX512_FP16 instructions Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32 in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx). There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8 operands predated our current conventions; those instructions moved to map 3. FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3 is very sparsely populated. Most of the FP16 instructions share opcodes and prefix (EVEX.pp) bits with the related FP32 operations. Intel AVX512 FP16 instructions has new displacements scaling rules, please refer to the public software developer manual for detail information. gas/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (struct Broadcast_Operation): Adjust comment. (cpu_arch): Add .avx512_fp16. (cpu_noarch): Add noavx512_fp16. (pte): Add evexmap5 and evexmap6. (build_evex_prefix): Handle EVEXMAP5 and EVEXMAP6. (check_VecOperations): Handle {1to32}. (check_VecOperands): Handle CheckRegNumb. (check_word_reg): Handle Toqword. (i386_error): Add invalid_dest_and_src_register_set. (match_template): Handle invalid_dest_and_src_register_set. * doc/c-i386.texi: Document avx512_fp16, noavx512_fp16. opcodes/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (EXwScalarS): New. (EXxh): Ditto. (EXxhc): Ditto. (EXxmmqh): Ditto. (EXxmmqdh): Ditto. (EXEvexXwb): Ditto. (DistinctDest_Fixup): Ditto. (enum): Add xh_mode, evex_half_bcst_xmmqh_mode, evex_half_bcst_xmmqdh_mode and w_swap_mode. (enum): Add PREFIX_EVEX_0F3A08_W_0, PREFIX_EVEX_0F3A0A_W_0, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3AC2, PREFIX_EVEX_MAP5_10, PREFIX_EVEX_MAP5_11, PREFIX_EVEX_MAP5_1D, PREFIX_EVEX_MAP5_2A, PREFIX_EVEX_MAP5_2C, PREFIX_EVEX_MAP5_2D, PREFIX_EVEX_MAP5_2E, PREFIX_EVEX_MAP5_2F, PREFIX_EVEX_MAP5_51, PREFIX_EVEX_MAP5_58, PREFIX_EVEX_MAP5_59, PREFIX_EVEX_MAP5_5A_W_0, PREFIX_EVEX_MAP5_5A_W_1, PREFIX_EVEX_MAP5_5B_W_0, PREFIX_EVEX_MAP5_5B_W_1, PREFIX_EVEX_MAP5_5C, PREFIX_EVEX_MAP5_5D, PREFIX_EVEX_MAP5_5E, PREFIX_EVEX_MAP5_5F, PREFIX_EVEX_MAP5_78, PREFIX_EVEX_MAP5_79, PREFIX_EVEX_MAP5_7A, PREFIX_EVEX_MAP5_7B, PREFIX_EVEX_MAP5_7C, PREFIX_EVEX_MAP5_7D_W_0, PREFIX_EVEX_MAP6_13, PREFIX_EVEX_MAP6_56, PREFIX_EVEX_MAP6_57, PREFIX_EVEX_MAP6_D6, PREFIX_EVEX_MAP6_D7 (enum): Add EVEX_MAP5 and EVEX_MAP6. (enum): Add EVEX_W_MAP5_5A, EVEX_W_MAP5_5B, EVEX_W_MAP5_78_P_0, EVEX_W_MAP5_78_P_2, EVEX_W_MAP5_79_P_0, EVEX_W_MAP5_79_P_2, EVEX_W_MAP5_7A_P_2, EVEX_W_MAP5_7A_P_3, EVEX_W_MAP5_7B_P_2, EVEX_W_MAP5_7C_P_0, EVEX_W_MAP5_7C_P_2, EVEX_W_MAP5_7D, EVEX_W_MAP6_13_P_0, EVEX_W_MAP6_13_P_2, (get_valid_dis386): Properly handle new instructions. (intel_operand_size): Handle new modes. (OP_E_memory): Ditto. (OP_EX): Ditto. * i386-dis-evex.h: Updated for AVX512_FP16. * i386-dis-evex-mod.h: Updated for AVX512_FP16. * i386-dis-evex-prefix.h: Updated for AVX512_FP16. * i386-dis-evex-reg.h : Updated for AVX512_FP16. * i386-dis-evex-w.h : Updated for AVX512_FP16. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_FP16_FLAGS, and CPU_ANY_AVX512_FP16_FLAGS. Update CPU_ANY_AVX512F_FLAGS and CPU_ANY_AVX512BW_FLAGS. (cpu_flags): Add CpuAVX512_FP16. (opcode_modifiers): Add DistinctDest. * i386-opc.h (enum): (AVX512_FP16): New. (i386_opcode_modifier): Add reqdistinctreg. (i386_cpu_flags): Add cpuavx512_fp16. (EVEXMAP5): Defined as a macro. (EVEXMAP6): Ditto. * i386-opc.tbl: Add Intel AVX512_FP16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Ditto.
2021-06-14 11:05:05 +08:00
{ "vrsqrt28p%XW", { XM, EXx, EXxEVexS }, PREFIX_DATA },
x86: drop vex_scalar_w_dq_mode It has only a single use and can easily be represented by dq_mode instead. Plus its handling in intel_operand_size() was duplicating that of vex_vsib_{d,q}_w_dq_mode anyway.
2021-07-22 19:09:03 +08:00
{ "vrsqrt28s%XW", { XMScalar, VexScalar, EXdq, EXxEVexS }, PREFIX_DATA },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ Bad_Opcode },
x86: simplify decode of opcodes valid with (embedded) 66 prefix only The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14 16:33:40 +08:00
{ VEX_W_TABLE (VEX_W_0F38CF) },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
/* D0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* D8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
Revert "2.41 Release sources" This reverts commit 675b9d612cc59446e84e2c6d89b45500cb603a8d. See https://sourceware.org/pipermail/binutils/2023-August/128761.html.
2023-08-02 19:06:23 +08:00
{ "%XEvaesencY", { XM, Vex, EXx }, PREFIX_DATA },
{ "%XEvaesenclastY", { XM, Vex, EXx }, PREFIX_DATA },
{ "%XEvaesdecY", { XM, Vex, EXx }, PREFIX_DATA },
{ "%XEvaesdeclastY", { XM, Vex, EXx }, PREFIX_DATA },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
/* E0 */
Support APX GPR32 with extend evex prefix This patch adds non-ND, non-NF forms of EVEX promotion insn. EVEX extension of legacy instructions: All promoted legacy instructions are placed in EVEX map 4, which is currently reserved. EVEX extension of EVEX instructions: All existing EVEX instructions are extended by APX using the extended EVEX prefix, so that they can access all 32 GPRs. EVEX extension of VEX instructions: Promoting a VEX instruction into the EVEX space does not change the map id, the opcode, or the operand encoding of the VEX instruction. Note: The promoted versions of MOVBE will be extended to include the “MOVBE reg1, reg2”. gas/ChangeLog: 2023-12-28 Lingling Kong <lingling.kong@intel.com> H.J. Lu <hongjiu.lu@intel.com> Lili Cui <lili.cui@intel.com> Lin Hu <lin1.hu@intel.com> * config/tc-i386.c (struct _i386_insn): Add has_egpr. (need_evex_encoding): Adjusted for apx. (cpu_flags_match): Ditto. (install_template): Handled APX combines. (is_apx_evex_encoding): Test apx evex encoding. (build_apx_evex_prefix): Enabe APX evex prefix. (md_assemble): Handle apx with evex encoding. (process_suffix): Handle apx map4 prefix. (check_register): Assign i.vec_encoding for APX evex instructions. * testsuite/gas/i386/x86-64-evex.d: Adjust test cases. * testsuite/gas/i386/x86-64.exp: Adjust x86-64-inval-movbe. opcodes/ChangeLog: * i386-dis-evex-len.h: Handle EVEX_LEN_0F38F2, EVEX_LEN_0F38F3. * i386-dis-evex-prefix.h: Handle PREFIX_EVEX_0F38F2_L_0, PREFIX_EVEX_0F38F3_L_0, PREFIX_EVEX_MAP4_D8, PREFIX_EVEX_MAP4_DA, PREFIX_EVEX_MAP4_DB, PREFIX_EVEX_MAP4_DC, PREFIX_EVEX_MAP4_DD, PREFIX_EVEX_MAP4_DE, PREFIX_EVEX_MAP4_DF, PREFIX_EVEX_MAP4_F0, PREFIX_EVEX_MAP4_F1, PREFIX_EVEX_MAP4_F2, PREFIX_EVEX_MAP4_F8. * i386-dis-evex-reg.h: Handle REG_EVEX_0F38F3_L_0_P_0. * i386-dis-evex.h: Add EVEX_MAP4_ for legacy insn promote to apx to use gpr32 * opcodes/i386-dis-evex-x86-64.h: Handle Add X86_64_EVEX_0F90, X86_64_EVEX_0F92, X86_64_EVEX_0F93, X86_64_EVEX_0F38F2, X86_64_EVEX_0F38F3, X86_64_EVEX_0F38F5, X86_64_EVEX_0F38F6, X86_64_EVEX_0F38F7, X86_64_EVEX_0F3AF0, X86_64_EVEX_0F91. * i386-dis.c (struct instr_info): Deleted bool r. (PREFIX_NP_OR_DATA): New. (NO_PREFIX): New. (putop): Ditto. (X86_64_EVEX_FROM_VEX_TABLE): Diito. (get_valid_dis386): Decode insn erex in extend evex prefix. Handle EVEX_MAP4 (print_insn): Handle PREFIX_DATA_AND_NP_ONLY. (print_register): Handle apx instructions decode. (OP_E_memory): Diito. (OP_G): Diito. (OP_XMM): Diito. (DistinctDest_Fixup): Diito. * i386-gen.c (process_i386_opcode_modifier): Add EVEXMAP4. * i386-opc.h (SPACE_EVEXMAP4): Add legacy insn promote to evex. * i386-opc.tbl: Handle some legacy and vex insns don't support gpr32. And add some legacy insn (map2 / 3) promote to evex.
2023-12-28 09:06:40 +08:00
{ X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38E0) },
{ X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38E1) },
{ X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38E2) },
{ X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38E3) },
{ X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38E4) },
{ X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38E5) },
{ X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38E6) },
{ X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38E7) },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
/* E8 */
Support APX GPR32 with extend evex prefix This patch adds non-ND, non-NF forms of EVEX promotion insn. EVEX extension of legacy instructions: All promoted legacy instructions are placed in EVEX map 4, which is currently reserved. EVEX extension of EVEX instructions: All existing EVEX instructions are extended by APX using the extended EVEX prefix, so that they can access all 32 GPRs. EVEX extension of VEX instructions: Promoting a VEX instruction into the EVEX space does not change the map id, the opcode, or the operand encoding of the VEX instruction. Note: The promoted versions of MOVBE will be extended to include the “MOVBE reg1, reg2”. gas/ChangeLog: 2023-12-28 Lingling Kong <lingling.kong@intel.com> H.J. Lu <hongjiu.lu@intel.com> Lili Cui <lili.cui@intel.com> Lin Hu <lin1.hu@intel.com> * config/tc-i386.c (struct _i386_insn): Add has_egpr. (need_evex_encoding): Adjusted for apx. (cpu_flags_match): Ditto. (install_template): Handled APX combines. (is_apx_evex_encoding): Test apx evex encoding. (build_apx_evex_prefix): Enabe APX evex prefix. (md_assemble): Handle apx with evex encoding. (process_suffix): Handle apx map4 prefix. (check_register): Assign i.vec_encoding for APX evex instructions. * testsuite/gas/i386/x86-64-evex.d: Adjust test cases. * testsuite/gas/i386/x86-64.exp: Adjust x86-64-inval-movbe. opcodes/ChangeLog: * i386-dis-evex-len.h: Handle EVEX_LEN_0F38F2, EVEX_LEN_0F38F3. * i386-dis-evex-prefix.h: Handle PREFIX_EVEX_0F38F2_L_0, PREFIX_EVEX_0F38F3_L_0, PREFIX_EVEX_MAP4_D8, PREFIX_EVEX_MAP4_DA, PREFIX_EVEX_MAP4_DB, PREFIX_EVEX_MAP4_DC, PREFIX_EVEX_MAP4_DD, PREFIX_EVEX_MAP4_DE, PREFIX_EVEX_MAP4_DF, PREFIX_EVEX_MAP4_F0, PREFIX_EVEX_MAP4_F1, PREFIX_EVEX_MAP4_F2, PREFIX_EVEX_MAP4_F8. * i386-dis-evex-reg.h: Handle REG_EVEX_0F38F3_L_0_P_0. * i386-dis-evex.h: Add EVEX_MAP4_ for legacy insn promote to apx to use gpr32 * opcodes/i386-dis-evex-x86-64.h: Handle Add X86_64_EVEX_0F90, X86_64_EVEX_0F92, X86_64_EVEX_0F93, X86_64_EVEX_0F38F2, X86_64_EVEX_0F38F3, X86_64_EVEX_0F38F5, X86_64_EVEX_0F38F6, X86_64_EVEX_0F38F7, X86_64_EVEX_0F3AF0, X86_64_EVEX_0F91. * i386-dis.c (struct instr_info): Deleted bool r. (PREFIX_NP_OR_DATA): New. (NO_PREFIX): New. (putop): Ditto. (X86_64_EVEX_FROM_VEX_TABLE): Diito. (get_valid_dis386): Decode insn erex in extend evex prefix. Handle EVEX_MAP4 (print_insn): Handle PREFIX_DATA_AND_NP_ONLY. (print_register): Handle apx instructions decode. (OP_E_memory): Diito. (OP_G): Diito. (OP_XMM): Diito. (DistinctDest_Fixup): Diito. * i386-gen.c (process_i386_opcode_modifier): Add EVEXMAP4. * i386-opc.h (SPACE_EVEXMAP4): Add legacy insn promote to evex. * i386-opc.tbl: Handle some legacy and vex insns don't support gpr32. And add some legacy insn (map2 / 3) promote to evex.
2023-12-28 09:06:40 +08:00
{ X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38E8) },
{ X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38E9) },
{ X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38EA) },
{ X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38EB) },
{ X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38EC) },
{ X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38ED) },
{ X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38EE) },
{ X86_64_EVEX_FROM_VEX_TABLE (X86_64_VEX_0F38EF) },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
/* F0 */
{ Bad_Opcode },
{ Bad_Opcode },
x86/APX: no need to have decode go through x86_64_table[] As suggested during review already, all such entries have their first slot as Bad_Opcode, so by adding two more enumerators we can avoid doing that decode step altogether.
2024-01-26 17:34:24 +08:00
{ X86_64_EVEX_PFX_TABLE (PREFIX_VEX_0F38F2_L_0) },
{ X86_64_EVEX_PFX_TABLE (PREFIX_VEX_0F38F3_L_0) },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ Bad_Opcode },
x86/APX: no need to have decode go through x86_64_table[] As suggested during review already, all such entries have their first slot as Bad_Opcode, so by adding two more enumerators we can avoid doing that decode step altogether.
2024-01-26 17:34:24 +08:00
{ X86_64_EVEX_PFX_TABLE (PREFIX_VEX_0F38F5_L_0) },
{ X86_64_EVEX_PFX_TABLE (PREFIX_VEX_0F38F6_L_0) },
{ X86_64_EVEX_PFX_TABLE (PREFIX_VEX_0F38F7_L_0) },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
/* F8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
},
/* EVEX_0F3A */
{
/* 00 */
x86: reuse VEX entries for EVEX vperm{q,pd} By matching VEX decode order (L before W), some EVEX entries can refer back to VEX ones instead of carrying duplicates.
2021-03-10 15:18:24 +08:00
{ EVEX_LEN_TABLE (EVEX_LEN_0F3A00) },
{ EVEX_LEN_TABLE (EVEX_LEN_0F3A01) },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ Bad_Opcode },
x86: simplify decode of opcodes valid with (embedded) 66 prefix only The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14 16:33:40 +08:00
{ "valign%DQ", { XM, Vex, EXx, Ib }, PREFIX_DATA },
{ VEX_W_TABLE (VEX_W_0F3A04) },
x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns When no AVX512-specific functionality is in use, the disassembly of AVX512VL insns is indistinguishable from their AVX counterparts (if such exist). Emit the {evex} pseudo-prefix in such cases. Where applicable drop stray uses of PREFIX_OPCODE from table entries.
2022-10-24 15:30:58 +08:00
{ "%XEvpermilp%XD", { XM, EXx, Ib }, PREFIX_DATA },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ Bad_Opcode },
{ Bad_Opcode },
/* 08 */
x86: reduce AVX512-FP16 set of insns decoded through vex_w_table[] Like already indicated during review of the original submission, there's really only very few insns where going through this table is easier / cheaper than using suitable macros. Utilize %XH more and introduce similar %XS and %XD (which subsequently can be used for further table size reduction). While there also switch to using oappend() in 'XH' macro processing.
2022-01-14 17:54:21 +08:00
{ PREFIX_TABLE (PREFIX_EVEX_0F3A08) },
x86: reduce AVX512 FP set of insns decoded through vex_w_table[] Like for AVX512-FP16, there's not that many FP insns where going through this table is easier / cheaper than using suitable macros. Utilize %XS and %XD more to eliminate a fair number of table entries. While doing this I noticed a few anomalies. Where lines get touched / moved anyway, these are being addressed right here: - vmovshdup used EXx for its 2nd operand, thus displaying seemingly valid broadcast when EVEX.b is set with a memory operand; use EXEvexXNoBcst instead just like vmovsldup already does - vmovlhps used EXx for its 3rd operand, when all sibling entries use EXq; switch to EXq there for consistency (the two differ only for memory operands)
2022-01-14 17:54:55 +08:00
{ "vrndscalep%XD", { XM, EXx, EXxEVexS, Ib }, PREFIX_DATA },
x86: reduce AVX512-FP16 set of insns decoded through vex_w_table[] Like already indicated during review of the original submission, there's really only very few insns where going through this table is easier / cheaper than using suitable macros. Utilize %XH more and introduce similar %XS and %XD (which subsequently can be used for further table size reduction). While there also switch to using oappend() in 'XH' macro processing.
2022-01-14 17:54:21 +08:00
{ PREFIX_TABLE (PREFIX_EVEX_0F3A0A) },
x86: reduce AVX512 FP set of insns decoded through vex_w_table[] Like for AVX512-FP16, there's not that many FP insns where going through this table is easier / cheaper than using suitable macros. Utilize %XS and %XD more to eliminate a fair number of table entries. While doing this I noticed a few anomalies. Where lines get touched / moved anyway, these are being addressed right here: - vmovshdup used EXx for its 2nd operand, thus displaying seemingly valid broadcast when EVEX.b is set with a memory operand; use EXEvexXNoBcst instead just like vmovsldup already does - vmovlhps used EXx for its 3rd operand, when all sibling entries use EXq; switch to EXq there for consistency (the two differ only for memory operands)
2022-01-14 17:54:55 +08:00
{ "vrndscales%XD", { XMScalar, VexScalar, EXq, EXxEVexS, Ib }, PREFIX_DATA },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns When no AVX512-specific functionality is in use, the disassembly of AVX512VL insns is indistinguishable from their AVX counterparts (if such exist). Emit the {evex} pseudo-prefix in such cases. Where applicable drop stray uses of PREFIX_OPCODE from table entries.
2022-10-24 15:30:58 +08:00
{ "%XEvpalignr", { XM, Vex, EXx, Ib }, PREFIX_DATA },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
/* 10 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
x86: reuse further VEX entries for EVEX When the VEX.L=1 decode matches that of both EVEX.L'L=1 and EVEX.L'L=2 (typically when all three are invalid) the (smaller) VEX table entry can be reused by EVEX, instead of duplicating data. (Note that XM and XMM as well as EXxmm_md and EXd are equivalent at least for the purposes here.)
2021-03-10 15:19:11 +08:00
{ VEX_LEN_TABLE (VEX_LEN_0F3A14) },
{ VEX_LEN_TABLE (VEX_LEN_0F3A15) },
{ VEX_LEN_TABLE (VEX_LEN_0F3A16) },
{ VEX_LEN_TABLE (VEX_LEN_0F3A17) },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
/* 18 */
x86: re-arrange order of decode for various EVEX opcodes The order of decodes influences the overall number of table entries. Reduce table size quite a bit by first decoding few-alternatives attributes common to all valid leaves. This also adds a PREFIX_DATA 7531c61332db ("x86: simplify decode of opcodes valid with (embedded) 66 prefix only") missed to apply to vbroadcastf64x4.
2021-03-10 15:16:54 +08:00
{ EVEX_LEN_TABLE (EVEX_LEN_0F3A18) },
{ EVEX_LEN_TABLE (EVEX_LEN_0F3A19) },
{ EVEX_LEN_TABLE (EVEX_LEN_0F3A1A) },
{ EVEX_LEN_TABLE (EVEX_LEN_0F3A1B) },
x86: simplify decode of opcodes valid with (embedded) 66 prefix only The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14 16:33:40 +08:00
{ Bad_Opcode },
{ VEX_W_TABLE (VEX_W_0F3A1D) },
x86: drop OP_Mask() By moving its vex.r check there it becomes fully redundant with OP_G().
2021-07-22 19:01:09 +08:00
{ "vpcmpu%DQ", { MaskG, Vex, EXx, VPCMP }, PREFIX_DATA },
{ "vpcmp%DQ", { MaskG, Vex, EXx, VPCMP }, PREFIX_DATA },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
/* 20 */
x86: reuse further VEX entries for EVEX When the VEX.L=1 decode matches that of both EVEX.L'L=1 and EVEX.L'L=2 (typically when all three are invalid) the (smaller) VEX table entry can be reused by EVEX, instead of duplicating data. (Note that XM and XMM as well as EXxmm_md and EXd are equivalent at least for the purposes here.)
2021-03-10 15:19:11 +08:00
{ VEX_LEN_TABLE (VEX_LEN_0F3A20) },
x86: simplify decode of opcodes valid with (embedded) 66 prefix only The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14 16:33:40 +08:00
{ VEX_W_TABLE (EVEX_W_0F3A21) },
x86: reuse further VEX entries for EVEX When the VEX.L=1 decode matches that of both EVEX.L'L=1 and EVEX.L'L=2 (typically when all three are invalid) the (smaller) VEX table entry can be reused by EVEX, instead of duplicating data. (Note that XM and XMM as well as EXxmm_md and EXd are equivalent at least for the purposes here.)
2021-03-10 15:19:11 +08:00
{ VEX_LEN_TABLE (VEX_LEN_0F3A22) },
x86: re-arrange order of decode for various EVEX opcodes The order of decodes influences the overall number of table entries. Reduce table size quite a bit by first decoding few-alternatives attributes common to all valid leaves. This also adds a PREFIX_DATA 7531c61332db ("x86: simplify decode of opcodes valid with (embedded) 66 prefix only") missed to apply to vbroadcastf64x4.
2021-03-10 15:16:54 +08:00
{ EVEX_LEN_TABLE (EVEX_LEN_0F3A23) },
x86: simplify decode of opcodes valid with (embedded) 66 prefix only The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14 16:33:40 +08:00
{ Bad_Opcode },
{ "vpternlog%DQ", { XM, Vex, EXx, Ib }, PREFIX_DATA },
[PATCH 1/2] Enable Intel AVX512_FP16 instructions Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32 in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx). There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8 operands predated our current conventions; those instructions moved to map 3. FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3 is very sparsely populated. Most of the FP16 instructions share opcodes and prefix (EVEX.pp) bits with the related FP32 operations. Intel AVX512 FP16 instructions has new displacements scaling rules, please refer to the public software developer manual for detail information. gas/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (struct Broadcast_Operation): Adjust comment. (cpu_arch): Add .avx512_fp16. (cpu_noarch): Add noavx512_fp16. (pte): Add evexmap5 and evexmap6. (build_evex_prefix): Handle EVEXMAP5 and EVEXMAP6. (check_VecOperations): Handle {1to32}. (check_VecOperands): Handle CheckRegNumb. (check_word_reg): Handle Toqword. (i386_error): Add invalid_dest_and_src_register_set. (match_template): Handle invalid_dest_and_src_register_set. * doc/c-i386.texi: Document avx512_fp16, noavx512_fp16. opcodes/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (EXwScalarS): New. (EXxh): Ditto. (EXxhc): Ditto. (EXxmmqh): Ditto. (EXxmmqdh): Ditto. (EXEvexXwb): Ditto. (DistinctDest_Fixup): Ditto. (enum): Add xh_mode, evex_half_bcst_xmmqh_mode, evex_half_bcst_xmmqdh_mode and w_swap_mode. (enum): Add PREFIX_EVEX_0F3A08_W_0, PREFIX_EVEX_0F3A0A_W_0, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3AC2, PREFIX_EVEX_MAP5_10, PREFIX_EVEX_MAP5_11, PREFIX_EVEX_MAP5_1D, PREFIX_EVEX_MAP5_2A, PREFIX_EVEX_MAP5_2C, PREFIX_EVEX_MAP5_2D, PREFIX_EVEX_MAP5_2E, PREFIX_EVEX_MAP5_2F, PREFIX_EVEX_MAP5_51, PREFIX_EVEX_MAP5_58, PREFIX_EVEX_MAP5_59, PREFIX_EVEX_MAP5_5A_W_0, PREFIX_EVEX_MAP5_5A_W_1, PREFIX_EVEX_MAP5_5B_W_0, PREFIX_EVEX_MAP5_5B_W_1, PREFIX_EVEX_MAP5_5C, PREFIX_EVEX_MAP5_5D, PREFIX_EVEX_MAP5_5E, PREFIX_EVEX_MAP5_5F, PREFIX_EVEX_MAP5_78, PREFIX_EVEX_MAP5_79, PREFIX_EVEX_MAP5_7A, PREFIX_EVEX_MAP5_7B, PREFIX_EVEX_MAP5_7C, PREFIX_EVEX_MAP5_7D_W_0, PREFIX_EVEX_MAP6_13, PREFIX_EVEX_MAP6_56, PREFIX_EVEX_MAP6_57, PREFIX_EVEX_MAP6_D6, PREFIX_EVEX_MAP6_D7 (enum): Add EVEX_MAP5 and EVEX_MAP6. (enum): Add EVEX_W_MAP5_5A, EVEX_W_MAP5_5B, EVEX_W_MAP5_78_P_0, EVEX_W_MAP5_78_P_2, EVEX_W_MAP5_79_P_0, EVEX_W_MAP5_79_P_2, EVEX_W_MAP5_7A_P_2, EVEX_W_MAP5_7A_P_3, EVEX_W_MAP5_7B_P_2, EVEX_W_MAP5_7C_P_0, EVEX_W_MAP5_7C_P_2, EVEX_W_MAP5_7D, EVEX_W_MAP6_13_P_0, EVEX_W_MAP6_13_P_2, (get_valid_dis386): Properly handle new instructions. (intel_operand_size): Handle new modes. (OP_E_memory): Ditto. (OP_EX): Ditto. * i386-dis-evex.h: Updated for AVX512_FP16. * i386-dis-evex-mod.h: Updated for AVX512_FP16. * i386-dis-evex-prefix.h: Updated for AVX512_FP16. * i386-dis-evex-reg.h : Updated for AVX512_FP16. * i386-dis-evex-w.h : Updated for AVX512_FP16. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_FP16_FLAGS, and CPU_ANY_AVX512_FP16_FLAGS. Update CPU_ANY_AVX512F_FLAGS and CPU_ANY_AVX512BW_FLAGS. (cpu_flags): Add CpuAVX512_FP16. (opcode_modifiers): Add DistinctDest. * i386-opc.h (enum): (AVX512_FP16): New. (i386_opcode_modifier): Add reqdistinctreg. (i386_cpu_flags): Add cpuavx512_fp16. (EVEXMAP5): Defined as a macro. (EVEXMAP6): Ditto. * i386-opc.tbl: Add Intel AVX512_FP16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Ditto.
2021-06-14 11:05:05 +08:00
{ PREFIX_TABLE (PREFIX_EVEX_0F3A26) },
{ PREFIX_TABLE (PREFIX_EVEX_0F3A27) },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
/* 28 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 30 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 38 */
x86: re-arrange order of decode for various EVEX opcodes The order of decodes influences the overall number of table entries. Reduce table size quite a bit by first decoding few-alternatives attributes common to all valid leaves. This also adds a PREFIX_DATA 7531c61332db ("x86: simplify decode of opcodes valid with (embedded) 66 prefix only") missed to apply to vbroadcastf64x4.
2021-03-10 15:16:54 +08:00
{ EVEX_LEN_TABLE (EVEX_LEN_0F3A38) },
{ EVEX_LEN_TABLE (EVEX_LEN_0F3A39) },
{ EVEX_LEN_TABLE (EVEX_LEN_0F3A3A) },
{ EVEX_LEN_TABLE (EVEX_LEN_0F3A3B) },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ Bad_Opcode },
{ Bad_Opcode },
x86: drop OP_Mask() By moving its vex.r check there it becomes fully redundant with OP_G().
2021-07-22 19:01:09 +08:00
{ "vpcmpu%BW", { MaskG, Vex, EXx, VPCMP }, PREFIX_DATA },
{ "vpcmp%BW", { MaskG, Vex, EXx, VPCMP }, PREFIX_DATA },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
/* 40 */
{ Bad_Opcode },
{ Bad_Opcode },
x86: simplify decode of opcodes valid with (embedded) 66 prefix only The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14 16:33:40 +08:00
{ VEX_W_TABLE (EVEX_W_0F3A42) },
x86: re-arrange order of decode for various EVEX opcodes The order of decodes influences the overall number of table entries. Reduce table size quite a bit by first decoding few-alternatives attributes common to all valid leaves. This also adds a PREFIX_DATA 7531c61332db ("x86: simplify decode of opcodes valid with (embedded) 66 prefix only") missed to apply to vbroadcastf64x4.
2021-03-10 15:16:54 +08:00
{ EVEX_LEN_TABLE (EVEX_LEN_0F3A43) },
Revert "2.41 Release sources" This reverts commit 675b9d612cc59446e84e2c6d89b45500cb603a8d. See https://sourceware.org/pipermail/binutils/2023-August/128761.html.
2023-08-02 19:06:23 +08:00
{ "%XEvpclmulqdqY", { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 48 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 50 */
x86: simplify decode of opcodes valid with (embedded) 66 prefix only The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14 16:33:40 +08:00
{ "vrangep%XW", { XM, Vex, EXx, EXxEVexS, Ib }, PREFIX_DATA },
x86: drop vex_scalar_w_dq_mode It has only a single use and can easily be represented by dq_mode instead. Plus its handling in intel_operand_size() was duplicating that of vex_vsib_{d,q}_w_dq_mode anyway.
2021-07-22 19:09:03 +08:00
{ "vranges%XW", { XMScalar, VexScalar, EXdq, EXxEVexS, Ib }, PREFIX_DATA },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ Bad_Opcode },
{ Bad_Opcode },
x86: simplify decode of opcodes valid with (embedded) 66 prefix only The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14 16:33:40 +08:00
{ "vfixupimmp%XW", { XM, Vex, EXx, EXxEVexS, Ib }, PREFIX_DATA },
x86: drop vex_scalar_w_dq_mode It has only a single use and can easily be represented by dq_mode instead. Plus its handling in intel_operand_size() was duplicating that of vex_vsib_{d,q}_w_dq_mode anyway.
2021-07-22 19:09:03 +08:00
{ "vfixupimms%XW", { XMScalar, VexScalar, EXdq, EXxEVexS, Ib }, PREFIX_DATA },
[PATCH 1/2] Enable Intel AVX512_FP16 instructions Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32 in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx). There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8 operands predated our current conventions; those instructions moved to map 3. FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3 is very sparsely populated. Most of the FP16 instructions share opcodes and prefix (EVEX.pp) bits with the related FP32 operations. Intel AVX512 FP16 instructions has new displacements scaling rules, please refer to the public software developer manual for detail information. gas/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (struct Broadcast_Operation): Adjust comment. (cpu_arch): Add .avx512_fp16. (cpu_noarch): Add noavx512_fp16. (pte): Add evexmap5 and evexmap6. (build_evex_prefix): Handle EVEXMAP5 and EVEXMAP6. (check_VecOperations): Handle {1to32}. (check_VecOperands): Handle CheckRegNumb. (check_word_reg): Handle Toqword. (i386_error): Add invalid_dest_and_src_register_set. (match_template): Handle invalid_dest_and_src_register_set. * doc/c-i386.texi: Document avx512_fp16, noavx512_fp16. opcodes/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (EXwScalarS): New. (EXxh): Ditto. (EXxhc): Ditto. (EXxmmqh): Ditto. (EXxmmqdh): Ditto. (EXEvexXwb): Ditto. (DistinctDest_Fixup): Ditto. (enum): Add xh_mode, evex_half_bcst_xmmqh_mode, evex_half_bcst_xmmqdh_mode and w_swap_mode. (enum): Add PREFIX_EVEX_0F3A08_W_0, PREFIX_EVEX_0F3A0A_W_0, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3AC2, PREFIX_EVEX_MAP5_10, PREFIX_EVEX_MAP5_11, PREFIX_EVEX_MAP5_1D, PREFIX_EVEX_MAP5_2A, PREFIX_EVEX_MAP5_2C, PREFIX_EVEX_MAP5_2D, PREFIX_EVEX_MAP5_2E, PREFIX_EVEX_MAP5_2F, PREFIX_EVEX_MAP5_51, PREFIX_EVEX_MAP5_58, PREFIX_EVEX_MAP5_59, PREFIX_EVEX_MAP5_5A_W_0, PREFIX_EVEX_MAP5_5A_W_1, PREFIX_EVEX_MAP5_5B_W_0, PREFIX_EVEX_MAP5_5B_W_1, PREFIX_EVEX_MAP5_5C, PREFIX_EVEX_MAP5_5D, PREFIX_EVEX_MAP5_5E, PREFIX_EVEX_MAP5_5F, PREFIX_EVEX_MAP5_78, PREFIX_EVEX_MAP5_79, PREFIX_EVEX_MAP5_7A, PREFIX_EVEX_MAP5_7B, PREFIX_EVEX_MAP5_7C, PREFIX_EVEX_MAP5_7D_W_0, PREFIX_EVEX_MAP6_13, PREFIX_EVEX_MAP6_56, PREFIX_EVEX_MAP6_57, PREFIX_EVEX_MAP6_D6, PREFIX_EVEX_MAP6_D7 (enum): Add EVEX_MAP5 and EVEX_MAP6. (enum): Add EVEX_W_MAP5_5A, EVEX_W_MAP5_5B, EVEX_W_MAP5_78_P_0, EVEX_W_MAP5_78_P_2, EVEX_W_MAP5_79_P_0, EVEX_W_MAP5_79_P_2, EVEX_W_MAP5_7A_P_2, EVEX_W_MAP5_7A_P_3, EVEX_W_MAP5_7B_P_2, EVEX_W_MAP5_7C_P_0, EVEX_W_MAP5_7C_P_2, EVEX_W_MAP5_7D, EVEX_W_MAP6_13_P_0, EVEX_W_MAP6_13_P_2, (get_valid_dis386): Properly handle new instructions. (intel_operand_size): Handle new modes. (OP_E_memory): Ditto. (OP_EX): Ditto. * i386-dis-evex.h: Updated for AVX512_FP16. * i386-dis-evex-mod.h: Updated for AVX512_FP16. * i386-dis-evex-prefix.h: Updated for AVX512_FP16. * i386-dis-evex-reg.h : Updated for AVX512_FP16. * i386-dis-evex-w.h : Updated for AVX512_FP16. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_FP16_FLAGS, and CPU_ANY_AVX512_FP16_FLAGS. Update CPU_ANY_AVX512F_FLAGS and CPU_ANY_AVX512BW_FLAGS. (cpu_flags): Add CpuAVX512_FP16. (opcode_modifiers): Add DistinctDest. * i386-opc.h (enum): (AVX512_FP16): New. (i386_opcode_modifier): Add reqdistinctreg. (i386_cpu_flags): Add cpuavx512_fp16. (EVEXMAP5): Defined as a macro. (EVEXMAP6): Ditto. * i386-opc.tbl: Add Intel AVX512_FP16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Ditto.
2021-06-14 11:05:05 +08:00
{ PREFIX_TABLE (PREFIX_EVEX_0F3A56) },
{ PREFIX_TABLE (PREFIX_EVEX_0F3A57) },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
/* 58 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 60 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
[PATCH 1/2] Enable Intel AVX512_FP16 instructions Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32 in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx). There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8 operands predated our current conventions; those instructions moved to map 3. FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3 is very sparsely populated. Most of the FP16 instructions share opcodes and prefix (EVEX.pp) bits with the related FP32 operations. Intel AVX512 FP16 instructions has new displacements scaling rules, please refer to the public software developer manual for detail information. gas/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (struct Broadcast_Operation): Adjust comment. (cpu_arch): Add .avx512_fp16. (cpu_noarch): Add noavx512_fp16. (pte): Add evexmap5 and evexmap6. (build_evex_prefix): Handle EVEXMAP5 and EVEXMAP6. (check_VecOperations): Handle {1to32}. (check_VecOperands): Handle CheckRegNumb. (check_word_reg): Handle Toqword. (i386_error): Add invalid_dest_and_src_register_set. (match_template): Handle invalid_dest_and_src_register_set. * doc/c-i386.texi: Document avx512_fp16, noavx512_fp16. opcodes/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (EXwScalarS): New. (EXxh): Ditto. (EXxhc): Ditto. (EXxmmqh): Ditto. (EXxmmqdh): Ditto. (EXEvexXwb): Ditto. (DistinctDest_Fixup): Ditto. (enum): Add xh_mode, evex_half_bcst_xmmqh_mode, evex_half_bcst_xmmqdh_mode and w_swap_mode. (enum): Add PREFIX_EVEX_0F3A08_W_0, PREFIX_EVEX_0F3A0A_W_0, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3AC2, PREFIX_EVEX_MAP5_10, PREFIX_EVEX_MAP5_11, PREFIX_EVEX_MAP5_1D, PREFIX_EVEX_MAP5_2A, PREFIX_EVEX_MAP5_2C, PREFIX_EVEX_MAP5_2D, PREFIX_EVEX_MAP5_2E, PREFIX_EVEX_MAP5_2F, PREFIX_EVEX_MAP5_51, PREFIX_EVEX_MAP5_58, PREFIX_EVEX_MAP5_59, PREFIX_EVEX_MAP5_5A_W_0, PREFIX_EVEX_MAP5_5A_W_1, PREFIX_EVEX_MAP5_5B_W_0, PREFIX_EVEX_MAP5_5B_W_1, PREFIX_EVEX_MAP5_5C, PREFIX_EVEX_MAP5_5D, PREFIX_EVEX_MAP5_5E, PREFIX_EVEX_MAP5_5F, PREFIX_EVEX_MAP5_78, PREFIX_EVEX_MAP5_79, PREFIX_EVEX_MAP5_7A, PREFIX_EVEX_MAP5_7B, PREFIX_EVEX_MAP5_7C, PREFIX_EVEX_MAP5_7D_W_0, PREFIX_EVEX_MAP6_13, PREFIX_EVEX_MAP6_56, PREFIX_EVEX_MAP6_57, PREFIX_EVEX_MAP6_D6, PREFIX_EVEX_MAP6_D7 (enum): Add EVEX_MAP5 and EVEX_MAP6. (enum): Add EVEX_W_MAP5_5A, EVEX_W_MAP5_5B, EVEX_W_MAP5_78_P_0, EVEX_W_MAP5_78_P_2, EVEX_W_MAP5_79_P_0, EVEX_W_MAP5_79_P_2, EVEX_W_MAP5_7A_P_2, EVEX_W_MAP5_7A_P_3, EVEX_W_MAP5_7B_P_2, EVEX_W_MAP5_7C_P_0, EVEX_W_MAP5_7C_P_2, EVEX_W_MAP5_7D, EVEX_W_MAP6_13_P_0, EVEX_W_MAP6_13_P_2, (get_valid_dis386): Properly handle new instructions. (intel_operand_size): Handle new modes. (OP_E_memory): Ditto. (OP_EX): Ditto. * i386-dis-evex.h: Updated for AVX512_FP16. * i386-dis-evex-mod.h: Updated for AVX512_FP16. * i386-dis-evex-prefix.h: Updated for AVX512_FP16. * i386-dis-evex-reg.h : Updated for AVX512_FP16. * i386-dis-evex-w.h : Updated for AVX512_FP16. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_FP16_FLAGS, and CPU_ANY_AVX512_FP16_FLAGS. Update CPU_ANY_AVX512F_FLAGS and CPU_ANY_AVX512BW_FLAGS. (cpu_flags): Add CpuAVX512_FP16. (opcode_modifiers): Add DistinctDest. * i386-opc.h (enum): (AVX512_FP16): New. (i386_opcode_modifier): Add reqdistinctreg. (i386_cpu_flags): Add cpuavx512_fp16. (EVEXMAP5): Defined as a macro. (EVEXMAP6): Ditto. * i386-opc.tbl: Add Intel AVX512_FP16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Ditto.
2021-06-14 11:05:05 +08:00
{ PREFIX_TABLE (PREFIX_EVEX_0F3A66) },
{ PREFIX_TABLE (PREFIX_EVEX_0F3A67) },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
/* 68 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 70 */
x86: simplify decode of opcodes valid with (embedded) 66 prefix only The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14 16:33:40 +08:00
{ VEX_W_TABLE (EVEX_W_0F3A70) },
{ "vpshld%DQ", { XM, Vex, EXx, Ib }, PREFIX_DATA },
{ VEX_W_TABLE (EVEX_W_0F3A72) },
{ "vpshrd%DQ", { XM, Vex, EXx, Ib }, PREFIX_DATA },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 78 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 80 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 88 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 90 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 98 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* A0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* A8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* B0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* B8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* C0 */
{ Bad_Opcode },
{ Bad_Opcode },
[PATCH 1/2] Enable Intel AVX512_FP16 instructions Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32 in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx). There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8 operands predated our current conventions; those instructions moved to map 3. FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3 is very sparsely populated. Most of the FP16 instructions share opcodes and prefix (EVEX.pp) bits with the related FP32 operations. Intel AVX512 FP16 instructions has new displacements scaling rules, please refer to the public software developer manual for detail information. gas/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (struct Broadcast_Operation): Adjust comment. (cpu_arch): Add .avx512_fp16. (cpu_noarch): Add noavx512_fp16. (pte): Add evexmap5 and evexmap6. (build_evex_prefix): Handle EVEXMAP5 and EVEXMAP6. (check_VecOperations): Handle {1to32}. (check_VecOperands): Handle CheckRegNumb. (check_word_reg): Handle Toqword. (i386_error): Add invalid_dest_and_src_register_set. (match_template): Handle invalid_dest_and_src_register_set. * doc/c-i386.texi: Document avx512_fp16, noavx512_fp16. opcodes/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (EXwScalarS): New. (EXxh): Ditto. (EXxhc): Ditto. (EXxmmqh): Ditto. (EXxmmqdh): Ditto. (EXEvexXwb): Ditto. (DistinctDest_Fixup): Ditto. (enum): Add xh_mode, evex_half_bcst_xmmqh_mode, evex_half_bcst_xmmqdh_mode and w_swap_mode. (enum): Add PREFIX_EVEX_0F3A08_W_0, PREFIX_EVEX_0F3A0A_W_0, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3AC2, PREFIX_EVEX_MAP5_10, PREFIX_EVEX_MAP5_11, PREFIX_EVEX_MAP5_1D, PREFIX_EVEX_MAP5_2A, PREFIX_EVEX_MAP5_2C, PREFIX_EVEX_MAP5_2D, PREFIX_EVEX_MAP5_2E, PREFIX_EVEX_MAP5_2F, PREFIX_EVEX_MAP5_51, PREFIX_EVEX_MAP5_58, PREFIX_EVEX_MAP5_59, PREFIX_EVEX_MAP5_5A_W_0, PREFIX_EVEX_MAP5_5A_W_1, PREFIX_EVEX_MAP5_5B_W_0, PREFIX_EVEX_MAP5_5B_W_1, PREFIX_EVEX_MAP5_5C, PREFIX_EVEX_MAP5_5D, PREFIX_EVEX_MAP5_5E, PREFIX_EVEX_MAP5_5F, PREFIX_EVEX_MAP5_78, PREFIX_EVEX_MAP5_79, PREFIX_EVEX_MAP5_7A, PREFIX_EVEX_MAP5_7B, PREFIX_EVEX_MAP5_7C, PREFIX_EVEX_MAP5_7D_W_0, PREFIX_EVEX_MAP6_13, PREFIX_EVEX_MAP6_56, PREFIX_EVEX_MAP6_57, PREFIX_EVEX_MAP6_D6, PREFIX_EVEX_MAP6_D7 (enum): Add EVEX_MAP5 and EVEX_MAP6. (enum): Add EVEX_W_MAP5_5A, EVEX_W_MAP5_5B, EVEX_W_MAP5_78_P_0, EVEX_W_MAP5_78_P_2, EVEX_W_MAP5_79_P_0, EVEX_W_MAP5_79_P_2, EVEX_W_MAP5_7A_P_2, EVEX_W_MAP5_7A_P_3, EVEX_W_MAP5_7B_P_2, EVEX_W_MAP5_7C_P_0, EVEX_W_MAP5_7C_P_2, EVEX_W_MAP5_7D, EVEX_W_MAP6_13_P_0, EVEX_W_MAP6_13_P_2, (get_valid_dis386): Properly handle new instructions. (intel_operand_size): Handle new modes. (OP_E_memory): Ditto. (OP_EX): Ditto. * i386-dis-evex.h: Updated for AVX512_FP16. * i386-dis-evex-mod.h: Updated for AVX512_FP16. * i386-dis-evex-prefix.h: Updated for AVX512_FP16. * i386-dis-evex-reg.h : Updated for AVX512_FP16. * i386-dis-evex-w.h : Updated for AVX512_FP16. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_FP16_FLAGS, and CPU_ANY_AVX512_FP16_FLAGS. Update CPU_ANY_AVX512F_FLAGS and CPU_ANY_AVX512BW_FLAGS. (cpu_flags): Add CpuAVX512_FP16. (opcode_modifiers): Add DistinctDest. * i386-opc.h (enum): (AVX512_FP16): New. (i386_opcode_modifier): Add reqdistinctreg. (i386_cpu_flags): Add cpuavx512_fp16. (EVEXMAP5): Defined as a macro. (EVEXMAP6): Ditto. * i386-opc.tbl: Add Intel AVX512_FP16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Ditto.
2021-06-14 11:05:05 +08:00
{ PREFIX_TABLE (PREFIX_EVEX_0F3AC2) },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* C8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
x86: simplify decode of opcodes valid with (embedded) 66 prefix only The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14 16:33:40 +08:00
{ VEX_W_TABLE (VEX_W_0F3ACE) },
{ VEX_W_TABLE (VEX_W_0F3ACF) },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
/* D0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* D8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* E0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* E8 */
{ Bad_Opcode },
Created an empty EVEX_MAP4_ sub-table for EVEX instructions. opcode/ChangeLog: * i386-dis-evex.hi: Added an empty EVEX_MAP4_ sub-table for legacy insn promote to EVEX insn. * opcodes/i386-dis-evex.h: Add EVEX_MAP4.
2023-12-28 09:06:40 +08:00
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* F0 */
x86/APX: no need to have decode go through x86_64_table[] As suggested during review already, all such entries have their first slot as Bad_Opcode, so by adding two more enumerators we can avoid doing that decode step altogether.
2024-01-26 17:34:24 +08:00
{ X86_64_EVEX_PFX_TABLE (PREFIX_VEX_0F3AF0_L_0) },
Created an empty EVEX_MAP4_ sub-table for EVEX instructions. opcode/ChangeLog: * i386-dis-evex.hi: Added an empty EVEX_MAP4_ sub-table for legacy insn promote to EVEX insn. * opcodes/i386-dis-evex.h: Add EVEX_MAP4.
2023-12-28 09:06:40 +08:00
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* F8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
},
/* EVEX_MAP4_ */
{
/* 00 */
Support APX NF For the case when NDD and NF are both 0 in evex-promoted format, we will fully support and test it in another patch. gas/ChangeLog: * NEWS: Support Intel APX NF. * config/tc-i386.c (enum i386_error): Add unsupported_nf. (struct _i386_insn): Add has_nf. (is_apx_evex_encoding): Ditto. (build_apx_evex_prefix): Encode the NF bit. (md_assemble): Handle unsupported_nf. (parse_insn): Handle Prefix_NF and report bad for illegal combination. (can_convert_NDD_to_legacy): Replace i.tm.opcode_modifier.nf with i.has_nf. (match_template): Support D for APX_F insns and check NF support. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Add bad test for NF bit. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. * testsuite/gas/i386/x86-64-apx-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-inval.s: Ditto. * testsuite/gas/i386/x86-64.exp: Add apx nf tests. * testsuite/gas/i386/x86-64-apx-nf-intel.d: New test. * testsuite/gas/i386/x86-64-apx-nf.d: Ditto. * testsuite/gas/i386/x86-64-apx-nf.s: Ditto. opcodes/ChangeLog: * i386-dis-evex.h: Add %NF to the instructions that support APX NF and add new instruction imul, popcnt, tzcnt and lzcnt to EVEX table. * i386-dis-evex-reg.h: Ditto. * i386-dis.c (struct instr_info): Add nf. (struct dis386): Add "NF" for EVEX.NF. (get_valid_dis386): Set ins->vex.nf and report bad-nf for illegal case. (print_insn): Handle ins.vex.nf. (putop): Handle "%NF". * i386-opc.h (Prefix_NF): New. * i386-opc.tbl: Added new entries to support full APX NF instructions. * i386-mnem.h: Regenerated. * i386-tbl.h: Regenerated.
2024-04-07 17:28:25 +08:00
{ "%NFaddB", { VexGb, Eb, Gb }, NO_PREFIX },
{ "%NFaddS", { VexGv, Ev, Gv }, PREFIX_NP_OR_DATA },
{ "%NFaddB", { VexGb, Gb, EbS }, NO_PREFIX },
{ "%NFaddS", { VexGv, Gv, EvS }, PREFIX_NP_OR_DATA },
Created an empty EVEX_MAP4_ sub-table for EVEX instructions. opcode/ChangeLog: * i386-dis-evex.hi: Added an empty EVEX_MAP4_ sub-table for legacy insn promote to EVEX insn. * opcodes/i386-dis-evex.h: Add EVEX_MAP4.
2023-12-28 09:06:40 +08:00
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 08 */
Support APX NF For the case when NDD and NF are both 0 in evex-promoted format, we will fully support and test it in another patch. gas/ChangeLog: * NEWS: Support Intel APX NF. * config/tc-i386.c (enum i386_error): Add unsupported_nf. (struct _i386_insn): Add has_nf. (is_apx_evex_encoding): Ditto. (build_apx_evex_prefix): Encode the NF bit. (md_assemble): Handle unsupported_nf. (parse_insn): Handle Prefix_NF and report bad for illegal combination. (can_convert_NDD_to_legacy): Replace i.tm.opcode_modifier.nf with i.has_nf. (match_template): Support D for APX_F insns and check NF support. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Add bad test for NF bit. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. * testsuite/gas/i386/x86-64-apx-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-inval.s: Ditto. * testsuite/gas/i386/x86-64.exp: Add apx nf tests. * testsuite/gas/i386/x86-64-apx-nf-intel.d: New test. * testsuite/gas/i386/x86-64-apx-nf.d: Ditto. * testsuite/gas/i386/x86-64-apx-nf.s: Ditto. opcodes/ChangeLog: * i386-dis-evex.h: Add %NF to the instructions that support APX NF and add new instruction imul, popcnt, tzcnt and lzcnt to EVEX table. * i386-dis-evex-reg.h: Ditto. * i386-dis.c (struct instr_info): Add nf. (struct dis386): Add "NF" for EVEX.NF. (get_valid_dis386): Set ins->vex.nf and report bad-nf for illegal case. (print_insn): Handle ins.vex.nf. (putop): Handle "%NF". * i386-opc.h (Prefix_NF): New. * i386-opc.tbl: Added new entries to support full APX NF instructions. * i386-mnem.h: Regenerated. * i386-tbl.h: Regenerated.
2024-04-07 17:28:25 +08:00
{ "%NForB", { VexGb, Eb, Gb }, NO_PREFIX },
{ "%NForS", { VexGv, Ev, Gv }, PREFIX_NP_OR_DATA },
{ "%NForB", { VexGb, Gb, EbS }, NO_PREFIX },
{ "%NForS", { VexGv, Gv, EvS }, PREFIX_NP_OR_DATA },
Created an empty EVEX_MAP4_ sub-table for EVEX instructions. opcode/ChangeLog: * i386-dis-evex.hi: Added an empty EVEX_MAP4_ sub-table for legacy insn promote to EVEX insn. * opcodes/i386-dis-evex.h: Add EVEX_MAP4.
2023-12-28 09:06:40 +08:00
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 10 */
Support APX NF For the case when NDD and NF are both 0 in evex-promoted format, we will fully support and test it in another patch. gas/ChangeLog: * NEWS: Support Intel APX NF. * config/tc-i386.c (enum i386_error): Add unsupported_nf. (struct _i386_insn): Add has_nf. (is_apx_evex_encoding): Ditto. (build_apx_evex_prefix): Encode the NF bit. (md_assemble): Handle unsupported_nf. (parse_insn): Handle Prefix_NF and report bad for illegal combination. (can_convert_NDD_to_legacy): Replace i.tm.opcode_modifier.nf with i.has_nf. (match_template): Support D for APX_F insns and check NF support. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Add bad test for NF bit. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. * testsuite/gas/i386/x86-64-apx-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-inval.s: Ditto. * testsuite/gas/i386/x86-64.exp: Add apx nf tests. * testsuite/gas/i386/x86-64-apx-nf-intel.d: New test. * testsuite/gas/i386/x86-64-apx-nf.d: Ditto. * testsuite/gas/i386/x86-64-apx-nf.s: Ditto. opcodes/ChangeLog: * i386-dis-evex.h: Add %NF to the instructions that support APX NF and add new instruction imul, popcnt, tzcnt and lzcnt to EVEX table. * i386-dis-evex-reg.h: Ditto. * i386-dis.c (struct instr_info): Add nf. (struct dis386): Add "NF" for EVEX.NF. (get_valid_dis386): Set ins->vex.nf and report bad-nf for illegal case. (print_insn): Handle ins.vex.nf. (putop): Handle "%NF". * i386-opc.h (Prefix_NF): New. * i386-opc.tbl: Added new entries to support full APX NF instructions. * i386-mnem.h: Regenerated. * i386-tbl.h: Regenerated.
2024-04-07 17:28:25 +08:00
{ "adcB", { VexGb, Eb, Gb }, NO_PREFIX },
{ "adcS", { VexGv, Ev, Gv }, PREFIX_NP_OR_DATA },
{ "adcB", { VexGb, Gb, EbS }, NO_PREFIX },
{ "adcS", { VexGv, Gv, EvS }, PREFIX_NP_OR_DATA },
Created an empty EVEX_MAP4_ sub-table for EVEX instructions. opcode/ChangeLog: * i386-dis-evex.hi: Added an empty EVEX_MAP4_ sub-table for legacy insn promote to EVEX insn. * opcodes/i386-dis-evex.h: Add EVEX_MAP4.
2023-12-28 09:06:40 +08:00
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 18 */
Support APX NF For the case when NDD and NF are both 0 in evex-promoted format, we will fully support and test it in another patch. gas/ChangeLog: * NEWS: Support Intel APX NF. * config/tc-i386.c (enum i386_error): Add unsupported_nf. (struct _i386_insn): Add has_nf. (is_apx_evex_encoding): Ditto. (build_apx_evex_prefix): Encode the NF bit. (md_assemble): Handle unsupported_nf. (parse_insn): Handle Prefix_NF and report bad for illegal combination. (can_convert_NDD_to_legacy): Replace i.tm.opcode_modifier.nf with i.has_nf. (match_template): Support D for APX_F insns and check NF support. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Add bad test for NF bit. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. * testsuite/gas/i386/x86-64-apx-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-inval.s: Ditto. * testsuite/gas/i386/x86-64.exp: Add apx nf tests. * testsuite/gas/i386/x86-64-apx-nf-intel.d: New test. * testsuite/gas/i386/x86-64-apx-nf.d: Ditto. * testsuite/gas/i386/x86-64-apx-nf.s: Ditto. opcodes/ChangeLog: * i386-dis-evex.h: Add %NF to the instructions that support APX NF and add new instruction imul, popcnt, tzcnt and lzcnt to EVEX table. * i386-dis-evex-reg.h: Ditto. * i386-dis.c (struct instr_info): Add nf. (struct dis386): Add "NF" for EVEX.NF. (get_valid_dis386): Set ins->vex.nf and report bad-nf for illegal case. (print_insn): Handle ins.vex.nf. (putop): Handle "%NF". * i386-opc.h (Prefix_NF): New. * i386-opc.tbl: Added new entries to support full APX NF instructions. * i386-mnem.h: Regenerated. * i386-tbl.h: Regenerated.
2024-04-07 17:28:25 +08:00
{ "sbbB", { VexGb, Eb, Gb }, NO_PREFIX },
{ "sbbS", { VexGv, Ev, Gv }, PREFIX_NP_OR_DATA },
{ "sbbB", { VexGb, Gb, EbS }, NO_PREFIX },
{ "sbbS", { VexGv, Gv, EvS }, PREFIX_NP_OR_DATA },
Created an empty EVEX_MAP4_ sub-table for EVEX instructions. opcode/ChangeLog: * i386-dis-evex.hi: Added an empty EVEX_MAP4_ sub-table for legacy insn promote to EVEX insn. * opcodes/i386-dis-evex.h: Add EVEX_MAP4.
2023-12-28 09:06:40 +08:00
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 20 */
Support APX NF For the case when NDD and NF are both 0 in evex-promoted format, we will fully support and test it in another patch. gas/ChangeLog: * NEWS: Support Intel APX NF. * config/tc-i386.c (enum i386_error): Add unsupported_nf. (struct _i386_insn): Add has_nf. (is_apx_evex_encoding): Ditto. (build_apx_evex_prefix): Encode the NF bit. (md_assemble): Handle unsupported_nf. (parse_insn): Handle Prefix_NF and report bad for illegal combination. (can_convert_NDD_to_legacy): Replace i.tm.opcode_modifier.nf with i.has_nf. (match_template): Support D for APX_F insns and check NF support. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Add bad test for NF bit. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. * testsuite/gas/i386/x86-64-apx-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-inval.s: Ditto. * testsuite/gas/i386/x86-64.exp: Add apx nf tests. * testsuite/gas/i386/x86-64-apx-nf-intel.d: New test. * testsuite/gas/i386/x86-64-apx-nf.d: Ditto. * testsuite/gas/i386/x86-64-apx-nf.s: Ditto. opcodes/ChangeLog: * i386-dis-evex.h: Add %NF to the instructions that support APX NF and add new instruction imul, popcnt, tzcnt and lzcnt to EVEX table. * i386-dis-evex-reg.h: Ditto. * i386-dis.c (struct instr_info): Add nf. (struct dis386): Add "NF" for EVEX.NF. (get_valid_dis386): Set ins->vex.nf and report bad-nf for illegal case. (print_insn): Handle ins.vex.nf. (putop): Handle "%NF". * i386-opc.h (Prefix_NF): New. * i386-opc.tbl: Added new entries to support full APX NF instructions. * i386-mnem.h: Regenerated. * i386-tbl.h: Regenerated.
2024-04-07 17:28:25 +08:00
{ "%NFandB", { VexGb, Eb, Gb }, NO_PREFIX },
{ "%NFandS", { VexGv, Ev, Gv }, PREFIX_NP_OR_DATA },
{ "%NFandB", { VexGb, Gb, EbS }, NO_PREFIX },
{ "%NFandS", { VexGv, Gv, EvS }, PREFIX_NP_OR_DATA },
{ "%NFshldS", { VexGv, Ev, Gv, Ib }, PREFIX_NP_OR_DATA },
Created an empty EVEX_MAP4_ sub-table for EVEX instructions. opcode/ChangeLog: * i386-dis-evex.hi: Added an empty EVEX_MAP4_ sub-table for legacy insn promote to EVEX insn. * opcodes/i386-dis-evex.h: Add EVEX_MAP4.
2023-12-28 09:06:40 +08:00
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 28 */
Support APX NF For the case when NDD and NF are both 0 in evex-promoted format, we will fully support and test it in another patch. gas/ChangeLog: * NEWS: Support Intel APX NF. * config/tc-i386.c (enum i386_error): Add unsupported_nf. (struct _i386_insn): Add has_nf. (is_apx_evex_encoding): Ditto. (build_apx_evex_prefix): Encode the NF bit. (md_assemble): Handle unsupported_nf. (parse_insn): Handle Prefix_NF and report bad for illegal combination. (can_convert_NDD_to_legacy): Replace i.tm.opcode_modifier.nf with i.has_nf. (match_template): Support D for APX_F insns and check NF support. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Add bad test for NF bit. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. * testsuite/gas/i386/x86-64-apx-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-inval.s: Ditto. * testsuite/gas/i386/x86-64.exp: Add apx nf tests. * testsuite/gas/i386/x86-64-apx-nf-intel.d: New test. * testsuite/gas/i386/x86-64-apx-nf.d: Ditto. * testsuite/gas/i386/x86-64-apx-nf.s: Ditto. opcodes/ChangeLog: * i386-dis-evex.h: Add %NF to the instructions that support APX NF and add new instruction imul, popcnt, tzcnt and lzcnt to EVEX table. * i386-dis-evex-reg.h: Ditto. * i386-dis.c (struct instr_info): Add nf. (struct dis386): Add "NF" for EVEX.NF. (get_valid_dis386): Set ins->vex.nf and report bad-nf for illegal case. (print_insn): Handle ins.vex.nf. (putop): Handle "%NF". * i386-opc.h (Prefix_NF): New. * i386-opc.tbl: Added new entries to support full APX NF instructions. * i386-mnem.h: Regenerated. * i386-tbl.h: Regenerated.
2024-04-07 17:28:25 +08:00
{ "%NFsubB", { VexGb, Eb, Gb }, NO_PREFIX },
{ "%NFsubS", { VexGv, Ev, Gv }, PREFIX_NP_OR_DATA },
{ "%NFsubB", { VexGb, Gb, EbS }, NO_PREFIX },
{ "%NFsubS", { VexGv, Gv, EvS }, PREFIX_NP_OR_DATA },
{ "%NFshrdS", { VexGv, Ev, Gv, Ib }, PREFIX_NP_OR_DATA },
Created an empty EVEX_MAP4_ sub-table for EVEX instructions. opcode/ChangeLog: * i386-dis-evex.hi: Added an empty EVEX_MAP4_ sub-table for legacy insn promote to EVEX insn. * opcodes/i386-dis-evex.h: Add EVEX_MAP4.
2023-12-28 09:06:40 +08:00
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 30 */
Support APX NF For the case when NDD and NF are both 0 in evex-promoted format, we will fully support and test it in another patch. gas/ChangeLog: * NEWS: Support Intel APX NF. * config/tc-i386.c (enum i386_error): Add unsupported_nf. (struct _i386_insn): Add has_nf. (is_apx_evex_encoding): Ditto. (build_apx_evex_prefix): Encode the NF bit. (md_assemble): Handle unsupported_nf. (parse_insn): Handle Prefix_NF and report bad for illegal combination. (can_convert_NDD_to_legacy): Replace i.tm.opcode_modifier.nf with i.has_nf. (match_template): Support D for APX_F insns and check NF support. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Add bad test for NF bit. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. * testsuite/gas/i386/x86-64-apx-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-inval.s: Ditto. * testsuite/gas/i386/x86-64.exp: Add apx nf tests. * testsuite/gas/i386/x86-64-apx-nf-intel.d: New test. * testsuite/gas/i386/x86-64-apx-nf.d: Ditto. * testsuite/gas/i386/x86-64-apx-nf.s: Ditto. opcodes/ChangeLog: * i386-dis-evex.h: Add %NF to the instructions that support APX NF and add new instruction imul, popcnt, tzcnt and lzcnt to EVEX table. * i386-dis-evex-reg.h: Ditto. * i386-dis.c (struct instr_info): Add nf. (struct dis386): Add "NF" for EVEX.NF. (get_valid_dis386): Set ins->vex.nf and report bad-nf for illegal case. (print_insn): Handle ins.vex.nf. (putop): Handle "%NF". * i386-opc.h (Prefix_NF): New. * i386-opc.tbl: Added new entries to support full APX NF instructions. * i386-mnem.h: Regenerated. * i386-tbl.h: Regenerated.
2024-04-07 17:28:25 +08:00
{ "%NFxorB", { VexGb, Eb, Gb }, NO_PREFIX },
{ "%NFxorS", { VexGv, Ev, Gv }, PREFIX_NP_OR_DATA },
{ "%NFxorB", { VexGb, Gb, EbS }, NO_PREFIX },
{ "%NFxorS", { VexGv, Gv, EvS }, PREFIX_NP_OR_DATA },
Created an empty EVEX_MAP4_ sub-table for EVEX instructions. opcode/ChangeLog: * i386-dis-evex.hi: Added an empty EVEX_MAP4_ sub-table for legacy insn promote to EVEX insn. * opcodes/i386-dis-evex.h: Add EVEX_MAP4.
2023-12-28 09:06:40 +08:00
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 38 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 40 */
Support APX zero-upper This patch is to enable ZU for IMUL (opcodes 0x69 and 0x6B) and SETcc. Since the spec only recommends one form of setzu, I won't be adding set<cc>reg32/reg64 support in this patch. gas/ChangeLog: * config/tc-i386.c (build_apx_evex_prefix): Handle ZU. * testsuite/gas/i386/x86-64.exp: Added new tests for ZU. * testsuite/gas/i386/x86-64.exp: Added new tests for ZU. * testsuite/gas/i386/x86-64-apx-zu-intel.d: New test. * testsuite/gas/i386/x86-64-apx-zu-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-zu-inval.s: Ditto. * testsuite/gas/i386/x86-64-apx-zu.d: Ditto. * testsuite/gas/i386/x86-64-apx-zu.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-prefix.h: Handle PREFIX_EVEX_MAP4_40 ~ PREFIX_EVEX_MAP4_4F. * i386-dis-evex.h: Ditto. * i386-dis.c (struct dis386): Add new micro 'ZU'. (putop): Handle %ZU. * i386-gen.c: Added ZU. * i386-opc.h: Ditto. * i386-opc.tbl: Added new templates to support ZU.
2024-05-22 16:15:47 +08:00
{ PREFIX_TABLE (PREFIX_EVEX_MAP4_40) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP4_41) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP4_42) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP4_43) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP4_44) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP4_45) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP4_46) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP4_47) },
Created an empty EVEX_MAP4_ sub-table for EVEX instructions. opcode/ChangeLog: * i386-dis-evex.hi: Added an empty EVEX_MAP4_ sub-table for legacy insn promote to EVEX insn. * opcodes/i386-dis-evex.h: Add EVEX_MAP4.
2023-12-28 09:06:40 +08:00
/* 48 */
Support APX zero-upper This patch is to enable ZU for IMUL (opcodes 0x69 and 0x6B) and SETcc. Since the spec only recommends one form of setzu, I won't be adding set<cc>reg32/reg64 support in this patch. gas/ChangeLog: * config/tc-i386.c (build_apx_evex_prefix): Handle ZU. * testsuite/gas/i386/x86-64.exp: Added new tests for ZU. * testsuite/gas/i386/x86-64.exp: Added new tests for ZU. * testsuite/gas/i386/x86-64-apx-zu-intel.d: New test. * testsuite/gas/i386/x86-64-apx-zu-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-zu-inval.s: Ditto. * testsuite/gas/i386/x86-64-apx-zu.d: Ditto. * testsuite/gas/i386/x86-64-apx-zu.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-prefix.h: Handle PREFIX_EVEX_MAP4_40 ~ PREFIX_EVEX_MAP4_4F. * i386-dis-evex.h: Ditto. * i386-dis.c (struct dis386): Add new micro 'ZU'. (putop): Handle %ZU. * i386-gen.c: Added ZU. * i386-opc.h: Ditto. * i386-opc.tbl: Added new templates to support ZU.
2024-05-22 16:15:47 +08:00
{ PREFIX_TABLE (PREFIX_EVEX_MAP4_48) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP4_49) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP4_4A) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP4_4B) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP4_4C) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP4_4D) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP4_4E) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP4_4F) },
Created an empty EVEX_MAP4_ sub-table for EVEX instructions. opcode/ChangeLog: * i386-dis-evex.hi: Added an empty EVEX_MAP4_ sub-table for legacy insn promote to EVEX insn. * opcodes/i386-dis-evex.h: Add EVEX_MAP4.
2023-12-28 09:06:40 +08:00
/* 50 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 58 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 60 */
Support {evex} pseudo prefix for decode evex promoted insns without egpr32. This patch is based on APX NF patch and also adds test cases for Checking 64-bit insns not sizeable through register operands with evex. gas/ChangeLog: * testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d: Added no-egpr testcases for movbe. * testsuite/gas/i386/x86-64-apx-evex-promoted-wig.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted.s: Ditto. * testsuite/gas/i386/x86-64.exp: Added tests. * testsuite/gas/i386/noreg64-evex.d: New test. * testsuite/gas/i386/noreg64-evex.e: Ditto. * testsuite/gas/i386/noreg64-evex.s: Ditto. * testsuite/gas/i386/x86-64-apx_f-evex.d: Ditto. * testsuite/gas/i386/x86-64-apx_f-evex.s: Ditto. opcodes/ChangeLog: * i386-dis-evex.h: Added %ME to movbe. * i386-dis.c : Added %XE to evex_from_vex instructions to output {evex}. (struct dis386): New %ME. (putop): Handle %ME and output {evex} for evex_from_legacy instructions. * Return early when the instruction name is (bad).
2024-04-09 10:58:39 +08:00
{ "%MEmovbeS", { Gv, Ev }, PREFIX_NP_OR_DATA },
{ "%MEmovbeS", { Ev, Gv }, PREFIX_NP_OR_DATA },
Created an empty EVEX_MAP4_ sub-table for EVEX instructions. opcode/ChangeLog: * i386-dis-evex.hi: Added an empty EVEX_MAP4_ sub-table for legacy insn promote to EVEX insn. * opcodes/i386-dis-evex.h: Add EVEX_MAP4.
2023-12-28 09:06:40 +08:00
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
Support APX GPR32 with extend evex prefix This patch adds non-ND, non-NF forms of EVEX promotion insn. EVEX extension of legacy instructions: All promoted legacy instructions are placed in EVEX map 4, which is currently reserved. EVEX extension of EVEX instructions: All existing EVEX instructions are extended by APX using the extended EVEX prefix, so that they can access all 32 GPRs. EVEX extension of VEX instructions: Promoting a VEX instruction into the EVEX space does not change the map id, the opcode, or the operand encoding of the VEX instruction. Note: The promoted versions of MOVBE will be extended to include the “MOVBE reg1, reg2”. gas/ChangeLog: 2023-12-28 Lingling Kong <lingling.kong@intel.com> H.J. Lu <hongjiu.lu@intel.com> Lili Cui <lili.cui@intel.com> Lin Hu <lin1.hu@intel.com> * config/tc-i386.c (struct _i386_insn): Add has_egpr. (need_evex_encoding): Adjusted for apx. (cpu_flags_match): Ditto. (install_template): Handled APX combines. (is_apx_evex_encoding): Test apx evex encoding. (build_apx_evex_prefix): Enabe APX evex prefix. (md_assemble): Handle apx with evex encoding. (process_suffix): Handle apx map4 prefix. (check_register): Assign i.vec_encoding for APX evex instructions. * testsuite/gas/i386/x86-64-evex.d: Adjust test cases. * testsuite/gas/i386/x86-64.exp: Adjust x86-64-inval-movbe. opcodes/ChangeLog: * i386-dis-evex-len.h: Handle EVEX_LEN_0F38F2, EVEX_LEN_0F38F3. * i386-dis-evex-prefix.h: Handle PREFIX_EVEX_0F38F2_L_0, PREFIX_EVEX_0F38F3_L_0, PREFIX_EVEX_MAP4_D8, PREFIX_EVEX_MAP4_DA, PREFIX_EVEX_MAP4_DB, PREFIX_EVEX_MAP4_DC, PREFIX_EVEX_MAP4_DD, PREFIX_EVEX_MAP4_DE, PREFIX_EVEX_MAP4_DF, PREFIX_EVEX_MAP4_F0, PREFIX_EVEX_MAP4_F1, PREFIX_EVEX_MAP4_F2, PREFIX_EVEX_MAP4_F8. * i386-dis-evex-reg.h: Handle REG_EVEX_0F38F3_L_0_P_0. * i386-dis-evex.h: Add EVEX_MAP4_ for legacy insn promote to apx to use gpr32 * opcodes/i386-dis-evex-x86-64.h: Handle Add X86_64_EVEX_0F90, X86_64_EVEX_0F92, X86_64_EVEX_0F93, X86_64_EVEX_0F38F2, X86_64_EVEX_0F38F3, X86_64_EVEX_0F38F5, X86_64_EVEX_0F38F6, X86_64_EVEX_0F38F7, X86_64_EVEX_0F3AF0, X86_64_EVEX_0F91. * i386-dis.c (struct instr_info): Deleted bool r. (PREFIX_NP_OR_DATA): New. (NO_PREFIX): New. (putop): Ditto. (X86_64_EVEX_FROM_VEX_TABLE): Diito. (get_valid_dis386): Decode insn erex in extend evex prefix. Handle EVEX_MAP4 (print_insn): Handle PREFIX_DATA_AND_NP_ONLY. (print_register): Handle apx instructions decode. (OP_E_memory): Diito. (OP_G): Diito. (OP_XMM): Diito. (DistinctDest_Fixup): Diito. * i386-gen.c (process_i386_opcode_modifier): Add EVEXMAP4. * i386-opc.h (SPACE_EVEXMAP4): Add legacy insn promote to evex. * i386-opc.tbl: Handle some legacy and vex insns don't support gpr32. And add some legacy insn (map2 / 3) promote to evex.
2023-12-28 09:06:40 +08:00
{ "wrussK", { M, Gdq }, PREFIX_DATA },
{ PREFIX_TABLE (PREFIX_0F38F6) },
Created an empty EVEX_MAP4_ sub-table for EVEX instructions. opcode/ChangeLog: * i386-dis-evex.hi: Added an empty EVEX_MAP4_ sub-table for legacy insn promote to EVEX insn. * opcodes/i386-dis-evex.h: Add EVEX_MAP4.
2023-12-28 09:06:40 +08:00
{ Bad_Opcode },
/* 68 */
{ Bad_Opcode },
Support APX zero-upper This patch is to enable ZU for IMUL (opcodes 0x69 and 0x6B) and SETcc. Since the spec only recommends one form of setzu, I won't be adding set<cc>reg32/reg64 support in this patch. gas/ChangeLog: * config/tc-i386.c (build_apx_evex_prefix): Handle ZU. * testsuite/gas/i386/x86-64.exp: Added new tests for ZU. * testsuite/gas/i386/x86-64.exp: Added new tests for ZU. * testsuite/gas/i386/x86-64-apx-zu-intel.d: New test. * testsuite/gas/i386/x86-64-apx-zu-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-zu-inval.s: Ditto. * testsuite/gas/i386/x86-64-apx-zu.d: Ditto. * testsuite/gas/i386/x86-64-apx-zu.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-prefix.h: Handle PREFIX_EVEX_MAP4_40 ~ PREFIX_EVEX_MAP4_4F. * i386-dis-evex.h: Ditto. * i386-dis.c (struct dis386): Add new micro 'ZU'. (putop): Handle %ZU. * i386-gen.c: Added ZU. * i386-opc.h: Ditto. * i386-opc.tbl: Added new templates to support ZU.
2024-05-22 16:15:47 +08:00
{ "%NFimul%ZUS", { Gv, Ev, Iv }, PREFIX_NP_OR_DATA },
Created an empty EVEX_MAP4_ sub-table for EVEX instructions. opcode/ChangeLog: * i386-dis-evex.hi: Added an empty EVEX_MAP4_ sub-table for legacy insn promote to EVEX insn. * opcodes/i386-dis-evex.h: Add EVEX_MAP4.
2023-12-28 09:06:40 +08:00
{ Bad_Opcode },
Support APX zero-upper This patch is to enable ZU for IMUL (opcodes 0x69 and 0x6B) and SETcc. Since the spec only recommends one form of setzu, I won't be adding set<cc>reg32/reg64 support in this patch. gas/ChangeLog: * config/tc-i386.c (build_apx_evex_prefix): Handle ZU. * testsuite/gas/i386/x86-64.exp: Added new tests for ZU. * testsuite/gas/i386/x86-64.exp: Added new tests for ZU. * testsuite/gas/i386/x86-64-apx-zu-intel.d: New test. * testsuite/gas/i386/x86-64-apx-zu-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-zu-inval.s: Ditto. * testsuite/gas/i386/x86-64-apx-zu.d: Ditto. * testsuite/gas/i386/x86-64-apx-zu.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-prefix.h: Handle PREFIX_EVEX_MAP4_40 ~ PREFIX_EVEX_MAP4_4F. * i386-dis-evex.h: Ditto. * i386-dis.c (struct dis386): Add new micro 'ZU'. (putop): Handle %ZU. * i386-gen.c: Added ZU. * i386-opc.h: Ditto. * i386-opc.tbl: Added new templates to support ZU.
2024-05-22 16:15:47 +08:00
{ "%NFimul%ZUS", { Gv, Ev, sIb }, PREFIX_NP_OR_DATA },
Created an empty EVEX_MAP4_ sub-table for EVEX instructions. opcode/ChangeLog: * i386-dis-evex.hi: Added an empty EVEX_MAP4_ sub-table for legacy insn promote to EVEX insn. * opcodes/i386-dis-evex.h: Add EVEX_MAP4.
2023-12-28 09:06:40 +08:00
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 70 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 78 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 80 */
Support APX NDD opcodes/ChangeLog: * opcodes/i386-dis-evex-reg.h: Handle for REG_EVEX_MAP4_80, REG_EVEX_MAP4_81, REG_EVEX_MAP4_83, REG_EVEX_MAP4_F6, REG_EVEX_MAP4_F7, REG_EVEX_MAP4_FE, REG_EVEX_MAP4_FF. * opcodes/i386-dis-evex.h: Add NDD insn. * opcodes/i386-dis.c (nd): New define. (VexGb): Ditto. (VexGv): Ditto. (get_valid_dis386): Change for NDD decode. (print_insn): Ditto. (putop): Ditto. (intel_operand_size): Ditto. (OP_E_memory): Ditto. (OP_VEX): Ditto. * opcodes/i386-opc.h (VexVVVV_DST): New. * opcodes/i386-opc.tbl: Add APX NDD instructions and adjust VexVVVV. * opcodes/i386-tbl.h: Regenerated. gas/ChangeLog: * gas/config/tc-i386.c (operand_size_match): Support APX NDD that the number of operands is 3. (build_apx_evex_prefix): Change for ndd encode. (process_operands): Ditto. (build_modrm_byte): Ditto. (match_template): Support swap the first two operands for APX NDD. * testsuite/gas/i386/x86-64.exp: Add x86-64-apx-ndd. * testsuite/gas/i386/x86-64-apx-ndd.d: New test. * testsuite/gas/i386/x86-64-apx-ndd.s: Ditto. * testsuite/gas/i386/x86-64-pseudos.d: Add test. * testsuite/gas/i386/x86-64-pseudos.s: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d : Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s : Ditto.
2023-12-28 09:06:40 +08:00
{ REG_TABLE (REG_EVEX_MAP4_80) },
{ REG_TABLE (REG_EVEX_MAP4_81) },
Created an empty EVEX_MAP4_ sub-table for EVEX instructions. opcode/ChangeLog: * i386-dis-evex.hi: Added an empty EVEX_MAP4_ sub-table for legacy insn promote to EVEX insn. * opcodes/i386-dis-evex.h: Add EVEX_MAP4.
2023-12-28 09:06:40 +08:00
{ Bad_Opcode },
Support APX NDD opcodes/ChangeLog: * opcodes/i386-dis-evex-reg.h: Handle for REG_EVEX_MAP4_80, REG_EVEX_MAP4_81, REG_EVEX_MAP4_83, REG_EVEX_MAP4_F6, REG_EVEX_MAP4_F7, REG_EVEX_MAP4_FE, REG_EVEX_MAP4_FF. * opcodes/i386-dis-evex.h: Add NDD insn. * opcodes/i386-dis.c (nd): New define. (VexGb): Ditto. (VexGv): Ditto. (get_valid_dis386): Change for NDD decode. (print_insn): Ditto. (putop): Ditto. (intel_operand_size): Ditto. (OP_E_memory): Ditto. (OP_VEX): Ditto. * opcodes/i386-opc.h (VexVVVV_DST): New. * opcodes/i386-opc.tbl: Add APX NDD instructions and adjust VexVVVV. * opcodes/i386-tbl.h: Regenerated. gas/ChangeLog: * gas/config/tc-i386.c (operand_size_match): Support APX NDD that the number of operands is 3. (build_apx_evex_prefix): Change for ndd encode. (process_operands): Ditto. (build_modrm_byte): Ditto. (match_template): Support swap the first two operands for APX NDD. * testsuite/gas/i386/x86-64.exp: Add x86-64-apx-ndd. * testsuite/gas/i386/x86-64-apx-ndd.d: New test. * testsuite/gas/i386/x86-64-apx-ndd.s: Ditto. * testsuite/gas/i386/x86-64-pseudos.d: Add test. * testsuite/gas/i386/x86-64-pseudos.s: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d : Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s : Ditto.
2023-12-28 09:06:40 +08:00
{ REG_TABLE (REG_EVEX_MAP4_83) },
Created an empty EVEX_MAP4_ sub-table for EVEX instructions. opcode/ChangeLog: * i386-dis-evex.hi: Added an empty EVEX_MAP4_ sub-table for legacy insn promote to EVEX insn. * opcodes/i386-dis-evex.h: Add EVEX_MAP4.
2023-12-28 09:06:40 +08:00
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 88 */
Support APX NF For the case when NDD and NF are both 0 in evex-promoted format, we will fully support and test it in another patch. gas/ChangeLog: * NEWS: Support Intel APX NF. * config/tc-i386.c (enum i386_error): Add unsupported_nf. (struct _i386_insn): Add has_nf. (is_apx_evex_encoding): Ditto. (build_apx_evex_prefix): Encode the NF bit. (md_assemble): Handle unsupported_nf. (parse_insn): Handle Prefix_NF and report bad for illegal combination. (can_convert_NDD_to_legacy): Replace i.tm.opcode_modifier.nf with i.has_nf. (match_template): Support D for APX_F insns and check NF support. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Add bad test for NF bit. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. * testsuite/gas/i386/x86-64-apx-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-inval.s: Ditto. * testsuite/gas/i386/x86-64.exp: Add apx nf tests. * testsuite/gas/i386/x86-64-apx-nf-intel.d: New test. * testsuite/gas/i386/x86-64-apx-nf.d: Ditto. * testsuite/gas/i386/x86-64-apx-nf.s: Ditto. opcodes/ChangeLog: * i386-dis-evex.h: Add %NF to the instructions that support APX NF and add new instruction imul, popcnt, tzcnt and lzcnt to EVEX table. * i386-dis-evex-reg.h: Ditto. * i386-dis.c (struct instr_info): Add nf. (struct dis386): Add "NF" for EVEX.NF. (get_valid_dis386): Set ins->vex.nf and report bad-nf for illegal case. (print_insn): Handle ins.vex.nf. (putop): Handle "%NF". * i386-opc.h (Prefix_NF): New. * i386-opc.tbl: Added new entries to support full APX NF instructions. * i386-mnem.h: Regenerated. * i386-tbl.h: Regenerated.
2024-04-07 17:28:25 +08:00
{ "%NFpopcntS", { Gv, Ev }, PREFIX_NP_OR_DATA },
Created an empty EVEX_MAP4_ sub-table for EVEX instructions. opcode/ChangeLog: * i386-dis-evex.hi: Added an empty EVEX_MAP4_ sub-table for legacy insn promote to EVEX insn. * opcodes/i386-dis-evex.h: Add EVEX_MAP4.
2023-12-28 09:06:40 +08:00
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
Support APX Push2/Pop2 PPX functionality for PUSH/POP is not implemented in this patch and will be implemented separately. gas/ChangeLog: 2023-12-28 Zewei Mo <zewei.mo@intel.com> H.J. Lu <hongjiu.lu@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c: (enum i386_error): New unsupported_rsp_register and invalid_src_register_set. (md_assemble): Add handler for unsupported_rsp_register and invalid_src_register_set. (check_APX_operands): Add invalid check for push2/pop2. (match_template): Handle check_APX_operands. * testsuite/gas/i386/i386.exp: Add apx-push2pop2 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2.d: New test. * testsuite/gas/i386/x86-64-apx-push2pop2.s: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2-intel.d: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2-inval.s: Ditto. * testsuite/gas/i386/apx-push2pop2-inval.s: Ditto. * testsuite/gas/i386/apx-push2pop2-inval.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Added bad testcases for POP2. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-reg.h: Add REG_EVEX_MAP4_8F. * i386-dis-evex-w.h: Add EVEX_W_MAP4_8F_R_0 and EVEX_W_MAP4_FF_R_6 * i386-dis-evex.h: Add REG_EVEX_MAP4_8F. * i386-dis.c (PUSH2_POP2_Fixup): Add special handling for PUSH2/POP2. (get_valid_dis386): Add handler for vector length and address_mode for APX-Push2/Pop2 insn. (nd): define nd as b for EVEX-promoted instrutions. (OP_VEX): Add handler of 64-bit vvvv register for APX-Push2/Pop2 insn. * i386-gen.c: Add Push2Pop2 bitfield. * i386-opc.h: Regenerated. * i386-opc.tbl: Regenerated.
2023-12-28 09:06:40 +08:00
{ REG_TABLE (REG_EVEX_MAP4_8F) },
Created an empty EVEX_MAP4_ sub-table for EVEX instructions. opcode/ChangeLog: * i386-dis-evex.hi: Added an empty EVEX_MAP4_ sub-table for legacy insn promote to EVEX insn. * opcodes/i386-dis-evex.h: Add EVEX_MAP4.
2023-12-28 09:06:40 +08:00
/* 90 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 98 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* A0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
Support APX NF For the case when NDD and NF are both 0 in evex-promoted format, we will fully support and test it in another patch. gas/ChangeLog: * NEWS: Support Intel APX NF. * config/tc-i386.c (enum i386_error): Add unsupported_nf. (struct _i386_insn): Add has_nf. (is_apx_evex_encoding): Ditto. (build_apx_evex_prefix): Encode the NF bit. (md_assemble): Handle unsupported_nf. (parse_insn): Handle Prefix_NF and report bad for illegal combination. (can_convert_NDD_to_legacy): Replace i.tm.opcode_modifier.nf with i.has_nf. (match_template): Support D for APX_F insns and check NF support. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Add bad test for NF bit. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. * testsuite/gas/i386/x86-64-apx-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-inval.s: Ditto. * testsuite/gas/i386/x86-64.exp: Add apx nf tests. * testsuite/gas/i386/x86-64-apx-nf-intel.d: New test. * testsuite/gas/i386/x86-64-apx-nf.d: Ditto. * testsuite/gas/i386/x86-64-apx-nf.s: Ditto. opcodes/ChangeLog: * i386-dis-evex.h: Add %NF to the instructions that support APX NF and add new instruction imul, popcnt, tzcnt and lzcnt to EVEX table. * i386-dis-evex-reg.h: Ditto. * i386-dis.c (struct instr_info): Add nf. (struct dis386): Add "NF" for EVEX.NF. (get_valid_dis386): Set ins->vex.nf and report bad-nf for illegal case. (print_insn): Handle ins.vex.nf. (putop): Handle "%NF". * i386-opc.h (Prefix_NF): New. * i386-opc.tbl: Added new entries to support full APX NF instructions. * i386-mnem.h: Regenerated. * i386-tbl.h: Regenerated.
2024-04-07 17:28:25 +08:00
{ "%NFshldS", { VexGv, Ev, Gv, CL }, PREFIX_NP_OR_DATA },
Created an empty EVEX_MAP4_ sub-table for EVEX instructions. opcode/ChangeLog: * i386-dis-evex.hi: Added an empty EVEX_MAP4_ sub-table for legacy insn promote to EVEX insn. * opcodes/i386-dis-evex.h: Add EVEX_MAP4.
2023-12-28 09:06:40 +08:00
{ Bad_Opcode },
{ Bad_Opcode },
/* A8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
Support APX NF For the case when NDD and NF are both 0 in evex-promoted format, we will fully support and test it in another patch. gas/ChangeLog: * NEWS: Support Intel APX NF. * config/tc-i386.c (enum i386_error): Add unsupported_nf. (struct _i386_insn): Add has_nf. (is_apx_evex_encoding): Ditto. (build_apx_evex_prefix): Encode the NF bit. (md_assemble): Handle unsupported_nf. (parse_insn): Handle Prefix_NF and report bad for illegal combination. (can_convert_NDD_to_legacy): Replace i.tm.opcode_modifier.nf with i.has_nf. (match_template): Support D for APX_F insns and check NF support. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Add bad test for NF bit. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. * testsuite/gas/i386/x86-64-apx-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-inval.s: Ditto. * testsuite/gas/i386/x86-64.exp: Add apx nf tests. * testsuite/gas/i386/x86-64-apx-nf-intel.d: New test. * testsuite/gas/i386/x86-64-apx-nf.d: Ditto. * testsuite/gas/i386/x86-64-apx-nf.s: Ditto. opcodes/ChangeLog: * i386-dis-evex.h: Add %NF to the instructions that support APX NF and add new instruction imul, popcnt, tzcnt and lzcnt to EVEX table. * i386-dis-evex-reg.h: Ditto. * i386-dis.c (struct instr_info): Add nf. (struct dis386): Add "NF" for EVEX.NF. (get_valid_dis386): Set ins->vex.nf and report bad-nf for illegal case. (print_insn): Handle ins.vex.nf. (putop): Handle "%NF". * i386-opc.h (Prefix_NF): New. * i386-opc.tbl: Added new entries to support full APX NF instructions. * i386-mnem.h: Regenerated. * i386-tbl.h: Regenerated.
2024-04-07 17:28:25 +08:00
{ "%NFshrdS", { VexGv, Ev, Gv, CL }, PREFIX_NP_OR_DATA },
Created an empty EVEX_MAP4_ sub-table for EVEX instructions. opcode/ChangeLog: * i386-dis-evex.hi: Added an empty EVEX_MAP4_ sub-table for legacy insn promote to EVEX insn. * opcodes/i386-dis-evex.h: Add EVEX_MAP4.
2023-12-28 09:06:40 +08:00
{ Bad_Opcode },
Support APX NF For the case when NDD and NF are both 0 in evex-promoted format, we will fully support and test it in another patch. gas/ChangeLog: * NEWS: Support Intel APX NF. * config/tc-i386.c (enum i386_error): Add unsupported_nf. (struct _i386_insn): Add has_nf. (is_apx_evex_encoding): Ditto. (build_apx_evex_prefix): Encode the NF bit. (md_assemble): Handle unsupported_nf. (parse_insn): Handle Prefix_NF and report bad for illegal combination. (can_convert_NDD_to_legacy): Replace i.tm.opcode_modifier.nf with i.has_nf. (match_template): Support D for APX_F insns and check NF support. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Add bad test for NF bit. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. * testsuite/gas/i386/x86-64-apx-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-inval.s: Ditto. * testsuite/gas/i386/x86-64.exp: Add apx nf tests. * testsuite/gas/i386/x86-64-apx-nf-intel.d: New test. * testsuite/gas/i386/x86-64-apx-nf.d: Ditto. * testsuite/gas/i386/x86-64-apx-nf.s: Ditto. opcodes/ChangeLog: * i386-dis-evex.h: Add %NF to the instructions that support APX NF and add new instruction imul, popcnt, tzcnt and lzcnt to EVEX table. * i386-dis-evex-reg.h: Ditto. * i386-dis.c (struct instr_info): Add nf. (struct dis386): Add "NF" for EVEX.NF. (get_valid_dis386): Set ins->vex.nf and report bad-nf for illegal case. (print_insn): Handle ins.vex.nf. (putop): Handle "%NF". * i386-opc.h (Prefix_NF): New. * i386-opc.tbl: Added new entries to support full APX NF instructions. * i386-mnem.h: Regenerated. * i386-tbl.h: Regenerated.
2024-04-07 17:28:25 +08:00
{ "%NFimulS", { VexGv, Gv, Ev }, PREFIX_NP_OR_DATA },
Created an empty EVEX_MAP4_ sub-table for EVEX instructions. opcode/ChangeLog: * i386-dis-evex.hi: Added an empty EVEX_MAP4_ sub-table for legacy insn promote to EVEX insn. * opcodes/i386-dis-evex.h: Add EVEX_MAP4.
2023-12-28 09:06:40 +08:00
/* B0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* B8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* C0 */
Support APX NDD opcodes/ChangeLog: * opcodes/i386-dis-evex-reg.h: Handle for REG_EVEX_MAP4_80, REG_EVEX_MAP4_81, REG_EVEX_MAP4_83, REG_EVEX_MAP4_F6, REG_EVEX_MAP4_F7, REG_EVEX_MAP4_FE, REG_EVEX_MAP4_FF. * opcodes/i386-dis-evex.h: Add NDD insn. * opcodes/i386-dis.c (nd): New define. (VexGb): Ditto. (VexGv): Ditto. (get_valid_dis386): Change for NDD decode. (print_insn): Ditto. (putop): Ditto. (intel_operand_size): Ditto. (OP_E_memory): Ditto. (OP_VEX): Ditto. * opcodes/i386-opc.h (VexVVVV_DST): New. * opcodes/i386-opc.tbl: Add APX NDD instructions and adjust VexVVVV. * opcodes/i386-tbl.h: Regenerated. gas/ChangeLog: * gas/config/tc-i386.c (operand_size_match): Support APX NDD that the number of operands is 3. (build_apx_evex_prefix): Change for ndd encode. (process_operands): Ditto. (build_modrm_byte): Ditto. (match_template): Support swap the first two operands for APX NDD. * testsuite/gas/i386/x86-64.exp: Add x86-64-apx-ndd. * testsuite/gas/i386/x86-64-apx-ndd.d: New test. * testsuite/gas/i386/x86-64-apx-ndd.s: Ditto. * testsuite/gas/i386/x86-64-pseudos.d: Add test. * testsuite/gas/i386/x86-64-pseudos.s: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d : Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s : Ditto.
2023-12-28 09:06:40 +08:00
{ REG_TABLE (REG_C0) },
{ REG_TABLE (REG_C1) },
Created an empty EVEX_MAP4_ sub-table for EVEX instructions. opcode/ChangeLog: * i386-dis-evex.hi: Added an empty EVEX_MAP4_ sub-table for legacy insn promote to EVEX insn. * opcodes/i386-dis-evex.h: Add EVEX_MAP4.
2023-12-28 09:06:40 +08:00
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* C8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* D0 */
Support APX NDD opcodes/ChangeLog: * opcodes/i386-dis-evex-reg.h: Handle for REG_EVEX_MAP4_80, REG_EVEX_MAP4_81, REG_EVEX_MAP4_83, REG_EVEX_MAP4_F6, REG_EVEX_MAP4_F7, REG_EVEX_MAP4_FE, REG_EVEX_MAP4_FF. * opcodes/i386-dis-evex.h: Add NDD insn. * opcodes/i386-dis.c (nd): New define. (VexGb): Ditto. (VexGv): Ditto. (get_valid_dis386): Change for NDD decode. (print_insn): Ditto. (putop): Ditto. (intel_operand_size): Ditto. (OP_E_memory): Ditto. (OP_VEX): Ditto. * opcodes/i386-opc.h (VexVVVV_DST): New. * opcodes/i386-opc.tbl: Add APX NDD instructions and adjust VexVVVV. * opcodes/i386-tbl.h: Regenerated. gas/ChangeLog: * gas/config/tc-i386.c (operand_size_match): Support APX NDD that the number of operands is 3. (build_apx_evex_prefix): Change for ndd encode. (process_operands): Ditto. (build_modrm_byte): Ditto. (match_template): Support swap the first two operands for APX NDD. * testsuite/gas/i386/x86-64.exp: Add x86-64-apx-ndd. * testsuite/gas/i386/x86-64-apx-ndd.d: New test. * testsuite/gas/i386/x86-64-apx-ndd.s: Ditto. * testsuite/gas/i386/x86-64-pseudos.d: Add test. * testsuite/gas/i386/x86-64-pseudos.s: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d : Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s : Ditto.
2023-12-28 09:06:40 +08:00
{ REG_TABLE (REG_D0) },
{ REG_TABLE (REG_D1) },
{ REG_TABLE (REG_D2) },
{ REG_TABLE (REG_D3) },
x86/APX: Remove KEYLOCKER and SHA promotions from EVEX MAP4 APX spec removed KEYLOCKER and SHA promotions from EVEX MAP4. https://www.intel.com/content/www/us/en/developer/articles/technical/advanced-performance-extensions-apx.html gas/ChangeLog: * NEWS: Mention that remove KEYLOCKER and SHA promotions from EVEX * MAP4. * config/tc-i386.c (process_operands): Removed special handling of * KEYLOCKER and SHA. * testsuite/gas/i386/x86-64-apx-egpr-promote-inval.l: Removed KEYLOCKER * and SHA instructions. * testsuite/gas/i386/x86-64-apx-egpr-promote-inval.s: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-wig.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-prefix.h: Removed KEYLOCKER and SHA instructions. * i386-dis-evex.h: Ditto. * i386-opc.tbl: Ditto. * i386-dis.c (print_vector_reg): Removed special handling of KEYLOCKER * and SHA.
2024-04-02 14:40:18 +08:00
{ Bad_Opcode },
Created an empty EVEX_MAP4_ sub-table for EVEX instructions. opcode/ChangeLog: * i386-dis-evex.hi: Added an empty EVEX_MAP4_ sub-table for legacy insn promote to EVEX insn. * opcodes/i386-dis-evex.h: Add EVEX_MAP4.
2023-12-28 09:06:40 +08:00
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* D8 */
x86/APX: Remove KEYLOCKER and SHA promotions from EVEX MAP4 APX spec removed KEYLOCKER and SHA promotions from EVEX MAP4. https://www.intel.com/content/www/us/en/developer/articles/technical/advanced-performance-extensions-apx.html gas/ChangeLog: * NEWS: Mention that remove KEYLOCKER and SHA promotions from EVEX * MAP4. * config/tc-i386.c (process_operands): Removed special handling of * KEYLOCKER and SHA. * testsuite/gas/i386/x86-64-apx-egpr-promote-inval.l: Removed KEYLOCKER * and SHA instructions. * testsuite/gas/i386/x86-64-apx-egpr-promote-inval.s: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-wig.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-prefix.h: Removed KEYLOCKER and SHA instructions. * i386-dis-evex.h: Ditto. * i386-opc.tbl: Ditto. * i386-dis.c (print_vector_reg): Removed special handling of KEYLOCKER * and SHA.
2024-04-02 14:40:18 +08:00
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
Created an empty EVEX_MAP4_ sub-table for EVEX instructions. opcode/ChangeLog: * i386-dis-evex.hi: Added an empty EVEX_MAP4_ sub-table for legacy insn promote to EVEX insn. * opcodes/i386-dis-evex.h: Add EVEX_MAP4.
2023-12-28 09:06:40 +08:00
/* E0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* E8 */
{ Bad_Opcode },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* F0 */
Support APX GPR32 with extend evex prefix This patch adds non-ND, non-NF forms of EVEX promotion insn. EVEX extension of legacy instructions: All promoted legacy instructions are placed in EVEX map 4, which is currently reserved. EVEX extension of EVEX instructions: All existing EVEX instructions are extended by APX using the extended EVEX prefix, so that they can access all 32 GPRs. EVEX extension of VEX instructions: Promoting a VEX instruction into the EVEX space does not change the map id, the opcode, or the operand encoding of the VEX instruction. Note: The promoted versions of MOVBE will be extended to include the “MOVBE reg1, reg2”. gas/ChangeLog: 2023-12-28 Lingling Kong <lingling.kong@intel.com> H.J. Lu <hongjiu.lu@intel.com> Lili Cui <lili.cui@intel.com> Lin Hu <lin1.hu@intel.com> * config/tc-i386.c (struct _i386_insn): Add has_egpr. (need_evex_encoding): Adjusted for apx. (cpu_flags_match): Ditto. (install_template): Handled APX combines. (is_apx_evex_encoding): Test apx evex encoding. (build_apx_evex_prefix): Enabe APX evex prefix. (md_assemble): Handle apx with evex encoding. (process_suffix): Handle apx map4 prefix. (check_register): Assign i.vec_encoding for APX evex instructions. * testsuite/gas/i386/x86-64-evex.d: Adjust test cases. * testsuite/gas/i386/x86-64.exp: Adjust x86-64-inval-movbe. opcodes/ChangeLog: * i386-dis-evex-len.h: Handle EVEX_LEN_0F38F2, EVEX_LEN_0F38F3. * i386-dis-evex-prefix.h: Handle PREFIX_EVEX_0F38F2_L_0, PREFIX_EVEX_0F38F3_L_0, PREFIX_EVEX_MAP4_D8, PREFIX_EVEX_MAP4_DA, PREFIX_EVEX_MAP4_DB, PREFIX_EVEX_MAP4_DC, PREFIX_EVEX_MAP4_DD, PREFIX_EVEX_MAP4_DE, PREFIX_EVEX_MAP4_DF, PREFIX_EVEX_MAP4_F0, PREFIX_EVEX_MAP4_F1, PREFIX_EVEX_MAP4_F2, PREFIX_EVEX_MAP4_F8. * i386-dis-evex-reg.h: Handle REG_EVEX_0F38F3_L_0_P_0. * i386-dis-evex.h: Add EVEX_MAP4_ for legacy insn promote to apx to use gpr32 * opcodes/i386-dis-evex-x86-64.h: Handle Add X86_64_EVEX_0F90, X86_64_EVEX_0F92, X86_64_EVEX_0F93, X86_64_EVEX_0F38F2, X86_64_EVEX_0F38F3, X86_64_EVEX_0F38F5, X86_64_EVEX_0F38F6, X86_64_EVEX_0F38F7, X86_64_EVEX_0F3AF0, X86_64_EVEX_0F91. * i386-dis.c (struct instr_info): Deleted bool r. (PREFIX_NP_OR_DATA): New. (NO_PREFIX): New. (putop): Ditto. (X86_64_EVEX_FROM_VEX_TABLE): Diito. (get_valid_dis386): Decode insn erex in extend evex prefix. Handle EVEX_MAP4 (print_insn): Handle PREFIX_DATA_AND_NP_ONLY. (print_register): Handle apx instructions decode. (OP_E_memory): Diito. (OP_G): Diito. (OP_XMM): Diito. (DistinctDest_Fixup): Diito. * i386-gen.c (process_i386_opcode_modifier): Add EVEXMAP4. * i386-opc.h (SPACE_EVEXMAP4): Add legacy insn promote to evex. * i386-opc.tbl: Handle some legacy and vex insns don't support gpr32. And add some legacy insn (map2 / 3) promote to evex.
2023-12-28 09:06:40 +08:00
{ PREFIX_TABLE (PREFIX_EVEX_MAP4_F0) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP4_F1) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP4_F2) },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ Bad_Opcode },
Support APX NF For the case when NDD and NF are both 0 in evex-promoted format, we will fully support and test it in another patch. gas/ChangeLog: * NEWS: Support Intel APX NF. * config/tc-i386.c (enum i386_error): Add unsupported_nf. (struct _i386_insn): Add has_nf. (is_apx_evex_encoding): Ditto. (build_apx_evex_prefix): Encode the NF bit. (md_assemble): Handle unsupported_nf. (parse_insn): Handle Prefix_NF and report bad for illegal combination. (can_convert_NDD_to_legacy): Replace i.tm.opcode_modifier.nf with i.has_nf. (match_template): Support D for APX_F insns and check NF support. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Add bad test for NF bit. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. * testsuite/gas/i386/x86-64-apx-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-inval.s: Ditto. * testsuite/gas/i386/x86-64.exp: Add apx nf tests. * testsuite/gas/i386/x86-64-apx-nf-intel.d: New test. * testsuite/gas/i386/x86-64-apx-nf.d: Ditto. * testsuite/gas/i386/x86-64-apx-nf.s: Ditto. opcodes/ChangeLog: * i386-dis-evex.h: Add %NF to the instructions that support APX NF and add new instruction imul, popcnt, tzcnt and lzcnt to EVEX table. * i386-dis-evex-reg.h: Ditto. * i386-dis.c (struct instr_info): Add nf. (struct dis386): Add "NF" for EVEX.NF. (get_valid_dis386): Set ins->vex.nf and report bad-nf for illegal case. (print_insn): Handle ins.vex.nf. (putop): Handle "%NF". * i386-opc.h (Prefix_NF): New. * i386-opc.tbl: Added new entries to support full APX NF instructions. * i386-mnem.h: Regenerated. * i386-tbl.h: Regenerated.
2024-04-07 17:28:25 +08:00
{ "%NFtzcntS", { Gv, Ev }, PREFIX_NP_OR_DATA },
{ "%NFlzcntS", { Gv, Ev }, PREFIX_NP_OR_DATA },
Support APX NDD opcodes/ChangeLog: * opcodes/i386-dis-evex-reg.h: Handle for REG_EVEX_MAP4_80, REG_EVEX_MAP4_81, REG_EVEX_MAP4_83, REG_EVEX_MAP4_F6, REG_EVEX_MAP4_F7, REG_EVEX_MAP4_FE, REG_EVEX_MAP4_FF. * opcodes/i386-dis-evex.h: Add NDD insn. * opcodes/i386-dis.c (nd): New define. (VexGb): Ditto. (VexGv): Ditto. (get_valid_dis386): Change for NDD decode. (print_insn): Ditto. (putop): Ditto. (intel_operand_size): Ditto. (OP_E_memory): Ditto. (OP_VEX): Ditto. * opcodes/i386-opc.h (VexVVVV_DST): New. * opcodes/i386-opc.tbl: Add APX NDD instructions and adjust VexVVVV. * opcodes/i386-tbl.h: Regenerated. gas/ChangeLog: * gas/config/tc-i386.c (operand_size_match): Support APX NDD that the number of operands is 3. (build_apx_evex_prefix): Change for ndd encode. (process_operands): Ditto. (build_modrm_byte): Ditto. (match_template): Support swap the first two operands for APX NDD. * testsuite/gas/i386/x86-64.exp: Add x86-64-apx-ndd. * testsuite/gas/i386/x86-64-apx-ndd.d: New test. * testsuite/gas/i386/x86-64-apx-ndd.s: Ditto. * testsuite/gas/i386/x86-64-pseudos.d: Add test. * testsuite/gas/i386/x86-64-pseudos.s: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d : Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s : Ditto.
2023-12-28 09:06:40 +08:00
{ REG_TABLE (REG_EVEX_MAP4_F6) },
{ REG_TABLE (REG_EVEX_MAP4_F7) },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
/* F8 */
Support APX GPR32 with extend evex prefix This patch adds non-ND, non-NF forms of EVEX promotion insn. EVEX extension of legacy instructions: All promoted legacy instructions are placed in EVEX map 4, which is currently reserved. EVEX extension of EVEX instructions: All existing EVEX instructions are extended by APX using the extended EVEX prefix, so that they can access all 32 GPRs. EVEX extension of VEX instructions: Promoting a VEX instruction into the EVEX space does not change the map id, the opcode, or the operand encoding of the VEX instruction. Note: The promoted versions of MOVBE will be extended to include the “MOVBE reg1, reg2”. gas/ChangeLog: 2023-12-28 Lingling Kong <lingling.kong@intel.com> H.J. Lu <hongjiu.lu@intel.com> Lili Cui <lili.cui@intel.com> Lin Hu <lin1.hu@intel.com> * config/tc-i386.c (struct _i386_insn): Add has_egpr. (need_evex_encoding): Adjusted for apx. (cpu_flags_match): Ditto. (install_template): Handled APX combines. (is_apx_evex_encoding): Test apx evex encoding. (build_apx_evex_prefix): Enabe APX evex prefix. (md_assemble): Handle apx with evex encoding. (process_suffix): Handle apx map4 prefix. (check_register): Assign i.vec_encoding for APX evex instructions. * testsuite/gas/i386/x86-64-evex.d: Adjust test cases. * testsuite/gas/i386/x86-64.exp: Adjust x86-64-inval-movbe. opcodes/ChangeLog: * i386-dis-evex-len.h: Handle EVEX_LEN_0F38F2, EVEX_LEN_0F38F3. * i386-dis-evex-prefix.h: Handle PREFIX_EVEX_0F38F2_L_0, PREFIX_EVEX_0F38F3_L_0, PREFIX_EVEX_MAP4_D8, PREFIX_EVEX_MAP4_DA, PREFIX_EVEX_MAP4_DB, PREFIX_EVEX_MAP4_DC, PREFIX_EVEX_MAP4_DD, PREFIX_EVEX_MAP4_DE, PREFIX_EVEX_MAP4_DF, PREFIX_EVEX_MAP4_F0, PREFIX_EVEX_MAP4_F1, PREFIX_EVEX_MAP4_F2, PREFIX_EVEX_MAP4_F8. * i386-dis-evex-reg.h: Handle REG_EVEX_0F38F3_L_0_P_0. * i386-dis-evex.h: Add EVEX_MAP4_ for legacy insn promote to apx to use gpr32 * opcodes/i386-dis-evex-x86-64.h: Handle Add X86_64_EVEX_0F90, X86_64_EVEX_0F92, X86_64_EVEX_0F93, X86_64_EVEX_0F38F2, X86_64_EVEX_0F38F3, X86_64_EVEX_0F38F5, X86_64_EVEX_0F38F6, X86_64_EVEX_0F38F7, X86_64_EVEX_0F3AF0, X86_64_EVEX_0F91. * i386-dis.c (struct instr_info): Deleted bool r. (PREFIX_NP_OR_DATA): New. (NO_PREFIX): New. (putop): Ditto. (X86_64_EVEX_FROM_VEX_TABLE): Diito. (get_valid_dis386): Decode insn erex in extend evex prefix. Handle EVEX_MAP4 (print_insn): Handle PREFIX_DATA_AND_NP_ONLY. (print_register): Handle apx instructions decode. (OP_E_memory): Diito. (OP_G): Diito. (OP_XMM): Diito. (DistinctDest_Fixup): Diito. * i386-gen.c (process_i386_opcode_modifier): Add EVEXMAP4. * i386-opc.h (SPACE_EVEXMAP4): Add legacy insn promote to evex. * i386-opc.tbl: Handle some legacy and vex insns don't support gpr32. And add some legacy insn (map2 / 3) promote to evex.
2023-12-28 09:06:40 +08:00
{ PREFIX_TABLE (PREFIX_EVEX_MAP4_F8) },
{ "movdiri", { Mdq, Gdq }, NO_PREFIX },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ Bad_Opcode },
{ Bad_Opcode },
Support APX GPR32 with extend evex prefix This patch adds non-ND, non-NF forms of EVEX promotion insn. EVEX extension of legacy instructions: All promoted legacy instructions are placed in EVEX map 4, which is currently reserved. EVEX extension of EVEX instructions: All existing EVEX instructions are extended by APX using the extended EVEX prefix, so that they can access all 32 GPRs. EVEX extension of VEX instructions: Promoting a VEX instruction into the EVEX space does not change the map id, the opcode, or the operand encoding of the VEX instruction. Note: The promoted versions of MOVBE will be extended to include the “MOVBE reg1, reg2”. gas/ChangeLog: 2023-12-28 Lingling Kong <lingling.kong@intel.com> H.J. Lu <hongjiu.lu@intel.com> Lili Cui <lili.cui@intel.com> Lin Hu <lin1.hu@intel.com> * config/tc-i386.c (struct _i386_insn): Add has_egpr. (need_evex_encoding): Adjusted for apx. (cpu_flags_match): Ditto. (install_template): Handled APX combines. (is_apx_evex_encoding): Test apx evex encoding. (build_apx_evex_prefix): Enabe APX evex prefix. (md_assemble): Handle apx with evex encoding. (process_suffix): Handle apx map4 prefix. (check_register): Assign i.vec_encoding for APX evex instructions. * testsuite/gas/i386/x86-64-evex.d: Adjust test cases. * testsuite/gas/i386/x86-64.exp: Adjust x86-64-inval-movbe. opcodes/ChangeLog: * i386-dis-evex-len.h: Handle EVEX_LEN_0F38F2, EVEX_LEN_0F38F3. * i386-dis-evex-prefix.h: Handle PREFIX_EVEX_0F38F2_L_0, PREFIX_EVEX_0F38F3_L_0, PREFIX_EVEX_MAP4_D8, PREFIX_EVEX_MAP4_DA, PREFIX_EVEX_MAP4_DB, PREFIX_EVEX_MAP4_DC, PREFIX_EVEX_MAP4_DD, PREFIX_EVEX_MAP4_DE, PREFIX_EVEX_MAP4_DF, PREFIX_EVEX_MAP4_F0, PREFIX_EVEX_MAP4_F1, PREFIX_EVEX_MAP4_F2, PREFIX_EVEX_MAP4_F8. * i386-dis-evex-reg.h: Handle REG_EVEX_0F38F3_L_0_P_0. * i386-dis-evex.h: Add EVEX_MAP4_ for legacy insn promote to apx to use gpr32 * opcodes/i386-dis-evex-x86-64.h: Handle Add X86_64_EVEX_0F90, X86_64_EVEX_0F92, X86_64_EVEX_0F93, X86_64_EVEX_0F38F2, X86_64_EVEX_0F38F3, X86_64_EVEX_0F38F5, X86_64_EVEX_0F38F6, X86_64_EVEX_0F38F7, X86_64_EVEX_0F3AF0, X86_64_EVEX_0F91. * i386-dis.c (struct instr_info): Deleted bool r. (PREFIX_NP_OR_DATA): New. (NO_PREFIX): New. (putop): Ditto. (X86_64_EVEX_FROM_VEX_TABLE): Diito. (get_valid_dis386): Decode insn erex in extend evex prefix. Handle EVEX_MAP4 (print_insn): Handle PREFIX_DATA_AND_NP_ONLY. (print_register): Handle apx instructions decode. (OP_E_memory): Diito. (OP_G): Diito. (OP_XMM): Diito. (DistinctDest_Fixup): Diito. * i386-gen.c (process_i386_opcode_modifier): Add EVEXMAP4. * i386-opc.h (SPACE_EVEXMAP4): Add legacy insn promote to evex. * i386-opc.tbl: Handle some legacy and vex insns don't support gpr32. And add some legacy insn (map2 / 3) promote to evex.
2023-12-28 09:06:40 +08:00
{ PREFIX_TABLE (PREFIX_0F38FC) },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
{ Bad_Opcode },
Support APX NDD opcodes/ChangeLog: * opcodes/i386-dis-evex-reg.h: Handle for REG_EVEX_MAP4_80, REG_EVEX_MAP4_81, REG_EVEX_MAP4_83, REG_EVEX_MAP4_F6, REG_EVEX_MAP4_F7, REG_EVEX_MAP4_FE, REG_EVEX_MAP4_FF. * opcodes/i386-dis-evex.h: Add NDD insn. * opcodes/i386-dis.c (nd): New define. (VexGb): Ditto. (VexGv): Ditto. (get_valid_dis386): Change for NDD decode. (print_insn): Ditto. (putop): Ditto. (intel_operand_size): Ditto. (OP_E_memory): Ditto. (OP_VEX): Ditto. * opcodes/i386-opc.h (VexVVVV_DST): New. * opcodes/i386-opc.tbl: Add APX NDD instructions and adjust VexVVVV. * opcodes/i386-tbl.h: Regenerated. gas/ChangeLog: * gas/config/tc-i386.c (operand_size_match): Support APX NDD that the number of operands is 3. (build_apx_evex_prefix): Change for ndd encode. (process_operands): Ditto. (build_modrm_byte): Ditto. (match_template): Support swap the first two operands for APX NDD. * testsuite/gas/i386/x86-64.exp: Add x86-64-apx-ndd. * testsuite/gas/i386/x86-64-apx-ndd.d: New test. * testsuite/gas/i386/x86-64-apx-ndd.s: Ditto. * testsuite/gas/i386/x86-64-pseudos.d: Add test. * testsuite/gas/i386/x86-64-pseudos.s: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d : Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s : Ditto.
2023-12-28 09:06:40 +08:00
{ REG_TABLE (REG_EVEX_MAP4_FE) },
{ REG_TABLE (REG_EVEX_MAP4_FF) },
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
},
[PATCH 1/2] Enable Intel AVX512_FP16 instructions Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32 in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx). There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8 operands predated our current conventions; those instructions moved to map 3. FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3 is very sparsely populated. Most of the FP16 instructions share opcodes and prefix (EVEX.pp) bits with the related FP32 operations. Intel AVX512 FP16 instructions has new displacements scaling rules, please refer to the public software developer manual for detail information. gas/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (struct Broadcast_Operation): Adjust comment. (cpu_arch): Add .avx512_fp16. (cpu_noarch): Add noavx512_fp16. (pte): Add evexmap5 and evexmap6. (build_evex_prefix): Handle EVEXMAP5 and EVEXMAP6. (check_VecOperations): Handle {1to32}. (check_VecOperands): Handle CheckRegNumb. (check_word_reg): Handle Toqword. (i386_error): Add invalid_dest_and_src_register_set. (match_template): Handle invalid_dest_and_src_register_set. * doc/c-i386.texi: Document avx512_fp16, noavx512_fp16. opcodes/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (EXwScalarS): New. (EXxh): Ditto. (EXxhc): Ditto. (EXxmmqh): Ditto. (EXxmmqdh): Ditto. (EXEvexXwb): Ditto. (DistinctDest_Fixup): Ditto. (enum): Add xh_mode, evex_half_bcst_xmmqh_mode, evex_half_bcst_xmmqdh_mode and w_swap_mode. (enum): Add PREFIX_EVEX_0F3A08_W_0, PREFIX_EVEX_0F3A0A_W_0, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3AC2, PREFIX_EVEX_MAP5_10, PREFIX_EVEX_MAP5_11, PREFIX_EVEX_MAP5_1D, PREFIX_EVEX_MAP5_2A, PREFIX_EVEX_MAP5_2C, PREFIX_EVEX_MAP5_2D, PREFIX_EVEX_MAP5_2E, PREFIX_EVEX_MAP5_2F, PREFIX_EVEX_MAP5_51, PREFIX_EVEX_MAP5_58, PREFIX_EVEX_MAP5_59, PREFIX_EVEX_MAP5_5A_W_0, PREFIX_EVEX_MAP5_5A_W_1, PREFIX_EVEX_MAP5_5B_W_0, PREFIX_EVEX_MAP5_5B_W_1, PREFIX_EVEX_MAP5_5C, PREFIX_EVEX_MAP5_5D, PREFIX_EVEX_MAP5_5E, PREFIX_EVEX_MAP5_5F, PREFIX_EVEX_MAP5_78, PREFIX_EVEX_MAP5_79, PREFIX_EVEX_MAP5_7A, PREFIX_EVEX_MAP5_7B, PREFIX_EVEX_MAP5_7C, PREFIX_EVEX_MAP5_7D_W_0, PREFIX_EVEX_MAP6_13, PREFIX_EVEX_MAP6_56, PREFIX_EVEX_MAP6_57, PREFIX_EVEX_MAP6_D6, PREFIX_EVEX_MAP6_D7 (enum): Add EVEX_MAP5 and EVEX_MAP6. (enum): Add EVEX_W_MAP5_5A, EVEX_W_MAP5_5B, EVEX_W_MAP5_78_P_0, EVEX_W_MAP5_78_P_2, EVEX_W_MAP5_79_P_0, EVEX_W_MAP5_79_P_2, EVEX_W_MAP5_7A_P_2, EVEX_W_MAP5_7A_P_3, EVEX_W_MAP5_7B_P_2, EVEX_W_MAP5_7C_P_0, EVEX_W_MAP5_7C_P_2, EVEX_W_MAP5_7D, EVEX_W_MAP6_13_P_0, EVEX_W_MAP6_13_P_2, (get_valid_dis386): Properly handle new instructions. (intel_operand_size): Handle new modes. (OP_E_memory): Ditto. (OP_EX): Ditto. * i386-dis-evex.h: Updated for AVX512_FP16. * i386-dis-evex-mod.h: Updated for AVX512_FP16. * i386-dis-evex-prefix.h: Updated for AVX512_FP16. * i386-dis-evex-reg.h : Updated for AVX512_FP16. * i386-dis-evex-w.h : Updated for AVX512_FP16. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_FP16_FLAGS, and CPU_ANY_AVX512_FP16_FLAGS. Update CPU_ANY_AVX512F_FLAGS and CPU_ANY_AVX512BW_FLAGS. (cpu_flags): Add CpuAVX512_FP16. (opcode_modifiers): Add DistinctDest. * i386-opc.h (enum): (AVX512_FP16): New. (i386_opcode_modifier): Add reqdistinctreg. (i386_cpu_flags): Add cpuavx512_fp16. (EVEXMAP5): Defined as a macro. (EVEXMAP6): Ditto. * i386-opc.tbl: Add Intel AVX512_FP16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Ditto.
2021-06-14 11:05:05 +08:00
/* EVEX_MAP5_ */
{
/* 00 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 08 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 10 */
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_10) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_11) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 18 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_1D) },
{ Bad_Opcode },
{ Bad_Opcode },
/* 20 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 28 */
{ Bad_Opcode },
{ Bad_Opcode },
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_2A) },
{ Bad_Opcode },
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_2C) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_2D) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_2E) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_2F) },
/* 30 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 38 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 40 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 48 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 50 */
{ Bad_Opcode },
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_51) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 58 */
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_58) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_59) },
x86: reduce AVX512-FP16 set of insns decoded through vex_w_table[] Like already indicated during review of the original submission, there's really only very few insns where going through this table is easier / cheaper than using suitable macros. Utilize %XH more and introduce similar %XS and %XD (which subsequently can be used for further table size reduction). While there also switch to using oappend() in 'XH' macro processing.
2022-01-14 17:54:21 +08:00
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_5A) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_5B) },
[PATCH 1/2] Enable Intel AVX512_FP16 instructions Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32 in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx). There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8 operands predated our current conventions; those instructions moved to map 3. FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3 is very sparsely populated. Most of the FP16 instructions share opcodes and prefix (EVEX.pp) bits with the related FP32 operations. Intel AVX512 FP16 instructions has new displacements scaling rules, please refer to the public software developer manual for detail information. gas/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (struct Broadcast_Operation): Adjust comment. (cpu_arch): Add .avx512_fp16. (cpu_noarch): Add noavx512_fp16. (pte): Add evexmap5 and evexmap6. (build_evex_prefix): Handle EVEXMAP5 and EVEXMAP6. (check_VecOperations): Handle {1to32}. (check_VecOperands): Handle CheckRegNumb. (check_word_reg): Handle Toqword. (i386_error): Add invalid_dest_and_src_register_set. (match_template): Handle invalid_dest_and_src_register_set. * doc/c-i386.texi: Document avx512_fp16, noavx512_fp16. opcodes/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (EXwScalarS): New. (EXxh): Ditto. (EXxhc): Ditto. (EXxmmqh): Ditto. (EXxmmqdh): Ditto. (EXEvexXwb): Ditto. (DistinctDest_Fixup): Ditto. (enum): Add xh_mode, evex_half_bcst_xmmqh_mode, evex_half_bcst_xmmqdh_mode and w_swap_mode. (enum): Add PREFIX_EVEX_0F3A08_W_0, PREFIX_EVEX_0F3A0A_W_0, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3AC2, PREFIX_EVEX_MAP5_10, PREFIX_EVEX_MAP5_11, PREFIX_EVEX_MAP5_1D, PREFIX_EVEX_MAP5_2A, PREFIX_EVEX_MAP5_2C, PREFIX_EVEX_MAP5_2D, PREFIX_EVEX_MAP5_2E, PREFIX_EVEX_MAP5_2F, PREFIX_EVEX_MAP5_51, PREFIX_EVEX_MAP5_58, PREFIX_EVEX_MAP5_59, PREFIX_EVEX_MAP5_5A_W_0, PREFIX_EVEX_MAP5_5A_W_1, PREFIX_EVEX_MAP5_5B_W_0, PREFIX_EVEX_MAP5_5B_W_1, PREFIX_EVEX_MAP5_5C, PREFIX_EVEX_MAP5_5D, PREFIX_EVEX_MAP5_5E, PREFIX_EVEX_MAP5_5F, PREFIX_EVEX_MAP5_78, PREFIX_EVEX_MAP5_79, PREFIX_EVEX_MAP5_7A, PREFIX_EVEX_MAP5_7B, PREFIX_EVEX_MAP5_7C, PREFIX_EVEX_MAP5_7D_W_0, PREFIX_EVEX_MAP6_13, PREFIX_EVEX_MAP6_56, PREFIX_EVEX_MAP6_57, PREFIX_EVEX_MAP6_D6, PREFIX_EVEX_MAP6_D7 (enum): Add EVEX_MAP5 and EVEX_MAP6. (enum): Add EVEX_W_MAP5_5A, EVEX_W_MAP5_5B, EVEX_W_MAP5_78_P_0, EVEX_W_MAP5_78_P_2, EVEX_W_MAP5_79_P_0, EVEX_W_MAP5_79_P_2, EVEX_W_MAP5_7A_P_2, EVEX_W_MAP5_7A_P_3, EVEX_W_MAP5_7B_P_2, EVEX_W_MAP5_7C_P_0, EVEX_W_MAP5_7C_P_2, EVEX_W_MAP5_7D, EVEX_W_MAP6_13_P_0, EVEX_W_MAP6_13_P_2, (get_valid_dis386): Properly handle new instructions. (intel_operand_size): Handle new modes. (OP_E_memory): Ditto. (OP_EX): Ditto. * i386-dis-evex.h: Updated for AVX512_FP16. * i386-dis-evex-mod.h: Updated for AVX512_FP16. * i386-dis-evex-prefix.h: Updated for AVX512_FP16. * i386-dis-evex-reg.h : Updated for AVX512_FP16. * i386-dis-evex-w.h : Updated for AVX512_FP16. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_FP16_FLAGS, and CPU_ANY_AVX512_FP16_FLAGS. Update CPU_ANY_AVX512F_FLAGS and CPU_ANY_AVX512BW_FLAGS. (cpu_flags): Add CpuAVX512_FP16. (opcode_modifiers): Add DistinctDest. * i386-opc.h (enum): (AVX512_FP16): New. (i386_opcode_modifier): Add reqdistinctreg. (i386_cpu_flags): Add cpuavx512_fp16. (EVEXMAP5): Defined as a macro. (EVEXMAP6): Ditto. * i386-opc.tbl: Add Intel AVX512_FP16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Ditto.
2021-06-14 11:05:05 +08:00
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_5C) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_5D) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_5E) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_5F) },
/* 60 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 68 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
Revert "2.41 Release sources" This reverts commit 675b9d612cc59446e84e2c6d89b45500cb603a8d. See https://sourceware.org/pipermail/binutils/2023-August/128761.html.
2023-08-02 19:06:23 +08:00
{ "vmovwY", { XMScalar, Edw }, PREFIX_DATA },
[PATCH 1/2] Enable Intel AVX512_FP16 instructions Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32 in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx). There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8 operands predated our current conventions; those instructions moved to map 3. FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3 is very sparsely populated. Most of the FP16 instructions share opcodes and prefix (EVEX.pp) bits with the related FP32 operations. Intel AVX512 FP16 instructions has new displacements scaling rules, please refer to the public software developer manual for detail information. gas/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (struct Broadcast_Operation): Adjust comment. (cpu_arch): Add .avx512_fp16. (cpu_noarch): Add noavx512_fp16. (pte): Add evexmap5 and evexmap6. (build_evex_prefix): Handle EVEXMAP5 and EVEXMAP6. (check_VecOperations): Handle {1to32}. (check_VecOperands): Handle CheckRegNumb. (check_word_reg): Handle Toqword. (i386_error): Add invalid_dest_and_src_register_set. (match_template): Handle invalid_dest_and_src_register_set. * doc/c-i386.texi: Document avx512_fp16, noavx512_fp16. opcodes/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (EXwScalarS): New. (EXxh): Ditto. (EXxhc): Ditto. (EXxmmqh): Ditto. (EXxmmqdh): Ditto. (EXEvexXwb): Ditto. (DistinctDest_Fixup): Ditto. (enum): Add xh_mode, evex_half_bcst_xmmqh_mode, evex_half_bcst_xmmqdh_mode and w_swap_mode. (enum): Add PREFIX_EVEX_0F3A08_W_0, PREFIX_EVEX_0F3A0A_W_0, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3AC2, PREFIX_EVEX_MAP5_10, PREFIX_EVEX_MAP5_11, PREFIX_EVEX_MAP5_1D, PREFIX_EVEX_MAP5_2A, PREFIX_EVEX_MAP5_2C, PREFIX_EVEX_MAP5_2D, PREFIX_EVEX_MAP5_2E, PREFIX_EVEX_MAP5_2F, PREFIX_EVEX_MAP5_51, PREFIX_EVEX_MAP5_58, PREFIX_EVEX_MAP5_59, PREFIX_EVEX_MAP5_5A_W_0, PREFIX_EVEX_MAP5_5A_W_1, PREFIX_EVEX_MAP5_5B_W_0, PREFIX_EVEX_MAP5_5B_W_1, PREFIX_EVEX_MAP5_5C, PREFIX_EVEX_MAP5_5D, PREFIX_EVEX_MAP5_5E, PREFIX_EVEX_MAP5_5F, PREFIX_EVEX_MAP5_78, PREFIX_EVEX_MAP5_79, PREFIX_EVEX_MAP5_7A, PREFIX_EVEX_MAP5_7B, PREFIX_EVEX_MAP5_7C, PREFIX_EVEX_MAP5_7D_W_0, PREFIX_EVEX_MAP6_13, PREFIX_EVEX_MAP6_56, PREFIX_EVEX_MAP6_57, PREFIX_EVEX_MAP6_D6, PREFIX_EVEX_MAP6_D7 (enum): Add EVEX_MAP5 and EVEX_MAP6. (enum): Add EVEX_W_MAP5_5A, EVEX_W_MAP5_5B, EVEX_W_MAP5_78_P_0, EVEX_W_MAP5_78_P_2, EVEX_W_MAP5_79_P_0, EVEX_W_MAP5_79_P_2, EVEX_W_MAP5_7A_P_2, EVEX_W_MAP5_7A_P_3, EVEX_W_MAP5_7B_P_2, EVEX_W_MAP5_7C_P_0, EVEX_W_MAP5_7C_P_2, EVEX_W_MAP5_7D, EVEX_W_MAP6_13_P_0, EVEX_W_MAP6_13_P_2, (get_valid_dis386): Properly handle new instructions. (intel_operand_size): Handle new modes. (OP_E_memory): Ditto. (OP_EX): Ditto. * i386-dis-evex.h: Updated for AVX512_FP16. * i386-dis-evex-mod.h: Updated for AVX512_FP16. * i386-dis-evex-prefix.h: Updated for AVX512_FP16. * i386-dis-evex-reg.h : Updated for AVX512_FP16. * i386-dis-evex-w.h : Updated for AVX512_FP16. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_FP16_FLAGS, and CPU_ANY_AVX512_FP16_FLAGS. Update CPU_ANY_AVX512F_FLAGS and CPU_ANY_AVX512BW_FLAGS. (cpu_flags): Add CpuAVX512_FP16. (opcode_modifiers): Add DistinctDest. * i386-opc.h (enum): (AVX512_FP16): New. (i386_opcode_modifier): Add reqdistinctreg. (i386_cpu_flags): Add cpuavx512_fp16. (EVEXMAP5): Defined as a macro. (EVEXMAP6): Ditto. * i386-opc.tbl: Add Intel AVX512_FP16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Ditto.
2021-06-14 11:05:05 +08:00
{ Bad_Opcode },
/* 70 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 78 */
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_78) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_79) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_7A) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_7B) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_7C) },
x86: reduce AVX512-FP16 set of insns decoded through vex_w_table[] Like already indicated during review of the original submission, there's really only very few insns where going through this table is easier / cheaper than using suitable macros. Utilize %XH more and introduce similar %XS and %XD (which subsequently can be used for further table size reduction). While there also switch to using oappend() in 'XH' macro processing.
2022-01-14 17:54:21 +08:00
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_7D) },
[PATCH 1/2] Enable Intel AVX512_FP16 instructions Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32 in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx). There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8 operands predated our current conventions; those instructions moved to map 3. FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3 is very sparsely populated. Most of the FP16 instructions share opcodes and prefix (EVEX.pp) bits with the related FP32 operations. Intel AVX512 FP16 instructions has new displacements scaling rules, please refer to the public software developer manual for detail information. gas/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (struct Broadcast_Operation): Adjust comment. (cpu_arch): Add .avx512_fp16. (cpu_noarch): Add noavx512_fp16. (pte): Add evexmap5 and evexmap6. (build_evex_prefix): Handle EVEXMAP5 and EVEXMAP6. (check_VecOperations): Handle {1to32}. (check_VecOperands): Handle CheckRegNumb. (check_word_reg): Handle Toqword. (i386_error): Add invalid_dest_and_src_register_set. (match_template): Handle invalid_dest_and_src_register_set. * doc/c-i386.texi: Document avx512_fp16, noavx512_fp16. opcodes/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (EXwScalarS): New. (EXxh): Ditto. (EXxhc): Ditto. (EXxmmqh): Ditto. (EXxmmqdh): Ditto. (EXEvexXwb): Ditto. (DistinctDest_Fixup): Ditto. (enum): Add xh_mode, evex_half_bcst_xmmqh_mode, evex_half_bcst_xmmqdh_mode and w_swap_mode. (enum): Add PREFIX_EVEX_0F3A08_W_0, PREFIX_EVEX_0F3A0A_W_0, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3AC2, PREFIX_EVEX_MAP5_10, PREFIX_EVEX_MAP5_11, PREFIX_EVEX_MAP5_1D, PREFIX_EVEX_MAP5_2A, PREFIX_EVEX_MAP5_2C, PREFIX_EVEX_MAP5_2D, PREFIX_EVEX_MAP5_2E, PREFIX_EVEX_MAP5_2F, PREFIX_EVEX_MAP5_51, PREFIX_EVEX_MAP5_58, PREFIX_EVEX_MAP5_59, PREFIX_EVEX_MAP5_5A_W_0, PREFIX_EVEX_MAP5_5A_W_1, PREFIX_EVEX_MAP5_5B_W_0, PREFIX_EVEX_MAP5_5B_W_1, PREFIX_EVEX_MAP5_5C, PREFIX_EVEX_MAP5_5D, PREFIX_EVEX_MAP5_5E, PREFIX_EVEX_MAP5_5F, PREFIX_EVEX_MAP5_78, PREFIX_EVEX_MAP5_79, PREFIX_EVEX_MAP5_7A, PREFIX_EVEX_MAP5_7B, PREFIX_EVEX_MAP5_7C, PREFIX_EVEX_MAP5_7D_W_0, PREFIX_EVEX_MAP6_13, PREFIX_EVEX_MAP6_56, PREFIX_EVEX_MAP6_57, PREFIX_EVEX_MAP6_D6, PREFIX_EVEX_MAP6_D7 (enum): Add EVEX_MAP5 and EVEX_MAP6. (enum): Add EVEX_W_MAP5_5A, EVEX_W_MAP5_5B, EVEX_W_MAP5_78_P_0, EVEX_W_MAP5_78_P_2, EVEX_W_MAP5_79_P_0, EVEX_W_MAP5_79_P_2, EVEX_W_MAP5_7A_P_2, EVEX_W_MAP5_7A_P_3, EVEX_W_MAP5_7B_P_2, EVEX_W_MAP5_7C_P_0, EVEX_W_MAP5_7C_P_2, EVEX_W_MAP5_7D, EVEX_W_MAP6_13_P_0, EVEX_W_MAP6_13_P_2, (get_valid_dis386): Properly handle new instructions. (intel_operand_size): Handle new modes. (OP_E_memory): Ditto. (OP_EX): Ditto. * i386-dis-evex.h: Updated for AVX512_FP16. * i386-dis-evex-mod.h: Updated for AVX512_FP16. * i386-dis-evex-prefix.h: Updated for AVX512_FP16. * i386-dis-evex-reg.h : Updated for AVX512_FP16. * i386-dis-evex-w.h : Updated for AVX512_FP16. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_FP16_FLAGS, and CPU_ANY_AVX512_FP16_FLAGS. Update CPU_ANY_AVX512F_FLAGS and CPU_ANY_AVX512BW_FLAGS. (cpu_flags): Add CpuAVX512_FP16. (opcode_modifiers): Add DistinctDest. * i386-opc.h (enum): (AVX512_FP16): New. (i386_opcode_modifier): Add reqdistinctreg. (i386_cpu_flags): Add cpuavx512_fp16. (EVEXMAP5): Defined as a macro. (EVEXMAP6): Ditto. * i386-opc.tbl: Add Intel AVX512_FP16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Ditto.
2021-06-14 11:05:05 +08:00
{ "vmovw", { Edw, XMScalar }, PREFIX_DATA },
{ Bad_Opcode },
/* 80 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 88 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 90 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 98 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* A0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* A8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* B0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* B8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* C0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* C8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* D0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* D8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* E0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* E8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* F0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* F8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
},
/* EVEX_MAP6_ */
{
/* 00 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 08 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 10 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ PREFIX_TABLE (PREFIX_EVEX_MAP6_13) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 18 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 20 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 28 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ "vscalefp%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
x86: consistently use scalar_mode for AVX512-FP16 scalar insns For some reason the original AVFX512F insns were not taken as a basis here, causing unnecessary divergence. While not an active issue, it is still relevant to note that OP_XMM() has special treatment of e.g. scalar_mode (marking broadcast as invalid). Such would better be consistent for all sufficiently similar insns.
2022-01-14 17:55:42 +08:00
{ "vscalefs%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
[PATCH 1/2] Enable Intel AVX512_FP16 instructions Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32 in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx). There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8 operands predated our current conventions; those instructions moved to map 3. FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3 is very sparsely populated. Most of the FP16 instructions share opcodes and prefix (EVEX.pp) bits with the related FP32 operations. Intel AVX512 FP16 instructions has new displacements scaling rules, please refer to the public software developer manual for detail information. gas/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (struct Broadcast_Operation): Adjust comment. (cpu_arch): Add .avx512_fp16. (cpu_noarch): Add noavx512_fp16. (pte): Add evexmap5 and evexmap6. (build_evex_prefix): Handle EVEXMAP5 and EVEXMAP6. (check_VecOperations): Handle {1to32}. (check_VecOperands): Handle CheckRegNumb. (check_word_reg): Handle Toqword. (i386_error): Add invalid_dest_and_src_register_set. (match_template): Handle invalid_dest_and_src_register_set. * doc/c-i386.texi: Document avx512_fp16, noavx512_fp16. opcodes/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (EXwScalarS): New. (EXxh): Ditto. (EXxhc): Ditto. (EXxmmqh): Ditto. (EXxmmqdh): Ditto. (EXEvexXwb): Ditto. (DistinctDest_Fixup): Ditto. (enum): Add xh_mode, evex_half_bcst_xmmqh_mode, evex_half_bcst_xmmqdh_mode and w_swap_mode. (enum): Add PREFIX_EVEX_0F3A08_W_0, PREFIX_EVEX_0F3A0A_W_0, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3AC2, PREFIX_EVEX_MAP5_10, PREFIX_EVEX_MAP5_11, PREFIX_EVEX_MAP5_1D, PREFIX_EVEX_MAP5_2A, PREFIX_EVEX_MAP5_2C, PREFIX_EVEX_MAP5_2D, PREFIX_EVEX_MAP5_2E, PREFIX_EVEX_MAP5_2F, PREFIX_EVEX_MAP5_51, PREFIX_EVEX_MAP5_58, PREFIX_EVEX_MAP5_59, PREFIX_EVEX_MAP5_5A_W_0, PREFIX_EVEX_MAP5_5A_W_1, PREFIX_EVEX_MAP5_5B_W_0, PREFIX_EVEX_MAP5_5B_W_1, PREFIX_EVEX_MAP5_5C, PREFIX_EVEX_MAP5_5D, PREFIX_EVEX_MAP5_5E, PREFIX_EVEX_MAP5_5F, PREFIX_EVEX_MAP5_78, PREFIX_EVEX_MAP5_79, PREFIX_EVEX_MAP5_7A, PREFIX_EVEX_MAP5_7B, PREFIX_EVEX_MAP5_7C, PREFIX_EVEX_MAP5_7D_W_0, PREFIX_EVEX_MAP6_13, PREFIX_EVEX_MAP6_56, PREFIX_EVEX_MAP6_57, PREFIX_EVEX_MAP6_D6, PREFIX_EVEX_MAP6_D7 (enum): Add EVEX_MAP5 and EVEX_MAP6. (enum): Add EVEX_W_MAP5_5A, EVEX_W_MAP5_5B, EVEX_W_MAP5_78_P_0, EVEX_W_MAP5_78_P_2, EVEX_W_MAP5_79_P_0, EVEX_W_MAP5_79_P_2, EVEX_W_MAP5_7A_P_2, EVEX_W_MAP5_7A_P_3, EVEX_W_MAP5_7B_P_2, EVEX_W_MAP5_7C_P_0, EVEX_W_MAP5_7C_P_2, EVEX_W_MAP5_7D, EVEX_W_MAP6_13_P_0, EVEX_W_MAP6_13_P_2, (get_valid_dis386): Properly handle new instructions. (intel_operand_size): Handle new modes. (OP_E_memory): Ditto. (OP_EX): Ditto. * i386-dis-evex.h: Updated for AVX512_FP16. * i386-dis-evex-mod.h: Updated for AVX512_FP16. * i386-dis-evex-prefix.h: Updated for AVX512_FP16. * i386-dis-evex-reg.h : Updated for AVX512_FP16. * i386-dis-evex-w.h : Updated for AVX512_FP16. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_FP16_FLAGS, and CPU_ANY_AVX512_FP16_FLAGS. Update CPU_ANY_AVX512F_FLAGS and CPU_ANY_AVX512BW_FLAGS. (cpu_flags): Add CpuAVX512_FP16. (opcode_modifiers): Add DistinctDest. * i386-opc.h (enum): (AVX512_FP16): New. (i386_opcode_modifier): Add reqdistinctreg. (i386_cpu_flags): Add cpuavx512_fp16. (EVEXMAP5): Defined as a macro. (EVEXMAP6): Ditto. * i386-opc.tbl: Add Intel AVX512_FP16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Ditto.
2021-06-14 11:05:05 +08:00
{ Bad_Opcode },
{ Bad_Opcode },
/* 30 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 38 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 40 */
{ Bad_Opcode },
{ Bad_Opcode },
{ "vgetexpp%XH", { XM, EXxh, EXxEVexS }, PREFIX_DATA },
x86: consistently use scalar_mode for AVX512-FP16 scalar insns For some reason the original AVFX512F insns were not taken as a basis here, causing unnecessary divergence. While not an active issue, it is still relevant to note that OP_XMM() has special treatment of e.g. scalar_mode (marking broadcast as invalid). Such would better be consistent for all sufficiently similar insns.
2022-01-14 17:55:42 +08:00
{ "vgetexps%XH", { XMScalar, VexScalar, EXw, EXxEVexS }, PREFIX_DATA },
[PATCH 1/2] Enable Intel AVX512_FP16 instructions Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32 in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx). There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8 operands predated our current conventions; those instructions moved to map 3. FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3 is very sparsely populated. Most of the FP16 instructions share opcodes and prefix (EVEX.pp) bits with the related FP32 operations. Intel AVX512 FP16 instructions has new displacements scaling rules, please refer to the public software developer manual for detail information. gas/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (struct Broadcast_Operation): Adjust comment. (cpu_arch): Add .avx512_fp16. (cpu_noarch): Add noavx512_fp16. (pte): Add evexmap5 and evexmap6. (build_evex_prefix): Handle EVEXMAP5 and EVEXMAP6. (check_VecOperations): Handle {1to32}. (check_VecOperands): Handle CheckRegNumb. (check_word_reg): Handle Toqword. (i386_error): Add invalid_dest_and_src_register_set. (match_template): Handle invalid_dest_and_src_register_set. * doc/c-i386.texi: Document avx512_fp16, noavx512_fp16. opcodes/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (EXwScalarS): New. (EXxh): Ditto. (EXxhc): Ditto. (EXxmmqh): Ditto. (EXxmmqdh): Ditto. (EXEvexXwb): Ditto. (DistinctDest_Fixup): Ditto. (enum): Add xh_mode, evex_half_bcst_xmmqh_mode, evex_half_bcst_xmmqdh_mode and w_swap_mode. (enum): Add PREFIX_EVEX_0F3A08_W_0, PREFIX_EVEX_0F3A0A_W_0, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3AC2, PREFIX_EVEX_MAP5_10, PREFIX_EVEX_MAP5_11, PREFIX_EVEX_MAP5_1D, PREFIX_EVEX_MAP5_2A, PREFIX_EVEX_MAP5_2C, PREFIX_EVEX_MAP5_2D, PREFIX_EVEX_MAP5_2E, PREFIX_EVEX_MAP5_2F, PREFIX_EVEX_MAP5_51, PREFIX_EVEX_MAP5_58, PREFIX_EVEX_MAP5_59, PREFIX_EVEX_MAP5_5A_W_0, PREFIX_EVEX_MAP5_5A_W_1, PREFIX_EVEX_MAP5_5B_W_0, PREFIX_EVEX_MAP5_5B_W_1, PREFIX_EVEX_MAP5_5C, PREFIX_EVEX_MAP5_5D, PREFIX_EVEX_MAP5_5E, PREFIX_EVEX_MAP5_5F, PREFIX_EVEX_MAP5_78, PREFIX_EVEX_MAP5_79, PREFIX_EVEX_MAP5_7A, PREFIX_EVEX_MAP5_7B, PREFIX_EVEX_MAP5_7C, PREFIX_EVEX_MAP5_7D_W_0, PREFIX_EVEX_MAP6_13, PREFIX_EVEX_MAP6_56, PREFIX_EVEX_MAP6_57, PREFIX_EVEX_MAP6_D6, PREFIX_EVEX_MAP6_D7 (enum): Add EVEX_MAP5 and EVEX_MAP6. (enum): Add EVEX_W_MAP5_5A, EVEX_W_MAP5_5B, EVEX_W_MAP5_78_P_0, EVEX_W_MAP5_78_P_2, EVEX_W_MAP5_79_P_0, EVEX_W_MAP5_79_P_2, EVEX_W_MAP5_7A_P_2, EVEX_W_MAP5_7A_P_3, EVEX_W_MAP5_7B_P_2, EVEX_W_MAP5_7C_P_0, EVEX_W_MAP5_7C_P_2, EVEX_W_MAP5_7D, EVEX_W_MAP6_13_P_0, EVEX_W_MAP6_13_P_2, (get_valid_dis386): Properly handle new instructions. (intel_operand_size): Handle new modes. (OP_E_memory): Ditto. (OP_EX): Ditto. * i386-dis-evex.h: Updated for AVX512_FP16. * i386-dis-evex-mod.h: Updated for AVX512_FP16. * i386-dis-evex-prefix.h: Updated for AVX512_FP16. * i386-dis-evex-reg.h : Updated for AVX512_FP16. * i386-dis-evex-w.h : Updated for AVX512_FP16. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_FP16_FLAGS, and CPU_ANY_AVX512_FP16_FLAGS. Update CPU_ANY_AVX512F_FLAGS and CPU_ANY_AVX512BW_FLAGS. (cpu_flags): Add CpuAVX512_FP16. (opcode_modifiers): Add DistinctDest. * i386-opc.h (enum): (AVX512_FP16): New. (i386_opcode_modifier): Add reqdistinctreg. (i386_cpu_flags): Add cpuavx512_fp16. (EVEXMAP5): Defined as a macro. (EVEXMAP6): Ditto. * i386-opc.tbl: Add Intel AVX512_FP16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Ditto.
2021-06-14 11:05:05 +08:00
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 48 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ "vrcpp%XH", { XM, EXxh }, PREFIX_DATA },
x86: consistently use scalar_mode for AVX512-FP16 scalar insns For some reason the original AVFX512F insns were not taken as a basis here, causing unnecessary divergence. While not an active issue, it is still relevant to note that OP_XMM() has special treatment of e.g. scalar_mode (marking broadcast as invalid). Such would better be consistent for all sufficiently similar insns.
2022-01-14 17:55:42 +08:00
{ "vrcps%XH", { XMScalar, VexScalar, EXw }, PREFIX_DATA },
[PATCH 1/2] Enable Intel AVX512_FP16 instructions Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32 in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx). There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8 operands predated our current conventions; those instructions moved to map 3. FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3 is very sparsely populated. Most of the FP16 instructions share opcodes and prefix (EVEX.pp) bits with the related FP32 operations. Intel AVX512 FP16 instructions has new displacements scaling rules, please refer to the public software developer manual for detail information. gas/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (struct Broadcast_Operation): Adjust comment. (cpu_arch): Add .avx512_fp16. (cpu_noarch): Add noavx512_fp16. (pte): Add evexmap5 and evexmap6. (build_evex_prefix): Handle EVEXMAP5 and EVEXMAP6. (check_VecOperations): Handle {1to32}. (check_VecOperands): Handle CheckRegNumb. (check_word_reg): Handle Toqword. (i386_error): Add invalid_dest_and_src_register_set. (match_template): Handle invalid_dest_and_src_register_set. * doc/c-i386.texi: Document avx512_fp16, noavx512_fp16. opcodes/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (EXwScalarS): New. (EXxh): Ditto. (EXxhc): Ditto. (EXxmmqh): Ditto. (EXxmmqdh): Ditto. (EXEvexXwb): Ditto. (DistinctDest_Fixup): Ditto. (enum): Add xh_mode, evex_half_bcst_xmmqh_mode, evex_half_bcst_xmmqdh_mode and w_swap_mode. (enum): Add PREFIX_EVEX_0F3A08_W_0, PREFIX_EVEX_0F3A0A_W_0, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3AC2, PREFIX_EVEX_MAP5_10, PREFIX_EVEX_MAP5_11, PREFIX_EVEX_MAP5_1D, PREFIX_EVEX_MAP5_2A, PREFIX_EVEX_MAP5_2C, PREFIX_EVEX_MAP5_2D, PREFIX_EVEX_MAP5_2E, PREFIX_EVEX_MAP5_2F, PREFIX_EVEX_MAP5_51, PREFIX_EVEX_MAP5_58, PREFIX_EVEX_MAP5_59, PREFIX_EVEX_MAP5_5A_W_0, PREFIX_EVEX_MAP5_5A_W_1, PREFIX_EVEX_MAP5_5B_W_0, PREFIX_EVEX_MAP5_5B_W_1, PREFIX_EVEX_MAP5_5C, PREFIX_EVEX_MAP5_5D, PREFIX_EVEX_MAP5_5E, PREFIX_EVEX_MAP5_5F, PREFIX_EVEX_MAP5_78, PREFIX_EVEX_MAP5_79, PREFIX_EVEX_MAP5_7A, PREFIX_EVEX_MAP5_7B, PREFIX_EVEX_MAP5_7C, PREFIX_EVEX_MAP5_7D_W_0, PREFIX_EVEX_MAP6_13, PREFIX_EVEX_MAP6_56, PREFIX_EVEX_MAP6_57, PREFIX_EVEX_MAP6_D6, PREFIX_EVEX_MAP6_D7 (enum): Add EVEX_MAP5 and EVEX_MAP6. (enum): Add EVEX_W_MAP5_5A, EVEX_W_MAP5_5B, EVEX_W_MAP5_78_P_0, EVEX_W_MAP5_78_P_2, EVEX_W_MAP5_79_P_0, EVEX_W_MAP5_79_P_2, EVEX_W_MAP5_7A_P_2, EVEX_W_MAP5_7A_P_3, EVEX_W_MAP5_7B_P_2, EVEX_W_MAP5_7C_P_0, EVEX_W_MAP5_7C_P_2, EVEX_W_MAP5_7D, EVEX_W_MAP6_13_P_0, EVEX_W_MAP6_13_P_2, (get_valid_dis386): Properly handle new instructions. (intel_operand_size): Handle new modes. (OP_E_memory): Ditto. (OP_EX): Ditto. * i386-dis-evex.h: Updated for AVX512_FP16. * i386-dis-evex-mod.h: Updated for AVX512_FP16. * i386-dis-evex-prefix.h: Updated for AVX512_FP16. * i386-dis-evex-reg.h : Updated for AVX512_FP16. * i386-dis-evex-w.h : Updated for AVX512_FP16. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_FP16_FLAGS, and CPU_ANY_AVX512_FP16_FLAGS. Update CPU_ANY_AVX512F_FLAGS and CPU_ANY_AVX512BW_FLAGS. (cpu_flags): Add CpuAVX512_FP16. (opcode_modifiers): Add DistinctDest. * i386-opc.h (enum): (AVX512_FP16): New. (i386_opcode_modifier): Add reqdistinctreg. (i386_cpu_flags): Add cpuavx512_fp16. (EVEXMAP5): Defined as a macro. (EVEXMAP6): Ditto. * i386-opc.tbl: Add Intel AVX512_FP16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Ditto.
2021-06-14 11:05:05 +08:00
{ "vrsqrtp%XH", { XM, EXxh }, PREFIX_DATA },
x86: consistently use scalar_mode for AVX512-FP16 scalar insns For some reason the original AVFX512F insns were not taken as a basis here, causing unnecessary divergence. While not an active issue, it is still relevant to note that OP_XMM() has special treatment of e.g. scalar_mode (marking broadcast as invalid). Such would better be consistent for all sufficiently similar insns.
2022-01-14 17:55:42 +08:00
{ "vrsqrts%XH", { XMScalar, VexScalar, EXw }, PREFIX_DATA },
[PATCH 1/2] Enable Intel AVX512_FP16 instructions Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32 in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx). There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8 operands predated our current conventions; those instructions moved to map 3. FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3 is very sparsely populated. Most of the FP16 instructions share opcodes and prefix (EVEX.pp) bits with the related FP32 operations. Intel AVX512 FP16 instructions has new displacements scaling rules, please refer to the public software developer manual for detail information. gas/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (struct Broadcast_Operation): Adjust comment. (cpu_arch): Add .avx512_fp16. (cpu_noarch): Add noavx512_fp16. (pte): Add evexmap5 and evexmap6. (build_evex_prefix): Handle EVEXMAP5 and EVEXMAP6. (check_VecOperations): Handle {1to32}. (check_VecOperands): Handle CheckRegNumb. (check_word_reg): Handle Toqword. (i386_error): Add invalid_dest_and_src_register_set. (match_template): Handle invalid_dest_and_src_register_set. * doc/c-i386.texi: Document avx512_fp16, noavx512_fp16. opcodes/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (EXwScalarS): New. (EXxh): Ditto. (EXxhc): Ditto. (EXxmmqh): Ditto. (EXxmmqdh): Ditto. (EXEvexXwb): Ditto. (DistinctDest_Fixup): Ditto. (enum): Add xh_mode, evex_half_bcst_xmmqh_mode, evex_half_bcst_xmmqdh_mode and w_swap_mode. (enum): Add PREFIX_EVEX_0F3A08_W_0, PREFIX_EVEX_0F3A0A_W_0, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3AC2, PREFIX_EVEX_MAP5_10, PREFIX_EVEX_MAP5_11, PREFIX_EVEX_MAP5_1D, PREFIX_EVEX_MAP5_2A, PREFIX_EVEX_MAP5_2C, PREFIX_EVEX_MAP5_2D, PREFIX_EVEX_MAP5_2E, PREFIX_EVEX_MAP5_2F, PREFIX_EVEX_MAP5_51, PREFIX_EVEX_MAP5_58, PREFIX_EVEX_MAP5_59, PREFIX_EVEX_MAP5_5A_W_0, PREFIX_EVEX_MAP5_5A_W_1, PREFIX_EVEX_MAP5_5B_W_0, PREFIX_EVEX_MAP5_5B_W_1, PREFIX_EVEX_MAP5_5C, PREFIX_EVEX_MAP5_5D, PREFIX_EVEX_MAP5_5E, PREFIX_EVEX_MAP5_5F, PREFIX_EVEX_MAP5_78, PREFIX_EVEX_MAP5_79, PREFIX_EVEX_MAP5_7A, PREFIX_EVEX_MAP5_7B, PREFIX_EVEX_MAP5_7C, PREFIX_EVEX_MAP5_7D_W_0, PREFIX_EVEX_MAP6_13, PREFIX_EVEX_MAP6_56, PREFIX_EVEX_MAP6_57, PREFIX_EVEX_MAP6_D6, PREFIX_EVEX_MAP6_D7 (enum): Add EVEX_MAP5 and EVEX_MAP6. (enum): Add EVEX_W_MAP5_5A, EVEX_W_MAP5_5B, EVEX_W_MAP5_78_P_0, EVEX_W_MAP5_78_P_2, EVEX_W_MAP5_79_P_0, EVEX_W_MAP5_79_P_2, EVEX_W_MAP5_7A_P_2, EVEX_W_MAP5_7A_P_3, EVEX_W_MAP5_7B_P_2, EVEX_W_MAP5_7C_P_0, EVEX_W_MAP5_7C_P_2, EVEX_W_MAP5_7D, EVEX_W_MAP6_13_P_0, EVEX_W_MAP6_13_P_2, (get_valid_dis386): Properly handle new instructions. (intel_operand_size): Handle new modes. (OP_E_memory): Ditto. (OP_EX): Ditto. * i386-dis-evex.h: Updated for AVX512_FP16. * i386-dis-evex-mod.h: Updated for AVX512_FP16. * i386-dis-evex-prefix.h: Updated for AVX512_FP16. * i386-dis-evex-reg.h : Updated for AVX512_FP16. * i386-dis-evex-w.h : Updated for AVX512_FP16. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_FP16_FLAGS, and CPU_ANY_AVX512_FP16_FLAGS. Update CPU_ANY_AVX512F_FLAGS and CPU_ANY_AVX512BW_FLAGS. (cpu_flags): Add CpuAVX512_FP16. (opcode_modifiers): Add DistinctDest. * i386-opc.h (enum): (AVX512_FP16): New. (i386_opcode_modifier): Add reqdistinctreg. (i386_cpu_flags): Add cpuavx512_fp16. (EVEXMAP5): Defined as a macro. (EVEXMAP6): Ditto. * i386-opc.tbl: Add Intel AVX512_FP16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Ditto.
2021-06-14 11:05:05 +08:00
/* 50 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ PREFIX_TABLE (PREFIX_EVEX_MAP6_56) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP6_57) },
/* 58 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 60 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 68 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 70 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 78 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 80 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 88 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 90 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ "vfmaddsub132p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
{ "vfmsubadd132p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
/* 98 */
{ "vfmadd132p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
x86: consistently use scalar_mode for AVX512-FP16 scalar insns For some reason the original AVFX512F insns were not taken as a basis here, causing unnecessary divergence. While not an active issue, it is still relevant to note that OP_XMM() has special treatment of e.g. scalar_mode (marking broadcast as invalid). Such would better be consistent for all sufficiently similar insns.
2022-01-14 17:55:42 +08:00
{ "vfmadd132s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
[PATCH 1/2] Enable Intel AVX512_FP16 instructions Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32 in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx). There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8 operands predated our current conventions; those instructions moved to map 3. FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3 is very sparsely populated. Most of the FP16 instructions share opcodes and prefix (EVEX.pp) bits with the related FP32 operations. Intel AVX512 FP16 instructions has new displacements scaling rules, please refer to the public software developer manual for detail information. gas/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (struct Broadcast_Operation): Adjust comment. (cpu_arch): Add .avx512_fp16. (cpu_noarch): Add noavx512_fp16. (pte): Add evexmap5 and evexmap6. (build_evex_prefix): Handle EVEXMAP5 and EVEXMAP6. (check_VecOperations): Handle {1to32}. (check_VecOperands): Handle CheckRegNumb. (check_word_reg): Handle Toqword. (i386_error): Add invalid_dest_and_src_register_set. (match_template): Handle invalid_dest_and_src_register_set. * doc/c-i386.texi: Document avx512_fp16, noavx512_fp16. opcodes/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (EXwScalarS): New. (EXxh): Ditto. (EXxhc): Ditto. (EXxmmqh): Ditto. (EXxmmqdh): Ditto. (EXEvexXwb): Ditto. (DistinctDest_Fixup): Ditto. (enum): Add xh_mode, evex_half_bcst_xmmqh_mode, evex_half_bcst_xmmqdh_mode and w_swap_mode. (enum): Add PREFIX_EVEX_0F3A08_W_0, PREFIX_EVEX_0F3A0A_W_0, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3AC2, PREFIX_EVEX_MAP5_10, PREFIX_EVEX_MAP5_11, PREFIX_EVEX_MAP5_1D, PREFIX_EVEX_MAP5_2A, PREFIX_EVEX_MAP5_2C, PREFIX_EVEX_MAP5_2D, PREFIX_EVEX_MAP5_2E, PREFIX_EVEX_MAP5_2F, PREFIX_EVEX_MAP5_51, PREFIX_EVEX_MAP5_58, PREFIX_EVEX_MAP5_59, PREFIX_EVEX_MAP5_5A_W_0, PREFIX_EVEX_MAP5_5A_W_1, PREFIX_EVEX_MAP5_5B_W_0, PREFIX_EVEX_MAP5_5B_W_1, PREFIX_EVEX_MAP5_5C, PREFIX_EVEX_MAP5_5D, PREFIX_EVEX_MAP5_5E, PREFIX_EVEX_MAP5_5F, PREFIX_EVEX_MAP5_78, PREFIX_EVEX_MAP5_79, PREFIX_EVEX_MAP5_7A, PREFIX_EVEX_MAP5_7B, PREFIX_EVEX_MAP5_7C, PREFIX_EVEX_MAP5_7D_W_0, PREFIX_EVEX_MAP6_13, PREFIX_EVEX_MAP6_56, PREFIX_EVEX_MAP6_57, PREFIX_EVEX_MAP6_D6, PREFIX_EVEX_MAP6_D7 (enum): Add EVEX_MAP5 and EVEX_MAP6. (enum): Add EVEX_W_MAP5_5A, EVEX_W_MAP5_5B, EVEX_W_MAP5_78_P_0, EVEX_W_MAP5_78_P_2, EVEX_W_MAP5_79_P_0, EVEX_W_MAP5_79_P_2, EVEX_W_MAP5_7A_P_2, EVEX_W_MAP5_7A_P_3, EVEX_W_MAP5_7B_P_2, EVEX_W_MAP5_7C_P_0, EVEX_W_MAP5_7C_P_2, EVEX_W_MAP5_7D, EVEX_W_MAP6_13_P_0, EVEX_W_MAP6_13_P_2, (get_valid_dis386): Properly handle new instructions. (intel_operand_size): Handle new modes. (OP_E_memory): Ditto. (OP_EX): Ditto. * i386-dis-evex.h: Updated for AVX512_FP16. * i386-dis-evex-mod.h: Updated for AVX512_FP16. * i386-dis-evex-prefix.h: Updated for AVX512_FP16. * i386-dis-evex-reg.h : Updated for AVX512_FP16. * i386-dis-evex-w.h : Updated for AVX512_FP16. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_FP16_FLAGS, and CPU_ANY_AVX512_FP16_FLAGS. Update CPU_ANY_AVX512F_FLAGS and CPU_ANY_AVX512BW_FLAGS. (cpu_flags): Add CpuAVX512_FP16. (opcode_modifiers): Add DistinctDest. * i386-opc.h (enum): (AVX512_FP16): New. (i386_opcode_modifier): Add reqdistinctreg. (i386_cpu_flags): Add cpuavx512_fp16. (EVEXMAP5): Defined as a macro. (EVEXMAP6): Ditto. * i386-opc.tbl: Add Intel AVX512_FP16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Ditto.
2021-06-14 11:05:05 +08:00
{ "vfmsub132p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
x86: consistently use scalar_mode for AVX512-FP16 scalar insns For some reason the original AVFX512F insns were not taken as a basis here, causing unnecessary divergence. While not an active issue, it is still relevant to note that OP_XMM() has special treatment of e.g. scalar_mode (marking broadcast as invalid). Such would better be consistent for all sufficiently similar insns.
2022-01-14 17:55:42 +08:00
{ "vfmsub132s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
[PATCH 1/2] Enable Intel AVX512_FP16 instructions Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32 in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx). There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8 operands predated our current conventions; those instructions moved to map 3. FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3 is very sparsely populated. Most of the FP16 instructions share opcodes and prefix (EVEX.pp) bits with the related FP32 operations. Intel AVX512 FP16 instructions has new displacements scaling rules, please refer to the public software developer manual for detail information. gas/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (struct Broadcast_Operation): Adjust comment. (cpu_arch): Add .avx512_fp16. (cpu_noarch): Add noavx512_fp16. (pte): Add evexmap5 and evexmap6. (build_evex_prefix): Handle EVEXMAP5 and EVEXMAP6. (check_VecOperations): Handle {1to32}. (check_VecOperands): Handle CheckRegNumb. (check_word_reg): Handle Toqword. (i386_error): Add invalid_dest_and_src_register_set. (match_template): Handle invalid_dest_and_src_register_set. * doc/c-i386.texi: Document avx512_fp16, noavx512_fp16. opcodes/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (EXwScalarS): New. (EXxh): Ditto. (EXxhc): Ditto. (EXxmmqh): Ditto. (EXxmmqdh): Ditto. (EXEvexXwb): Ditto. (DistinctDest_Fixup): Ditto. (enum): Add xh_mode, evex_half_bcst_xmmqh_mode, evex_half_bcst_xmmqdh_mode and w_swap_mode. (enum): Add PREFIX_EVEX_0F3A08_W_0, PREFIX_EVEX_0F3A0A_W_0, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3AC2, PREFIX_EVEX_MAP5_10, PREFIX_EVEX_MAP5_11, PREFIX_EVEX_MAP5_1D, PREFIX_EVEX_MAP5_2A, PREFIX_EVEX_MAP5_2C, PREFIX_EVEX_MAP5_2D, PREFIX_EVEX_MAP5_2E, PREFIX_EVEX_MAP5_2F, PREFIX_EVEX_MAP5_51, PREFIX_EVEX_MAP5_58, PREFIX_EVEX_MAP5_59, PREFIX_EVEX_MAP5_5A_W_0, PREFIX_EVEX_MAP5_5A_W_1, PREFIX_EVEX_MAP5_5B_W_0, PREFIX_EVEX_MAP5_5B_W_1, PREFIX_EVEX_MAP5_5C, PREFIX_EVEX_MAP5_5D, PREFIX_EVEX_MAP5_5E, PREFIX_EVEX_MAP5_5F, PREFIX_EVEX_MAP5_78, PREFIX_EVEX_MAP5_79, PREFIX_EVEX_MAP5_7A, PREFIX_EVEX_MAP5_7B, PREFIX_EVEX_MAP5_7C, PREFIX_EVEX_MAP5_7D_W_0, PREFIX_EVEX_MAP6_13, PREFIX_EVEX_MAP6_56, PREFIX_EVEX_MAP6_57, PREFIX_EVEX_MAP6_D6, PREFIX_EVEX_MAP6_D7 (enum): Add EVEX_MAP5 and EVEX_MAP6. (enum): Add EVEX_W_MAP5_5A, EVEX_W_MAP5_5B, EVEX_W_MAP5_78_P_0, EVEX_W_MAP5_78_P_2, EVEX_W_MAP5_79_P_0, EVEX_W_MAP5_79_P_2, EVEX_W_MAP5_7A_P_2, EVEX_W_MAP5_7A_P_3, EVEX_W_MAP5_7B_P_2, EVEX_W_MAP5_7C_P_0, EVEX_W_MAP5_7C_P_2, EVEX_W_MAP5_7D, EVEX_W_MAP6_13_P_0, EVEX_W_MAP6_13_P_2, (get_valid_dis386): Properly handle new instructions. (intel_operand_size): Handle new modes. (OP_E_memory): Ditto. (OP_EX): Ditto. * i386-dis-evex.h: Updated for AVX512_FP16. * i386-dis-evex-mod.h: Updated for AVX512_FP16. * i386-dis-evex-prefix.h: Updated for AVX512_FP16. * i386-dis-evex-reg.h : Updated for AVX512_FP16. * i386-dis-evex-w.h : Updated for AVX512_FP16. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_FP16_FLAGS, and CPU_ANY_AVX512_FP16_FLAGS. Update CPU_ANY_AVX512F_FLAGS and CPU_ANY_AVX512BW_FLAGS. (cpu_flags): Add CpuAVX512_FP16. (opcode_modifiers): Add DistinctDest. * i386-opc.h (enum): (AVX512_FP16): New. (i386_opcode_modifier): Add reqdistinctreg. (i386_cpu_flags): Add cpuavx512_fp16. (EVEXMAP5): Defined as a macro. (EVEXMAP6): Ditto. * i386-opc.tbl: Add Intel AVX512_FP16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Ditto.
2021-06-14 11:05:05 +08:00
{ "vfnmadd132p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
x86: consistently use scalar_mode for AVX512-FP16 scalar insns For some reason the original AVFX512F insns were not taken as a basis here, causing unnecessary divergence. While not an active issue, it is still relevant to note that OP_XMM() has special treatment of e.g. scalar_mode (marking broadcast as invalid). Such would better be consistent for all sufficiently similar insns.
2022-01-14 17:55:42 +08:00
{ "vfnmadd132s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
[PATCH 1/2] Enable Intel AVX512_FP16 instructions Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32 in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx). There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8 operands predated our current conventions; those instructions moved to map 3. FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3 is very sparsely populated. Most of the FP16 instructions share opcodes and prefix (EVEX.pp) bits with the related FP32 operations. Intel AVX512 FP16 instructions has new displacements scaling rules, please refer to the public software developer manual for detail information. gas/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (struct Broadcast_Operation): Adjust comment. (cpu_arch): Add .avx512_fp16. (cpu_noarch): Add noavx512_fp16. (pte): Add evexmap5 and evexmap6. (build_evex_prefix): Handle EVEXMAP5 and EVEXMAP6. (check_VecOperations): Handle {1to32}. (check_VecOperands): Handle CheckRegNumb. (check_word_reg): Handle Toqword. (i386_error): Add invalid_dest_and_src_register_set. (match_template): Handle invalid_dest_and_src_register_set. * doc/c-i386.texi: Document avx512_fp16, noavx512_fp16. opcodes/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (EXwScalarS): New. (EXxh): Ditto. (EXxhc): Ditto. (EXxmmqh): Ditto. (EXxmmqdh): Ditto. (EXEvexXwb): Ditto. (DistinctDest_Fixup): Ditto. (enum): Add xh_mode, evex_half_bcst_xmmqh_mode, evex_half_bcst_xmmqdh_mode and w_swap_mode. (enum): Add PREFIX_EVEX_0F3A08_W_0, PREFIX_EVEX_0F3A0A_W_0, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3AC2, PREFIX_EVEX_MAP5_10, PREFIX_EVEX_MAP5_11, PREFIX_EVEX_MAP5_1D, PREFIX_EVEX_MAP5_2A, PREFIX_EVEX_MAP5_2C, PREFIX_EVEX_MAP5_2D, PREFIX_EVEX_MAP5_2E, PREFIX_EVEX_MAP5_2F, PREFIX_EVEX_MAP5_51, PREFIX_EVEX_MAP5_58, PREFIX_EVEX_MAP5_59, PREFIX_EVEX_MAP5_5A_W_0, PREFIX_EVEX_MAP5_5A_W_1, PREFIX_EVEX_MAP5_5B_W_0, PREFIX_EVEX_MAP5_5B_W_1, PREFIX_EVEX_MAP5_5C, PREFIX_EVEX_MAP5_5D, PREFIX_EVEX_MAP5_5E, PREFIX_EVEX_MAP5_5F, PREFIX_EVEX_MAP5_78, PREFIX_EVEX_MAP5_79, PREFIX_EVEX_MAP5_7A, PREFIX_EVEX_MAP5_7B, PREFIX_EVEX_MAP5_7C, PREFIX_EVEX_MAP5_7D_W_0, PREFIX_EVEX_MAP6_13, PREFIX_EVEX_MAP6_56, PREFIX_EVEX_MAP6_57, PREFIX_EVEX_MAP6_D6, PREFIX_EVEX_MAP6_D7 (enum): Add EVEX_MAP5 and EVEX_MAP6. (enum): Add EVEX_W_MAP5_5A, EVEX_W_MAP5_5B, EVEX_W_MAP5_78_P_0, EVEX_W_MAP5_78_P_2, EVEX_W_MAP5_79_P_0, EVEX_W_MAP5_79_P_2, EVEX_W_MAP5_7A_P_2, EVEX_W_MAP5_7A_P_3, EVEX_W_MAP5_7B_P_2, EVEX_W_MAP5_7C_P_0, EVEX_W_MAP5_7C_P_2, EVEX_W_MAP5_7D, EVEX_W_MAP6_13_P_0, EVEX_W_MAP6_13_P_2, (get_valid_dis386): Properly handle new instructions. (intel_operand_size): Handle new modes. (OP_E_memory): Ditto. (OP_EX): Ditto. * i386-dis-evex.h: Updated for AVX512_FP16. * i386-dis-evex-mod.h: Updated for AVX512_FP16. * i386-dis-evex-prefix.h: Updated for AVX512_FP16. * i386-dis-evex-reg.h : Updated for AVX512_FP16. * i386-dis-evex-w.h : Updated for AVX512_FP16. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_FP16_FLAGS, and CPU_ANY_AVX512_FP16_FLAGS. Update CPU_ANY_AVX512F_FLAGS and CPU_ANY_AVX512BW_FLAGS. (cpu_flags): Add CpuAVX512_FP16. (opcode_modifiers): Add DistinctDest. * i386-opc.h (enum): (AVX512_FP16): New. (i386_opcode_modifier): Add reqdistinctreg. (i386_cpu_flags): Add cpuavx512_fp16. (EVEXMAP5): Defined as a macro. (EVEXMAP6): Ditto. * i386-opc.tbl: Add Intel AVX512_FP16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Ditto.
2021-06-14 11:05:05 +08:00
{ "vfnmsub132p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
x86: consistently use scalar_mode for AVX512-FP16 scalar insns For some reason the original AVFX512F insns were not taken as a basis here, causing unnecessary divergence. While not an active issue, it is still relevant to note that OP_XMM() has special treatment of e.g. scalar_mode (marking broadcast as invalid). Such would better be consistent for all sufficiently similar insns.
2022-01-14 17:55:42 +08:00
{ "vfnmsub132s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
[PATCH 1/2] Enable Intel AVX512_FP16 instructions Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32 in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx). There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8 operands predated our current conventions; those instructions moved to map 3. FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3 is very sparsely populated. Most of the FP16 instructions share opcodes and prefix (EVEX.pp) bits with the related FP32 operations. Intel AVX512 FP16 instructions has new displacements scaling rules, please refer to the public software developer manual for detail information. gas/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (struct Broadcast_Operation): Adjust comment. (cpu_arch): Add .avx512_fp16. (cpu_noarch): Add noavx512_fp16. (pte): Add evexmap5 and evexmap6. (build_evex_prefix): Handle EVEXMAP5 and EVEXMAP6. (check_VecOperations): Handle {1to32}. (check_VecOperands): Handle CheckRegNumb. (check_word_reg): Handle Toqword. (i386_error): Add invalid_dest_and_src_register_set. (match_template): Handle invalid_dest_and_src_register_set. * doc/c-i386.texi: Document avx512_fp16, noavx512_fp16. opcodes/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (EXwScalarS): New. (EXxh): Ditto. (EXxhc): Ditto. (EXxmmqh): Ditto. (EXxmmqdh): Ditto. (EXEvexXwb): Ditto. (DistinctDest_Fixup): Ditto. (enum): Add xh_mode, evex_half_bcst_xmmqh_mode, evex_half_bcst_xmmqdh_mode and w_swap_mode. (enum): Add PREFIX_EVEX_0F3A08_W_0, PREFIX_EVEX_0F3A0A_W_0, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3AC2, PREFIX_EVEX_MAP5_10, PREFIX_EVEX_MAP5_11, PREFIX_EVEX_MAP5_1D, PREFIX_EVEX_MAP5_2A, PREFIX_EVEX_MAP5_2C, PREFIX_EVEX_MAP5_2D, PREFIX_EVEX_MAP5_2E, PREFIX_EVEX_MAP5_2F, PREFIX_EVEX_MAP5_51, PREFIX_EVEX_MAP5_58, PREFIX_EVEX_MAP5_59, PREFIX_EVEX_MAP5_5A_W_0, PREFIX_EVEX_MAP5_5A_W_1, PREFIX_EVEX_MAP5_5B_W_0, PREFIX_EVEX_MAP5_5B_W_1, PREFIX_EVEX_MAP5_5C, PREFIX_EVEX_MAP5_5D, PREFIX_EVEX_MAP5_5E, PREFIX_EVEX_MAP5_5F, PREFIX_EVEX_MAP5_78, PREFIX_EVEX_MAP5_79, PREFIX_EVEX_MAP5_7A, PREFIX_EVEX_MAP5_7B, PREFIX_EVEX_MAP5_7C, PREFIX_EVEX_MAP5_7D_W_0, PREFIX_EVEX_MAP6_13, PREFIX_EVEX_MAP6_56, PREFIX_EVEX_MAP6_57, PREFIX_EVEX_MAP6_D6, PREFIX_EVEX_MAP6_D7 (enum): Add EVEX_MAP5 and EVEX_MAP6. (enum): Add EVEX_W_MAP5_5A, EVEX_W_MAP5_5B, EVEX_W_MAP5_78_P_0, EVEX_W_MAP5_78_P_2, EVEX_W_MAP5_79_P_0, EVEX_W_MAP5_79_P_2, EVEX_W_MAP5_7A_P_2, EVEX_W_MAP5_7A_P_3, EVEX_W_MAP5_7B_P_2, EVEX_W_MAP5_7C_P_0, EVEX_W_MAP5_7C_P_2, EVEX_W_MAP5_7D, EVEX_W_MAP6_13_P_0, EVEX_W_MAP6_13_P_2, (get_valid_dis386): Properly handle new instructions. (intel_operand_size): Handle new modes. (OP_E_memory): Ditto. (OP_EX): Ditto. * i386-dis-evex.h: Updated for AVX512_FP16. * i386-dis-evex-mod.h: Updated for AVX512_FP16. * i386-dis-evex-prefix.h: Updated for AVX512_FP16. * i386-dis-evex-reg.h : Updated for AVX512_FP16. * i386-dis-evex-w.h : Updated for AVX512_FP16. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_FP16_FLAGS, and CPU_ANY_AVX512_FP16_FLAGS. Update CPU_ANY_AVX512F_FLAGS and CPU_ANY_AVX512BW_FLAGS. (cpu_flags): Add CpuAVX512_FP16. (opcode_modifiers): Add DistinctDest. * i386-opc.h (enum): (AVX512_FP16): New. (i386_opcode_modifier): Add reqdistinctreg. (i386_cpu_flags): Add cpuavx512_fp16. (EVEXMAP5): Defined as a macro. (EVEXMAP6): Ditto. * i386-opc.tbl: Add Intel AVX512_FP16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Ditto.
2021-06-14 11:05:05 +08:00
/* A0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ "vfmaddsub213p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
{ "vfmsubadd213p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
/* A8 */
{ "vfmadd213p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
x86: consistently use scalar_mode for AVX512-FP16 scalar insns For some reason the original AVFX512F insns were not taken as a basis here, causing unnecessary divergence. While not an active issue, it is still relevant to note that OP_XMM() has special treatment of e.g. scalar_mode (marking broadcast as invalid). Such would better be consistent for all sufficiently similar insns.
2022-01-14 17:55:42 +08:00
{ "vfmadd213s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
[PATCH 1/2] Enable Intel AVX512_FP16 instructions Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32 in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx). There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8 operands predated our current conventions; those instructions moved to map 3. FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3 is very sparsely populated. Most of the FP16 instructions share opcodes and prefix (EVEX.pp) bits with the related FP32 operations. Intel AVX512 FP16 instructions has new displacements scaling rules, please refer to the public software developer manual for detail information. gas/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (struct Broadcast_Operation): Adjust comment. (cpu_arch): Add .avx512_fp16. (cpu_noarch): Add noavx512_fp16. (pte): Add evexmap5 and evexmap6. (build_evex_prefix): Handle EVEXMAP5 and EVEXMAP6. (check_VecOperations): Handle {1to32}. (check_VecOperands): Handle CheckRegNumb. (check_word_reg): Handle Toqword. (i386_error): Add invalid_dest_and_src_register_set. (match_template): Handle invalid_dest_and_src_register_set. * doc/c-i386.texi: Document avx512_fp16, noavx512_fp16. opcodes/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (EXwScalarS): New. (EXxh): Ditto. (EXxhc): Ditto. (EXxmmqh): Ditto. (EXxmmqdh): Ditto. (EXEvexXwb): Ditto. (DistinctDest_Fixup): Ditto. (enum): Add xh_mode, evex_half_bcst_xmmqh_mode, evex_half_bcst_xmmqdh_mode and w_swap_mode. (enum): Add PREFIX_EVEX_0F3A08_W_0, PREFIX_EVEX_0F3A0A_W_0, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3AC2, PREFIX_EVEX_MAP5_10, PREFIX_EVEX_MAP5_11, PREFIX_EVEX_MAP5_1D, PREFIX_EVEX_MAP5_2A, PREFIX_EVEX_MAP5_2C, PREFIX_EVEX_MAP5_2D, PREFIX_EVEX_MAP5_2E, PREFIX_EVEX_MAP5_2F, PREFIX_EVEX_MAP5_51, PREFIX_EVEX_MAP5_58, PREFIX_EVEX_MAP5_59, PREFIX_EVEX_MAP5_5A_W_0, PREFIX_EVEX_MAP5_5A_W_1, PREFIX_EVEX_MAP5_5B_W_0, PREFIX_EVEX_MAP5_5B_W_1, PREFIX_EVEX_MAP5_5C, PREFIX_EVEX_MAP5_5D, PREFIX_EVEX_MAP5_5E, PREFIX_EVEX_MAP5_5F, PREFIX_EVEX_MAP5_78, PREFIX_EVEX_MAP5_79, PREFIX_EVEX_MAP5_7A, PREFIX_EVEX_MAP5_7B, PREFIX_EVEX_MAP5_7C, PREFIX_EVEX_MAP5_7D_W_0, PREFIX_EVEX_MAP6_13, PREFIX_EVEX_MAP6_56, PREFIX_EVEX_MAP6_57, PREFIX_EVEX_MAP6_D6, PREFIX_EVEX_MAP6_D7 (enum): Add EVEX_MAP5 and EVEX_MAP6. (enum): Add EVEX_W_MAP5_5A, EVEX_W_MAP5_5B, EVEX_W_MAP5_78_P_0, EVEX_W_MAP5_78_P_2, EVEX_W_MAP5_79_P_0, EVEX_W_MAP5_79_P_2, EVEX_W_MAP5_7A_P_2, EVEX_W_MAP5_7A_P_3, EVEX_W_MAP5_7B_P_2, EVEX_W_MAP5_7C_P_0, EVEX_W_MAP5_7C_P_2, EVEX_W_MAP5_7D, EVEX_W_MAP6_13_P_0, EVEX_W_MAP6_13_P_2, (get_valid_dis386): Properly handle new instructions. (intel_operand_size): Handle new modes. (OP_E_memory): Ditto. (OP_EX): Ditto. * i386-dis-evex.h: Updated for AVX512_FP16. * i386-dis-evex-mod.h: Updated for AVX512_FP16. * i386-dis-evex-prefix.h: Updated for AVX512_FP16. * i386-dis-evex-reg.h : Updated for AVX512_FP16. * i386-dis-evex-w.h : Updated for AVX512_FP16. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_FP16_FLAGS, and CPU_ANY_AVX512_FP16_FLAGS. Update CPU_ANY_AVX512F_FLAGS and CPU_ANY_AVX512BW_FLAGS. (cpu_flags): Add CpuAVX512_FP16. (opcode_modifiers): Add DistinctDest. * i386-opc.h (enum): (AVX512_FP16): New. (i386_opcode_modifier): Add reqdistinctreg. (i386_cpu_flags): Add cpuavx512_fp16. (EVEXMAP5): Defined as a macro. (EVEXMAP6): Ditto. * i386-opc.tbl: Add Intel AVX512_FP16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Ditto.
2021-06-14 11:05:05 +08:00
{ "vfmsub213p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
x86: consistently use scalar_mode for AVX512-FP16 scalar insns For some reason the original AVFX512F insns were not taken as a basis here, causing unnecessary divergence. While not an active issue, it is still relevant to note that OP_XMM() has special treatment of e.g. scalar_mode (marking broadcast as invalid). Such would better be consistent for all sufficiently similar insns.
2022-01-14 17:55:42 +08:00
{ "vfmsub213s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
[PATCH 1/2] Enable Intel AVX512_FP16 instructions Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32 in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx). There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8 operands predated our current conventions; those instructions moved to map 3. FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3 is very sparsely populated. Most of the FP16 instructions share opcodes and prefix (EVEX.pp) bits with the related FP32 operations. Intel AVX512 FP16 instructions has new displacements scaling rules, please refer to the public software developer manual for detail information. gas/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (struct Broadcast_Operation): Adjust comment. (cpu_arch): Add .avx512_fp16. (cpu_noarch): Add noavx512_fp16. (pte): Add evexmap5 and evexmap6. (build_evex_prefix): Handle EVEXMAP5 and EVEXMAP6. (check_VecOperations): Handle {1to32}. (check_VecOperands): Handle CheckRegNumb. (check_word_reg): Handle Toqword. (i386_error): Add invalid_dest_and_src_register_set. (match_template): Handle invalid_dest_and_src_register_set. * doc/c-i386.texi: Document avx512_fp16, noavx512_fp16. opcodes/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (EXwScalarS): New. (EXxh): Ditto. (EXxhc): Ditto. (EXxmmqh): Ditto. (EXxmmqdh): Ditto. (EXEvexXwb): Ditto. (DistinctDest_Fixup): Ditto. (enum): Add xh_mode, evex_half_bcst_xmmqh_mode, evex_half_bcst_xmmqdh_mode and w_swap_mode. (enum): Add PREFIX_EVEX_0F3A08_W_0, PREFIX_EVEX_0F3A0A_W_0, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3AC2, PREFIX_EVEX_MAP5_10, PREFIX_EVEX_MAP5_11, PREFIX_EVEX_MAP5_1D, PREFIX_EVEX_MAP5_2A, PREFIX_EVEX_MAP5_2C, PREFIX_EVEX_MAP5_2D, PREFIX_EVEX_MAP5_2E, PREFIX_EVEX_MAP5_2F, PREFIX_EVEX_MAP5_51, PREFIX_EVEX_MAP5_58, PREFIX_EVEX_MAP5_59, PREFIX_EVEX_MAP5_5A_W_0, PREFIX_EVEX_MAP5_5A_W_1, PREFIX_EVEX_MAP5_5B_W_0, PREFIX_EVEX_MAP5_5B_W_1, PREFIX_EVEX_MAP5_5C, PREFIX_EVEX_MAP5_5D, PREFIX_EVEX_MAP5_5E, PREFIX_EVEX_MAP5_5F, PREFIX_EVEX_MAP5_78, PREFIX_EVEX_MAP5_79, PREFIX_EVEX_MAP5_7A, PREFIX_EVEX_MAP5_7B, PREFIX_EVEX_MAP5_7C, PREFIX_EVEX_MAP5_7D_W_0, PREFIX_EVEX_MAP6_13, PREFIX_EVEX_MAP6_56, PREFIX_EVEX_MAP6_57, PREFIX_EVEX_MAP6_D6, PREFIX_EVEX_MAP6_D7 (enum): Add EVEX_MAP5 and EVEX_MAP6. (enum): Add EVEX_W_MAP5_5A, EVEX_W_MAP5_5B, EVEX_W_MAP5_78_P_0, EVEX_W_MAP5_78_P_2, EVEX_W_MAP5_79_P_0, EVEX_W_MAP5_79_P_2, EVEX_W_MAP5_7A_P_2, EVEX_W_MAP5_7A_P_3, EVEX_W_MAP5_7B_P_2, EVEX_W_MAP5_7C_P_0, EVEX_W_MAP5_7C_P_2, EVEX_W_MAP5_7D, EVEX_W_MAP6_13_P_0, EVEX_W_MAP6_13_P_2, (get_valid_dis386): Properly handle new instructions. (intel_operand_size): Handle new modes. (OP_E_memory): Ditto. (OP_EX): Ditto. * i386-dis-evex.h: Updated for AVX512_FP16. * i386-dis-evex-mod.h: Updated for AVX512_FP16. * i386-dis-evex-prefix.h: Updated for AVX512_FP16. * i386-dis-evex-reg.h : Updated for AVX512_FP16. * i386-dis-evex-w.h : Updated for AVX512_FP16. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_FP16_FLAGS, and CPU_ANY_AVX512_FP16_FLAGS. Update CPU_ANY_AVX512F_FLAGS and CPU_ANY_AVX512BW_FLAGS. (cpu_flags): Add CpuAVX512_FP16. (opcode_modifiers): Add DistinctDest. * i386-opc.h (enum): (AVX512_FP16): New. (i386_opcode_modifier): Add reqdistinctreg. (i386_cpu_flags): Add cpuavx512_fp16. (EVEXMAP5): Defined as a macro. (EVEXMAP6): Ditto. * i386-opc.tbl: Add Intel AVX512_FP16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Ditto.
2021-06-14 11:05:05 +08:00
{ "vfnmadd213p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
x86: consistently use scalar_mode for AVX512-FP16 scalar insns For some reason the original AVFX512F insns were not taken as a basis here, causing unnecessary divergence. While not an active issue, it is still relevant to note that OP_XMM() has special treatment of e.g. scalar_mode (marking broadcast as invalid). Such would better be consistent for all sufficiently similar insns.
2022-01-14 17:55:42 +08:00
{ "vfnmadd213s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
[PATCH 1/2] Enable Intel AVX512_FP16 instructions Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32 in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx). There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8 operands predated our current conventions; those instructions moved to map 3. FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3 is very sparsely populated. Most of the FP16 instructions share opcodes and prefix (EVEX.pp) bits with the related FP32 operations. Intel AVX512 FP16 instructions has new displacements scaling rules, please refer to the public software developer manual for detail information. gas/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (struct Broadcast_Operation): Adjust comment. (cpu_arch): Add .avx512_fp16. (cpu_noarch): Add noavx512_fp16. (pte): Add evexmap5 and evexmap6. (build_evex_prefix): Handle EVEXMAP5 and EVEXMAP6. (check_VecOperations): Handle {1to32}. (check_VecOperands): Handle CheckRegNumb. (check_word_reg): Handle Toqword. (i386_error): Add invalid_dest_and_src_register_set. (match_template): Handle invalid_dest_and_src_register_set. * doc/c-i386.texi: Document avx512_fp16, noavx512_fp16. opcodes/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (EXwScalarS): New. (EXxh): Ditto. (EXxhc): Ditto. (EXxmmqh): Ditto. (EXxmmqdh): Ditto. (EXEvexXwb): Ditto. (DistinctDest_Fixup): Ditto. (enum): Add xh_mode, evex_half_bcst_xmmqh_mode, evex_half_bcst_xmmqdh_mode and w_swap_mode. (enum): Add PREFIX_EVEX_0F3A08_W_0, PREFIX_EVEX_0F3A0A_W_0, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3AC2, PREFIX_EVEX_MAP5_10, PREFIX_EVEX_MAP5_11, PREFIX_EVEX_MAP5_1D, PREFIX_EVEX_MAP5_2A, PREFIX_EVEX_MAP5_2C, PREFIX_EVEX_MAP5_2D, PREFIX_EVEX_MAP5_2E, PREFIX_EVEX_MAP5_2F, PREFIX_EVEX_MAP5_51, PREFIX_EVEX_MAP5_58, PREFIX_EVEX_MAP5_59, PREFIX_EVEX_MAP5_5A_W_0, PREFIX_EVEX_MAP5_5A_W_1, PREFIX_EVEX_MAP5_5B_W_0, PREFIX_EVEX_MAP5_5B_W_1, PREFIX_EVEX_MAP5_5C, PREFIX_EVEX_MAP5_5D, PREFIX_EVEX_MAP5_5E, PREFIX_EVEX_MAP5_5F, PREFIX_EVEX_MAP5_78, PREFIX_EVEX_MAP5_79, PREFIX_EVEX_MAP5_7A, PREFIX_EVEX_MAP5_7B, PREFIX_EVEX_MAP5_7C, PREFIX_EVEX_MAP5_7D_W_0, PREFIX_EVEX_MAP6_13, PREFIX_EVEX_MAP6_56, PREFIX_EVEX_MAP6_57, PREFIX_EVEX_MAP6_D6, PREFIX_EVEX_MAP6_D7 (enum): Add EVEX_MAP5 and EVEX_MAP6. (enum): Add EVEX_W_MAP5_5A, EVEX_W_MAP5_5B, EVEX_W_MAP5_78_P_0, EVEX_W_MAP5_78_P_2, EVEX_W_MAP5_79_P_0, EVEX_W_MAP5_79_P_2, EVEX_W_MAP5_7A_P_2, EVEX_W_MAP5_7A_P_3, EVEX_W_MAP5_7B_P_2, EVEX_W_MAP5_7C_P_0, EVEX_W_MAP5_7C_P_2, EVEX_W_MAP5_7D, EVEX_W_MAP6_13_P_0, EVEX_W_MAP6_13_P_2, (get_valid_dis386): Properly handle new instructions. (intel_operand_size): Handle new modes. (OP_E_memory): Ditto. (OP_EX): Ditto. * i386-dis-evex.h: Updated for AVX512_FP16. * i386-dis-evex-mod.h: Updated for AVX512_FP16. * i386-dis-evex-prefix.h: Updated for AVX512_FP16. * i386-dis-evex-reg.h : Updated for AVX512_FP16. * i386-dis-evex-w.h : Updated for AVX512_FP16. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_FP16_FLAGS, and CPU_ANY_AVX512_FP16_FLAGS. Update CPU_ANY_AVX512F_FLAGS and CPU_ANY_AVX512BW_FLAGS. (cpu_flags): Add CpuAVX512_FP16. (opcode_modifiers): Add DistinctDest. * i386-opc.h (enum): (AVX512_FP16): New. (i386_opcode_modifier): Add reqdistinctreg. (i386_cpu_flags): Add cpuavx512_fp16. (EVEXMAP5): Defined as a macro. (EVEXMAP6): Ditto. * i386-opc.tbl: Add Intel AVX512_FP16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Ditto.
2021-06-14 11:05:05 +08:00
{ "vfnmsub213p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
x86: consistently use scalar_mode for AVX512-FP16 scalar insns For some reason the original AVFX512F insns were not taken as a basis here, causing unnecessary divergence. While not an active issue, it is still relevant to note that OP_XMM() has special treatment of e.g. scalar_mode (marking broadcast as invalid). Such would better be consistent for all sufficiently similar insns.
2022-01-14 17:55:42 +08:00
{ "vfnmsub213s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
[PATCH 1/2] Enable Intel AVX512_FP16 instructions Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32 in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx). There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8 operands predated our current conventions; those instructions moved to map 3. FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3 is very sparsely populated. Most of the FP16 instructions share opcodes and prefix (EVEX.pp) bits with the related FP32 operations. Intel AVX512 FP16 instructions has new displacements scaling rules, please refer to the public software developer manual for detail information. gas/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (struct Broadcast_Operation): Adjust comment. (cpu_arch): Add .avx512_fp16. (cpu_noarch): Add noavx512_fp16. (pte): Add evexmap5 and evexmap6. (build_evex_prefix): Handle EVEXMAP5 and EVEXMAP6. (check_VecOperations): Handle {1to32}. (check_VecOperands): Handle CheckRegNumb. (check_word_reg): Handle Toqword. (i386_error): Add invalid_dest_and_src_register_set. (match_template): Handle invalid_dest_and_src_register_set. * doc/c-i386.texi: Document avx512_fp16, noavx512_fp16. opcodes/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (EXwScalarS): New. (EXxh): Ditto. (EXxhc): Ditto. (EXxmmqh): Ditto. (EXxmmqdh): Ditto. (EXEvexXwb): Ditto. (DistinctDest_Fixup): Ditto. (enum): Add xh_mode, evex_half_bcst_xmmqh_mode, evex_half_bcst_xmmqdh_mode and w_swap_mode. (enum): Add PREFIX_EVEX_0F3A08_W_0, PREFIX_EVEX_0F3A0A_W_0, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3AC2, PREFIX_EVEX_MAP5_10, PREFIX_EVEX_MAP5_11, PREFIX_EVEX_MAP5_1D, PREFIX_EVEX_MAP5_2A, PREFIX_EVEX_MAP5_2C, PREFIX_EVEX_MAP5_2D, PREFIX_EVEX_MAP5_2E, PREFIX_EVEX_MAP5_2F, PREFIX_EVEX_MAP5_51, PREFIX_EVEX_MAP5_58, PREFIX_EVEX_MAP5_59, PREFIX_EVEX_MAP5_5A_W_0, PREFIX_EVEX_MAP5_5A_W_1, PREFIX_EVEX_MAP5_5B_W_0, PREFIX_EVEX_MAP5_5B_W_1, PREFIX_EVEX_MAP5_5C, PREFIX_EVEX_MAP5_5D, PREFIX_EVEX_MAP5_5E, PREFIX_EVEX_MAP5_5F, PREFIX_EVEX_MAP5_78, PREFIX_EVEX_MAP5_79, PREFIX_EVEX_MAP5_7A, PREFIX_EVEX_MAP5_7B, PREFIX_EVEX_MAP5_7C, PREFIX_EVEX_MAP5_7D_W_0, PREFIX_EVEX_MAP6_13, PREFIX_EVEX_MAP6_56, PREFIX_EVEX_MAP6_57, PREFIX_EVEX_MAP6_D6, PREFIX_EVEX_MAP6_D7 (enum): Add EVEX_MAP5 and EVEX_MAP6. (enum): Add EVEX_W_MAP5_5A, EVEX_W_MAP5_5B, EVEX_W_MAP5_78_P_0, EVEX_W_MAP5_78_P_2, EVEX_W_MAP5_79_P_0, EVEX_W_MAP5_79_P_2, EVEX_W_MAP5_7A_P_2, EVEX_W_MAP5_7A_P_3, EVEX_W_MAP5_7B_P_2, EVEX_W_MAP5_7C_P_0, EVEX_W_MAP5_7C_P_2, EVEX_W_MAP5_7D, EVEX_W_MAP6_13_P_0, EVEX_W_MAP6_13_P_2, (get_valid_dis386): Properly handle new instructions. (intel_operand_size): Handle new modes. (OP_E_memory): Ditto. (OP_EX): Ditto. * i386-dis-evex.h: Updated for AVX512_FP16. * i386-dis-evex-mod.h: Updated for AVX512_FP16. * i386-dis-evex-prefix.h: Updated for AVX512_FP16. * i386-dis-evex-reg.h : Updated for AVX512_FP16. * i386-dis-evex-w.h : Updated for AVX512_FP16. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_FP16_FLAGS, and CPU_ANY_AVX512_FP16_FLAGS. Update CPU_ANY_AVX512F_FLAGS and CPU_ANY_AVX512BW_FLAGS. (cpu_flags): Add CpuAVX512_FP16. (opcode_modifiers): Add DistinctDest. * i386-opc.h (enum): (AVX512_FP16): New. (i386_opcode_modifier): Add reqdistinctreg. (i386_cpu_flags): Add cpuavx512_fp16. (EVEXMAP5): Defined as a macro. (EVEXMAP6): Ditto. * i386-opc.tbl: Add Intel AVX512_FP16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Ditto.
2021-06-14 11:05:05 +08:00
/* B0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ "vfmaddsub231p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
{ "vfmsubadd231p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
/* B8 */
{ "vfmadd231p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
x86: consistently use scalar_mode for AVX512-FP16 scalar insns For some reason the original AVFX512F insns were not taken as a basis here, causing unnecessary divergence. While not an active issue, it is still relevant to note that OP_XMM() has special treatment of e.g. scalar_mode (marking broadcast as invalid). Such would better be consistent for all sufficiently similar insns.
2022-01-14 17:55:42 +08:00
{ "vfmadd231s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
[PATCH 1/2] Enable Intel AVX512_FP16 instructions Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32 in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx). There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8 operands predated our current conventions; those instructions moved to map 3. FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3 is very sparsely populated. Most of the FP16 instructions share opcodes and prefix (EVEX.pp) bits with the related FP32 operations. Intel AVX512 FP16 instructions has new displacements scaling rules, please refer to the public software developer manual for detail information. gas/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (struct Broadcast_Operation): Adjust comment. (cpu_arch): Add .avx512_fp16. (cpu_noarch): Add noavx512_fp16. (pte): Add evexmap5 and evexmap6. (build_evex_prefix): Handle EVEXMAP5 and EVEXMAP6. (check_VecOperations): Handle {1to32}. (check_VecOperands): Handle CheckRegNumb. (check_word_reg): Handle Toqword. (i386_error): Add invalid_dest_and_src_register_set. (match_template): Handle invalid_dest_and_src_register_set. * doc/c-i386.texi: Document avx512_fp16, noavx512_fp16. opcodes/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (EXwScalarS): New. (EXxh): Ditto. (EXxhc): Ditto. (EXxmmqh): Ditto. (EXxmmqdh): Ditto. (EXEvexXwb): Ditto. (DistinctDest_Fixup): Ditto. (enum): Add xh_mode, evex_half_bcst_xmmqh_mode, evex_half_bcst_xmmqdh_mode and w_swap_mode. (enum): Add PREFIX_EVEX_0F3A08_W_0, PREFIX_EVEX_0F3A0A_W_0, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3AC2, PREFIX_EVEX_MAP5_10, PREFIX_EVEX_MAP5_11, PREFIX_EVEX_MAP5_1D, PREFIX_EVEX_MAP5_2A, PREFIX_EVEX_MAP5_2C, PREFIX_EVEX_MAP5_2D, PREFIX_EVEX_MAP5_2E, PREFIX_EVEX_MAP5_2F, PREFIX_EVEX_MAP5_51, PREFIX_EVEX_MAP5_58, PREFIX_EVEX_MAP5_59, PREFIX_EVEX_MAP5_5A_W_0, PREFIX_EVEX_MAP5_5A_W_1, PREFIX_EVEX_MAP5_5B_W_0, PREFIX_EVEX_MAP5_5B_W_1, PREFIX_EVEX_MAP5_5C, PREFIX_EVEX_MAP5_5D, PREFIX_EVEX_MAP5_5E, PREFIX_EVEX_MAP5_5F, PREFIX_EVEX_MAP5_78, PREFIX_EVEX_MAP5_79, PREFIX_EVEX_MAP5_7A, PREFIX_EVEX_MAP5_7B, PREFIX_EVEX_MAP5_7C, PREFIX_EVEX_MAP5_7D_W_0, PREFIX_EVEX_MAP6_13, PREFIX_EVEX_MAP6_56, PREFIX_EVEX_MAP6_57, PREFIX_EVEX_MAP6_D6, PREFIX_EVEX_MAP6_D7 (enum): Add EVEX_MAP5 and EVEX_MAP6. (enum): Add EVEX_W_MAP5_5A, EVEX_W_MAP5_5B, EVEX_W_MAP5_78_P_0, EVEX_W_MAP5_78_P_2, EVEX_W_MAP5_79_P_0, EVEX_W_MAP5_79_P_2, EVEX_W_MAP5_7A_P_2, EVEX_W_MAP5_7A_P_3, EVEX_W_MAP5_7B_P_2, EVEX_W_MAP5_7C_P_0, EVEX_W_MAP5_7C_P_2, EVEX_W_MAP5_7D, EVEX_W_MAP6_13_P_0, EVEX_W_MAP6_13_P_2, (get_valid_dis386): Properly handle new instructions. (intel_operand_size): Handle new modes. (OP_E_memory): Ditto. (OP_EX): Ditto. * i386-dis-evex.h: Updated for AVX512_FP16. * i386-dis-evex-mod.h: Updated for AVX512_FP16. * i386-dis-evex-prefix.h: Updated for AVX512_FP16. * i386-dis-evex-reg.h : Updated for AVX512_FP16. * i386-dis-evex-w.h : Updated for AVX512_FP16. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_FP16_FLAGS, and CPU_ANY_AVX512_FP16_FLAGS. Update CPU_ANY_AVX512F_FLAGS and CPU_ANY_AVX512BW_FLAGS. (cpu_flags): Add CpuAVX512_FP16. (opcode_modifiers): Add DistinctDest. * i386-opc.h (enum): (AVX512_FP16): New. (i386_opcode_modifier): Add reqdistinctreg. (i386_cpu_flags): Add cpuavx512_fp16. (EVEXMAP5): Defined as a macro. (EVEXMAP6): Ditto. * i386-opc.tbl: Add Intel AVX512_FP16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Ditto.
2021-06-14 11:05:05 +08:00
{ "vfmsub231p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
x86: consistently use scalar_mode for AVX512-FP16 scalar insns For some reason the original AVFX512F insns were not taken as a basis here, causing unnecessary divergence. While not an active issue, it is still relevant to note that OP_XMM() has special treatment of e.g. scalar_mode (marking broadcast as invalid). Such would better be consistent for all sufficiently similar insns.
2022-01-14 17:55:42 +08:00
{ "vfmsub231s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
[PATCH 1/2] Enable Intel AVX512_FP16 instructions Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32 in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx). There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8 operands predated our current conventions; those instructions moved to map 3. FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3 is very sparsely populated. Most of the FP16 instructions share opcodes and prefix (EVEX.pp) bits with the related FP32 operations. Intel AVX512 FP16 instructions has new displacements scaling rules, please refer to the public software developer manual for detail information. gas/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (struct Broadcast_Operation): Adjust comment. (cpu_arch): Add .avx512_fp16. (cpu_noarch): Add noavx512_fp16. (pte): Add evexmap5 and evexmap6. (build_evex_prefix): Handle EVEXMAP5 and EVEXMAP6. (check_VecOperations): Handle {1to32}. (check_VecOperands): Handle CheckRegNumb. (check_word_reg): Handle Toqword. (i386_error): Add invalid_dest_and_src_register_set. (match_template): Handle invalid_dest_and_src_register_set. * doc/c-i386.texi: Document avx512_fp16, noavx512_fp16. opcodes/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (EXwScalarS): New. (EXxh): Ditto. (EXxhc): Ditto. (EXxmmqh): Ditto. (EXxmmqdh): Ditto. (EXEvexXwb): Ditto. (DistinctDest_Fixup): Ditto. (enum): Add xh_mode, evex_half_bcst_xmmqh_mode, evex_half_bcst_xmmqdh_mode and w_swap_mode. (enum): Add PREFIX_EVEX_0F3A08_W_0, PREFIX_EVEX_0F3A0A_W_0, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3AC2, PREFIX_EVEX_MAP5_10, PREFIX_EVEX_MAP5_11, PREFIX_EVEX_MAP5_1D, PREFIX_EVEX_MAP5_2A, PREFIX_EVEX_MAP5_2C, PREFIX_EVEX_MAP5_2D, PREFIX_EVEX_MAP5_2E, PREFIX_EVEX_MAP5_2F, PREFIX_EVEX_MAP5_51, PREFIX_EVEX_MAP5_58, PREFIX_EVEX_MAP5_59, PREFIX_EVEX_MAP5_5A_W_0, PREFIX_EVEX_MAP5_5A_W_1, PREFIX_EVEX_MAP5_5B_W_0, PREFIX_EVEX_MAP5_5B_W_1, PREFIX_EVEX_MAP5_5C, PREFIX_EVEX_MAP5_5D, PREFIX_EVEX_MAP5_5E, PREFIX_EVEX_MAP5_5F, PREFIX_EVEX_MAP5_78, PREFIX_EVEX_MAP5_79, PREFIX_EVEX_MAP5_7A, PREFIX_EVEX_MAP5_7B, PREFIX_EVEX_MAP5_7C, PREFIX_EVEX_MAP5_7D_W_0, PREFIX_EVEX_MAP6_13, PREFIX_EVEX_MAP6_56, PREFIX_EVEX_MAP6_57, PREFIX_EVEX_MAP6_D6, PREFIX_EVEX_MAP6_D7 (enum): Add EVEX_MAP5 and EVEX_MAP6. (enum): Add EVEX_W_MAP5_5A, EVEX_W_MAP5_5B, EVEX_W_MAP5_78_P_0, EVEX_W_MAP5_78_P_2, EVEX_W_MAP5_79_P_0, EVEX_W_MAP5_79_P_2, EVEX_W_MAP5_7A_P_2, EVEX_W_MAP5_7A_P_3, EVEX_W_MAP5_7B_P_2, EVEX_W_MAP5_7C_P_0, EVEX_W_MAP5_7C_P_2, EVEX_W_MAP5_7D, EVEX_W_MAP6_13_P_0, EVEX_W_MAP6_13_P_2, (get_valid_dis386): Properly handle new instructions. (intel_operand_size): Handle new modes. (OP_E_memory): Ditto. (OP_EX): Ditto. * i386-dis-evex.h: Updated for AVX512_FP16. * i386-dis-evex-mod.h: Updated for AVX512_FP16. * i386-dis-evex-prefix.h: Updated for AVX512_FP16. * i386-dis-evex-reg.h : Updated for AVX512_FP16. * i386-dis-evex-w.h : Updated for AVX512_FP16. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_FP16_FLAGS, and CPU_ANY_AVX512_FP16_FLAGS. Update CPU_ANY_AVX512F_FLAGS and CPU_ANY_AVX512BW_FLAGS. (cpu_flags): Add CpuAVX512_FP16. (opcode_modifiers): Add DistinctDest. * i386-opc.h (enum): (AVX512_FP16): New. (i386_opcode_modifier): Add reqdistinctreg. (i386_cpu_flags): Add cpuavx512_fp16. (EVEXMAP5): Defined as a macro. (EVEXMAP6): Ditto. * i386-opc.tbl: Add Intel AVX512_FP16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Ditto.
2021-06-14 11:05:05 +08:00
{ "vfnmadd231p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
x86: consistently use scalar_mode for AVX512-FP16 scalar insns For some reason the original AVFX512F insns were not taken as a basis here, causing unnecessary divergence. While not an active issue, it is still relevant to note that OP_XMM() has special treatment of e.g. scalar_mode (marking broadcast as invalid). Such would better be consistent for all sufficiently similar insns.
2022-01-14 17:55:42 +08:00
{ "vfnmadd231s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
[PATCH 1/2] Enable Intel AVX512_FP16 instructions Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32 in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx). There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8 operands predated our current conventions; those instructions moved to map 3. FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3 is very sparsely populated. Most of the FP16 instructions share opcodes and prefix (EVEX.pp) bits with the related FP32 operations. Intel AVX512 FP16 instructions has new displacements scaling rules, please refer to the public software developer manual for detail information. gas/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (struct Broadcast_Operation): Adjust comment. (cpu_arch): Add .avx512_fp16. (cpu_noarch): Add noavx512_fp16. (pte): Add evexmap5 and evexmap6. (build_evex_prefix): Handle EVEXMAP5 and EVEXMAP6. (check_VecOperations): Handle {1to32}. (check_VecOperands): Handle CheckRegNumb. (check_word_reg): Handle Toqword. (i386_error): Add invalid_dest_and_src_register_set. (match_template): Handle invalid_dest_and_src_register_set. * doc/c-i386.texi: Document avx512_fp16, noavx512_fp16. opcodes/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (EXwScalarS): New. (EXxh): Ditto. (EXxhc): Ditto. (EXxmmqh): Ditto. (EXxmmqdh): Ditto. (EXEvexXwb): Ditto. (DistinctDest_Fixup): Ditto. (enum): Add xh_mode, evex_half_bcst_xmmqh_mode, evex_half_bcst_xmmqdh_mode and w_swap_mode. (enum): Add PREFIX_EVEX_0F3A08_W_0, PREFIX_EVEX_0F3A0A_W_0, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3AC2, PREFIX_EVEX_MAP5_10, PREFIX_EVEX_MAP5_11, PREFIX_EVEX_MAP5_1D, PREFIX_EVEX_MAP5_2A, PREFIX_EVEX_MAP5_2C, PREFIX_EVEX_MAP5_2D, PREFIX_EVEX_MAP5_2E, PREFIX_EVEX_MAP5_2F, PREFIX_EVEX_MAP5_51, PREFIX_EVEX_MAP5_58, PREFIX_EVEX_MAP5_59, PREFIX_EVEX_MAP5_5A_W_0, PREFIX_EVEX_MAP5_5A_W_1, PREFIX_EVEX_MAP5_5B_W_0, PREFIX_EVEX_MAP5_5B_W_1, PREFIX_EVEX_MAP5_5C, PREFIX_EVEX_MAP5_5D, PREFIX_EVEX_MAP5_5E, PREFIX_EVEX_MAP5_5F, PREFIX_EVEX_MAP5_78, PREFIX_EVEX_MAP5_79, PREFIX_EVEX_MAP5_7A, PREFIX_EVEX_MAP5_7B, PREFIX_EVEX_MAP5_7C, PREFIX_EVEX_MAP5_7D_W_0, PREFIX_EVEX_MAP6_13, PREFIX_EVEX_MAP6_56, PREFIX_EVEX_MAP6_57, PREFIX_EVEX_MAP6_D6, PREFIX_EVEX_MAP6_D7 (enum): Add EVEX_MAP5 and EVEX_MAP6. (enum): Add EVEX_W_MAP5_5A, EVEX_W_MAP5_5B, EVEX_W_MAP5_78_P_0, EVEX_W_MAP5_78_P_2, EVEX_W_MAP5_79_P_0, EVEX_W_MAP5_79_P_2, EVEX_W_MAP5_7A_P_2, EVEX_W_MAP5_7A_P_3, EVEX_W_MAP5_7B_P_2, EVEX_W_MAP5_7C_P_0, EVEX_W_MAP5_7C_P_2, EVEX_W_MAP5_7D, EVEX_W_MAP6_13_P_0, EVEX_W_MAP6_13_P_2, (get_valid_dis386): Properly handle new instructions. (intel_operand_size): Handle new modes. (OP_E_memory): Ditto. (OP_EX): Ditto. * i386-dis-evex.h: Updated for AVX512_FP16. * i386-dis-evex-mod.h: Updated for AVX512_FP16. * i386-dis-evex-prefix.h: Updated for AVX512_FP16. * i386-dis-evex-reg.h : Updated for AVX512_FP16. * i386-dis-evex-w.h : Updated for AVX512_FP16. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_FP16_FLAGS, and CPU_ANY_AVX512_FP16_FLAGS. Update CPU_ANY_AVX512F_FLAGS and CPU_ANY_AVX512BW_FLAGS. (cpu_flags): Add CpuAVX512_FP16. (opcode_modifiers): Add DistinctDest. * i386-opc.h (enum): (AVX512_FP16): New. (i386_opcode_modifier): Add reqdistinctreg. (i386_cpu_flags): Add cpuavx512_fp16. (EVEXMAP5): Defined as a macro. (EVEXMAP6): Ditto. * i386-opc.tbl: Add Intel AVX512_FP16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Ditto.
2021-06-14 11:05:05 +08:00
{ "vfnmsub231p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
x86: consistently use scalar_mode for AVX512-FP16 scalar insns For some reason the original AVFX512F insns were not taken as a basis here, causing unnecessary divergence. While not an active issue, it is still relevant to note that OP_XMM() has special treatment of e.g. scalar_mode (marking broadcast as invalid). Such would better be consistent for all sufficiently similar insns.
2022-01-14 17:55:42 +08:00
{ "vfnmsub231s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA },
[PATCH 1/2] Enable Intel AVX512_FP16 instructions Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32 in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx). There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8 operands predated our current conventions; those instructions moved to map 3. FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3 is very sparsely populated. Most of the FP16 instructions share opcodes and prefix (EVEX.pp) bits with the related FP32 operations. Intel AVX512 FP16 instructions has new displacements scaling rules, please refer to the public software developer manual for detail information. gas/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (struct Broadcast_Operation): Adjust comment. (cpu_arch): Add .avx512_fp16. (cpu_noarch): Add noavx512_fp16. (pte): Add evexmap5 and evexmap6. (build_evex_prefix): Handle EVEXMAP5 and EVEXMAP6. (check_VecOperations): Handle {1to32}. (check_VecOperands): Handle CheckRegNumb. (check_word_reg): Handle Toqword. (i386_error): Add invalid_dest_and_src_register_set. (match_template): Handle invalid_dest_and_src_register_set. * doc/c-i386.texi: Document avx512_fp16, noavx512_fp16. opcodes/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (EXwScalarS): New. (EXxh): Ditto. (EXxhc): Ditto. (EXxmmqh): Ditto. (EXxmmqdh): Ditto. (EXEvexXwb): Ditto. (DistinctDest_Fixup): Ditto. (enum): Add xh_mode, evex_half_bcst_xmmqh_mode, evex_half_bcst_xmmqdh_mode and w_swap_mode. (enum): Add PREFIX_EVEX_0F3A08_W_0, PREFIX_EVEX_0F3A0A_W_0, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3AC2, PREFIX_EVEX_MAP5_10, PREFIX_EVEX_MAP5_11, PREFIX_EVEX_MAP5_1D, PREFIX_EVEX_MAP5_2A, PREFIX_EVEX_MAP5_2C, PREFIX_EVEX_MAP5_2D, PREFIX_EVEX_MAP5_2E, PREFIX_EVEX_MAP5_2F, PREFIX_EVEX_MAP5_51, PREFIX_EVEX_MAP5_58, PREFIX_EVEX_MAP5_59, PREFIX_EVEX_MAP5_5A_W_0, PREFIX_EVEX_MAP5_5A_W_1, PREFIX_EVEX_MAP5_5B_W_0, PREFIX_EVEX_MAP5_5B_W_1, PREFIX_EVEX_MAP5_5C, PREFIX_EVEX_MAP5_5D, PREFIX_EVEX_MAP5_5E, PREFIX_EVEX_MAP5_5F, PREFIX_EVEX_MAP5_78, PREFIX_EVEX_MAP5_79, PREFIX_EVEX_MAP5_7A, PREFIX_EVEX_MAP5_7B, PREFIX_EVEX_MAP5_7C, PREFIX_EVEX_MAP5_7D_W_0, PREFIX_EVEX_MAP6_13, PREFIX_EVEX_MAP6_56, PREFIX_EVEX_MAP6_57, PREFIX_EVEX_MAP6_D6, PREFIX_EVEX_MAP6_D7 (enum): Add EVEX_MAP5 and EVEX_MAP6. (enum): Add EVEX_W_MAP5_5A, EVEX_W_MAP5_5B, EVEX_W_MAP5_78_P_0, EVEX_W_MAP5_78_P_2, EVEX_W_MAP5_79_P_0, EVEX_W_MAP5_79_P_2, EVEX_W_MAP5_7A_P_2, EVEX_W_MAP5_7A_P_3, EVEX_W_MAP5_7B_P_2, EVEX_W_MAP5_7C_P_0, EVEX_W_MAP5_7C_P_2, EVEX_W_MAP5_7D, EVEX_W_MAP6_13_P_0, EVEX_W_MAP6_13_P_2, (get_valid_dis386): Properly handle new instructions. (intel_operand_size): Handle new modes. (OP_E_memory): Ditto. (OP_EX): Ditto. * i386-dis-evex.h: Updated for AVX512_FP16. * i386-dis-evex-mod.h: Updated for AVX512_FP16. * i386-dis-evex-prefix.h: Updated for AVX512_FP16. * i386-dis-evex-reg.h : Updated for AVX512_FP16. * i386-dis-evex-w.h : Updated for AVX512_FP16. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_FP16_FLAGS, and CPU_ANY_AVX512_FP16_FLAGS. Update CPU_ANY_AVX512F_FLAGS and CPU_ANY_AVX512BW_FLAGS. (cpu_flags): Add CpuAVX512_FP16. (opcode_modifiers): Add DistinctDest. * i386-opc.h (enum): (AVX512_FP16): New. (i386_opcode_modifier): Add reqdistinctreg. (i386_cpu_flags): Add cpuavx512_fp16. (EVEXMAP5): Defined as a macro. (EVEXMAP6): Ditto. * i386-opc.tbl: Add Intel AVX512_FP16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Ditto.
2021-06-14 11:05:05 +08:00
/* C0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* C8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* D0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ PREFIX_TABLE (PREFIX_EVEX_MAP6_D6) },
{ PREFIX_TABLE (PREFIX_EVEX_MAP6_D7) },
/* D8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* E0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* E8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* F0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* F8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
},
Add Intel AVX-512 support binutils/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and numeration in comments. (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to dwarf table. gas/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * config/tc-i386-intel.c (O_zmmword_ptr): New. (i386_types): Add zmmword. (i386_intel_simplify_register): Allow regzmm. (i386_intel_simplify): Handle zmmwords. (i386_intel_operand): Handle RC/SAE, vector operations and zmmwords. * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. (struct RC_Operation): New. (struct Mask_Operation): New. (struct Broadcast_Operation): New. (vex_prefix): Size of bytes increased to 4 to support EVEX encoding. (enum i386_error): Add new error codes: unsupported_broadcast, broadcast_not_on_src_operand, broadcast_needed, unsupported_masking, mask_not_on_destination, no_default_mask, unsupported_rc_sae, rc_sae_operand_not_last_imm, invalid_register_operand, try_vector_disp8. (struct _i386_insn): Add new fields vrex, need_vrex, mask, rounding, broadcast, memshift. (struct RC_name): New. (RC_NamesTable): New. (evexlig): New. (evexwig): New. (extra_symbol_chars): Add '{'. (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. (i386_operand_type): Add regzmm, regmask and vec_disp8. (match_mem_size): Handle zmmwords. (operand_type_match): Handle zmm-registers. (mode_from_disp_size): Handle vec_disp8. (fits_in_vec_disp8): New. (md_begin): Handle {} properly. (type_names): Add "rZMM", "Mask reg" and "Vector d8". (build_vex_prefix): Handle vrex. (build_evex_prefix): New. (process_immext): Adjust to properly handle EVEX. (md_assemble): Add EVEX encoding support. (swap_2_operands): Correctly handle operands with masking, broadcasting or RC/SAE. (check_VecOperands): Support EVEX features. (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. (match_template): Support regzmm and handle new error codes. (process_suffix): Handle zmmwords and zmm-registers. (check_byte_reg): Extend to zmm-registers. (process_operands): Extend to zmm-registers. (build_modrm_byte): Handle EVEX. (output_insn): Adjust to properly handle EVEX case. (disp_size): Handle vec_disp8. (output_disp): Support compressed disp8*N evex feature. (output_imm): Handle RC/SAE immediates properly. (check_VecOperations): New. (i386_immediate): Handle EVEX features. (i386_index_check): Handle zmmwords and zmm-registers. (RC_SAE_immediate): New. (i386_att_operand): Handle EVEX features. (parse_real_register): Add a check for ZMM/Mask registers. (OPTION_MEVEXLIG): New. (OPTION_MEVEXWIG): New. (md_longopts): Add mevexlig and mevexwig. (md_parse_option): Handle mevexlig and mevexwig options. (md_show_usage): Add description for mevexlig and mevexwig. * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. gas/testsuite/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * gas/cfi/cfi-i386.s: Add tests for k0-k7. * gas/cfi/cfi-i386.d: Change to reflect above mentioned changes. * gas/cfi/cfi-x86_64.s: Add tests for xmm16-31, k0-7. * gas/cfi/cfi-x86_64.d: Change to reflect above mentioned changes. * gas/i386/ilp32/cfi/cfi-x86_64.d: Ditto. * gas/i386/intel-regs.s: Add tests for zmm0 and xmm16 registers. * gas/i386/intel-regs.d: Change correspondingly. * gas/i386/prefetch-intel.d: Reflect implementation of prefetchwt1. * gas/i386/prefetch.d: Ditto. * gas/i386/x86-64-prefetch-intel.d: Ditto. * gas/i386/x86-64-prefetch.d: Ditto. * gas/i386/avx512f-intel.d: New. * gas/i386/avx512f-nondef.d: New. * gas/i386/avx512f-nondef.s: New. * gas/i386/avx512f-opts-intel.d: New. * gas/i386/avx512f-opts.d: New. * gas/i386/avx512f-opts.s: New. * gas/i386/avx512f.d: New. * gas/i386/avx512f.s: New. * gas/i386/avx512cd-intel.d: New. * gas/i386/avx512cd.d: New. * gas/i386/avx512cd.s: New. * gas/i386/avx512er-intel.d: New. * gas/i386/avx512er.d: New. * gas/i386/avx512er.s: New. * gas/i386/avx512pf-intel.d: New. * gas/i386/avx512pf.d: New. * gas/i386/avx512pf.s: New. * gas/i386/evex-lig.s: New. * gas/i386/evex-lig256-intel.d: New. * gas/i386/evex-lig256.d: New. * gas/i386/evex-lig512-intel.d: New. * gas/i386/evex-lig512.d: New. * gas/i386/evex-wig.s: New. * gas/i386/evex-wig1-intel.d: New. * gas/i386/evex-wig1.d: New. * gas/i386/inval-avx512f.l: New. * gas/i386/inval-avx512f.s: New. * gas/i386/x86-64-avx512f-intel.d: New. * gas/i386/x86-64-avx512f-nondef.d: New. * gas/i386/x86-64-avx512f-nondef.s: New. * gas/i386/x86-64-avx512f-opts-intel.d: New. * gas/i386/x86-64-avx512f-opts.d: New. * gas/i386/x86-64-avx512f-opts.s: New. * gas/i386/x86-64-avx512f.d: New. * gas/i386/x86-64-avx512f.s: New. * gas/i386/x86-64-avx512cd-intel.d: New. * gas/i386/x86-64-avx512cd.d: New. * gas/i386/x86-64-avx512cd.s: New. * gas/i386/x86-64-avx512er-intel.d: New. * gas/i386/x86-64-avx512er.d: New. * gas/i386/x86-64-avx512er.s: New. * gas/i386/x86-64-avx512pf-intel.d: New. * gas/i386/x86-64-avx512pf.d: New. * gas/i386/x86-64-avx512pf.s: New. * gas/i386/x86-64-evex-lig.s: New. * gas/i386/x86-64-evex-lig256-intel.d: New. * gas/i386/x86-64-evex-lig256.d: New. * gas/i386/x86-64-evex-lig512-intel.d: New. * gas/i386/x86-64-evex-lig512.d: New. * gas/i386/x86-64-evex-wig.s: New. * gas/i386/x86-64-evex-wig1-intel.d: New. * gas/i386/x86-64-evex-wig1.d: New. * gas/i386/x86-64-inval-avx512f.l: New. * gas/i386/x86-64-inval-avx512f.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. opcodes/ 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> Sergey Lega <sergey.s.lega@intel.com> Anna Tikhonova <anna.tikhonova@intel.com> Ilya Tocar <ilya.tocar@intel.com> Andrey Turetskiy <andrey.turetskiy@intel.com> Ilya Verbin <ilya.verbin@intel.com> Kirill Yukhin <kirill.yukhin@intel.com> Michael Zolotukhin <michael.v.zolotukhin@intel.com> * i386-dis-evex.h: New. * i386-dis.c (OP_Rounding): New. (VPCMP_Fixup): New. (OP_Mask): New. (Rdq): New. (XMxmmq): New. (EXdScalarS): New. (EXymm): New. (EXEvexHalfBcstXmmq): New. (EXxmm_mdq): New. (EXEvexXGscat): New. (EXEvexXNoBcst): New. (VPCMP): New. (EXxEVexR): New. (EXxEVexS): New. (XMask): New. (MaskG): New. (MaskE): New. (MaskR): New. (MaskVex): New. (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode, evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode, evex_rounding_mode, evex_sae_mode, mask_mode. (USE_EVEX_TABLE): New. (EVEX_TABLE): New. (EVEX enum): New. (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6, REG_EVEX_0F38C7. (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6. (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11, PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A, PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D, PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51, PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A, PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D, PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62, PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F, PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1, PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4, PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2, PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78, PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B, PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2, PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813, PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823, PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827, PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A, PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831, PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834, PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837, PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D, PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55. (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0, VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0, VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0, VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1, VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0, EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0, EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1, EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3, EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3, EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3, EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3, EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2, EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2, EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0, EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2, EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2, EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1, EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2, EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2, EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1, EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1, EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2, EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1, EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2, EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1, EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1, EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1, EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2, EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2, EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2, EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2. (struct vex): Add fields evex, r, v, mask_register_specifier, zeroing, ll, b. (intel_names_xmm): Add upper 16 registers. (att_names_xmm): Ditto. (intel_names_ymm): Ditto. (att_names_ymm): Ditto. (names_zmm): New. (intel_names_zmm): Ditto. (att_names_zmm): Ditto. (names_mask): Ditto. (intel_names_mask): Ditto. (att_names_mask): Ditto. (names_rounding): Ditto. (names_broadcast): Ditto. (x86_64_table): Add escape to evex-table. (reg_table): Include reg_table evex-entries from i386-dis-evex.h. Fix prefetchwt1 instruction. (prefix_table): Add entries for new instructions. (vex_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (mod_table): Ditto. (get_valid_dis386): Properly handle new instructions. (print_insn): Handle zmm and mask registers, print mask operand. (intel_operand_size): Support EVEX, new modes and sizes. (OP_E_register): Handle new modes. (OP_E_memory): Ditto. (OP_G): Ditto. (OP_XMM): Ditto. (OP_EX): Ditto. (OP_VEX): Ditto. * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER, CpuAVX512PF and CpuVREX. (operand_type_init): Add OPERAND_TYPE_REGZMM, OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8. (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast, StaticRounding, SAE, Disp8MemShift, NoDefMask. (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword. * i386-init.h: Regenerate. * i386-opc.h (CpuAVX512F): New. (CpuAVX512CD): New. (CpuAVX512ER): New. (CpuAVX512PF): New. (CpuVREX): New. (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er, cpuavx512pf and cpuvrex fields. (VecSIB): Add VecSIB512. (EVex): New. (Masking): New. (VecESize): New. (Broadcast): New. (StaticRounding): New. (SAE): New. (Disp8MemShift): New. (NoDefMask): New. (i386_opcode_modifier): Add evex, masking, vecesize, broadcast, staticrounding, sae, disp8memshift and nodefmask. (RegZMM): New. (Zmmword): Ditto. (Vec_Disp8): Ditto. (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8 fields. (RegVRex): New. * i386-opc.tbl: Add AVX512 instructions. * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM registers, mask registers. * i386-tbl.h: Regenerate.
2013-07-27 01:20:25 +08:00
};
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