1999-04-16 09:35:26 +08:00
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/* run front end support for arm
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2017-01-01 14:50:51 +08:00
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Copyright (C) 1995-2017 Free Software Foundation, Inc.
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1999-04-16 09:35:26 +08:00
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2002-01-09 23:08:21 +08:00
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This file is part of ARM SIM.
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1999-04-16 09:35:26 +08:00
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2007-08-24 22:30:15 +08:00
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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1999-04-16 09:35:26 +08:00
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2007-08-24 22:30:15 +08:00
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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1999-04-16 09:35:26 +08:00
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2007-08-24 22:30:15 +08:00
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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1999-04-16 09:35:26 +08:00
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2002-01-09 23:08:21 +08:00
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/* This file provides the interface between the simulator and
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run.c and gdb (when the simulator is linked with gdb).
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1999-04-16 09:35:26 +08:00
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All simulator interaction should go through this file. */
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2012-05-20 00:46:16 +08:00
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#include "config.h"
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1999-04-16 09:35:26 +08:00
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#include <stdio.h>
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#include <stdarg.h>
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2000-02-09 04:54:27 +08:00
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#include <string.h>
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1999-04-16 09:35:26 +08:00
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#include <bfd.h>
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#include <signal.h>
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2002-06-09 23:45:54 +08:00
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#include "gdb/callback.h"
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#include "gdb/remote-sim.h"
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2015-03-30 15:05:57 +08:00
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#include "sim-main.h"
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#include "sim-options.h"
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1999-04-16 09:35:26 +08:00
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#include "armemu.h"
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#include "dbg_rdi.h"
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2000-02-09 04:54:27 +08:00
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#include "ansidecl.h"
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2002-06-13 05:19:43 +08:00
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#include "gdb/sim-arm.h"
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2005-11-29 02:33:03 +08:00
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#include "gdb/signals.h"
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2012-08-01 22:38:19 +08:00
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#include "libiberty.h"
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2014-03-14 23:21:23 +08:00
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#include "iwmmxt.h"
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2005-03-31 00:21:33 +08:00
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2015-03-30 15:05:57 +08:00
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/* TODO: This should get pulled from the SIM_DESC. */
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1999-04-16 09:35:26 +08:00
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host_callback *sim_callback;
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2015-03-30 15:05:57 +08:00
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/* TODO: This should get merged into sim_cpu. */
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struct ARMul_State *state;
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1999-04-16 09:35:26 +08:00
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/* Memory size in bytes. */
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2015-03-30 15:05:57 +08:00
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/* TODO: Memory should be converted to the common memory module. */
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2002-09-28 07:57:50 +08:00
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static int mem_size = (1 << 21);
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1999-04-16 09:35:26 +08:00
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1999-04-27 02:34:20 +08:00
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int stop_simulator;
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2014-03-14 23:21:23 +08:00
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#include "dis-asm.h"
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2015-03-30 15:05:57 +08:00
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/* TODO: Tracing should be converted to common tracing module. */
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2014-03-14 23:21:23 +08:00
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int trace = 0;
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int disas = 0;
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int trace_funcs = 0;
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static struct disassemble_info info;
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static char opbuf[1000];
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static int
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op_printf (char *buf, char *fmt, ...)
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{
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int ret;
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va_list ap;
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va_start (ap, fmt);
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ret = vsprintf (opbuf + strlen (opbuf), fmt, ap);
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va_end (ap);
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return ret;
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}
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static int
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sim_dis_read (bfd_vma memaddr ATTRIBUTE_UNUSED,
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bfd_byte * ptr,
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unsigned int length,
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struct disassemble_info * info)
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{
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ARMword val = (ARMword) *((ARMword *) info->application_data);
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while (length--)
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{
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* ptr ++ = val & 0xFF;
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val >>= 8;
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}
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return 0;
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}
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void
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print_insn (ARMword instr)
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{
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int size;
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opbuf[0] = 0;
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info.application_data = & instr;
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size = print_insn_little_arm (0, & info);
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fprintf (stderr, " %*s\n", size, opbuf);
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}
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2003-03-20 20:25:07 +08:00
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/* Cirrus DSP registers.
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We need to define these registers outside of maverick.c because
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maverick.c might not be linked in unless --target=arm9e-* in which
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case wrapper.c will not compile because it tries to access Cirrus
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registers. This should all go away once we get the Cirrus and ARM
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Coprocessor to coexist in armcopro.c-- aldyh. */
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struct maverick_regs
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{
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union
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{
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int i;
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float f;
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} upper;
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2015-07-14 19:06:33 +08:00
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2003-03-20 20:25:07 +08:00
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union
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{
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int i;
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float f;
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} lower;
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};
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union maverick_acc_regs
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{
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long double ld; /* Acc registers are 72-bits. */
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};
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struct maverick_regs DSPregs[16];
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union maverick_acc_regs DSPacc[4];
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ARMword DSPsc;
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2000-02-05 15:30:26 +08:00
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static void
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2014-03-18 22:16:54 +08:00
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init (void)
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1999-04-16 09:35:26 +08:00
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{
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static int done;
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if (!done)
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{
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2000-02-05 15:30:26 +08:00
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ARMul_EmulateInit ();
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1999-04-16 09:35:26 +08:00
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state = ARMul_NewState ();
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2016-01-03 06:46:16 +08:00
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state->bigendSig = (CURRENT_TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? HIGH : LOW);
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2000-02-05 15:30:26 +08:00
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ARMul_MemoryInit (state, mem_size);
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ARMul_OSInit (state);
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2015-03-30 14:41:51 +08:00
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state->verbose = 0;
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1999-04-16 09:35:26 +08:00
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done = 1;
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}
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}
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2000-02-05 15:30:26 +08:00
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void
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2014-01-05 12:43:21 +08:00
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ARMul_ConsolePrint (ARMul_State * state,
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const char * format,
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...)
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1999-04-16 09:35:26 +08:00
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{
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va_list ap;
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if (state->verbose)
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{
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va_start (ap, format);
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vprintf (format, ap);
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va_end (ap);
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}
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}
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int
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2014-03-18 22:16:54 +08:00
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sim_write (SIM_DESC sd ATTRIBUTE_UNUSED,
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SIM_ADDR addr,
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const unsigned char * buffer,
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int size)
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1999-04-16 09:35:26 +08:00
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{
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int i;
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2000-09-16 07:55:50 +08:00
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1999-04-16 09:35:26 +08:00
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init ();
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2000-09-16 07:55:50 +08:00
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1999-04-16 09:35:26 +08:00
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for (i = 0; i < size; i++)
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2001-02-28 09:04:24 +08:00
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ARMul_SafeWriteByte (state, addr + i, buffer[i]);
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2000-09-16 07:55:50 +08:00
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1999-04-16 09:35:26 +08:00
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return size;
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}
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int
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2014-03-18 22:16:54 +08:00
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sim_read (SIM_DESC sd ATTRIBUTE_UNUSED,
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SIM_ADDR addr,
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unsigned char * buffer,
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int size)
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1999-04-16 09:35:26 +08:00
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{
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int i;
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2001-02-28 09:04:24 +08:00
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1999-04-16 09:35:26 +08:00
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init ();
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2002-01-09 23:08:21 +08:00
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1999-04-16 09:35:26 +08:00
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for (i = 0; i < size; i++)
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2001-02-28 09:04:24 +08:00
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buffer[i] = ARMul_SafeReadByte (state, addr + i);
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1999-04-16 09:35:26 +08:00
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return size;
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}
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int
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2014-03-18 22:16:54 +08:00
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sim_stop (SIM_DESC sd ATTRIBUTE_UNUSED)
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1999-04-16 09:35:26 +08:00
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{
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1999-04-27 02:34:20 +08:00
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state->Emulate = STOP;
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stop_simulator = 1;
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return 1;
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1999-04-16 09:35:26 +08:00
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}
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void
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2014-03-18 22:16:54 +08:00
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sim_resume (SIM_DESC sd ATTRIBUTE_UNUSED,
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int step,
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int siggnal ATTRIBUTE_UNUSED)
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1999-04-16 09:35:26 +08:00
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{
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state->EndCondition = 0;
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1999-04-27 02:34:20 +08:00
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stop_simulator = 0;
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1999-04-16 09:35:26 +08:00
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if (step)
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{
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state->Reg[15] = ARMul_DoInstr (state);
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if (state->EndCondition == 0)
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state->EndCondition = RDIError_BreakpointReached;
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}
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else
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{
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2000-02-05 15:30:26 +08:00
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state->NextInstr = RESUME; /* treat as PC change */
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1999-04-16 09:35:26 +08:00
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state->Reg[15] = ARMul_DoProg (state);
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}
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FLUSHPIPE;
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}
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SIM_RC
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2014-03-18 22:16:54 +08:00
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sim_create_inferior (SIM_DESC sd ATTRIBUTE_UNUSED,
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struct bfd * abfd,
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2016-01-03 14:51:44 +08:00
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char * const *argv,
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char * const *env)
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1999-04-16 09:35:26 +08:00
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{
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2000-02-05 15:30:26 +08:00
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int argvlen = 0;
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2000-07-04 15:18:18 +08:00
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int mach;
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1999-04-16 09:35:26 +08:00
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char **arg;
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2013-10-30 00:43:07 +08:00
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init ();
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1999-04-16 09:35:26 +08:00
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if (abfd != NULL)
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2013-10-30 00:20:48 +08:00
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{
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ARMul_SetPC (state, bfd_get_start_address (abfd));
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mach = bfd_get_mach (abfd);
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}
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1999-04-16 09:35:26 +08:00
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else
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2013-10-30 00:20:48 +08:00
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{
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ARMul_SetPC (state, 0); /* ??? */
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mach = 0;
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}
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2000-07-04 15:18:18 +08:00
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Add support for ARM v6 instructions.
* Makefile.in (SIM_EXTRA_CFLAGS): Add -lm.
* armdefs.h (ARMdval, ARMfval): New types.
(ARM_VFP_reg): New union.
(struct ARMul_State): Add VFP_Reg and FPSCR fields.
(VFP_fval, VFP_uword, VFP_sword, VFP_dval, VFP_dword): Accessor
macros for the new VFP_Reg field.
* armemu.c (handle_v6_insn): Add code to handle MOVW, MOVT,
QADD16, QASX, QSAX, QSUB16, QADD8, QSUB8, UADD16, USUB16, UADD8,
USUB8, SEL, REV, REV16, RBIT, BFC, BFI, SBFX and UBFX
instructions.
(handle_VFP_move): New function.
(ARMul_Emulate16): Add checks for newly supported v6
instructions. Add support for VMRS, VMOV and MRC instructions.
(Multiply64): Allow nRdHi == nRm and/or nRdLo == nRm when
operating in v6 mode.
* armemu.h (t_resolved): Define.
* armsupp.c: Include math.h.
(handle_VFP_xfer): New function. Handles VMOV, VSTM, VSTR, VPUSH,
VSTM, VLDM and VPOP instructions.
(ARMul_LDC): Test for co-processor 10 or 11 and pass call to the
new handle_VFP_xfer function.
(ARMul_STC): Likewise.
(handle_VFP_op): New function. Handles VMLA, VMLS, VNMLA, VNMLS,
VNMUL, VMUL, VADD, VSUB, VDIV, VMOV, VABS, VNEG, VSQRT, VCMP,
VCMPE and VCVT instructions.
(ARMul_CDP): Test for co-processor 10 or 11 and pass call to the
new handle_VFP_op function.
* thumbemu.c (tBIT, tBITS, ntBIT, ntBITS): New macros.
(test_cond): New function. Tests a condition and returns non-zero
if the condition has been met.
(handle_IT_block): New function.
(in_IT_block): New function.
(IT_block_allow): New function.
(ThumbExpandImm): New function.
(handle_T2_insn): New function. Handles T2 thumb instructions.
(handle_v6_thumb_insn): Add next_instr and pc parameters.
(ARMul_ThumbDecode): Add support for IT blocks. Add support for
v6 instructions.
* wrapper.c (sim_create_inferior): Detect a thumb address and call
SETT appropriately.
2015-06-29 02:14:36 +08:00
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#ifdef MODET
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if (abfd != NULL && (bfd_get_start_address (abfd) & 1))
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SETT;
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#endif
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2000-09-16 07:55:50 +08:00
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switch (mach)
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{
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default:
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2002-01-09 23:08:21 +08:00
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(*sim_callback->printf_filtered)
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(sim_callback,
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2002-05-27 22:12:00 +08:00
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"Unknown machine type '%d'; please update sim_create_inferior.\n",
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mach);
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2000-09-16 07:55:50 +08:00
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/* fall through */
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2000-11-30 09:55:12 +08:00
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case 0:
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2000-09-16 07:55:50 +08:00
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/* We wouldn't set the machine type with earlier toolchains, so we
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2000-11-30 09:55:12 +08:00
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explicitly select a processor capable of supporting all ARMs in
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32bit mode. */
|
2014-03-14 23:21:23 +08:00
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ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_v6_Prop);
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break;
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2002-01-09 22:59:22 +08:00
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case bfd_mach_arm_XScale:
|
2005-04-25 15:48:59 +08:00
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ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop | ARM_v6_Prop);
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2002-01-09 22:59:22 +08:00
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break;
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2012-06-13 18:07:11 +08:00
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case bfd_mach_arm_iWMMXt2:
|
2003-03-28 01:13:33 +08:00
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case bfd_mach_arm_iWMMXt:
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{
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extern int SWI_vector_installed;
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ARMword i;
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if (! SWI_vector_installed)
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{
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/* Intialise the hardware vectors to zero. */
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if (! SWI_vector_installed)
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for (i = ARMul_ResetV; i <= ARMFIQV; i += 4)
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ARMul_WriteWord (state, i, 0);
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/* ARM_WriteWord will have detected the write to the SWI vector,
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but we want SWI_vector_installed to remain at 0 so that thumb
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|
mode breakpoints will work. */
|
|
|
|
SWI_vector_installed = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop | ARM_iWMMXt_Prop);
|
|
|
|
break;
|
|
|
|
|
2003-03-20 20:25:07 +08:00
|
|
|
case bfd_mach_arm_ep9312:
|
|
|
|
ARMul_SelectProcessor (state, ARM_v4_Prop | ARM_ep9312_Prop);
|
|
|
|
break;
|
|
|
|
|
2000-11-30 09:55:12 +08:00
|
|
|
case bfd_mach_arm_5:
|
2002-02-05 19:22:26 +08:00
|
|
|
if (bfd_family_coff (abfd))
|
|
|
|
{
|
|
|
|
/* This is a special case in order to support COFF based ARM toolchains.
|
|
|
|
The COFF header does not have enough room to store all the different
|
|
|
|
kinds of ARM cpu, so the XScale, v5T and v5TE architectures all default
|
|
|
|
to v5. (See coff_set_flags() in bdf/coffcode.h). So if we see a v5
|
|
|
|
machine type here, we assume it could be any of the above architectures
|
|
|
|
and so select the most feature-full. */
|
|
|
|
ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
/* Otherwise drop through. */
|
2002-02-05 00:27:22 +08:00
|
|
|
|
2000-11-30 09:55:12 +08:00
|
|
|
case bfd_mach_arm_5T:
|
|
|
|
ARMul_SelectProcessor (state, ARM_v5_Prop);
|
|
|
|
break;
|
2000-09-16 07:55:50 +08:00
|
|
|
|
2000-11-30 09:55:12 +08:00
|
|
|
case bfd_mach_arm_5TE:
|
|
|
|
ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case bfd_mach_arm_4:
|
|
|
|
case bfd_mach_arm_4T:
|
|
|
|
ARMul_SelectProcessor (state, ARM_v4_Prop);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case bfd_mach_arm_3:
|
|
|
|
case bfd_mach_arm_3M:
|
2000-09-16 07:55:50 +08:00
|
|
|
ARMul_SelectProcessor (state, ARM_Lock_Prop);
|
|
|
|
break;
|
|
|
|
|
2000-11-30 09:55:12 +08:00
|
|
|
case bfd_mach_arm_2:
|
|
|
|
case bfd_mach_arm_2a:
|
2000-09-16 07:55:50 +08:00
|
|
|
ARMul_SelectProcessor (state, ARM_Fix26_Prop);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2014-03-14 23:21:23 +08:00
|
|
|
memset (& info, 0, sizeof (info));
|
|
|
|
INIT_DISASSEMBLE_INFO (info, stdout, op_printf);
|
|
|
|
info.read_memory_func = sim_dis_read;
|
|
|
|
info.arch = bfd_get_arch (abfd);
|
|
|
|
info.mach = bfd_get_mach (abfd);
|
|
|
|
info.endian_code = BFD_ENDIAN_LITTLE;
|
|
|
|
if (info.mach == 0)
|
|
|
|
info.arch = bfd_arch_arm;
|
|
|
|
disassemble_init_for_target (& info);
|
|
|
|
|
1999-04-16 09:35:26 +08:00
|
|
|
if (argv != NULL)
|
|
|
|
{
|
2001-02-15 06:21:20 +08:00
|
|
|
/* Set up the command line by laboriously stringing together
|
|
|
|
the environment carefully picked apart by our caller. */
|
|
|
|
|
|
|
|
/* Free any old stuff. */
|
1999-04-16 09:35:26 +08:00
|
|
|
if (state->CommandLine != NULL)
|
|
|
|
{
|
2000-02-05 15:30:26 +08:00
|
|
|
free (state->CommandLine);
|
1999-04-16 09:35:26 +08:00
|
|
|
state->CommandLine = NULL;
|
|
|
|
}
|
2000-02-05 15:30:26 +08:00
|
|
|
|
2001-02-15 06:21:20 +08:00
|
|
|
/* See how much we need. */
|
1999-04-16 09:35:26 +08:00
|
|
|
for (arg = argv; *arg != NULL; arg++)
|
2000-02-05 15:30:26 +08:00
|
|
|
argvlen += strlen (*arg) + 1;
|
|
|
|
|
2001-02-15 06:21:20 +08:00
|
|
|
/* Allocate it. */
|
2000-02-05 15:30:26 +08:00
|
|
|
state->CommandLine = malloc (argvlen + 1);
|
1999-04-16 09:35:26 +08:00
|
|
|
if (state->CommandLine != NULL)
|
|
|
|
{
|
|
|
|
arg = argv;
|
2000-02-05 15:30:26 +08:00
|
|
|
state->CommandLine[0] = '\0';
|
2001-02-15 06:21:20 +08:00
|
|
|
|
1999-04-16 09:35:26 +08:00
|
|
|
for (arg = argv; *arg != NULL; arg++)
|
|
|
|
{
|
2000-02-05 15:30:26 +08:00
|
|
|
strcat (state->CommandLine, *arg);
|
|
|
|
strcat (state->CommandLine, " ");
|
1999-04-16 09:35:26 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (env != NULL)
|
|
|
|
{
|
2001-02-15 06:21:20 +08:00
|
|
|
/* Now see if there's a MEMSIZE spec in the environment. */
|
1999-04-16 09:35:26 +08:00
|
|
|
while (*env)
|
|
|
|
{
|
2000-02-05 15:30:26 +08:00
|
|
|
if (strncmp (*env, "MEMSIZE=", sizeof ("MEMSIZE=") - 1) == 0)
|
1999-04-16 09:35:26 +08:00
|
|
|
{
|
|
|
|
char *end_of_num;
|
2000-02-05 15:30:26 +08:00
|
|
|
|
2001-02-15 06:21:20 +08:00
|
|
|
/* Set up memory limit. */
|
2000-02-05 15:30:26 +08:00
|
|
|
state->MemSize =
|
|
|
|
strtoul (*env + sizeof ("MEMSIZE=") - 1, &end_of_num, 0);
|
1999-04-16 09:35:26 +08:00
|
|
|
}
|
|
|
|
env++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return SIM_RC_OK;
|
|
|
|
}
|
|
|
|
|
2000-02-05 15:30:26 +08:00
|
|
|
static int
|
2014-03-18 22:16:54 +08:00
|
|
|
frommem (struct ARMul_State *state, unsigned char *memory)
|
1999-04-16 09:35:26 +08:00
|
|
|
{
|
|
|
|
if (state->bigendSig == HIGH)
|
2002-01-09 23:08:21 +08:00
|
|
|
return (memory[0] << 24) | (memory[1] << 16)
|
|
|
|
| (memory[2] << 8) | (memory[3] << 0);
|
1999-04-16 09:35:26 +08:00
|
|
|
else
|
2002-01-09 23:08:21 +08:00
|
|
|
return (memory[3] << 24) | (memory[2] << 16)
|
|
|
|
| (memory[1] << 8) | (memory[0] << 0);
|
1999-04-16 09:35:26 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2014-03-18 22:16:54 +08:00
|
|
|
tomem (struct ARMul_State *state,
|
|
|
|
unsigned char *memory,
|
|
|
|
int val)
|
1999-04-16 09:35:26 +08:00
|
|
|
{
|
|
|
|
if (state->bigendSig == HIGH)
|
|
|
|
{
|
|
|
|
memory[0] = val >> 24;
|
|
|
|
memory[1] = val >> 16;
|
|
|
|
memory[2] = val >> 8;
|
|
|
|
memory[3] = val >> 0;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
memory[3] = val >> 24;
|
|
|
|
memory[2] = val >> 16;
|
|
|
|
memory[1] = val >> 8;
|
|
|
|
memory[0] = val >> 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-12-30 16:28:45 +08:00
|
|
|
static int
|
|
|
|
arm_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
|
1999-04-16 09:35:26 +08:00
|
|
|
{
|
|
|
|
init ();
|
2000-11-30 09:55:12 +08:00
|
|
|
|
2002-06-13 05:19:43 +08:00
|
|
|
switch ((enum sim_arm_regs) rn)
|
2000-05-24 07:52:46 +08:00
|
|
|
{
|
2002-06-13 05:19:43 +08:00
|
|
|
case SIM_ARM_R0_REGNUM:
|
|
|
|
case SIM_ARM_R1_REGNUM:
|
|
|
|
case SIM_ARM_R2_REGNUM:
|
|
|
|
case SIM_ARM_R3_REGNUM:
|
|
|
|
case SIM_ARM_R4_REGNUM:
|
|
|
|
case SIM_ARM_R5_REGNUM:
|
|
|
|
case SIM_ARM_R6_REGNUM:
|
|
|
|
case SIM_ARM_R7_REGNUM:
|
|
|
|
case SIM_ARM_R8_REGNUM:
|
|
|
|
case SIM_ARM_R9_REGNUM:
|
|
|
|
case SIM_ARM_R10_REGNUM:
|
|
|
|
case SIM_ARM_R11_REGNUM:
|
|
|
|
case SIM_ARM_R12_REGNUM:
|
|
|
|
case SIM_ARM_R13_REGNUM:
|
|
|
|
case SIM_ARM_R14_REGNUM:
|
|
|
|
case SIM_ARM_R15_REGNUM: /* PC */
|
|
|
|
case SIM_ARM_FP0_REGNUM:
|
|
|
|
case SIM_ARM_FP1_REGNUM:
|
|
|
|
case SIM_ARM_FP2_REGNUM:
|
|
|
|
case SIM_ARM_FP3_REGNUM:
|
|
|
|
case SIM_ARM_FP4_REGNUM:
|
|
|
|
case SIM_ARM_FP5_REGNUM:
|
|
|
|
case SIM_ARM_FP6_REGNUM:
|
|
|
|
case SIM_ARM_FP7_REGNUM:
|
|
|
|
case SIM_ARM_FPS_REGNUM:
|
|
|
|
ARMul_SetReg (state, state->Mode, rn, frommem (state, memory));
|
|
|
|
break;
|
|
|
|
|
|
|
|
case SIM_ARM_PS_REGNUM:
|
2000-05-24 07:52:46 +08:00
|
|
|
state->Cpsr = frommem (state, memory);
|
2002-05-27 22:12:00 +08:00
|
|
|
ARMul_CPSRAltered (state);
|
2002-06-13 05:19:43 +08:00
|
|
|
break;
|
|
|
|
|
2003-03-20 20:25:07 +08:00
|
|
|
case SIM_ARM_MAVERIC_COP0R0_REGNUM:
|
|
|
|
case SIM_ARM_MAVERIC_COP0R1_REGNUM:
|
|
|
|
case SIM_ARM_MAVERIC_COP0R2_REGNUM:
|
|
|
|
case SIM_ARM_MAVERIC_COP0R3_REGNUM:
|
|
|
|
case SIM_ARM_MAVERIC_COP0R4_REGNUM:
|
|
|
|
case SIM_ARM_MAVERIC_COP0R5_REGNUM:
|
|
|
|
case SIM_ARM_MAVERIC_COP0R6_REGNUM:
|
|
|
|
case SIM_ARM_MAVERIC_COP0R7_REGNUM:
|
|
|
|
case SIM_ARM_MAVERIC_COP0R8_REGNUM:
|
|
|
|
case SIM_ARM_MAVERIC_COP0R9_REGNUM:
|
|
|
|
case SIM_ARM_MAVERIC_COP0R10_REGNUM:
|
|
|
|
case SIM_ARM_MAVERIC_COP0R11_REGNUM:
|
|
|
|
case SIM_ARM_MAVERIC_COP0R12_REGNUM:
|
|
|
|
case SIM_ARM_MAVERIC_COP0R13_REGNUM:
|
|
|
|
case SIM_ARM_MAVERIC_COP0R14_REGNUM:
|
|
|
|
case SIM_ARM_MAVERIC_COP0R15_REGNUM:
|
|
|
|
memcpy (& DSPregs [rn - SIM_ARM_MAVERIC_COP0R0_REGNUM],
|
|
|
|
memory, sizeof (struct maverick_regs));
|
|
|
|
return sizeof (struct maverick_regs);
|
|
|
|
|
|
|
|
case SIM_ARM_MAVERIC_DSPSC_REGNUM:
|
|
|
|
memcpy (&DSPsc, memory, sizeof DSPsc);
|
|
|
|
return sizeof DSPsc;
|
|
|
|
|
2003-03-28 01:13:33 +08:00
|
|
|
case SIM_ARM_IWMMXT_COP0R0_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP0R1_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP0R2_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP0R3_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP0R4_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP0R5_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP0R6_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP0R7_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP0R8_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP0R9_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP0R10_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP0R11_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP0R12_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP0R13_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP0R14_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP0R15_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP1R0_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP1R1_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP1R2_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP1R3_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP1R4_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP1R5_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP1R6_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP1R7_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP1R8_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP1R9_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP1R10_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP1R11_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP1R12_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP1R13_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP1R14_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP1R15_REGNUM:
|
|
|
|
return Store_Iwmmxt_Register (rn - SIM_ARM_IWMMXT_COP0R0_REGNUM, memory);
|
2003-03-30 18:39:22 +08:00
|
|
|
|
2002-06-13 05:19:43 +08:00
|
|
|
default:
|
|
|
|
return 0;
|
2000-05-24 07:52:46 +08:00
|
|
|
}
|
2002-06-13 05:19:43 +08:00
|
|
|
|
2012-08-01 22:38:19 +08:00
|
|
|
return length;
|
1999-04-16 09:35:26 +08:00
|
|
|
}
|
|
|
|
|
2015-12-30 16:28:45 +08:00
|
|
|
static int
|
|
|
|
arm_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
|
1999-04-16 09:35:26 +08:00
|
|
|
{
|
|
|
|
ARMword regval;
|
2012-08-01 22:38:19 +08:00
|
|
|
int len = length;
|
1999-04-16 09:35:26 +08:00
|
|
|
|
|
|
|
init ();
|
2000-11-30 09:55:12 +08:00
|
|
|
|
2002-06-13 05:19:43 +08:00
|
|
|
switch ((enum sim_arm_regs) rn)
|
|
|
|
{
|
|
|
|
case SIM_ARM_R0_REGNUM:
|
|
|
|
case SIM_ARM_R1_REGNUM:
|
|
|
|
case SIM_ARM_R2_REGNUM:
|
|
|
|
case SIM_ARM_R3_REGNUM:
|
|
|
|
case SIM_ARM_R4_REGNUM:
|
|
|
|
case SIM_ARM_R5_REGNUM:
|
|
|
|
case SIM_ARM_R6_REGNUM:
|
|
|
|
case SIM_ARM_R7_REGNUM:
|
|
|
|
case SIM_ARM_R8_REGNUM:
|
|
|
|
case SIM_ARM_R9_REGNUM:
|
|
|
|
case SIM_ARM_R10_REGNUM:
|
|
|
|
case SIM_ARM_R11_REGNUM:
|
|
|
|
case SIM_ARM_R12_REGNUM:
|
|
|
|
case SIM_ARM_R13_REGNUM:
|
|
|
|
case SIM_ARM_R14_REGNUM:
|
|
|
|
case SIM_ARM_R15_REGNUM: /* PC */
|
|
|
|
regval = ARMul_GetReg (state, state->Mode, rn);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case SIM_ARM_FP0_REGNUM:
|
|
|
|
case SIM_ARM_FP1_REGNUM:
|
|
|
|
case SIM_ARM_FP2_REGNUM:
|
|
|
|
case SIM_ARM_FP3_REGNUM:
|
|
|
|
case SIM_ARM_FP4_REGNUM:
|
|
|
|
case SIM_ARM_FP5_REGNUM:
|
|
|
|
case SIM_ARM_FP6_REGNUM:
|
|
|
|
case SIM_ARM_FP7_REGNUM:
|
|
|
|
case SIM_ARM_FPS_REGNUM:
|
|
|
|
memset (memory, 0, length);
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
case SIM_ARM_PS_REGNUM:
|
|
|
|
regval = ARMul_GetCPSR (state);
|
|
|
|
break;
|
|
|
|
|
2003-03-20 20:25:07 +08:00
|
|
|
case SIM_ARM_MAVERIC_COP0R0_REGNUM:
|
|
|
|
case SIM_ARM_MAVERIC_COP0R1_REGNUM:
|
|
|
|
case SIM_ARM_MAVERIC_COP0R2_REGNUM:
|
|
|
|
case SIM_ARM_MAVERIC_COP0R3_REGNUM:
|
|
|
|
case SIM_ARM_MAVERIC_COP0R4_REGNUM:
|
|
|
|
case SIM_ARM_MAVERIC_COP0R5_REGNUM:
|
|
|
|
case SIM_ARM_MAVERIC_COP0R6_REGNUM:
|
|
|
|
case SIM_ARM_MAVERIC_COP0R7_REGNUM:
|
|
|
|
case SIM_ARM_MAVERIC_COP0R8_REGNUM:
|
|
|
|
case SIM_ARM_MAVERIC_COP0R9_REGNUM:
|
|
|
|
case SIM_ARM_MAVERIC_COP0R10_REGNUM:
|
|
|
|
case SIM_ARM_MAVERIC_COP0R11_REGNUM:
|
|
|
|
case SIM_ARM_MAVERIC_COP0R12_REGNUM:
|
|
|
|
case SIM_ARM_MAVERIC_COP0R13_REGNUM:
|
|
|
|
case SIM_ARM_MAVERIC_COP0R14_REGNUM:
|
|
|
|
case SIM_ARM_MAVERIC_COP0R15_REGNUM:
|
|
|
|
memcpy (memory, & DSPregs [rn - SIM_ARM_MAVERIC_COP0R0_REGNUM],
|
|
|
|
sizeof (struct maverick_regs));
|
|
|
|
return sizeof (struct maverick_regs);
|
|
|
|
|
|
|
|
case SIM_ARM_MAVERIC_DSPSC_REGNUM:
|
|
|
|
memcpy (memory, & DSPsc, sizeof DSPsc);
|
|
|
|
return sizeof DSPsc;
|
|
|
|
|
2003-03-28 01:13:33 +08:00
|
|
|
case SIM_ARM_IWMMXT_COP0R0_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP0R1_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP0R2_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP0R3_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP0R4_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP0R5_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP0R6_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP0R7_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP0R8_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP0R9_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP0R10_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP0R11_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP0R12_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP0R13_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP0R14_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP0R15_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP1R0_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP1R1_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP1R2_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP1R3_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP1R4_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP1R5_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP1R6_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP1R7_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP1R8_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP1R9_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP1R10_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP1R11_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP1R12_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP1R13_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP1R14_REGNUM:
|
|
|
|
case SIM_ARM_IWMMXT_COP1R15_REGNUM:
|
|
|
|
return Fetch_Iwmmxt_Register (rn - SIM_ARM_IWMMXT_COP0R0_REGNUM, memory);
|
2003-03-30 18:39:22 +08:00
|
|
|
|
2002-06-13 05:19:43 +08:00
|
|
|
default:
|
|
|
|
return 0;
|
|
|
|
}
|
2002-01-09 22:59:22 +08:00
|
|
|
|
2012-08-01 22:38:19 +08:00
|
|
|
while (len)
|
2002-01-09 22:59:22 +08:00
|
|
|
{
|
|
|
|
tomem (state, memory, regval);
|
|
|
|
|
2012-08-01 22:38:19 +08:00
|
|
|
len -= 4;
|
2002-01-09 22:59:22 +08:00
|
|
|
memory += 4;
|
|
|
|
regval = 0;
|
2015-07-14 19:06:33 +08:00
|
|
|
}
|
2002-01-09 22:59:22 +08:00
|
|
|
|
2012-08-01 22:38:19 +08:00
|
|
|
return length;
|
1999-04-16 09:35:26 +08:00
|
|
|
}
|
|
|
|
|
2002-05-20 22:32:50 +08:00
|
|
|
typedef struct
|
|
|
|
{
|
|
|
|
char * swi_option;
|
|
|
|
unsigned int swi_mask;
|
|
|
|
} swi_options;
|
|
|
|
|
|
|
|
#define SWI_SWITCH "--swi-support"
|
|
|
|
|
|
|
|
static swi_options options[] =
|
|
|
|
{
|
|
|
|
{ "none", 0 },
|
|
|
|
{ "demon", SWI_MASK_DEMON },
|
|
|
|
{ "angel", SWI_MASK_ANGEL },
|
|
|
|
{ "redboot", SWI_MASK_REDBOOT },
|
|
|
|
{ "all", -1 },
|
|
|
|
{ "NONE", 0 },
|
|
|
|
{ "DEMON", SWI_MASK_DEMON },
|
|
|
|
{ "ANGEL", SWI_MASK_ANGEL },
|
|
|
|
{ "REDBOOT", SWI_MASK_REDBOOT },
|
|
|
|
{ "ALL", -1 }
|
|
|
|
};
|
|
|
|
|
|
|
|
|
2015-03-30 15:05:57 +08:00
|
|
|
static int
|
2014-03-18 22:16:54 +08:00
|
|
|
sim_target_parse_command_line (int argc, char ** argv)
|
2002-05-20 22:32:50 +08:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 1; i < argc; i++)
|
|
|
|
{
|
|
|
|
char * ptr = argv[i];
|
|
|
|
int arg;
|
|
|
|
|
|
|
|
if ((ptr == NULL) || (* ptr != '-'))
|
|
|
|
break;
|
|
|
|
|
2014-03-14 23:21:23 +08:00
|
|
|
if (strcmp (ptr, "-t") == 0)
|
|
|
|
{
|
|
|
|
trace = 1;
|
|
|
|
continue;
|
|
|
|
}
|
2015-07-14 19:06:33 +08:00
|
|
|
|
2014-03-14 23:21:23 +08:00
|
|
|
if (strcmp (ptr, "-z") == 0)
|
|
|
|
{
|
|
|
|
/* Remove this option from the argv array. */
|
|
|
|
for (arg = i; arg < argc; arg ++)
|
|
|
|
argv[arg] = argv[arg + 1];
|
|
|
|
argc --;
|
|
|
|
i --;
|
|
|
|
trace_funcs = 1;
|
|
|
|
continue;
|
|
|
|
}
|
2015-07-14 19:06:33 +08:00
|
|
|
|
2014-03-14 23:21:23 +08:00
|
|
|
if (strcmp (ptr, "-d") == 0)
|
|
|
|
{
|
|
|
|
/* Remove this option from the argv array. */
|
|
|
|
for (arg = i; arg < argc; arg ++)
|
|
|
|
argv[arg] = argv[arg + 1];
|
|
|
|
argc --;
|
|
|
|
i --;
|
|
|
|
disas = 1;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2002-05-20 22:32:50 +08:00
|
|
|
if (strncmp (ptr, SWI_SWITCH, sizeof SWI_SWITCH - 1) != 0)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (ptr[sizeof SWI_SWITCH - 1] == 0)
|
|
|
|
{
|
|
|
|
/* Remove this option from the argv array. */
|
|
|
|
for (arg = i; arg < argc; arg ++)
|
|
|
|
argv[arg] = argv[arg + 1];
|
|
|
|
argc --;
|
2015-07-14 19:06:33 +08:00
|
|
|
|
2002-05-20 22:32:50 +08:00
|
|
|
ptr = argv[i];
|
|
|
|
}
|
|
|
|
else
|
|
|
|
ptr += sizeof SWI_SWITCH;
|
|
|
|
|
|
|
|
swi_mask = 0;
|
2015-07-14 19:06:33 +08:00
|
|
|
|
2002-05-20 22:32:50 +08:00
|
|
|
while (* ptr)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
2017-02-13 13:12:35 +08:00
|
|
|
for (i = ARRAY_SIZE (options); i--;)
|
2002-05-20 22:32:50 +08:00
|
|
|
if (strncmp (ptr, options[i].swi_option,
|
|
|
|
strlen (options[i].swi_option)) == 0)
|
|
|
|
{
|
|
|
|
swi_mask |= options[i].swi_mask;
|
|
|
|
ptr += strlen (options[i].swi_option);
|
|
|
|
|
|
|
|
if (* ptr == ',')
|
|
|
|
++ ptr;
|
|
|
|
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (i < 0)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (* ptr != 0)
|
|
|
|
fprintf (stderr, "Ignoring swi options: %s\n", ptr);
|
2015-07-14 19:06:33 +08:00
|
|
|
|
2002-05-20 22:32:50 +08:00
|
|
|
/* Remove this option from the argv array. */
|
|
|
|
for (arg = i; arg < argc; arg ++)
|
|
|
|
argv[arg] = argv[arg + 1];
|
|
|
|
argc --;
|
|
|
|
i --;
|
|
|
|
}
|
|
|
|
return argc;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2014-03-18 22:16:54 +08:00
|
|
|
sim_target_parse_arg_array (char ** argv)
|
2002-05-20 22:32:50 +08:00
|
|
|
{
|
2016-01-03 14:40:46 +08:00
|
|
|
sim_target_parse_command_line (countargv (argv), argv);
|
2002-05-20 22:32:50 +08:00
|
|
|
}
|
|
|
|
|
2015-04-17 14:16:10 +08:00
|
|
|
static sim_cia
|
|
|
|
arm_pc_get (sim_cpu *cpu)
|
|
|
|
{
|
|
|
|
return PC;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
arm_pc_set (sim_cpu *cpu, sim_cia pc)
|
|
|
|
{
|
|
|
|
ARMul_SetPC (state, pc);
|
|
|
|
}
|
|
|
|
|
2015-03-30 15:05:57 +08:00
|
|
|
static void
|
|
|
|
free_state (SIM_DESC sd)
|
2002-05-20 22:32:50 +08:00
|
|
|
{
|
2015-03-30 15:05:57 +08:00
|
|
|
if (STATE_MODULES (sd) != NULL)
|
|
|
|
sim_module_uninstall (sd);
|
|
|
|
sim_cpu_free_all (sd);
|
|
|
|
sim_state_free (sd);
|
2002-05-20 22:32:50 +08:00
|
|
|
}
|
|
|
|
|
1999-04-16 09:35:26 +08:00
|
|
|
SIM_DESC
|
2015-03-30 15:05:57 +08:00
|
|
|
sim_open (SIM_OPEN_KIND kind,
|
|
|
|
host_callback *cb,
|
|
|
|
struct bfd *abfd,
|
2016-01-03 14:51:44 +08:00
|
|
|
char * const *argv)
|
1999-04-16 09:35:26 +08:00
|
|
|
{
|
2015-04-17 14:16:10 +08:00
|
|
|
int i;
|
2015-03-30 15:05:57 +08:00
|
|
|
SIM_DESC sd = sim_state_alloc (kind, cb);
|
|
|
|
SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
|
2014-03-18 22:16:54 +08:00
|
|
|
|
2015-03-30 15:05:57 +08:00
|
|
|
/* The cpu data is kept in a separately allocated chunk of memory. */
|
|
|
|
if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK)
|
|
|
|
{
|
|
|
|
free_state (sd);
|
|
|
|
return 0;
|
|
|
|
}
|
2014-03-18 22:16:54 +08:00
|
|
|
|
2015-03-30 15:05:57 +08:00
|
|
|
if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
|
|
|
|
{
|
|
|
|
free_state (sd);
|
|
|
|
return 0;
|
|
|
|
}
|
2000-02-05 15:30:26 +08:00
|
|
|
|
2016-01-04 10:40:34 +08:00
|
|
|
/* The parser will print an error message for us, so we silently return. */
|
2015-03-30 15:05:57 +08:00
|
|
|
if (sim_parse_args (sd, argv) != SIM_RC_OK)
|
1999-04-16 09:35:26 +08:00
|
|
|
{
|
2015-03-30 15:05:57 +08:00
|
|
|
free_state (sd);
|
|
|
|
return 0;
|
|
|
|
}
|
2000-02-05 15:30:26 +08:00
|
|
|
|
2015-03-30 15:05:57 +08:00
|
|
|
/* Check for/establish the a reference program image. */
|
|
|
|
if (sim_analyze_program (sd,
|
|
|
|
(STATE_PROG_ARGV (sd) != NULL
|
|
|
|
? *STATE_PROG_ARGV (sd)
|
|
|
|
: NULL), abfd) != SIM_RC_OK)
|
|
|
|
{
|
|
|
|
free_state (sd);
|
|
|
|
return 0;
|
|
|
|
}
|
2000-02-05 15:30:26 +08:00
|
|
|
|
2015-03-30 15:05:57 +08:00
|
|
|
/* Configure/verify the target byte order and other runtime
|
|
|
|
configuration options. */
|
|
|
|
if (sim_config (sd) != SIM_RC_OK)
|
|
|
|
{
|
|
|
|
sim_module_uninstall (sd);
|
|
|
|
return 0;
|
|
|
|
}
|
2000-02-05 15:30:26 +08:00
|
|
|
|
2015-03-30 15:05:57 +08:00
|
|
|
if (sim_post_argv_init (sd) != SIM_RC_OK)
|
|
|
|
{
|
|
|
|
/* Uninstall the modules to avoid memory leaks,
|
|
|
|
file descriptor leaks, etc. */
|
|
|
|
sim_module_uninstall (sd);
|
|
|
|
return 0;
|
|
|
|
}
|
2000-02-05 15:30:26 +08:00
|
|
|
|
2015-04-17 14:16:10 +08:00
|
|
|
/* CPU specific initialization. */
|
|
|
|
for (i = 0; i < MAX_NR_PROCESSORS; ++i)
|
|
|
|
{
|
|
|
|
SIM_CPU *cpu = STATE_CPU (sd, i);
|
|
|
|
|
2015-12-30 16:28:45 +08:00
|
|
|
CPU_REG_FETCH (cpu) = arm_reg_fetch;
|
|
|
|
CPU_REG_STORE (cpu) = arm_reg_store;
|
2015-04-17 14:16:10 +08:00
|
|
|
CPU_PC_FETCH (cpu) = arm_pc_get;
|
|
|
|
CPU_PC_STORE (cpu) = arm_pc_set;
|
|
|
|
}
|
|
|
|
|
2015-03-30 15:05:57 +08:00
|
|
|
sim_callback = cb;
|
2000-02-05 15:30:26 +08:00
|
|
|
|
2015-03-30 15:05:57 +08:00
|
|
|
sim_target_parse_arg_array (argv);
|
2000-02-05 15:30:26 +08:00
|
|
|
|
2015-03-30 15:05:57 +08:00
|
|
|
if (argv[1] != NULL)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* Scan for memory-size switches. */
|
|
|
|
for (i = 0; (argv[i] != NULL) && (argv[i][0] != 0); i++)
|
|
|
|
if (argv[i][0] == '-' && argv[i][1] == 'm')
|
2002-09-28 07:57:50 +08:00
|
|
|
{
|
|
|
|
if (argv[i][2] != '\0')
|
2015-03-30 15:05:57 +08:00
|
|
|
mem_size = atoi (&argv[i][2]);
|
2002-09-28 07:57:50 +08:00
|
|
|
else if (argv[i + 1] != NULL)
|
|
|
|
{
|
2015-03-30 15:05:57 +08:00
|
|
|
mem_size = atoi (argv[i + 1]);
|
2002-09-28 07:57:50 +08:00
|
|
|
i++;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
sim_callback->printf_filtered (sim_callback,
|
|
|
|
"Missing argument to -m option\n");
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
}
|
1999-04-16 09:35:26 +08:00
|
|
|
}
|
|
|
|
|
2015-03-30 15:05:57 +08:00
|
|
|
return sd;
|
1999-04-16 09:35:26 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2014-03-18 22:16:54 +08:00
|
|
|
sim_stop_reason (SIM_DESC sd ATTRIBUTE_UNUSED,
|
|
|
|
enum sim_stop *reason,
|
|
|
|
int *sigrc)
|
1999-04-16 09:35:26 +08:00
|
|
|
{
|
1999-04-27 02:34:20 +08:00
|
|
|
if (stop_simulator)
|
|
|
|
{
|
|
|
|
*reason = sim_stopped;
|
2012-05-25 00:51:47 +08:00
|
|
|
*sigrc = GDB_SIGNAL_INT;
|
1999-04-27 02:34:20 +08:00
|
|
|
}
|
|
|
|
else if (state->EndCondition == 0)
|
1999-04-16 09:35:26 +08:00
|
|
|
{
|
|
|
|
*reason = sim_exited;
|
|
|
|
*sigrc = state->Reg[0] & 255;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
*reason = sim_stopped;
|
|
|
|
if (state->EndCondition == RDIError_BreakpointReached)
|
2012-05-25 00:51:47 +08:00
|
|
|
*sigrc = GDB_SIGNAL_TRAP;
|
2003-03-28 01:13:33 +08:00
|
|
|
else if ( state->EndCondition == RDIError_DataAbort
|
|
|
|
|| state->EndCondition == RDIError_AddressException)
|
2012-05-25 00:51:47 +08:00
|
|
|
*sigrc = GDB_SIGNAL_BUS;
|
1999-04-16 09:35:26 +08:00
|
|
|
else
|
|
|
|
*sigrc = 0;
|
|
|
|
}
|
|
|
|
}
|