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binutils-gdb/sim/bfin/ChangeLog

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sim: gpio: add output support Make all of the pins bidirectional, and support sending signals when software drives the pins as outputs. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-26 13:47:14 +08:00
2011-04-26 Mike Frysinger <vapier@gentoo.org>
* dv-bfin_gpio.c (bfin_gpio_forward_ouput): New function.
(bfin_gpio_io_write_buffer): Store the current port state into
"data", and call bfin_gpio_forward_ouput when the data or dir
MMRs are updated.
(bfin_gpio_ports): Change p0..p15 to bidirect_port.
sim: gpio: update mask a/b signals better When the mask a/b MMRs are written, the output signal might change levels (as pins are [un]masked), so make sure we update the output level. Further, make sure we handle edge ints correctly by first sending a high signal followed by a low signal. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-26 13:46:02 +08:00
2011-04-26 Mike Frysinger <vapier@gentoo.org>
* dv-bfin_gpio.c (bfin_gpio): Add "int_state" member.
(bfin_gpio_forward_int, bfin_gpio_forward_ints): New functions.
(bfin_gpio_io_write_buffer): Call bfin_gpio_forward_int when the
mask a or mask b MMRs are written.
(bfin_gpio_port_event): When handling edge gpios, set the bit in
int_state, call bfin_gpio_forward_ints, and then clear the bit.
When handling level gpios, clear/set the bit in int_state rather
than returning immediately. Call bfin_gpio_forward_ints instead
of checking mask[ab] and calling HW_TRACE/hw_port_event directly.
sim: bfin: use store buffer with more 32bit insns A bunch of 32bit insns were not using the store buffer, so when they were used in parallel insns, they would incorrectly clobber a register early. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-17 01:37:55 +08:00
2011-04-16 Mike Frysinger <vapier@gentoo.org>
* bfin-sim.c (decode_dsp32alu_0): Call STORE instead of SET_DREG for
BYTEOP2P, BYTEOP3P, BYTEOP1P, BYTEOP16P, BYTEOP16M, BYTEPACK, and
BYTEUNPACK.
(decode_dsp32shift_0): Call STORE instead of SET_DREG for PACK,
BITMUX, EXTRACT, DEPOSIT, ALIGN8, ALIGN16, and ALIGN24.
sim: bfin: handle implicit DISALGNEXCPT with video insns When most video related insns are used in parallel with Ireg loads, the DISALGNEXCPT insn behavior is implicitly in effect. Reported-by: Anton Shokurov <shokurov.anton.v@yandex.ru> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-15 09:21:21 +08:00
2011-04-14 Mike Frysinger <vapier@gentoo.org>
* bfin-sim.c (decode_dsp32alu_0): Set DIS_ALGN_EXPT when handling
BYTEOP2P, BYTEOP3P, SAA, BYTEOP1P, BYTEOP16P, BYTEOP16M, BYTEPACK,
and BYTEUNPACK insns.
sim: bfin: respect the port level on signals to the SIC The SIC latches ints from peripherals to the CEC, but the peripherals need to be able to tell the SIC when to stop. So use the incoming level to figure out when to set the int bits and when to clear it. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-11 13:23:26 +08:00
2011-04-11 Mike Frysinger <vapier@gentoo.org>
* dv-bfin_sic.c (bfin_sic_port_event): New helper function.
(bfin_sic_52x_port_event, bfin_sic_537_port_event,
bfin_sic_54x_port_event, bfin_sic_561_port_event): Include level
in the trace output, and call the new bfin_sic_port_event func.
sim: bfin: add missing GPIO pin 15 Each GPIO block has 16 pins, and I only added 15 in the original port list. So add the missing 16th. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-11 13:22:23 +08:00
2011-04-11 Mike Frysinger <vapier@gentoo.org>
* dv-bfin_gpio.c (bfin_gpio_ports): Add p15.
sim: bfin: add OTP output port This doesn't currently generate any interrupts (as there doesn't appear to be any documentation to *when* it would even do so), but since the HRM does say an interrupt line exists between the OTP and the SIC, add one for completeness sake. This will make a follow up patch easier. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-02 06:32:04 +08:00
2011-04-01 Mike Frysinger <vapier@gentoo.org>
* dv-bfin_otp.c (bfin_otp_ports): Declare.
(bfin_otp_finish): Call set_hw_ports with bfin_otp_ports.
sim: bfin: regen configure to include new cfi device
2011-03-30 02:39:51 +08:00
2011-03-29 Mike Frysinger <vapier@gentoo.org>
* configure: Regenerate after common/aclocal.m4 changes.
sim: bfin: fix sign extension with 16bit acc add insns The current implementation attempts to handle the 16bit sign extension itself. Unfortunately, it gets it right in some cases. So rather than fix that logic, just drop it in favor of using 16bit signed casts. Now gcc will take care of getting the logic right. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-29 09:41:49 +08:00
2011-03-28 Robin Getz <robin.getz@analog.com>
* bfin-sim.c (decode_dsp32alu_0): Cast high 16bits of A0.W to bs16
and add to casted low 16bits of A0.L and store in val0. Cast high
16bits of A1.W to bs16 and add to casted low 16bits of A1.L and
store in val1. Delete bit checks of val0 and val1.
sim: bfin: handle saturation with RND12 sub insns The current handling of the subtraction insn with the RND12 modifier works when saturation isn't involved. So add handling for this edge case to match the hardware. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-27 12:03:05 +08:00
2011-03-26 Robin Getz <robin.getz@analog.com>
* bfin-sim.c (decode_dsp32alu_0): Set result to 0x7FFFFFFF when
the result was 0x80000000 for RND12 subtraction.
sim: bfin: add missing VS set with add/sub insns The 16bit add/sub insns missed setting the VS bit in ASTAT whenever the V bit was also set. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-26 14:02:41 +08:00
2011-03-26 Robin Getz <robin.getz@analog.com>
* bfin-sim.c (decode_dsp32alu_0): Set VS when V is set.
sim: bfin: add hw tracing to gpio/sic port events Makes it a lot easier to find out what's going on with interrupt lines if the ports have tracing output. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-25 08:13:57 +08:00
2011-03-24 Mike Frysinger <vapier@gentoo.org>
* dv-bfin_gpio.c (bfin_gpio_port_event): Call HW_TRACE at every
major code flow point.
* dv-bfin_sic.c (bfin_sic_forward_interrupts): Call HW_TRACE just
before calling hw_port_event on ourselves.
(bfin_sic_52x_port_event, bfin_sic_537_port_event,
bfin_sic_54x_port_event, bfin_sic_561_port_event): Call HW_TRACE
at the start of the function.
sim: bfin: fix GPIO logic bugs when processing events We need the DIR bit cleared, not set, in order for the pin to be treated as an input. When looking up the data value, we need to shift the "level" value over by "my_port" rather than "bit" as the latter has already been shifted over. We also should normalize the "level" coming in from the outside worlds to the set of {0,1} since those are the only values that matter to GPIOs. We need the BOTH bit set, not cleared, in order for the pin to trigger on both edges. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-25 08:13:23 +08:00
2011-03-24 Mike Frysinger <vapier@gentoo.org>
* dv-bfin_gpio.c (bfin_gpio_port_event): Split dir/inen bit checking.
Normalize "level" to 0/1 values. Shift "level" over by "my_port".
Invert port->both bit check.
sim: bfin: fix clear/set/toggle GPIO handling The clear/set/toggle MMRs aren't backed by "real" data; they implicitly perform bit operations on the associated data register. So when we go to process writes to them, we need to adjust the pointer accordingly so that the actual backing data is modified. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-25 08:12:47 +08:00
2011-03-24 Mike Frysinger <vapier@gentoo.org>
* dv-bfin_gpio.c (bfin_gpio_io_write_buffer): Subtract 2 from the
valuep pointer for clear MMRs, 4 for set MMRs, and 6 for toggle MMRs.
sim: bfin: document SIC limitation Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24 11:18:17 +08:00
2011-03-23 Mike Frysinger <vapier@gentoo.org>
* TODO: Document some known SIC issues.
sim: bfin: fix inverted W1C logic When I originally wrote the w1c helper funcs, I used it in a few places. Then I forgot how it worked and when I later documented it, I described the 3rd arg in the exact opposite way it is actually used. This error propagated to a bunch of devices registers that were not explicitly tested (a bunch of the devices are stubs which merely exist to say "no device is connected" to make device drivers happy). So once the documentation is unscrewed, fix all of the broken call sites. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24 11:17:14 +08:00
2011-03-23 Mike Frysinger <vapier@gentoo.org>
* devices.h (dv_w1c): Fix typos in documentation of "bits" arg.
* dv-bfin_cec.c (bfin_cec_io_write_buffer): Pass 0xffee to dv_w1c_4.
* dv-bfin_emac.c (bfin_emac_io_write_buffer): Pass 0xe1 to dv_w1c_4
for systat MMR and -1 to dv_w1c_4 for [rt]x_stky/mmc_[rt]irqs MMRs.
* dv-bfin_eppi.c (bfin_eppi_io_write_buffer): Pass 0x1ff to dv_w1c_2.
* dv-bfin_gpio.c (bfin_gpio_io_write_buffer): Invert bits to dv_w1c_2.
* dv-bfin_jtag.c (bfin_jtag_io_write_buffer): Invert bits to dv_w1c_4.
* dv-bfin_nfc.c (bfin_nfc_io_write_buffer): Invert bits to dv_w1c_2.
* dv-bfin_otp.c (bfin_otp_io_write_buffer): Invert bits to dv_w1c_2.
* dv-bfin_ppi.c (bfin_ppi_io_write_buffer): Invert bits to dv_w1c_2.
* dv-bfin_rtc.c (bfin_rtc_io_write_buffer): Invert bits to dv_w1c_2.
* dv-bfin_spi.c (bfin_spi_io_write_buffer): Invert bits to dv_w1c_2.
* dv-bfin_twi.c (bfin_twi_io_write_buffer): Invert bits to dv_w1c_2.
* dv-bfin_uart2.c (bfin_uart_io_write_buffer): Invert bits to dv_w1c_2.
sim: bfin: define more UART LSR bits We'll need these bits in an upcoming patch, so map out the whole LSR MMR now. Fix up indentation style while we're here. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24 11:16:50 +08:00
2011-03-23 Mike Frysinger <vapier@gentoo.org>
* dv-bfin_uart.h (TFI, BI, FE, PE, OE): Define.
sim: bfin: fix typo in TWI stat reg Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24 11:16:22 +08:00
2011-03-23 Mike Frysinger <vapier@gentoo.org>
* dv-bfin_twi.h (LOSTARB): Rename from LOSTARG.
sim: bfin: update VIT_MAX behavior to match hardware when Acc.X bits are set The Blackfin PRM says that the top 8 bits of the accumulator must be cleared when using the VIT_MAX insn, so the sim has followed this spec. Matching the hardware behavior though when the high bits are not cleared is easy to do and doesn't break existing behavior, so go for it. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24 11:14:20 +08:00
2011-03-23 Robin Getz <robin.getz@analog.com>
* bfin-sim.c (decode_dsp32shift_0): Set acc0 to the unextended
value for the VIT_MAX insn, and mask off the result when done.
sim: bfin: always do 16bit sign extension with the SEARCH insn The Blackfin PRM does not cover this case, but the hardware is clear: even if the search criteria is not met (and thus a new 16bit value is loaded up into the accumulator), the accumulator undergoes 16bit sign extension. So simply reload the low signed 16bits in that case. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24 11:13:32 +08:00
2011-03-23 Robin Getz <robin.getz@analog.com>
* bfin-sim.c (decode_dsp32alu_0): Set A1 to a1_lo when up_hi is false,
and set A0 to a0_lo when up_lo is false.
sim: bfin: update AV and AC ASTAT bits with acc negation The Acc=-Acc insn can overflow or carry with edge values, so make sure we update the ASTAT bits accordingly to match the hardware. Also fix a thinko where we always updated AC0 even when working with A1 regs. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24 11:12:16 +08:00
2011-03-23 Robin Getz <robin.getz@analog.com>
* bfin-sim.c (decode_dsp32alu_0): Call saturate_s40_astat instead of
saturate_s40, and use the v parameter to update the AV bit. Set the
AC bit only when the final result is 0.
sim: bfin: fix thinko in SIC pin encoding When encoding the SIC/pin info into unique input port ids, I used bases of 100 when I meant to use 0x100. Rather than simply fix the decoding math in the different functions, create a few helper macros to simplify the SIC/pin encoding and decoding steps. This makes the resulting tables nice & clear. And now that pins are clear, the 533 and 537 port_event handlers may easily be merged into one. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24 11:11:08 +08:00
2011-03-23 Mike Frysinger <vapier@gentoo.org>
* dv-bfin_sic.c (ENC, DEC_PIN, DEC_SIC): Define.
(bfin_sic_50x_ports, bfin_sic_51x_ports, bfin_sic_52x_ports,
bfin_sic_533_ports, bfin_sic_537_ports, bfin_sic_538_ports,
bfin_sic_54x_ports, bfin_sic_561_ports, bfin_sic_59x_ports):
Encode ids with the ENC macro.
(bfin_sic_52x_port_event, bfin_sic_537_port_event,
bfin_sic_54x_port_event, bfin_sic_561_port_event): Set idx
from my_port with DEC_SIC, and set bit from my_port with DEC_PIN.
(bfin_sic_533_port_event): Delete.
(bfin_sic_finish): Call set_hw_port_event with
bfin_sic_537_port_event for BF533 and BF59x targets.
sim: bfin: allow byteop[123]p src regs to be the same The hardware allows the byteop[123]p insns to use the same src reg pair, so remove the combination check in the sim. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24 11:08:15 +08:00
2011-03-23 Robin Getz <robin.getz@analog.com>
* bfin-sim.c (decode_dsp32alu_0): Drop the src0/src1 check for
BYTEOP1P, BYTEOP2P, and BYTEOP3P insns.
sim: bfin: fix thinko in bfin_gpio bus addresses The bus addresses have to be valid numbers, so 'g' and 'h' won't work. Oddly, the common code silently ignored this which is why I didn't notice in the first place. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24 11:07:33 +08:00
2011-03-23 Mike Frysinger <vapier@gentoo.org>
* machs.c (bf50x_dev, bf512_dev, bf516_dev, bf522_dev, bf526_dev,
bf533_dev, bf534_dev, bf537_dev, bf538_dev, bf561_dev, bf592_dev):
Change bfin_gpio addresses from f/g/h to 5/6/7.
(bfin_model_hw_tree_init): Add the bfin_gpio address base to 'a'.
sim: bfin: check for kill/pread If the host system (like Windows) doesn't support these functions, then make sure we don't use them. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-18 03:03:30 +08:00
2011-03-17 Mike Frysinger <vapier@gentoo.org>
* configure.ac (AC_CHECK_FUNCS): Check for kill and pread.
* configure: Regenerate.
* config.in: Regenerate.
* interp.c (bfin_syscall): Check for HAVE_{KILL,PREAD} before using
kill or pread.
sim: bfin: add GPIO device simulation This takes care of the MMR interface and pushing up interrupts. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-16 05:01:45 +08:00
2011-03-15 Mike Frysinger <vapier@gentoo.org>
* Makefile.in (dv-bfin_gpio.o): New target.
* configure.ac (SIM_AC_OPTION_HARDWARE): Add bfin_gpio.
* configure: Regenerate.
* dv-bfin_gpio.c, dv-bfin_gpio.h: New files.
* machs.c: Include dv-bfin_gpio.h.
(bf50x_mem, bf51x_mem, bf52x_mem, bf531_mem, bf532_mem, bf533_mem,
bf534_mem, bf536_mem, bf537_mem, bf538_mem, bf561_mem, bf592_mem):
Delete GPIO memory stubs.
(bf50x_dev, bf512_dev, bf516_dev, bf522_dev, bf526_dev, bf533_dev,
bf534_dev, bf537_dev, bf538_dev, bf561_dev, bf592_dev): Add GPIO
peripheral devices.
(bfin_model_hw_tree_init): Hook up GPIO interrupts to SIC.
sim: bfin: fix brace style
2011-03-16 04:44:11 +08:00
2011-03-15 Mike Frysinger <vapier@gentoo.org>
* bfroms/bf50x-0.0.h, bfroms/bf51x-0.0.h, bfroms/bf51x-0.1.h,
bfroms/bf51x-0.2.h, bfroms/bf526-0.0.h, bfroms/bf526-0.1.h,
bfroms/bf527-0.0.h, bfroms/bf527-0.1.h, bfroms/bf527-0.2.h,
bfroms/bf533-0.1.h, bfroms/bf533-0.2.h, bfroms/bf533-0.3.h,
bfroms/bf537-0.0.h, bfroms/bf537-0.1.h, bfroms/bf537-0.3.h,
bfroms/bf538-0.0.h, bfroms/bf54x-0.0.h, bfroms/bf54x-0.1.h,
bfroms/bf54x-0.2.h, bfroms/bf54x_l1-0.0.h, bfroms/bf54x_l1-0.1.h,
bfroms/bf54x_l1-0.2.h, bfroms/bf561-0.5.h, bfroms/bf59x-0.0.h,
bfroms/bf59x_l1-0.1.h, dv-bfin_cec.c, dv-bfin_ctimer.c,
dv-bfin_dma.c, dv-bfin_dmac.c, dv-bfin_ebiu_amc.c,
dv-bfin_ebiu_ddrc.c, dv-bfin_ebiu_sdc.c, dv-bfin_emac.c,
dv-bfin_eppi.c, dv-bfin_evt.c, dv-bfin_gptimer.c, dv-bfin_jtag.c,
dv-bfin_mmu.c, dv-bfin_nfc.c, dv-bfin_otp.c, dv-bfin_pll.c,
dv-bfin_ppi.c, dv-bfin_rtc.c, dv-bfin_sic.c, dv-bfin_spi.c,
dv-bfin_trace.c, dv-bfin_twi.c, dv-bfin_uart.c, dv-bfin_uart2.c,
dv-bfin_wdog.c, dv-bfin_wp.c, dv-eth_phy.c, gui.c,
linux-fixed-code.h, linux-targ-map.h, machs.c, Makefile.in: Fix style.
sim: bfin: handle AZ updates with 16bit adds/subs We weren't updating AZ when doing a 16bit add or sub insn. Implement it. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-16 04:10:40 +08:00
2011-03-15 Robin Getz <robin.getz@analog.com>
* bfin-sim.c (decode_dsp32alu_0): Set AZ based on val for 16bit adds
and subs.
sim: bfin: skip acc/ASTAT updates for moves No point in moving unchanged acc values to the acc regs, and avoid updating the acc ASTAT bits when only reading. This fixes incorrect changing of the ASTAT bits when they're only being read. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-16 04:10:12 +08:00
2011-03-15 Robin Getz <robin.getz@analog.com>
* bfin-sim.c (decode_macfunc): Move acc STOREs behind op != 3 check.
sim: bfin: handle AN (negative overflows) in dsp mult insns The current dsp mult handler does not take care of overflows which turn values negative (and thus set AN in ASTAT). So implement it. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-16 04:09:39 +08:00
2011-03-15 Robin Getz <robin.getz@analog.com>
* bfin-sim.c (decode_macfunc): New neg parameter. Set when the
high bit is set after extract_mult.
(decode_dsp32mac_0): Declare n_1 and n_0. Pass to the decode_macfunc
functions. Use these to update the AN bit.
sim: bfin: handle V overflows in dsp mult insns The current dsp mult handler does not take care of overflows and updating the V ASTAT bit. So implement it. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-16 04:09:09 +08:00
2011-03-15 Robin Getz <robin.getz@analog.com>
* bfin-sim.c (decode_dsp32mult_0): Declare v_i0 and v_i1. Pass to
the extract_mult functions. Include these when updating the V, VS,
and V_COPY bits.
sim: bfin: decode ASTAT on failure When testing ASTAT regs, specific bit differences carry a lot more meaning than when checking the value of a data register. So automatically decode the bits of the two values and print things out so that people don't have to manually do it themselves every time. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-16 04:08:27 +08:00
2011-03-15 Robin Getz <robin.getz@analog.com>
* bfin-sim.c (astat_names): New global bit array.
(decode_CC2stat_0): Delete local astat_name and astat_names.
(decode_psedodbg_assert_0): Move hardcoded offset into a variable.
Print out ASTAT bit values when checking an ASTAT register.
sim: bfin: handle saturation with fract multiplications The saturation behavior with fract modes differs from non-fract modes. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-16 04:04:04 +08:00
2010-03-15 Robin Getz <robin.getz@analog.com>
* bfin-sim.c (extract_mult): Handle M_IU.
sim: bfin: forgot to cvs add the changelog
2011-03-15 06:24:30 +08:00
2011-03-05 Mike Frysinger <vapier@gentoo.org>
* Makefile.in, TODO, aclocal.m4, bfin-sim.c, bfin-sim.h,
bfroms/all.h, bfroms/bf50x-0.0.h, bfroms/bf51x-0.0.h,
bfroms/bf51x-0.1.h, bfroms/bf51x-0.2.h, bfroms/bf526-0.0.h,
bfroms/bf526-0.1.h, bfroms/bf527-0.0.h, bfroms/bf527-0.1.h,
bfroms/bf527-0.2.h, bfroms/bf533-0.1.h, bfroms/bf533-0.2.h,
bfroms/bf533-0.3.h, bfroms/bf537-0.0.h, bfroms/bf537-0.1.h,
bfroms/bf537-0.3.h, bfroms/bf538-0.0.h, bfroms/bf54x-0.0.h,
bfroms/bf54x-0.1.h, bfroms/bf54x-0.2.h, bfroms/bf54x_l1-0.0.h,
bfroms/bf54x_l1-0.1.h, bfroms/bf54x_l1-0.2.h, bfroms/bf561-0.5.h,
bfroms/bf59x-0.0.h, bfroms/bf59x_l1-0.1.h, config.in, configure,
configure.ac, devices.c, devices.h, dv-bfin_cec.c, dv-bfin_cec.h,
dv-bfin_ctimer.c, dv-bfin_ctimer.h, dv-bfin_dma.c, dv-bfin_dma.h,
dv-bfin_dmac.c, dv-bfin_dmac.h, dv-bfin_ebiu_amc.c, dv-bfin_ebiu_amc.h,
dv-bfin_ebiu_ddrc.c, dv-bfin_ebiu_ddrc.h, dv-bfin_ebiu_sdc.c,
dv-bfin_ebiu_sdc.h, dv-bfin_emac.c, dv-bfin_emac.h, dv-bfin_eppi.c,
dv-bfin_eppi.h, dv-bfin_evt.c, dv-bfin_evt.h, dv-bfin_gptimer.c,
dv-bfin_gptimer.h, dv-bfin_jtag.c, dv-bfin_jtag.h, dv-bfin_mmu.c,
dv-bfin_mmu.h, dv-bfin_nfc.c, dv-bfin_nfc.h, dv-bfin_otp.c,
dv-bfin_otp.h, dv-bfin_pll.c, dv-bfin_pll.h, dv-bfin_ppi.c,
dv-bfin_ppi.h, dv-bfin_rtc.c, dv-bfin_rtc.h, dv-bfin_sic.c,
dv-bfin_sic.h, dv-bfin_spi.c, dv-bfin_spi.h, dv-bfin_trace.c,
dv-bfin_trace.h, dv-bfin_twi.c, dv-bfin_twi.h, dv-bfin_uart.c,
dv-bfin_uart.h, dv-bfin_uart2.c, dv-bfin_uart2.h, dv-bfin_wdog.c,
dv-bfin_wdog.h, dv-bfin_wp.c, dv-bfin_wp.h, dv-eth_phy.c, gui.c,
gui.h, insn_list.def, interp.c, linux-fixed-code.h, linux-fixed-code.s,
linux-targ-map.h, machs.c, machs.h, proc_list.def, sim-main.h,
tconfig.in: New Blackfin port.
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