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Add markers for 2.43 branch/release
2024-07-20 19:43:19 +08:00
2024-07-20 Nick Clifton <nickc@redhat.com>
* 2.43 branch point.
bpf: fix bpf expression parsing regression in GAS As a result of a switch instead of an if, as would issue non-specific error messages when it encountered an operand it could not parse in bpf. This patch fixes that regression and adds a test to prevent it from reoccurring. Tested for bpf-unknown-none on x86_64-redhat-linux. gas/ChangeLog: * config/tc-bpf.c (parse_expression): Change switch to if so that error * condition is handled. * testsuite/gas/bpf/bpf.exp: Invoke new test. * testsuite/gas/bpf/indcall-badoperand.d: New test. * testsuite/gas/bpf/indcall-badoperand.l: New test. * testsuite/gas/bpf/indcall-badoperand.s: New test.
2024-02-20 02:24:19 +08:00
2024-02-19 Will Hawkins <hawkinsw@obs.cr>
* config/tc-bpf.c (parse_expression): Change switch to if so that
error condition is handled.
* testsuite/gas/bpf/indcall-badoperand.d: New test.
* testsuite/gas/bpf/indcall-badoperand.l: Likewise.
* testsuite/gas/bpf/indcall-badoperand.s: Likewise.
* testsuite/gas/bpf/bpf.exp: Invoke new test.
bpf: gas: avoid UB in pointer subtraction The PARSE_ERROR macro in md_assemble performs pointer subtraction. If parse_expression returns NULL then the later will be part of the subtraction and therefore UB will be incurred. This patch changes md_assemble to: 1. Accommodate all invocations to parse_expression to the fact it will return NULL when a parse error occurs. 2. Avoid UB in PARSE_ERROR. Tested in bpf-unknown-none target / x86_64-linux-gnu host. gas/ChangeLog: * config/tc-bpf.c (md_assemble): Fix to take into account that parse_expression can return NULL. (PARSE_ERROR): Avoid passing invalid length to parse_error.
2024-02-20 03:39:48 +08:00
2024-02-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-bpf.c (md_assemble): Fix to take into account that
parse_expression can return NULL.
(PARSE_ERROR): Avoid passing invalid length to parse_error.
objdump, as: add callx support for BPF CPU v1 Albeit not being a currently valid BPF instruction, callx is generated by both clang and GCC when BPF programs are compiled unoptimized. Until now, GCC would emit it only whe using the experimental compiler-testing cpu version xbpf, whereas clang would emit it from v1. This patch makes GAS to accept callx also starting with cpu v1. opcodes/ChangeLog * bpf-opc.c: Move callx into the v1 BPF CPU variant. gas/ChangeLog * testsuite/gas/bpf/indcall-1-pseudoc.d: Do not select xbpf cpu version. * testsuite/gas/bpf/indcall-1.d: Likewise.
2024-02-15 22:11:44 +08:00
2024-02-15 Will Hawkins <hawkinsw@obs.cr>
* testsuite/gas/bpf/indcall-1-pseudoc.d: Do not select xbpf cpu
version.
* testsuite/gas/bpf/indcall-1.d: Likewise.
arc: Put DBNZ instruction to a separate class DBNZ instruction decrements its source register operand, and if the result is non-zero it branches to the location defined by a signed half-word displacement operand. DBNZ instruction is in BRANCH class as other branch instrucitons like B, Bcc, etc. However, DBNZ is the only branch instruction that stores a branch offset in the second operand. Thus it must be placed in a distinct class and treated differently. For example, current logic of arc_insn_get_branch_target in GDB assumes that a branch offset is always stored in the first operand for BRANCH class and it's wrong for DBNZ. include/ChangeLog: 2024-02-14 Yuriy Kolerov <ykolerov@synopsys.com> * opcode/arc.h (enum insn_class_t): Add DBNZ class. opcodes/ChangeLog: 2024-02-14 Yuriy Kolerov <ykolerov@synopsys.com> * arc-tbl.h (dbnz): Use "DBNZ" class. * arc-dis.c (arc_opcode_to_insn_type): Handle "DBNZ" class. gas/ChangeLog: 2024-02-14 Yuriy Kolerov <ykolerov@synopsys.com> * config/tc-arc.c (is_br_jmp_insn_p): Add check against "DBNZ".
2024-02-09 22:27:06 +08:00
2024-02-14 Yuriy Kolerov <ykolerov@synopsys.com>
* config/tc-arc.c (is_br_jmp_insn_p): Add check against "DBNZ".
bpf: there is no ldinddw nor ldabsdw instructions There are no legacy ldind nor ldabs BPF instructions with BPF_SIZE_DW. For some reason we were (incorrectly) supporting these. This patch updates the opcodes so the instructions get removed and modifies the GAS manual and testsuite accordingly. See discussion at https://lore.kernel.org/bpf/110aad7a-f8a3-46ed-9fda-2f8ee54dcb89@linux.dev Tested in bpf-uknonwn-none target, x86-64-linux-gnu host. include/ChangeLog: 2024-01-29 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/bpf.h (enum bpf_insn_id): Remove BPF_INSN_LDINDDW and BPF_INSN_LDABSDW instructions. opcodes/ChangeLog: 2024-01-29 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-opc.c (bpf_opcodes): Remove BPF_INSN_LDINDDW and BPF_INSN_LDABSDW instructions. gas/ChangeLog: 2024-01-29 Jose E. Marchesi <jose.marchesi@oracle.com> * doc/c-bpf.texi (BPF Instructions): There is no indirect 64-bit load instruction. (BPF Instructions): There is no absolute 64-bit load instruction. * testsuite/gas/bpf/mem.s: Update test accordingly. * testsuite/gas/bpf/mem-be-pseudoc.d: Likewise. * testsuite/gas/bpf/mem-be.d: Likewise. * testsuite/gas/bpf/mem-pseudoc.d: Likewise. * testsuite/gas/bpf/mem-pseudoc.s: Likewise. * testsuite/gas/bpf/mem.d: Likewise. * testsuite/gas/bpf/mem.s: Likewise.
2024-01-30 02:22:41 +08:00
2024-01-29 Jose E. Marchesi <jose.marchesi@oracle.com>
* doc/c-bpf.texi (BPF Instructions): There is no indirect 64-bit
load instruction.
(BPF Instructions): There is no absolute 64-bit load instruction.
* testsuite/gas/bpf/mem.s: Update test accordingly.
* testsuite/gas/bpf/mem-be-pseudoc.d: Likewise.
* testsuite/gas/bpf/mem-be.d: Likewise.
* testsuite/gas/bpf/mem-pseudoc.d: Likewise.
* testsuite/gas/bpf/mem-pseudoc.s: Likewise.
* testsuite/gas/bpf/mem.d: Likewise.
* testsuite/gas/bpf/mem.s: Likewise.
Change version to 2.42.50 and regenerate files
2024-01-15 23:13:36 +08:00
2024-01-15 Nick Clifton <nickc@redhat.com>
* configure: Regenerate.
* po/POTFILES.in: Regenerate.
* po/gas.pot: Regenerate.
Add markers for 2.42 branch
2024-01-15 22:42:15 +08:00
2024-01-15 Nick Clifton <nickc@redhat.com>
* 2.42 branch point.
gas: support double-slash line comments in BPF assembly This patch makes the BPF assembler to support double-slash line comments, like the llvm BPF assembler does. At this point both assemblers support the same commenting styles: - Line comments preceded by # or //. - Non-nestable block comments delimited by /* and */. This patch also adds a couple of tests to make sure all the comment styles work in both normal and pseudoc syntax. The manual is also updated to mention double-slash line comments.
2023-11-30 15:34:09 +08:00
2023-11-30 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-bpf.h (DOUBLESLASH_LINE_COMMENTS): Define.
* testsuite/gas/bpf/comments.s: New file.
* testsuite/gas/bpf/comments.d: Likewise.
* testsuite/gas/bpf/comments-pseudoc.d: Likewise.
* testsuite/gas/bpf/comments-pseudoc.s: Likewise.
* testsuite/gas/bpf/bpf.exp: Run comments and comments-pseudoc.
* doc/c-bpf.texi (BPF Special Characters): Document // comments.
* NEWS: Update.
gas: add NEWS entry for change of comment syntax in BPF assembler 2023-11-28 Jose E. Marchesi <jose.marchesi@oracle.com> * NEWS: Add entry about change of comment syntax in the BPF assembler.
2023-11-29 00:51:51 +08:00
2023-11-28 Jose E. Marchesi <jose.marchesi@oracle.com>
* NEWS: Add entry about change of comment syntax in the BPF
assembler.
gas: change meaning of ; in the BPF assembler The BPF assembler in clang uses semi-colon (;) to separate statements, not to be begin line comments. This patch adapts the GNU assembler accordingly. Testsuite and documentation updated accordingly. 2023-11-28 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.c: Semicolon does not start a comment, but separates multiple commands on a single line. * testsuite/gas/bpf/alu-pseudoc.s: Adapt test accordingly. * testsuite/gas/bpf/spacing-pseudoc.s: Likewise. * testsuite/gas/bpf/offset16-overflow.s: Likewise. * testsuite/gas/bpf/jump-relax-jump.s: Likewise. * testsuite/gas/bpf/jump-relax-ja.s: Likewise. * testsuite/gas/bpf/imm32-overflow.s: Likewise. * testsuite/gas/bpf/disp32-overflow.s: Likewise. * testsuite/gas/bpf/disp16-overflow-relax.s: Likewise. * testsuite/gas/bpf/disp16-overflow.s: Likewise. * doc/c-bpf.texi (BPF Special Characters): Update.
2023-11-28 18:58:58 +08:00
2023-11-28 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-bpf.c: Semicolon does not start a comment, but
separates multiple commands on a single line.
* testsuite/gas/bpf/alu-pseudoc.s: Adapt test accordingly.
* testsuite/gas/bpf/spacing-pseudoc.s: Likewise.
* testsuite/gas/bpf/offset16-overflow.s: Likewise.
* testsuite/gas/bpf/jump-relax-jump.s: Likewise.
* testsuite/gas/bpf/jump-relax-ja.s: Likewise.
* testsuite/gas/bpf/imm32-overflow.s: Likewise.
* testsuite/gas/bpf/disp32-overflow.s: Likewise.
* testsuite/gas/bpf/disp16-overflow-relax.s: Likewise.
* testsuite/gas/bpf/disp16-overflow.s: Likewise.
* doc/c-bpf.texi (BPF Special Characters): Update.
MIPS/GAS: Use addiu instead of addi in test elf-rel.
2023-11-23 22:28:31 +08:00
2023-11-23 YunQiang Su <yunqiang.su@cipunited.com>
* testsuite/gas/mips/elf-rel.s: Use addiu in place of addi.
* testsuite/gas/mips/elf-rel.d: Update expected output.
* testsuite/gas/mips/elfel-rel.d: Likewise.
MIPS/GAS: Fix test failures due to jr encoding changes on r6
2023-11-23 20:53:56 +08:00
2023-11-23 YunQiang Su <yunqiang.su@cipunited.com>
* testsuite/gas/mips/branch-section-1.d: Allow for r6 encoding of
JR instruction.
* testsuite/gas/mips/branch-weak-1.d: Likewise.
* testsuite/gas/mips/option-pic-1.d: Likewise.
* testsuite/gas/mips/option-pic-relax-0.d: Likewise.
* testsuite/gas/mips/option-pic-relax-1.d: Likewise.
gas: bpf: do not allow referring to register names as symbols in operands 2023-11-18 Jose E. Marchesi <jemarch@gnu.org> * config/tc-bpf.c (parse_bpf_register): Move before bpf_parse_name. (bpf_parse_name): Do not allow using symbols that are also register names as operands in pseudo-c syntax. * testsuite/gas/bpf/regs-for-symbols-pseudoc.d: New file. * testsuite/gas/bpf/regs-for-symbols-pseudoc.s: Likewise. * testsuite/gas/bpf/regs-for-symbols-pseudoc.l: Likewise. * doc/c-bpf.texi (BPF Registers): Document that it is not possible to refer to register names as symbols in instruction operands.
2023-11-19 01:12:44 +08:00
2023-11-18 Jose E. Marchesi <jemarch@gnu.org>
* config/tc-bpf.c (parse_bpf_register): Move before
bpf_parse_name.
(bpf_parse_name): Do not allow using symbols that are also
register names as operands in pseudo-c syntax.
* testsuite/gas/bpf/regs-for-symbols-pseudoc.d: New file.
* testsuite/gas/bpf/regs-for-symbols-pseudoc.s: Likewise.
* testsuite/gas/bpf/regs-for-symbols-pseudoc.l: Likewise.
* doc/c-bpf.texi (BPF Registers): Document that it is not possible
to refer to register names as symbols in instruction operands.
GAS/MIPS: add "--defsym r6=" for default when it's r6 * testsuite/gas/mips/mips.exp (mips_arch_create): Add "--defsym r6=" to as_flags for r6 targets.
2023-11-15 21:44:42 +08:00
2023-11-15 YunQiang Su <yunqiang.su@cipunited.com>
* testsuite/gas/mips/mips.exp (mips_arch_create): Add "--defsym
r6=" to as_flags for r6 targets.
Finalized intl-update patches * intl: Remove directory. Replaced with out-of-tree GNU gettext. * .gitignore: Add '/gettext*'. * configure.ac (host_libs): Replace intl with gettext. (hbaseargs, bbaseargs, baseargs): Split baseargs into {h,b}baseargs. (skip_barg): New flag. Skips appending current flag to bbaseargs. <library exemptions>: Exempt --with-libintl-{type,prefix} from target and build machine argument passing. * configure: Regenerate. * Makefile.def (host_modules): Replace intl module with gettext module. (configure-ld): Depend on configure-gettext. * Makefile.in: Regenerate. * src-release.sh: Remove references to the intl/ directory.
2023-11-15 20:53:04 +08:00
2023-11-15 Arsen Arsenović <arsen@aarsen.me>
* aclocal.m4: Regenerate.
* configure: Regenerate.
* po/Make-in ($(srcdir)/$(PACKAGE).pot): Output to a .pot
temporary file, to suppress xgettext checking charset names.
MIPS: Fix Irix gas testcases about pdr section * testsuite/gas/elf/elf.exp (section2): Add -mpdr option to assembler command line for mips-irix targets. * testsuite/gas/mips/elf-rel26.d: Add -mpdr command line option. * testsuite/gas/mips/mips16-e.d: Likewise. * testsuite/gas/mips/mips16-f.d: Likewise. * testsuite/gas/mips/mips16-hilo-match.d: Likewise. * testsuite/gas/mips/mips16-e-irix.d: Likewise. * testsuite/gas/mips/call-nonpic-1.d: Adjust regexp to allow for mips-irix targets. * testsuite/gas/mips/irix-no-pdr.d: New test file. * testsuite/gas/mips/mips.exp: Run new test for mips-irix targets.
2023-11-15 18:57:48 +08:00
2023-11-15 YunQiang Su <yunqiang.su@cipunited.com>
* testsuite/gas/elf/elf.exp (section2): Add -mpdr option to
assembler command line for mips-irix targets.
* testsuite/gas/mips/elf-rel26.d: Add -mpdr command line option.
* testsuite/gas/mips/mips16-e.d: Likewise.
* testsuite/gas/mips/mips16-f.d: Likewise.
* testsuite/gas/mips/mips16-hilo-match.d: Likewise.
* testsuite/gas/mips/mips16-e-irix.d: Likewise.
* testsuite/gas/mips/call-nonpic-1.d: Adjust regexp to allow for
mips-irix targets.
* testsuite/gas/mips/irix-no-pdr.d: New test file.
* testsuite/gas/mips/mips.exp: Run new test for mips-irix
targets.
gas: bpf: new test for MOV with C-like numbers ll suffix The BPF pseudo-c syntax supports both MOV and LDDW instructions: mov: r1 = EXPR lddw: r1 = EXPR ll Note that the white space between EXPR and `ll' is necessary in order to avoid ambiguity with the assembler's support for C-like numerical suffixes. This patch adds a new test to the GAS BPF testsuite to make sure that instructions like: r1 = 666ll are interpreted as `mov %r1,666', not as `lddw %r1,666'. This matches clang's assembler behavior. 2023-10-30 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/bpf/alu-pseudoc.s: Add test to make sure C-like suffix `ll' is not interpreted as lddw syntax. * testsuite/gas/bpf/alu-pseudoc.d: Update expected results. * testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.
2023-10-30 22:57:58 +08:00
2023-10-30 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/bpf/alu-pseudoc.s: Add test to make sure C-like
suffix `ll' is not interpreted as lddw syntax.
* testsuite/gas/bpf/alu-pseudoc.d: Update expected results.
* testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.
Fix memory leak in RiscV assembler. PR 30861 * config/tc-riscv.c (riscv_insert_uleb128_fixes): Release duplicated memory.
2023-10-02 23:23:14 +08:00
2023-10-02 Nick Clifton <nickc@redhat.com>
PR 30861
* config/tc-riscv.c (riscv_insert_uleb128_fixes): Release
duplicated memory.
Fix: Use of uninitialized memory * config/tc-riscv.c (riscv_ip_hardcode): Fully initialise the allocated riscv_opcode structure.
2023-09-18 19:03:58 +08:00
2023-09-18 Jacob Navia <jacob@jacob.remcomp.fr>
* config/tc-riscv.c (riscv_ip_hardcode): Fully initialise the
allocated riscv_opcode structure.
bpf: gas: consolidate handling of immediate overflows This commit changes the BPF GAS port in order to handle immediate overflows the same way than the clang BPF assembler: - For an immediate field of N bits, any written number (positive or negative) whose two's complement encoding fit in N its is accepted. This means that -2 is the same than 0xffffffe. It is up to the instructions to decide how to interpret the encoded value. - Immediate fields in jump instructions are no longer relaxed. Relaxing to jump instructions with wider range is only performed when expressions are involved. - The manual is updated to document this, and testsuite adapted accordingly. Tested in x86_64-linux-gnu host, bpf-unknown-none target. gas/ChangeLog: 2023-08-17 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.c (check_immediate_overflow): New function. (encode_insn): Use check_immediate_overflow. (md_assemble): Do not relax instructions with constant disp16 fields. * doc/c-bpf.texi (BPF Instructions): Add note about how numerical literal values are interpreted for instruction immediate operands. * testsuite/gas/bpf/disp16-overflow.s: Adapt accordingly. * testsuite/gas/bpf/jump-relax-jump.s: Likewise. * testsuite/gas/bpf/jump-relax-jump.d: Likewise. * testsuite/gas/bpf/jump-relax-jump-be.d: Likewise. * testsuite/gas/bpf/jump-relax-ja.s: Likewise. * testsuite/gas/bpf/jump-relax-ja.d: Likewise. * testsuite/gas/bpf/jump-relax-ja-be.d: Likewise. * testsuite/gas/bpf/disp16-overflow-relax.l: Likewise. * testsuite/gas/bpf/imm32-overflow.s: Likewise. * testsuite/gas/bpf/disp32-overflow.s: Likewise. * testsuite/gas/bpf/disp16-overflow.l: Likewise. * testsuite/gas/bpf/disp32-overflow.l: Likewise. * testsuite/gas/bpf/imm32-overflow.l: Likewise. * testsuite/gas/bpf/offset16-overflow.l: Likewise.
2023-08-17 15:38:37 +08:00
2023-08-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-bpf.c (check_immediate_overflow): New function.
(encode_insn): Use check_immediate_overflow.
(md_assemble): Do not relax instructions with
constant disp16 fields.
* doc/c-bpf.texi (BPF Instructions): Add note about how numerical
literal values are interpreted for instruction immediate operands.
* testsuite/gas/bpf/disp16-overflow.s: Adapt accordingly.
* testsuite/gas/bpf/jump-relax-jump.s: Likewise.
* testsuite/gas/bpf/jump-relax-jump.d: Likewise.
* testsuite/gas/bpf/jump-relax-jump-be.d: Likewise.
* testsuite/gas/bpf/jump-relax-ja.s: Likewise.
* testsuite/gas/bpf/jump-relax-ja.d: Likewise.
* testsuite/gas/bpf/jump-relax-ja-be.d: Likewise.
* testsuite/gas/bpf/disp16-overflow-relax.l: Likewise.
* testsuite/gas/bpf/imm32-overflow.s: Likewise.
* testsuite/gas/bpf/disp32-overflow.s: Likewise.
* testsuite/gas/bpf/disp16-overflow.l: Likewise.
* testsuite/gas/bpf/disp32-overflow.l: Likewise.
* testsuite/gas/bpf/imm32-overflow.l: Likewise.
* testsuite/gas/bpf/offset16-overflow.l: Likewise.
Revert "2.41 Release sources" This reverts commit 675b9d612cc59446e84e2c6d89b45500cb603a8d. See https://sourceware.org/pipermail/binutils/2023-August/128761.html.
2023-08-02 19:06:23 +08:00
2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com>
bpf: include, bfd, opcodes: add EF_BPF_CPUVER ELF header flags This patch adds support for EF_BPF_CPUVER bits in the ELF machine-dependent header flags. These bits encode the BPF CPU version for which the object file has been compiled for. The BPF assembler is updated so it annotates the object files it generates with these bits. The BPF disassembler is updated so it honors EF_BPF_CPUVER to use the appropriate ISA version if the user didn't specify an explicit ISA version in the command line. Note that a value of zero in EF_BPF_CPUVER is interpreted by the disassembler as "use the later supported version" (the BPF CPU versions start with v1.) The readelf utility is updated to pretty print EF_BPF_CPUVER when it prints out the ELF header: $ readelf -h a.out ELF Header: ... Flags: 0x4, CPU Version: 4 Tested in bpf-unknown-none. include/ChangeLog: 2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com> * elf/bpf.h (EF_BPF_CPUVER): Define. * opcode/bpf.h (BPF_XBPF): Change from 0xf to 0xff so it fits in EF_BPF_CPUVER. binutils/ChangeLog: 2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com> * readelf.c (get_machine_flags): Recognize and pretty print BPF machine flags. opcodes/ChangeLog: 2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-dis.c: Initialize asm_bpf_version to -1. (print_insn_bpf): Set BPF ISA version from the cpu version ELF header flags if no explicit version set in the command line. * disassemble.c (disassemble_init_for_target): Remove unused code. gas/ChangeLog: 2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.h (elf_tc_final_processing): Define. * config/tc-bpf.c (bpf_elf_final_processing): New function.
2023-07-31 04:39:30 +08:00
Revert "2.41 Release sources" This reverts commit 675b9d612cc59446e84e2c6d89b45500cb603a8d. See https://sourceware.org/pipermail/binutils/2023-August/128761.html.
2023-08-02 19:06:23 +08:00
* config/tc-bpf.h (elf_tc_final_processing): Define.
* config/tc-bpf.c (bpf_elf_final_processing): New function.
2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-bpf.c (signed_overflow): Copy function from
tc-aarch64.c.
(encode_insn): Check for overflow in constant immediates.
(add_relaxed_insn): Pass relax argument to encode_insn.
(add_fixed_insn): Likewise.
* testsuite/gas/bpf/disp16-overflow.d: New file.
* testsuite/gas/bpf/disp16-overflow.s: Likewise.
* testsuite/gas/bpf/disp16-overflow.l: Likewise.
* testsuite/gas/bpf/disp32-overflow.d: Likewise.
* testsuite/gas/bpf/disp32-overflow.s: Likewise.
* testsuite/gas/bpf/disp32-overflow.l: Likewise.
* testsuite/gas/bpf/imm32-overflow.d: Likewise.
* testsuite/gas/bpf/imm32-overflow.s: Likewise.
* testsuite/gas/bpf/imm32-overflow.l: Likewise.
* testsuite/gas/bpf/offset16-overflow.d: Likewise.
* testsuite/gas/bpf/offset16-overflow.s: Likewise.
* testsuite/gas/bpf/offset16-overflow.l: Likewise.
* testsuite/gas/bpf/disp16-overflow-relax.d: Likewise.
* testsuite/gas/bpf/disp16-overflow-relax.l: Likewise.
* testsuite/gas/bpf/disp16-overflow-relax.s: Likewise.
* testsuite/gas/bpf/jump-relax-jump-be.d: New file.
* testsuite/gas/bpf/bpf.exp: Run new tests.
2023-07-28 Jose E. Marchesi <jose.marchesi@oracle.com>
PR gas/30690
* config/tc-bpf.c (struct bpf_insn): Add fields is_relaxable and
relaxed_exp.
(enum options): Add OPTION_NO_RELAX.
(md_longopts): Likewise for -mno-relax.
(do_relax): New global.
(md_parse_option): Handle OPTION_NO_RELAX.
(RELAX_BRANCH_ENCODE): Define.
(RELAX_BRANCH_P): Likewise.
(RELAX_BRANCH_LENGTH): Likewise.
(RELAX_BRANCH_CONST): Likewise.
(RELAX_BRANCH_UNCOND): Likewise.
(relaxed_branch_length): New function.
(md_estimate_size_before_relax): Likewise.
(read_insn_word): Likewise.
(encode_int16): Likewise.
(encode_int32): Likewise.
(write_insn_bytes): Likewise.
(md_convert_frag): Likewise.
(encode_insn): Likewise.
(install_insn_fixups): Likewise.
(add_fixed_insn): Likewise.
(add_relaxed_insn): Likewise.
(md_assemble): Move instruction encoding logic to the above
new functions.
* testsuite/gas/bpf/jump-relax-ja.d: New test.
* testsuite/gas/bpf/jump-relax-ja-be.d: Likewise.
* testsuite/gas/bpf/jump-relax-ja.s: And corresponding source.
* testsuite/gas/bpf/jump-relax-jump.d: New test.
* testsuite/gas/bpf/jump-relax-jump-be.d: Likewise.
* testsuite/gas/bpf/jump-relax-jump.s: And corresponding source.
* testsuite/gas/bpf/bpf.exp: Run new tests.
* doc/c-bpf.texi (BPF Options): Document -mno-relax.
2023-07-26 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/bpf/alu.s: Add test for NEGI and NEG32I.
* testsuite/gas/bpf/alu32.s: Likewise.
* testsuite/gas/bpf/alu-pseudoc.s: Likewise.
* testsuite/gas/bpf/alu32-pseudoc.s: Likewise.
* testsuite/gas/bpf/alu.d: Add expected results.
* testsuite/gas/bpf/alu-be.d: Likewise.
* testsuite/gas/bpf/alu-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu32.d: Likewise.
* testsuite/gas/bpf/alu32-be.d: Likewise.
* testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise.
2023-07-26 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/bpf/alu.s: The register neg instruction gets only
one argument.
* testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu32-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu32-pseudoc.s: Likewise.
* testsuite/gas/bpf/alu-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu-pseudoc.s: Likewise.
* testsuite/gas/bpf/alu-be.d: Likewise.
* testsuite/gas/bpf/alu.d: Likewise.
* testsuite/gas/bpf/alu32-be.d: Likewise.
* testsuite/gas/bpf/alu32.d: Likewise.
* testsuite/gas/bpf/alu32.s: Likewise.
* doc/c-bpf.texi (BPF Instructions): Update accordingly.
2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* doc/c-bpf.texi (BPF Instructions): Document BSWAP* instructions.
* testsuite/gas/bpf/alu.s: Test BSWAP{16,32,64} instructions.
* testsuite/gas/bpf/alu.d: Likewise.
* testsuite/gas/bpf/alu-be.d: Likewise.
* testsuite/gas/bpf/alu-pseudoc.s: Likewise.
* testsuite/gas/bpf/alu-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.
2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* doc/c-bpf.texi (BPF Instructions): The pseudoc syntax for MOVS*
doesn't use `s=' but `='.
2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* doc/c-bpf.texi (BPF Instructions): Fix pseudoc syntax for MOVS*
and LDXS* instructions.
* testsuite/gas/bpf/mem-pseudoc.d: Likewise.
* testsuite/gas/bpf/mem-be-pseudoc.d: Likewise.
* testsuite/gas/bpf/mem-pseudoc.s: Likewise.
* testsuite/gas/bpf/alu-pseudoc.s: Likewise.
* testsuite/gas/bpf/alu-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu32-pseudoc.s: Likewise.
* testsuite/gas/bpf/alu32-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise.
2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-bpf.c (struct bpf_insn): New field `id'.
(md_assemble): Save the ids of successfully parsed instructions
and use the new BFD_RELOC_BPF_DISPCALL32 whenever appropriate.
(md_apply_fix): Adapt to the new BFD reloc.
* testsuite/gas/bpf/jump.s: Test JAL.
* testsuite/gas/bpf/jump.d: Likewise.
* testsuite/gas/bpf/jump-pseudoc.d: Likewise.
* testsuite/gas/bpf/jump-be.d: Likewise.
* testsuite/gas/bpf/jump-be-pseudoc.d: Likewise.
* doc/c-bpf.texi (BPF Instructions): Document new instruction
jal/gotol.
Document new operand type disp32.
2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/bpf/mem.s: Add signed load instructions.
* testsuite/gas/bpf/mem-pseudoc.s: Likewise.
* testsuite/gas/bpf/mem.d: Likewise.
* testsuite/gas/bpf/mem-pseudoc.d: Likewise.
* testsuite/gas/bpf/mem-be.d: Likewise.
* doc/c-bpf.texi (BPF Instructions): Document the signed load
instructions.
2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
bpf: opcodes, gas: support for signed register move V4 instructions This commit adds the signed register move (movs) instructions introduced in the BPF ISA version 4, including opcodes and assembler tests. Tested in bpf-unknown-none. include/ChangeLog: 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/bpf.h (BPF_OFFSET16_MOVS8): Define. (BPF_OFFSET16_MOVS16): Likewise. (BPF_OFFSET16_MOVS32): Likewise. (enum bpf_insn_id): Add entries for MOVS{8,16,32}R and MOVS32{8,16,32}R. opcodes/ChangeLog: 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-opc.c (bpf_opcodes): Add entries for MOVS{8,16,32}R and MOVS32{8,16,32}R instructions. and MOVS32I instructions. gas/ChangeLog: 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/bpf/alu.s: Test movs instructions. * testsuite/gas/bpf/alu-pseudoc.s: Likewise. * testsuite/gas/bpf/alu32.s: Likewise for movs32 instruction. * testsuite/gas/bpf/alu32-pseudoc.s: Likewise. * testsuite/gas/bpf/alu.d: Add expected results. * testsuite/gas/bpf/alu32.d: Likewise. * testsuite/gas/bpf/alu-be.d: Likewise. * testsuite/gas/bpf/alu32-be.d: Likewise. * testsuite/gas/bpf/alu-pseudoc.d: Likewise. * testsuite/gas/bpf/alu32-pseudoc.d: Likewise. * testsuite/gas/bpf/alu-be-pseudoc.d: Likewise. * testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise.
2023-07-21 23:22:58 +08:00
Revert "2.41 Release sources" This reverts commit 675b9d612cc59446e84e2c6d89b45500cb603a8d. See https://sourceware.org/pipermail/binutils/2023-August/128761.html.
2023-08-02 19:06:23 +08:00
* testsuite/gas/bpf/alu.s: Test movs instructions.
* testsuite/gas/bpf/alu-pseudoc.s: Likewise.
* testsuite/gas/bpf/alu32.s: Likewise for movs32 instruction.
* testsuite/gas/bpf/alu32-pseudoc.s: Likewise.
* testsuite/gas/bpf/alu.d: Add expected results.
* testsuite/gas/bpf/alu32.d: Likewise.
* testsuite/gas/bpf/alu-be.d: Likewise.
* testsuite/gas/bpf/alu32-be.d: Likewise.
* testsuite/gas/bpf/alu-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu32-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise.
bpf: opcodes, gas: support for signed register move V4 instructions This commit adds the signed register move (movs) instructions introduced in the BPF ISA version 4, including opcodes and assembler tests. Tested in bpf-unknown-none. include/ChangeLog: 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/bpf.h (BPF_OFFSET16_MOVS8): Define. (BPF_OFFSET16_MOVS16): Likewise. (BPF_OFFSET16_MOVS32): Likewise. (enum bpf_insn_id): Add entries for MOVS{8,16,32}R and MOVS32{8,16,32}R. opcodes/ChangeLog: 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-opc.c (bpf_opcodes): Add entries for MOVS{8,16,32}R and MOVS32{8,16,32}R instructions. and MOVS32I instructions. gas/ChangeLog: 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/bpf/alu.s: Test movs instructions. * testsuite/gas/bpf/alu-pseudoc.s: Likewise. * testsuite/gas/bpf/alu32.s: Likewise for movs32 instruction. * testsuite/gas/bpf/alu32-pseudoc.s: Likewise. * testsuite/gas/bpf/alu.d: Add expected results. * testsuite/gas/bpf/alu32.d: Likewise. * testsuite/gas/bpf/alu-be.d: Likewise. * testsuite/gas/bpf/alu32-be.d: Likewise. * testsuite/gas/bpf/alu-pseudoc.d: Likewise. * testsuite/gas/bpf/alu32-pseudoc.d: Likewise. * testsuite/gas/bpf/alu-be-pseudoc.d: Likewise. * testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise.
2023-07-21 23:22:58 +08:00
Change version number to 2.41.50 and regenerate files
2023-07-03 18:53:45 +08:00
2023-07-03 Nick Clifton <nickc@redhat.com>
* configure: Regenerate.
* po/gas.pot: Regenerate.
Add markers for the 2.41 branch
2023-07-03 18:12:15 +08:00
2023-07-03 Nick Clifton <nickc@redhat.com>
2.41 Branch Point.
Fix gas tests for aarch64-pe
2023-06-27 00:37:19 +08:00
2023-06-26 Nick Clifton <nickc@redhat.com>
* testsuite/gas/aarch64/bfloat16-directive-be.d: Adjust regexps
to allow for non-ELF based toolchains.
* testsuite/gas/aarch64/bfloat16-directive-le.d: Likewise.
* testsuite/gas/aarch64/optional.d: Likewise.
* testsuite/gas/aarch64/pr20364.d: Likewise.
* testsuite/gas/aarch64/adr_1.d: Skip for non-ELF based toolchains.
* testsuite/gas/aarch64/advsimd-mov-bad.d: Likewise.
* testsuite/gas/aarch64/b_1.d: Likewise.
* testsuite/gas/aarch64/beq_1.d: Likewise.
* testsuite/gas/aarch64/codealign_1.d: Likewise.
* testsuite/gas/aarch64/dwarf.d: Likewise.
* testsuite/gas/aarch64/ilp32-basic.d: Likewise.
* testsuite/gas/aarch64/int-insns.d: Likewise.
* testsuite/gas/aarch64/ldr_1.d: Likewise.
* testsuite/gas/aarch64/mapping_5.d: Likewise.
* testsuite/gas/aarch64/mapping_6.d: Likewise.
* testsuite/gas/aarch64/mops_invalid_2.d: Likewise.
* testsuite/gas/aarch64/movw_label.d: Likewise.
* testsuite/gas/aarch64/pac_ab_key.d: Likewise.
* testsuite/gas/aarch64/pac_negate_ra_state.d: Likewise.
* testsuite/gas/aarch64/pr27217.d: Likewise.
* testsuite/gas/aarch64/pr29519.d: Likewise.
* testsuite/gas/aarch64/programmer-friendly.d: Likewise.
* testsuite/gas/aarch64/reloc-data.d: Likewise.
* testsuite/gas/aarch64/reloc-dtprel_g0-ilp32.d: Likewise.
* testsuite/gas/aarch64/reloc-dtprel_g0.d: Likewise.
* testsuite/gas/aarch64/reloc-dtprel_g0_nc-ilp32.d: Likewise.
* testsuite/gas/aarch64/reloc-dtprel_g0_nc.d: Likewise.
* testsuite/gas/aarch64/reloc-dtprel_g1-ilp32.d: Likewise.
* testsuite/gas/aarch64/reloc-dtprel_g1.d: Likewise.
* testsuite/gas/aarch64/reloc-dtprel_g1_nc.d: Likewise.
* testsuite/gas/aarch64/reloc-dtprel_g2.d: Likewise.
* testsuite/gas/aarch64/reloc-dtprel_hi12-ilp32.d: Likewise.
* testsuite/gas/aarch64/reloc-dtprel_hi12.d: Likewise.
* testsuite/gas/aarch64/reloc-dtprel_lo12-1.d: Likewise.
* testsuite/gas/aarch64/reloc-dtprel_lo12-ilp32-1.d: Likewise.
* testsuite/gas/aarch64/reloc-dtprel_lo12-ldst16.d: Likewise.
* testsuite/gas/aarch64/reloc-dtprel_lo12-ldst32.d: Likewise.
* testsuite/gas/aarch64/reloc-dtprel_lo12-ldst64.d: Likewise.
* testsuite/gas/aarch64/reloc-dtprel_lo12-ldst8.d: Likewise.
* testsuite/gas/aarch64/reloc-dtprel_lo12_nc-ilp32.d: Likewise.
* testsuite/gas/aarch64/reloc-dtprel_lo12_nc-ldst16.d: Likewise.
* testsuite/gas/aarch64/reloc-dtprel_lo12_nc-ldst32.d: Likewise.
* testsuite/gas/aarch64/reloc-dtprel_lo12_nc-ldst64.d: Likewise.
* testsuite/gas/aarch64/reloc-dtprel_lo12_nc-ldst8.d: Likewise.
* testsuite/gas/aarch64/reloc-dtprel_lo12_nc.d: Likewise.
* testsuite/gas/aarch64/reloc-gotoff_g0_nc.d: Likewise.
* testsuite/gas/aarch64/reloc-gotoff_g1.d: Likewise.
* testsuite/gas/aarch64/reloc-gottprel_g0_nc.d: Likewise.
* testsuite/gas/aarch64/reloc-gottprel_g1.d: Likewise.
* testsuite/gas/aarch64/reloc-insn.d: Likewise.
* testsuite/gas/aarch64/reloc-prel_g0.d: Likewise.
* testsuite/gas/aarch64/reloc-prel_g0_nc.d: Likewise.
* testsuite/gas/aarch64/reloc-prel_g1.d: Likewise.
* testsuite/gas/aarch64/reloc-prel_g1_nc.d: Likewise.
* testsuite/gas/aarch64/reloc-prel_g2.d: Likewise.
* testsuite/gas/aarch64/reloc-prel_g2_nc.d: Likewise.
* testsuite/gas/aarch64/reloc-prel_g3.d: Likewise.
* testsuite/gas/aarch64/reloc-tlsdesc_off_g0_nc.d: Likewise.
* testsuite/gas/aarch64/reloc-tlsdesc_off_g1.d: Likewise.
* testsuite/gas/aarch64/reloc-tlsgd_g0_nc.d: Likewise.
* testsuite/gas/aarch64/reloc-tlsgd_g1.d: Likewise.
* testsuite/gas/aarch64/reloc-tlsldm-1.d: Likewise.
* testsuite/gas/aarch64/reloc-tlsldm-ilp32-1.d: Likewise.
* testsuite/gas/aarch64/reloc-tlsldm-page-1.d: Likewise.
* testsuite/gas/aarch64/reloc-tlsldm-page-ilp32-1.d: Likewise.
* testsuite/gas/aarch64/reloc-tlsldm_lo12_nc-1.d: Likewise.
* testsuite/gas/aarch64/reloc-tlsldm_lo12_nc-ilp32-1.d: Likewise.
* testsuite/gas/aarch64/reloc-tprel_lo12-ldst16-ilp32.d: Likewise.
* testsuite/gas/aarch64/reloc-tprel_lo12-ldst16.d: Likewise.
* testsuite/gas/aarch64/reloc-tprel_lo12-ldst32-ilp32.d: Likewise.
* testsuite/gas/aarch64/reloc-tprel_lo12-ldst32.d: Likewise.
* testsuite/gas/aarch64/reloc-tprel_lo12-ldst64-ilp32.d: Likewise.
* testsuite/gas/aarch64/reloc-tprel_lo12-ldst64.d: Likewise.
* testsuite/gas/aarch64/reloc-tprel_lo12-ldst8-ilp32.d: Likewise.
* testsuite/gas/aarch64/reloc-tprel_lo12-ldst8.d: Likewise.
* testsuite/gas/aarch64/reloc-tprel_lo12_nc-ldst16-ilp32.d: Likewise.
* testsuite/gas/aarch64/reloc-tprel_lo12_nc-ldst16.d: Likewise.
* testsuite/gas/aarch64/reloc-tprel_lo12_nc-ldst32-ilp32.d: Likewise.
* testsuite/gas/aarch64/reloc-tprel_lo12_nc-ldst32.d: Likewise.
* testsuite/gas/aarch64/reloc-tprel_lo12_nc-ldst64-ilp32.d: Likewise.
* testsuite/gas/aarch64/reloc-tprel_lo12_nc-ldst64.d: Likewise.
* testsuite/gas/aarch64/reloc-tprel_lo12_nc-ldst8-ilp32.d: Likewise.
* testsuite/gas/aarch64/reloc-tprel_lo12_nc-ldst8.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_1.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_10.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_11.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_12.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_13.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_14.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_15.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_16.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_17.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_18.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_19.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_2.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_20.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_21.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_22.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_23.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_24.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_25.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_26.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_27.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_28.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_3.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_4.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_5.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_6.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_7.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_8.d: Likewise.
* testsuite/gas/aarch64/sve-movprfx_9.d: Likewise.
* testsuite/gas/aarch64/symbol-variant_pcs-1.d: Likewise.
* testsuite/gas/aarch64/symbol-variant_pcs-2.d: Likewise.
* testsuite/gas/aarch64/symbol-variant_pcs-3.d: Likewise.
* testsuite/gas/aarch64/system.d: Likewise.
* testsuite/gas/aarch64/tail_padding.d: Likewise.
* testsuite/gas/aarch64/tbz_1.d: Likewise.
* testsuite/gas/aarch64/tls-desc.d: Likewise.
* testsuite/gas/aarch64/tls.d: Likewise.
gas: bpf: fix tests for pseudo-c syntax This patch fixes the GAS BPF testsuite so the tests for pseudo-c syntax are actually executed. 2023-04-27 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/bpf/mem.dump: New file. * testsuite/gas/bpf/mem-pseudoc.d: Likewise. * testsuite/gas/bpf/mem.d: #dump mem.dump. * testsuite/gas/bpf/lddw.dump: New file. * testsuite/gas/bpf/lddw-pseudoc.d: Likewise. * testsuite/gas/bpf/lddw.d: #dump lddw.dump. * testsuite/gas/bpf/jump.dump: New file. * testsuite/gas/bpf/jump-pseudoc.d: Likewise * testsuite/gas/bpf/jump.d: #dump jump.dump. * testsuite/gas/bpf/jump32.dump: New file. * testsuite/gas/bpf/jump32-pseudoc.d: Likewise. * testsuite/gas/bpf/jump32.d: #dump jump32.dump. * testsuite/gas/bpf/lddw-be.dump: New file. * testsuite/gas/bpf/lddw-be-pseudoc.d: Likewise. * testsuite/gas/bpf/lddw-be.d: #dump lddw-be.dump. * testsuite/gas/bpf/indcall-1.dump: New file. * testsuite/gas/bpf/indcall-1-pseudoc.d: Likewise. * testsuite/gas/bpf/indcall-1.d: #dump indcall-1.dump. * testsuite/gas/bpf/indcall-1-pseudoc.s (main): Fix lddw instruction. * testsuite/gas/bpf/atomic.dump: New file. * testsuite/gas/bpf/atomic-pseudoc.d: Likewise. * testsuite/gas/bpf/atomic.d: #dump atomic.dump. * testsuite/gas/bpf/alu32.dump: New file. * testsuite/gas/bpf/alu32-pseudoc.d: Likewise. * testsuite/gas/bpf/alu32.d: #dump alu32.dump. * testsuite/gas/bpf/alu.dump: New file. * testsuite/gas/bpf/alu-pseudoc.d: Likewise. * testsuite/gas/bpf/alu.d: #dump alu.dump. * testsuite/gas/bpf/alu-be.dump: New file. * testsuite/gas/bpf/alu-be-pseudoc.d: Likewise. * testsuite/gas/bpf/alu-be.d: #dump alu-be.dump. * testsuite/gas/bpf/alu32-be-pseudoc.d: New file. * testsuite/gas/bpf/alu32-be-dump: Likewise. * testsuite/gas/bpf/alu32-be.d: #dump alu32-be-dump. * testsuite/gas/bpf/bpf.exp: Run *-pseudoc tests.
2023-04-28 02:05:19 +08:00
2023-04-27 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/bpf/mem.dump: New file.
* testsuite/gas/bpf/mem-pseudoc.d: Likewise.
Fix gas tests for aarch64-pe
2023-06-27 00:37:19 +08:00
* testsuite/gas/bpf/mem.d: #dump mem.dump.
gas: bpf: fix tests for pseudo-c syntax This patch fixes the GAS BPF testsuite so the tests for pseudo-c syntax are actually executed. 2023-04-27 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/bpf/mem.dump: New file. * testsuite/gas/bpf/mem-pseudoc.d: Likewise. * testsuite/gas/bpf/mem.d: #dump mem.dump. * testsuite/gas/bpf/lddw.dump: New file. * testsuite/gas/bpf/lddw-pseudoc.d: Likewise. * testsuite/gas/bpf/lddw.d: #dump lddw.dump. * testsuite/gas/bpf/jump.dump: New file. * testsuite/gas/bpf/jump-pseudoc.d: Likewise * testsuite/gas/bpf/jump.d: #dump jump.dump. * testsuite/gas/bpf/jump32.dump: New file. * testsuite/gas/bpf/jump32-pseudoc.d: Likewise. * testsuite/gas/bpf/jump32.d: #dump jump32.dump. * testsuite/gas/bpf/lddw-be.dump: New file. * testsuite/gas/bpf/lddw-be-pseudoc.d: Likewise. * testsuite/gas/bpf/lddw-be.d: #dump lddw-be.dump. * testsuite/gas/bpf/indcall-1.dump: New file. * testsuite/gas/bpf/indcall-1-pseudoc.d: Likewise. * testsuite/gas/bpf/indcall-1.d: #dump indcall-1.dump. * testsuite/gas/bpf/indcall-1-pseudoc.s (main): Fix lddw instruction. * testsuite/gas/bpf/atomic.dump: New file. * testsuite/gas/bpf/atomic-pseudoc.d: Likewise. * testsuite/gas/bpf/atomic.d: #dump atomic.dump. * testsuite/gas/bpf/alu32.dump: New file. * testsuite/gas/bpf/alu32-pseudoc.d: Likewise. * testsuite/gas/bpf/alu32.d: #dump alu32.dump. * testsuite/gas/bpf/alu.dump: New file. * testsuite/gas/bpf/alu-pseudoc.d: Likewise. * testsuite/gas/bpf/alu.d: #dump alu.dump. * testsuite/gas/bpf/alu-be.dump: New file. * testsuite/gas/bpf/alu-be-pseudoc.d: Likewise. * testsuite/gas/bpf/alu-be.d: #dump alu-be.dump. * testsuite/gas/bpf/alu32-be-pseudoc.d: New file. * testsuite/gas/bpf/alu32-be-dump: Likewise. * testsuite/gas/bpf/alu32-be.d: #dump alu32-be-dump. * testsuite/gas/bpf/bpf.exp: Run *-pseudoc tests.
2023-04-28 02:05:19 +08:00
* testsuite/gas/bpf/lddw.dump: New file.
* testsuite/gas/bpf/lddw-pseudoc.d: Likewise.
* testsuite/gas/bpf/lddw.d: #dump lddw.dump.
* testsuite/gas/bpf/jump.dump: New file.
* testsuite/gas/bpf/jump-pseudoc.d: Likewise
* testsuite/gas/bpf/jump.d: #dump jump.dump.
* testsuite/gas/bpf/jump32.dump: New file.
* testsuite/gas/bpf/jump32-pseudoc.d: Likewise.
* testsuite/gas/bpf/jump32.d: #dump jump32.dump.
* testsuite/gas/bpf/lddw-be.dump: New file.
* testsuite/gas/bpf/lddw-be-pseudoc.d: Likewise.
* testsuite/gas/bpf/lddw-be.d: #dump lddw-be.dump.
* testsuite/gas/bpf/indcall-1.dump: New file.
* testsuite/gas/bpf/indcall-1-pseudoc.d: Likewise.
* testsuite/gas/bpf/indcall-1.d: #dump indcall-1.dump.
* testsuite/gas/bpf/indcall-1-pseudoc.s (main): Fix lddw
instruction.
* testsuite/gas/bpf/atomic.dump: New file.
* testsuite/gas/bpf/atomic-pseudoc.d: Likewise.
* testsuite/gas/bpf/atomic.d: #dump atomic.dump.
* testsuite/gas/bpf/alu32.dump: New file.
* testsuite/gas/bpf/alu32-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu32.d: #dump alu32.dump.
* testsuite/gas/bpf/alu.dump: New file.
* testsuite/gas/bpf/alu-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu.d: #dump alu.dump.
* testsuite/gas/bpf/alu-be.dump: New file.
* testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.
* testsuite/gas/bpf/alu-be.d: #dump alu-be.dump.
* testsuite/gas/bpf/alu32-be-pseudoc.d: New file.
* testsuite/gas/bpf/alu32-be-dump: Likewise.
* testsuite/gas/bpf/alu32-be.d: #dump alu32-be-dump.
* testsuite/gas/bpf/bpf.exp: Run *-pseudoc tests.
gas: documentation for the BPF pseudo-c asm syntax This patch expands the GAS manual in order to specify the alternate pseudo-C assembly syntax used in BPF, and now supported by the assembler. gas/ChangeLog: 2023-04-19 Jose E. Marchesi <jose.marchesi@oracle.com> PR gas/29757 * doc/c-bpf.texi (BPF Pseudo-C Syntax): New section.
2023-04-20 22:46:08 +08:00
2023-04-19 Jose E. Marchesi <jose.marchesi@oracle.com>
PR gas/29757
* doc/c-bpf.texi (BPF Pseudo-C Syntax): New section.
gas: BPF pseudo-c syntax tests This patch expands the GAS BPF testsuite in order to also test the alternative pseudo-C syntax used in BPF assembly. This includes three main changes: - Some general GAS tests involving assignment and equality operands in expressions (such as = and ==) are disabled in bpf-* targets, because the syntax collides with the pseudo-C BPF assembly syntax. - New tests are added to the BPF GAS testsuite that test the pseudo-c syntax. Tests for all BPF instructions are included. - New tests are added to the BPF GAS testsuite that test the support for both syntaxes in the same source. gas/ChangeLog: 2023-04-20 Guillermo E. Martinez <guillermo.e.martinez@oracle.com> PR gas/29728 * testsuite/gas/all/assign-bad-recursive.d: Skip test in bpf-* targets. * testsuite/gas/all/eqv-dot.d: Likewise. * testsuite/gas/all/gas.exp: Skip other assignment tests in bpf-*. * testsuite/gas/bpf/alu-pseudoc.s: New file. * testsuite/gas/bpf/pseudoc-normal.s: Likewise. * testsuite/gas/bpf/pseudoc-normal.d: Likewise. * testsuite/gas/bpf/pseudoc-normal-be.d: Likewise. * testsuite/gas/bpf/mem-pseudoc.s: Likewise. * testsuite/gas/bpf/lddw-pseudoc.s: Likewise. * testsuite/gas/bpf/jump32-pseudoc.s: Likewise. * testsuite/gas/bpf/jump-pseudoc.s: Likewise. * testsuite/gas/bpf/indcall-1-pseudoc.s: Likewise. * testsuite/gas/bpf/atomic-pseudoc.s: Likewise. * testsuite/gas/bpf/alu32-pseudoc.s: Likewise. * testsuite/gas/bpf/*.d: Add -pseudoc variants of the tests.
2023-04-20 22:43:03 +08:00
2023-04-20 Guillermo E. Martinez <guillermo.e.martinez@oracle.com>
PR gas/29728
* testsuite/gas/all/assign-bad-recursive.d: Skip test in bpf-*
targets.
* testsuite/gas/all/eqv-dot.d: Likewise.
* testsuite/gas/all/gas.exp: Skip other assignment tests in bpf-*.
* testsuite/gas/bpf/alu-pseudoc.s: New file.
* testsuite/gas/bpf/pseudoc-normal.s: Likewise.
* testsuite/gas/bpf/pseudoc-normal.d: Likewise.
* testsuite/gas/bpf/pseudoc-normal-be.d: Likewise.
* testsuite/gas/bpf/mem-pseudoc.s: Likewise.
* testsuite/gas/bpf/lddw-pseudoc.s: Likewise.
* testsuite/gas/bpf/jump32-pseudoc.s: Likewise.
* testsuite/gas/bpf/jump-pseudoc.s: Likewise.
* testsuite/gas/bpf/indcall-1-pseudoc.s: Likewise.
* testsuite/gas/bpf/atomic-pseudoc.s: Likewise.
* testsuite/gas/bpf/alu32-pseudoc.s: Likewise.
* testsuite/gas/bpf/*.d: Add -pseudoc variants of the tests.
gas: support for the BPF pseudo-c assembly syntax This patch adds support to the GNU assembler for an alternative assembly syntax used in BPF. This syntax is C-like and very unconventional for an assembly language, but it is generated by clang/llvm and is also used in inline asm templates in kernel code, so we ought to support it. After this patch, the assembler is able to parse instructions in both supported syntax: the normal assembly-like syntax and the pseudo-C syntax. Instruction formats can be mixed in the source program: the assembler recognizes the right syntax to use. gas/ChangeLog: 2023-04-20 Guillermo E. Martinez <guillermo.e.martinez@oracle.com> PR gas/29728 * config/tc-bpf.h (TC_EQUAL_IN_INSN): Define. * config/tc-bpf.c (LEX_IS_SYMBOL_COMPONENT): Define. (LEX_IS_WHITESPACE): Likewise. (LEX_IS_NEWLINE): Likewise. (LEX_IS_ARITHM_OP): Likewise. (LEX_IS_STAR): Likewise. (LEX_IS_CLSE_BR): Likewise. (LEX_IS_OPEN_BR): Likewise. (LEX_IS_EQUAL): Likewise. (LEX_IS_EXCLA): Likewise. (ST_EOI): Likewise. (MAX_TOKEN_SZ): Likewise. (init_pseudoc_lex): New function. (md_begin): Call init_pseudoc_lex. (valid_expr): New function. (build_bpf_non_generic_load): Likewise. (build_bpf_atomic_insn): Likewise. (build_bpf_jmp_insn): Likewise. (build_bpf_arithm_insn): Likewise. (build_bpf_endianness): Likewise. (build_bpf_load_store_insn): Likewise. (look_for_reserved_word): Likewise. (is_register): Likewise. (is_cast): Likewise. (get_token): Likewise. (bpf_pseudoc_to_normal_syntax): Likewise. (md_assemble): Try pseudo-C syntax if an instruction cannot be parsed.
2023-04-20 22:37:01 +08:00
2023-04-20 Guillermo E. Martinez <guillermo.e.martinez@oracle.com>
PR gas/29728
* config/tc-bpf.h (TC_EQUAL_IN_INSN): Define.
* config/tc-bpf.c (LEX_IS_SYMBOL_COMPONENT): Define.
(LEX_IS_WHITESPACE): Likewise.
(LEX_IS_NEWLINE): Likewise.
(LEX_IS_ARITHM_OP): Likewise.
(LEX_IS_STAR): Likewise.
(LEX_IS_CLSE_BR): Likewise.
(LEX_IS_OPEN_BR): Likewise.
(LEX_IS_EQUAL): Likewise.
(LEX_IS_EXCLA): Likewise.
(ST_EOI): Likewise.
(MAX_TOKEN_SZ): Likewise.
(init_pseudoc_lex): New function.
(md_begin): Call init_pseudoc_lex.
(valid_expr): New function.
(build_bpf_non_generic_load): Likewise.
(build_bpf_atomic_insn): Likewise.
(build_bpf_jmp_insn): Likewise.
(build_bpf_arithm_insn): Likewise.
(build_bpf_endianness): Likewise.
(build_bpf_load_store_insn): Likewise.
(look_for_reserved_word): Likewise.
(is_register): Likewise.
(is_cast): Likewise.
(get_token): Likewise.
(bpf_pseudoc_to_normal_syntax): Likewise.
(md_assemble): Try pseudo-C syntax if an instruction cannot be
parsed.
Symbols with GOT relocatios do not fix adjustbale gas * config/tc-loongarch.c (loongarch_fix_adjustable): Symbols with GOT relocatios do not fix adjustbale. * testsuite/gas/loongarch/macro_op_large_abs.d: Regenerated. * testsuite/gas/loongarch/macro_op_large_pc.d: Regenerated. ld * testsuite/ld-loongarch-elf/macro_op.d: Regenerated. -
2023-04-18 18:49:21 +08:00
2023-04-18 mengqinggang <mengqinggang@loongson.cn>
* config/tc-loongarch.c (loongarch_fix_adjustable): Symbols with
GOT relocatios do not fix adjustbale.
* testsuite/gas/loongarch/macro_op_large_abs.d: Regenerated.
* testsuite/gas/loongarch/macro_op_large_pc.d: Regenerated.
Assembler Internal Docs: Describe handling of opcodes for relaxation a bit better.
2023-04-18 18:21:58 +08:00
2023-04-18 Thomas Koenig <tkoenig@netcologne.de>
* doc/internals.texi (Relaxing with a table): Describe handling of
opcodes for relaxation a bit better.
arc: Update ARC's CFI tests. The double store/loads instructions (e.g. STD/LDD) are not baseline ARC ISA. The same holds for some short instructions. Update the tests to use base ARC ISA. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2023-04-13 15:22:48 +08:00
2023-04-13 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/cfi/cfi-arc-1.s: Use baseline instructions.
* testsuite/gas/cfi/cfi-arc-1.d: Update matching patterns.
arc: Update GAS test Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
2023-04-13 15:04:41 +08:00
2023-04-13 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/dsp.s: Remove unimplemented dsp instructions.
* testsuite/gas/arc/dsp.d: Update the test.
Fix assembler documentation regarding data directives. PR 30206 * doc/as.texi (Pseudo Ops): Document that data directives such as .byte and .int are not intended for encoding instructions.
2023-03-14 19:19:45 +08:00
2023-03-14 Nick Clifton <nickc@redhat.com>
PR 30206
* doc/as.texi (Pseudo Ops): Document that data directives such as
.byte and .int are not intended for encoding instructions.
[Aarch64] Add Binutils support for MEC This change supports MEC which is part of RME (Realm Management Extension).
2023-02-28 18:55:25 +08:00
2023-02-28 Richard Ball <richard.ball@arm.com>
* testsuite/gas/aarch64/mec-invalid.d: New test.
* testsuite/gas/aarch64/mec-invalid.l: New test.
* testsuite/gas/aarch64/mec-invalid.s: New test.
* testsuite/gas/aarch64/mec.d: New test.
* testsuite/gas/aarch64/mec.s: New test.
Do not change the timestamp when updating the gas asconfig file. PR 28909 * doc/local.mk (asconfig.texi): Use "cp -p" to preserve timestamps. * Makefile.in: Regenerate.
2023-02-27 21:35:49 +08:00
2023-02-27 Benson Muite <benson_muite@emailplus.org>
PR 28909
* doc/local.mk (asconfig.texi): Use "cp -p" to preserve
timestamps.
* Makefile.in: Regenerate.
Fix compilation of the assembler with sanitization enabled. * dwarf2dbg.c (emit_inc_line_addr): Use unsigned constants when checking addr_delta.
2023-02-01 17:49:07 +08:00
2023-02-01 Nick Clifton <nickc@redhat.com>
* dwarf2dbg.c (emit_inc_line_addr): Use unsigned constants when
checking addr_delta.
Add OpenBSD ARM GAS support.
2023-01-20 18:46:37 +08:00
2023-01-20 Frederic Cambus <fred@statdns.com>
* configure.tgt (arm-*-openbsd*): Add target.
Updated translations for the gas and binutils sub-directories
2023-01-16 18:45:38 +08:00
2023-01-16 Nick Clifton <nickc@redhat.com>
* po/ru.po: Updated Russian translation.
Fix a translation problem in the x86 assembler. PR 29952 * config/tc-i386.c (md_assemble): Avoid constructing translatable strings.
2023-01-03 20:03:02 +08:00
2023-01-03 Nick Clifton <nickc@redhat.com>
PR 29952
* config/tc-i386.c (md_assemble): Avoid constructing translatable
strings.
Updated translations for various languages and sub-directories
2023-01-03 19:32:42 +08:00
2023-01-03 Nick Clifton <nickc@redhat.com>
* po/fr.po: Updated French translation.
* po/uk.po: Updated Ukrainian translation.
Add markers for 2.40 branch
2022-12-31 20:05:28 +08:00
2022-12-31 Nick Clifton <nickc@redhat.com>
* 2.40 branch created.
Fix ARM and AArch64 assembler tests to work in a multi-arch environment. PR 29764 gas * testsuite/gas/arm/cpu-cortex-a76ae.d: Add arm prefix to the -m option passed to objdump. * testsuite/gas/arm/cpu-cortex-a77.d: Likewise. * testsuite/gas/aarch64/cpu-cortex-a76ae.d: Add aarch64 prefix to the -m option passed to objdump. * testsuite/gas/aarch64/cpu-cortex-a77.d: Likewise. bfd * cpu-arm.c (scan): Accept machine names prefixed with "arm:". * cpu-aarch64.c (scan): Accept machine names prefixed with "aarch64:". bin * doc/binutils.texi (objdump): Note that the -m option supports the <architecture>:<machine> syntax.
2022-11-22 00:44:02 +08:00
2022-11-21 Nick Clifton <nickc@redhat.com>
PR 29764
* testsuite/gas/arm/cpu-cortex-a76ae.d: Add arm prefix to the -m
option passed to objdump.
* testsuite/gas/arm/cpu-cortex-a77.d: Likewise.
* testsuite/gas/aarch64/cpu-cortex-a76ae.d: Add aarch64 prefix to
the -m option passed to objdump.
* testsuite/gas/aarch64/cpu-cortex-a77.d: Likewise.
RX assembler: switch arguments of thw MVTACGU insn.
2022-10-31 18:46:37 +08:00
2022-10-31 Nick Clifton <nickc@redhat.com>
* testsuite/gas/rx/mvtacgu.d: Update expected disassembly.
Error: attempt to get value of unresolved symbol `L0' * symbols.c (S_GET_VALUE): If the unresolved symbol is the fake label provide a more helpful error message to the user.
2022-10-11 18:52:38 +08:00
2022-10-11 Nick Clifton <nickc@redhat.com>
* symbols.c (S_GET_VALUE): If the unresolved symbol is the fake
label provide a more helpful error message to the user.
Re: Error: attempt to get value of unresolved symbol `L0' * symbols.c (S_GET_VALUE): If the unresolved symbol is the fake label provide a more helpful error message to the user. (S_GET_VALUE_WHERE): Like S_GET_VALUE, but includes a file/line number for error reporting purposes. * symbols.h (S_GET_VALUE_WHERE): Prototype. * write.c (fixup_segment): Use S_GET_VALUE_WHERE.
2022-10-11 22:28:10 +08:00
(S_GET_VALUE_WHERE): Like S_GET_VALUE, but includes a file/line
number for error reporting purposes.
* symbols.h (S_GET_VALUE_WHERE): Prototype.
* write.c (fixup_segment): Use S_GET_VALUE_WHERE.
Error: attempt to get value of unresolved symbol `L0' * symbols.c (S_GET_VALUE): If the unresolved symbol is the fake label provide a more helpful error message to the user.
2022-10-11 18:52:38 +08:00
The help document of as misses some many options PR 29623 * as.c (show_usage): Document the --dump-config, --gdwarf-cie-version, --hash-size, --multibyte-handling, and --reduce-memory-overheads options. * config/tc-i386.c (md_show_usage): Document the -O option. * doc/as.texi: Document the --dump-config, --emulation, --hash-size, and --reduce-memory-overheads options.
2022-09-28 19:56:04 +08:00
2022-09-28 Nick Clifton <nickc@redhat.com>
PR 29623
* as.c (show_usage): Document the --dump-config,
--gdwarf-cie-version, --hash-size, --multibyte-handling,
and --reduce-memory-overheads options.
* config/tc-i386.c (md_show_usage): Document the -O option.
* doc/as.texi: Document the --dump-config, --emulation,
--hash-size, and --reduce-memory-overheads options.
Gas generated incorrect debug info (top-level DW_TAG_unspecified_type DIE) PR 29559 * dwarf2dbg.c (out_debug_info): Place DW_TAG_unspecified_type at the end of the list of children, not at the start of the CU information. * testsuite/gas/elf/dwarf-3-func.d: Update expected output. * testsuite/gas/elf/dwarf-5-func-global.d: Likewise. * testsuite/gas/elf/dwarf-5-func-local.d: Likewise. * testsuite/gas/elf/dwarf-5-func.d: Likewise.
2022-09-08 19:43:33 +08:00
2022-09-08 Nick Clifton <nickc@redhat.com>
PR 29559
* dwarf2dbg.c (out_debug_info): Place DW_TAG_unspecified_type at
the end of the list of children, not at the start of the CU
information.
* testsuite/gas/elf/dwarf-3-func.d: Update expected output.
* testsuite/gas/elf/dwarf-5-func-global.d: Likewise.
* testsuite/gas/elf/dwarf-5-func-local.d: Likewise.
* testsuite/gas/elf/dwarf-5-func.d: Likewise.
Add OpenBSD AArch64 GAS support. * configure.tgt (aarch64*-*-openbsd*): Add target.
2022-08-31 22:50:04 +08:00
2022-08-31 Frederic Cambus <fred@statdns.com>
* configure.tgt (aarch64*-*-openbsd*): Add target.
Add a testcase for PR 29494. PR 29494 * testsuite/gas/arm/pr29494.s: New test source file. * testsuite/gas/arm/pr29494.d: New test driver.
2022-08-30 20:46:11 +08:00
2022-08-30 Nick Clifton <nickc@redhat.com>
PR 29494
* testsuite/gas/arm/pr29494.s: New test source file.
* testsuite/gas/arm/pr29494.d: New test driver.
GAS: Add a return type tag to DWARF DIEs generated for function symbols. PR 29517 * dwarf2dbg.c (GAS_ABBREV_COMP_UNIT): New defined constant. (GAS_ABBREV_SUBPROG): New defined constant. (GAS_ABBREV_NO_TYPE): New defined constant. (out_debug_abbrev): Use the new defined constants when emitting abbreviation numbers. Generate an abbreviation for an unspecified type. (out_debug_info): Use the new defined constants when referring to abbreviations. Generate a use of the no_type abbreviation. Reference the use when generating DIEs for functions. * testsuite/gas/elf/dwarf-3-func.d: Update to allow for newly extended output from the assembler. * testsuite/gas/elf/dwarf-5-func-global.d: Likewise. * testsuite/gas/elf/dwarf-5-func-local.d: Likewise. * testsuite/gas/elf/dwarf-5-func.d: Likewise.
2022-08-25 18:48:00 +08:00
2022-08-25 Nick Clifton <nickc@redhat.com>
PR 29517
* dwarf2dbg.c (GAS_ABBREV_COMP_UNIT): New defined constant.
(GAS_ABBREV_SUBPROG): New defined constant.
(GAS_ABBREV_NO_TYPE): New defined constant.
(out_debug_abbrev): Use the new defined constants when emitting
abbreviation numbers. Generate an abbreviation for an unspecified
type.
(out_debug_info): Use the new defined constants when referring to
abbreviations. Generate a use of the no_type abbreviation.
Reference the use when generating DIEs for functions.
* testsuite/gas/elf/dwarf-3-func.d: Update to allow for newly
extended output from the assembler.
* testsuite/gas/elf/dwarf-5-func-global.d: Likewise.
* testsuite/gas/elf/dwarf-5-func-local.d: Likewise.
* testsuite/gas/elf/dwarf-5-func.d: Likewise.
GAS: Allow AArch64 pseudo-ops to accept the command line separator character. PR 29519 * config/tc-aarch64.c (s_unreq): Use find_end_of_line(). (s_aarch64_cpu): Likewise. (s_aarch64_arch): Likewise. (s_aarch64_arch_extension): Likewise. * testsuite/gas/aarch64/pr29519.d: New test driver file. * testsuite/gas/aarch64/pr29519.s: New test source file.
2022-08-25 18:39:50 +08:00
2022-08-25 Nick Clifton <nickc@redhat.com>
PR 29519
* config/tc-aarch64.c (s_unreq): Use find_end_of_line().
(s_aarch64_cpu): Likewise.
(s_aarch64_arch): Likewise.
(s_aarch64_arch_extension): Likewise.
* testsuite/gas/aarch64/pr29519.d: New test driver file.
* testsuite/gas/aarch64/pr29519.s: New test source file.
Mach-O: i18n enablement on some error messages. * config/obj-macho.c (obj_mach_o_get_section_names): Wrap two string literals within with gettext macro.
2022-08-08 19:41:30 +08:00
2022-08-08 Tsukasa OI <research_trasio@irq.a4lg.com>
* config/obj-macho.c (obj_mach_o_get_section_names): Wrap two
string literals within with gettext macro.
When gas/read.c calls mbstowcs with a NULL destination, it should set size to 0 PR 29447 * read.c (read_symbol_name): Pass 0 as the length parameter when invoking mbstowc in order to check the validity of a wide string.
2022-08-05 17:29:48 +08:00
2022-08-05 Nick Clifton <nickc@redhat.com>
PR 29447
* read.c (read_symbol_name): Pass 0 as the length parameter when
invoking mbstowc in order to check the validity of a wide string.
arc: Update missing cipher. The ciphers 5,7, and 9 are missing when parsing an assembly instruction leading to errors when those ciphers are used. gas/config * tc-arc.c (md_assembly): Update strspn string with the missing ciphers. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2022-07-18 18:57:10 +08:00
2022-07-18 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (md_assembly): Update strspn string with the
missing ciphers.
Add markers for 2.39 branch
2022-07-08 17:41:07 +08:00
2022-07-08 Nick Clifton <nickc@redhat.com>
* 2.39 branch created.
oops - forgot changelog entry for the previous delta.
2022-05-18 23:26:21 +08:00
2022-05-18 Victor Do Nascimento <victor.donascimento@arm.com>
* config/tc-arm.c (parse_reg_list): Add handling of mixed register
types.
(reg_names): Enumerate pseudoregister according to mapped physical
register number.
(s_arm_unwind_save_pseudo): Modify function signature.
(s_arm_unwind_save_core): Likewise.
(s_arm_unwind_save_mixed): New function.
(s_arm_unwind_save): Generate register list mask to pass to nested
functions.
* testsuite/gas/arm/unwind-pacbti-m.s: Expand test for mixed
register type lists.
* testsuite/gas/arm/unwind-pacbti-m.d: Likewise.
* testsuite/gas/arm/unwind-pacbti-m-readelf.d: Likewise.
Add support for COFF secidx relocations bfd * coff-i386.c (in_reloc_p): Add R_SECTION. (howto_table): Add R_SECTION. (coff_pe_i386_relocation_section): Add support for R_SECTION. (coff_i386_reloc_type_lookup): Add support for BFD_RELOC_16_SECCIDX. * coff-x86_64.c (in_reloc_p): Add R_SECTION. (howto_table): Add R_SECTION. (coff_pe_amd64_relocation_section): Add support for R_SECTION. (coff_amd64_reloc_type_lookup): Add support for BFD_RELOC_16_SECCIDX. * reloc.c: Add BFD_RELOC_16_SECIDX. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. gas * config/tc-i386.c (pe_directive_secidx): New function. (md_pseudo_table): Add support for secidx. (x86_cons_fix_new): Likewise. (tc_gen_reloc): Likewise. * expr.c (op_rank): Add O_secidx. * expr.h (operatorT): Likewise. * symbols.c (resolve_symbol_value): Add support for O_secidx. * testsuite/gas/i386/secidx.s: New test source file. * testsuite/gas/i386/secidx.d: New test driver file. * testsuite/gas/i386/i386.exp: Run new test. include * coff/i386.h: Define R_SECTION. * coff/x86_64.h: Likewise. ld * testsuite/ld-pe/secidx1.s: New test source file. * testsuite/ld-pe/secidx2.s: New test source file. * testsuite/ld-pe/secidx.d: New test driver file. * testsuite/ld-pe/secidx_64.d: New test driver file. * testsuite/ld-pe/pe.exp: Add new tests.
2022-04-07 21:47:17 +08:00
2022-04-07 Mark Harmstone <mark@harmstone.com>
* config/tc-i386.c (pe_directive_secidx): New function.
(md_pseudo_table): Add support for secidx.
(x86_cons_fix_new): Likewise.
(tc_gen_reloc): Likewise.
* expr.c (op_rank): Add O_secidx.
* expr.h (operatorT): Likewise.
* symbols.c (resolve_symbol_value): Add support for O_secidx.
* testsuite/gas/i386/secidx.s: New test source file.
* testsuite/gas/i386/secidx.d: New test driver file.
* testsuite/gas/i386/i386.exp: Run new test.
IBM zSystems: Add support for z16 as CPU name. So far z16 was identified as arch14. After the machine has been announced we can now add the real name. gas/ChangeLog: * config/tc-s390.c (s390_parse_cpu): Add z16 as alternate CPU name. * doc/as.texi: Add z16 and arch14 to CPU string list. * doc/c-s390.texi: Add z16 to CPU string list. opcodes/ChangeLog: * s390-mkopc.c (main): Enable z16 as CPU string in the opcode table.
2022-04-07 13:45:49 +08:00
2022-04-07 Andreas Krebbel <krebbel@linux.ibm.com>
* config/tc-s390.c (s390_parse_cpu): Add z16 as alternate CPU
name.
* doc/as.texi: Add z16 and arch14 to CPU string list.
* doc/c-s390.texi: Add z16 to CPU string list.
Add code to display the contents of .debug_loclists sections which contain offset entry tables. PR 28981 * dwarf.c (fetch_indexed_value): Rename to fecth_indexed_addr and return the address, rather than a string. (fetch_indexed_value): New function - returns a value indexed by a DW_FORM_loclistx or DW_FORM_rnglistx form. (read_and_display_attr_value): Add support for DW_FORM_loclistx and DW_FORM_rnglistx. (process_debug_info): Load the loclists and rnglists sections. (display_loclists_list): Add support for DW_LLE_base_addressx, DW_LLE_startx_endx, DW_LLE_startx_length and DW_LLE_default_location. (display_offset_entry_loclists): New function. Displays a .debug_loclists section that contains offset entry tables. (display_debug_loc): Call the new function. (display_debug_rnglists_list): Add support for DW_RLE_base_addressx, DW_RLE_startx_endx and DW_RLE_startx_length. (display_debug_ranges): Display the contents of the section's header. * dwarf.h (struct debug_info): Add loclists_base field. * testsuite/binutils-all/dw5.W: Update expected output. * testsuite/binutils-all/x86-64/pr26808.dump: Likewise.
2022-04-06 21:43:37 +08:00
2022-04-06 Nick Clifton <nickc@redhat.com>
PR 28981
* testsuite/gas/elf/dwarf-5-irp.d: Update expected output.
z80 assembler: Fix new unexpected overflow warning in v2.37 PR 28791 * config/tc-z80.c (emit_data_val): Do not warn about overlarge constants generated by bit manipulation operators. * testsuite/gas/z80/pr28791.s: New test source file. * testsuite/gas/z80/pr28791.d: New test driver file.
2022-03-21 19:33:59 +08:00
2022-03-21 Nick Clifton <nickc@redhat.com>
PR 28791
* config/tc-z80.c (emit_data_val): Do not warn about overlarge
constants generated by bit manipulation operators.
* testsuite/gas/z80/pr28791.s: New test source file.
* testsuite/gas/z80/pr28791.d: New test driver file.
Updated French translation for the gas sub-directory.
2022-01-28 20:16:03 +08:00
2022-01-28 Nick Clifton <nickc@redhat.com>
* po/fr.po: Updated French translation.
Update Bulgarian, French, Romaniam and Ukranian translation for some of the sub-directories
2022-01-24 22:22:49 +08:00
2022-01-24 Nick Clifton <nickc@redhat.com>
* po/uk.po: Updated Ukranian translation.
Change version number to 2.38.50 and regenerate files
2022-01-22 20:39:28 +08:00
2022-01-22 Nick Clifton <nickc@redhat.com>
* configure: Regenerate.
* po/gas.pot: Regenerate.
Add markers for 2.38 branch
2022-01-22 20:08:55 +08:00
2022-01-22 Nick Clifton <nickc@redhat.com>
* 2.38 release branch created.
Update the config.guess and config.sub files from the master repository and regenerate files.
2022-01-18 00:21:22 +08:00
2022-01-17 Nick Clifton <nickc@redhat.com>
* Makefile.in: Regenerate.
* po/gas.pot: Regenerate.
Fix Z80 assembly failure. PR 28762 * app.c (do_scrub_chars): Correct handling when the symbol is not 'af'.
2022-01-17 21:00:17 +08:00
2022-01-17 Sergey Belyashov <sergey.belyashov@gmail.com>
PR 28762
* app.c (do_scrub_chars): Correct handling when the symbol is not 'af'.
Fix AVR assembler so that it creates relocs that will work with linker relaxation. PR 28686 gas * config/tc-avr.h (tc_fix_adjustable): Define. * config/tc-avr.c (avr_fix_adjustable): New function. * testsuite/gas/all/gas.exp: Skip tests that need adjustable fixups. * testsuite/gas/elf/elf.exp: Likewise. * testsuite/gas/avr/diffreloc_withrelax.d: Adjust expected output. * testsuite/gas/avr/pc-relative-reloc.d: Adjust expected output. ld * testsuite/ld-avr/avr-prop-7.d: Adjust expected output. * testsuite/ld-avr/avr-prop-8.d: Likewise. * testsuite/ld-avr/pr13402.d: Likewise.
2021-12-17 00:40:57 +08:00
2021-12-16 Nick Clifton <nickc@redhat.com>
PR 28686
* config/tc-avr.h (tc_fix_adjustable): Define.
* config/tc-avr.c (avr_fix_adjustable): New function.
* testsuite/gas/all/gas.exp: Skip tests that need adjustable fixups.
* testsuite/gas/elf/elf.exp: Likewise.
* testsuite/gas/avr/diffreloc_withrelax.d: Adjust expected output.
* testsuite/gas/avr/pc-relative-reloc.d: Adjust expected output.
[gas] Fix file 0 dir with -gdwarf-5 In out_dir_and_file_list, if file 0 is copied from file 1, only the filename is copied, and the dir and md5 fields are left to their default values. Fix this by adding the copy of the dir and md5 fields. gas/ChangeLog: 2021-11-26 Tom de Vries <tdevries@suse.de> PR 28629 * dwarf2dbg.c (out_dir_and_file_list): When copying file 1 to file 0, also copy dir and md5 fields. * testsuite/gas/i386/dwarf5-line-4.d: Adjust expected output.
2021-11-26 16:59:45 +08:00
2021-11-26 Tom de Vries <tdevries@suse.de>
PR 28629
* dwarf2dbg.c (out_dir_and_file_list): When copying file 1 to file 0,
also copy dir and md5 fields.
* testsuite/gas/i386/dwarf5-line-4.d: Adjust expected output.
Add multibyte character warning option to the assembler. * as.c (parse_args): Add support for --multibyte-handling. * as.h (multibyte_handling): Declare. * app.c (scan_for_multibyte_characters): New function. (do_scrub_chars): Call the new function if multibyte warning is enabled. * input-scrub,c (input_scrub_next_buffer): Call the multibyte scanning function if multibyte warnings are enabled. * symbols.c (struct symbol_flags): Add multibyte_warned bit. (symbol_init): Call the multibyte scanning function if multibyte symbol warnings are enabled. (S_SET_SEGMENT): Likewise. * NEWS: Mention the new feature. * doc/as.texi: Document the new feature. * testsuite/gas/all/multibyte.s: New test source file. * testsuite/gas/all/multibyte1.d: New test driver file. * testsuite/gas/all/multibyte1.l: New test expected output. * testsuite/gas/all/multibyte2.d: New test driver file. * testsuite/gas/all/multibyte2.l: New test expected output. * testsuite/gas/all/gas.exp: Run the new tests.
2021-11-19 00:48:19 +08:00
2021-11-18 Nick Clifton <nickc@redhat.com>
* as.c (parse_args): Add support for --multibyte-handling.
* as.h (multibyte_handling): Declare.
* app.c (scan_for_multibyte_characters): New function.
(do_scrub_chars): Call the new function if multibyte warning is
enabled.
* input-scrub,c (input_scrub_next_buffer): Call the multibyte
scanning function if multibyte warnings are enabled.
* symbols.c (struct symbol_flags): Add multibyte_warned bit.
(symbol_init): Call the multibyte scanning function if multibyte
symbol warnings are enabled.
(S_SET_SEGMENT): Likewise.
* NEWS: Mention the new feature.
* doc/as.texi: Document the new feature.
* testsuite/gas/all/multibyte.s: New test source file.
* testsuite/gas/all/multibyte1.d: New test driver file.
* testsuite/gas/all/multibyte1.l: New test expected output.
* testsuite/gas/all/multibyte2.d: New test driver file.
* testsuite/gas/all/multibyte2.l: New test expected output.
* testsuite/gas/all/gas.exp: Run the new tests.
Deal with full path in .file 0 directive Gas uses the directory part, if present, of the .file 0 directive to set entry 0 of the directory table in DWARF 5, which represents the "current directory". Now Gas also uses the file part of the same directive to set entry 0 of the file table, which represents the "current compilation file". But the latter need not be located in the former so GCC will use a full path in the file part when it is passed a full path: gcc -c /full/path/test.c -save-temps yields: .file 0 "/current/directory" "/full/path/test.c" in the assembly file and: The Directory Table (offset 0x22, lines 2, columns 1): Entry Name 0 (indirect line string, offset: 0x25): /current/directory 1 (indirect line string, offset: 0x38): /full/path The File Name Table (offset 0x30, lines 2, columns 2): Entry Dir Name 0 0 (indirect line string, offset: 0x43): /full/path/test.c in the object file. Note the full path and the questionable Dir value in the 0 entry of the file table.
2021-11-15 19:50:51 +08:00
2021-11-15 Eric Botcazou <ebotcazou@adacore.com>
* doc/as.texi (File): Update description of .file 0 directive.
* dwarf2dbg.c (get_directory_table_entry): Remove obsolete comment
and pass file0_dirname in recursive call.
(allocate_filename_to_slot): Deal with a full path in the file name
if the index number is 0.
* testsuite/gas/elf/dwarf-5-file0.d: Fix pasto.
* testsuite/gas/elf/dwarf-5-file0-2.d: Likewise.
* testsuite/gas/elf/dwarf-5-file0-3.d: New file.
* testsuite/gas/elf/dwarf-5-file0-3.s: Likewise.
* testsuite/gas/elf/elf.exp: Run dwarf-5-file0-3.
ARM assembler: Allow up to 32 single precision registers in the VPUSH and VPOP instructions. PR 28436 * config/tc-arm.c (do_vfp_nsyn_push_pop_check): New function. (do_vfp_nsyn_pop): Use the new function. (do_vfp_nsyn_push): Use the new function. * testsuite/gas/arm/v8_1m-mve.s: Add new instructions. * testsuite/gas/arm/v8_1m-mve.d: Updated expected disassembly.
2021-10-29 00:17:25 +08:00
2021-10-28 Markus Klein <markus.klein@sma.de>
PR 28436
* config/tc-arm.c (do_vfp_nsyn_push_pop_check): New function.
(do_vfp_nsyn_pop): Use the new function.
(do_vfp_nsyn_push): Use the new function.
* testsuite/gas/arm/v8_1m-mve.s: Add new instructions.
* testsuite/gas/arm/v8_1m-mve.d: Updated expected disassembly.
configure: regenerate in all projects that use libtool.m4 (including sim/, which has no changelog.) bfd/ChangeLog 2021-09-27 Nick Alcock <nick.alcock@oracle.com> * configure: Regenerate. binutils/ChangeLog 2021-09-27 Nick Alcock <nick.alcock@oracle.com> * configure: Regenerate. gas/ChangeLog 2021-09-27 Nick Alcock <nick.alcock@oracle.com> * configure: Regenerate. gprof/ChangeLog 2021-09-27 Nick Alcock <nick.alcock@oracle.com> * configure: Regenerate. ld/ChangeLog 2021-09-27 Nick Alcock <nick.alcock@oracle.com> * configure: Regenerate. libctf/ChangeLog 2021-09-27 Nick Alcock <nick.alcock@oracle.com> * configure: Regenerate. * Makefile.in: Regenerate. opcodes/ChangeLog 2021-09-27 Nick Alcock <nick.alcock@oracle.com> * configure: Regenerate. zlib/ChangeLog 2021-09-27 Nick Alcock <nick.alcock@oracle.com> * configure: Regenerate.
2021-09-28 03:31:21 +08:00
2021-09-27 Nick Alcock <nick.alcock@oracle.com>
* configure: Regenerate.
PowerPC: Enable mfppr mfppr32, mtppr and mtppr32 extended mnemonics on POWER5 SPR 896 and the mfppr mfppr32, mtppr and mtppr32 extended mnemonics were added in ISA 2.03, so enable them on POWER5 and later. opcodes/ * ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable on POWER5 and later. gas/ * testsuite/gas/ppc/power5.s: New test. * testsuite/gas/ppc/power5.d: Likewise. * testsuite/gas/ppc/ppc.exp: Run it. * testsuite/gas/ppc/power7.s: Remove tests for mfppr, mfppr32, mtppr and mtppr32. * testsuite/gas/ppc/power7.d: Likewise.
2021-09-26 07:21:17 +08:00
2021-09-25 Peter Bergner <bergner@linux.ibm.com>
* testsuite/gas/ppc/power5.s: New test.
* testsuite/gas/ppc/power5.d: Likewise.
* testsuite/gas/ppc/ppc.exp: Run it.
* testsuite/gas/ppc/power7.s: Remove tests for mfppr, mfppr32, mtppr
and mtppr32.
* testsuite/gas/ppc/power7.d: Likewise.
ia64: don't use get_symbol_name() for section parsing. With cross_section() later calling obj_elf_section(), it seems better to pre-parse the section name by the same function that will be used there. This way no differences in what is accepted will result. gas * config/tc-ia64.c (cross_section): Use obj_elf_section_name to parse the section name.
2021-09-13 18:00:25 +08:00
2021-09-13 Jan Beulich <jbeulich@suse.com>
* config/tc-ia64.c (cross_section): Use obj_elf_section_name to
parse the section name.
MIPS: don't use get_symbol_name() for section parsing. With s_change_section() later calling obj_elf_section(), it seems better to pre-parse the section name by the same function that will be used there. This way no differences in what is accepted will result. gas * config/tc-mips.c (s_change_section): Use obj_elf_section_name to parse the section name.
2021-09-13 18:02:48 +08:00
* config/tc-mips.c (s_change_section): Likewise.
ia64: don't use get_symbol_name() for section parsing. With cross_section() later calling obj_elf_section(), it seems better to pre-parse the section name by the same function that will be used there. This way no differences in what is accepted will result. gas * config/tc-ia64.c (cross_section): Use obj_elf_section_name to parse the section name.
2021-09-13 18:00:25 +08:00
Fix the V850 assembler's generation of relocations for the st.b instruction. PR 28292 gas * config/tc-v850.c (handle_lo16): Also accept BFD_RELOC_V850_LO16_SPLIT_OFFSET. * testsuite/gas/v850/split-lo16.s: Add extra line. * testsuite/gas/v850/split-lo16.d: Update expected disassembly. opcodes * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place of BFD_RELOC_16.
2021-09-02 19:16:10 +08:00
2021-09-02 Nick Clifton <nickc@redhat.com>
PR 28292
* config/tc-v850.c (handle_lo16): Also accept
BFD_RELOC_V850_LO16_SPLIT_OFFSET.
* testsuite/gas/v850/split-lo16.s: Add extra line.
* testsuite/gas/v850/split-lo16.d: Update expected disassembly.
Fix a typo in the RX asse,bler. The Double-precision floating-point exception handling control register name is DECNT not DCENT. * config/rx-parse.y (DECNT): Fixed typo. * testsuite/gas/rx/dpopm.sm (DECNT): Fixed typo. * testsuite/gas/rx/dpushm.sm (DECNT): Fixed typo. * testsuite/gas/rx/macros.inc (DECNT): Fixed typo.
2021-08-11 21:01:55 +08:00
2021-08-11 Darius Galis <darius.galis@cyberthorstudios.com>
* config/rx-parse.y (DECNT): Fixed typo.
* testsuite/gas/rx/dpopm.sm (DECNT): Fixed typo.
* testsuite/gas/rx/dpushm.sm (DECNT): Fixed typo.
* testsuite/gas/rx/macros.inc (DECNT): Fixed typo.
Fix an internal error in the CSKY assembler when asked to resolve an overlarge constant. PR 28215 * config/tc-csky.c (md_apply_fix): Correctly handle a fixup that involves an overlarge constant.
2021-08-11 20:49:30 +08:00
2021-08-11 Nick Clifton <nickc@redhat.com>
PR 28215
* config/tc-csky.c (md_apply_fix): Correctly handle a fixup that
involves an overlarge constant.
Add a -mno-dollar-line-separator command line option to the AVR assembler. Some frontends, like the gcc Objective-C frontend, emit symbols with $ characters in them. The AVR target code in gas treats $ as a line separator, so the code doesn?t assemble correctly. Provide a machine-specific option to disable treating $ as a line separator. * config/tc-avr.c (enum options): Add option flag. (struct option): Add option -mno-dollar-line-separator. (md_parse_option): Adjust treatment of $ when option is present. * config/tc-avr.h: Use avr_line_separator_chars.
2021-08-11 17:03:19 +08:00
2021-08-11 Matt Jacobson <mhjacobson@me.com>
* config/tc-avr.c (enum options): Add option flag.
(struct option): Add option -mno-dollar-line-separator.
(md_parse_option): Adjust treatment of $ when option is present.
(usage): Mention the new option.
* config/tc-avr.h: Use avr_line_separator_chars.
* doc/c-avr.texi: Document the new option.
Fix typo in previous delta
2021-08-11 15:44:40 +08:00
2021-08-11 Nick Clifton <nickc@redhat.com>
* config/tc-tic4x.c (tic4x_gen_to_words): Fix typo.
Updated Serbian and Russian translations for various sub-directories
2021-08-10 23:40:37 +08:00
2021-08-10 Nick Clifton <nickc@redhat.com>
* po/ru.po: Updated Russian translation.
GAS: DWARF-5: Ensure that the 0'th entry in the directory table contains the current working directory. * dwarf2dbg.c (get_directory_table_entry): Ensure that dir[0] contains current working directory. (out_dir_and_file_list): Likewise. * testsuite/gas/elf/dwarf-5-dir0.s: New test source file. * testsuite/gas/elf/dwarf-5-dir0.d: New test driver. * testsuite/gas/elf/elf.exp: Run the new test. * testsuite/gas/elf/dwarf-5-file0.d: Adjust expected output. * testsuite/gas/i386/dwarf5-line-1.d: Likewise. * testsuite/gas/i386/dwarf5-line-2.d: Likewise.
2021-08-10 00:23:22 +08:00
2021-08-09 Nick Clifton <nickc@redhat.com>
* dwarf2dbg.c (get_directory_table_entry): Ensure that dir[0]
contains current working directory.
(out_dir_and_file_list): Likewise.
* testsuite/gas/elf/dwarf-5-dir0.s: New test source file.
* testsuite/gas/elf/dwarf-5-dir0.d: New test driver.
* testsuite/gas/elf/elf.exp: Run the new test.
* testsuite/gas/elf/dwarf-5-file0.d: Adjust expected output.
* testsuite/gas/i386/dwarf5-line-1.d: Likewise.
* testsuite/gas/i386/dwarf5-line-2.d: Likewise.
gas: default TC_VALIDATE_FIX_SUB to 0 gas/write.c provides a fallback TC_VALIDATE_FIX_SUB define that can be a problem for some targets, the problem being that a non-zero definition of TC_VALIDATE_FIX_SUB says that some uses of fx_subsy are OK, in effect that the target will handle fx_subsy in md_apply_fix and/or tc_gen_reloc. A lot of targets don't have the necessary md_apply_fix and tc_gen_reloc support. So a safer default is to disallow fx_subsy by default. I've had a good look over target usage of fx_subsy, and think I've caught all the cases where targets need TC_VALIDATE_FIX_SUB. Possible failures would be limited to alpha, microblaze, ppc and s390 (the targets that define UNDEFINED_DIFFERENCE_OK), or targets that generate fixups with BFD_RELOC_GPREL32/16 and use a syntax explicitly showing a difference expression. * write.c (TC_VALIDATE_FIX_SUB): Default to 0. * config/tc-hppa.h (TC_VALIDATE_FIX_SUB): Define. * config/tc-microblaze.h (TC_VALIDATE_FIX_SUB): Define. * config/tc-alpha.h (TC_VALIDATE_FIX_SUB): Define for ECOFF. * config/tc-ppc.h (TC_VALIDATE_FIX_SUB): Don't define for ELF. Do define for XCOFF.
2021-07-10 14:28:44 +08:00
2021-07-14 Alan Modra <amodra@gmail.com>
* write.c (TC_VALIDATE_FIX_SUB): Default to 0.
* config/tc-hppa.h (TC_VALIDATE_FIX_SUB): Define.
* config/tc-microblaze.h (TC_VALIDATE_FIX_SUB): Define.
* config/tc-alpha.h (TC_VALIDATE_FIX_SUB): Define for ECOFF.
* config/tc-ppc.h (TC_VALIDATE_FIX_SUB): Don't define for ELF.
Do define for XCOFF.
objdump: add DWARF support for AIX DWARF sections have special names on AIX which need be handled by objdump in order to correctly print them. This patch also adds the correlation in bfd for future uses. bfd/ * libxcoff.h (struct xcoff_dwsect_name): Add DWARF name. * coff-rs6000.c (xcoff_dwsect_names): Update. * coffcode.h (sec_to_styp_flags): Likewise. (coff_new_section_hook): Likewise. binutils/ * dwarf.h (struct dwarf_section): Add XCOFF name. * dwarf.c (struct dwarf_section_display): Update. * objdump.c (load_debug_section): Add XCOFF name handler. (dump_dwarf_section): Likewise. gas/ * config/tc-ppc.c (ppc_change_debug_section): Update to match new name's field.
2021-06-11 17:00:56 +08:00
2021-07-14 Clément Chigot <clement.chigot@atos.net>
* config/tc-ppc.c (ppc_change_debug_section): Update to
match new name's field.
Add the SEC_ELF_OCTETS flag to debug sections created by the assembler. PR 28054 gas * config/obj-elf.c (obj_elf_change_section): Set the SEF_ELF_OCTETS flag on debug sections.
2021-07-13 00:12:13 +08:00
2021-07-12 Tucker <tuckkern@sourceware@gmail.com>
PR 28054
* config/obj-elf.c (obj_elf_change_section): Set the
SEF_ELF_OCTETS flag on debug sections.
Add changelog entries for last commit
2021-07-07 20:15:33 +08:00
2021-06-07 Andreas Krebbel <krebbel@linux.ibm.com>
* testsuite/gas/s390/zarch-arch14.d: Add qpaci.
* testsuite/gas/s390/zarch-arch14.s: Add qpaci.
Fix problems translating messages when a percentage sign appears at the end of a string. PR 28051 gas * config/tc-i386.c (offset_in_range): Reformat error messages in order to fix problems when translating. (md_assemble): Likewise. * messages.c (as_internal_value_out_of_range): Likewise. * read.c (emit_expr_with_reloc): Likewise. * testsuite/gas/all/overflow.l Change expected output format. * po/gas.pot: Regenerate. bfd * coff-rs6000.c (xcoff_reloc_type_tls): Reformat error messages in order to fix problems when translating. * cofflink.c (_bfd_coff_write_global_sym): Likewise. * elfnn-aarch64.c (_bfd_aarch64_erratum_843419_branch_to_stub): Likewise. * po/bfd.pot: Regenerate.
2021-07-07 17:25:41 +08:00
2021-07-07 Nick Clifton <nickc@redhat.com>
PR 28051
* config/tc-i386.c (offset_in_range): Reformat error messages in
order to fix problems when translating.
(md_assemble): Likewise.
* messages.c (as_internal_value_out_of_range): Likewise.
* read.c (emit_expr_with_reloc): Likewise.
* testsuite/gas/all/overflow.l Change expected output format.
* po/gas.pot: Regenerate.
Update version number and regenerate files
2021-07-03 22:16:48 +08:00
2021-07-03 Nick Clifton <nickc@redhat.com>
* configure: Regenerate.
* po/gas.pot: Regenerate.
Add markers for 2.37 branch
2021-07-03 21:50:57 +08:00
2021-07-03 Nick Clifton <nickc@redhat.com>
* 2.37 release branch created.
Re: Fix minor NDS32 renaming snafu Some extern declarations differ in constnes to their definitions too. Let's make sure this sort of thing doesn't happen again, but putting the externs in a header where they belong. gas/ * config/tc-nds32.c (nds32_keyword_gpr): Don't declare. (md_begin): Constify k. opcodes/ * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return. (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg. (nds32_field_table, nds32_opcode_table, nds32_keyword_table), (nds32_opcodes, nds32_operand_fields, nds32_keywords), (nds32_keyword_gpr): Move declarations to.. * nds32-asm.h: ..here, constifying to match definitions.
2021-07-02 15:57:31 +08:00
2021-07-02 Alan Modra <amodra@gmail.com>
* config/tc-nds32.c (nds32_keyword_gpr): Don't declare.
(md_begin): Constify k.
Fix minor NDS32 renaming snafu. * config/tc-nds32.c: Change all references of keyword_gpr to nds32_keyword_gpr.
2021-07-02 17:45:02 +08:00
2021-07-02 Nick Clifton <nickc@redhat.com>
* config/tc-nds32.c: Change all references of keyword_gpr to
nds32_keyword_gpr.
opcodes: constify & scope microblaze opcodes This is exporting the variable "opcodes" as a large writable blob. This is not a namespace friendly name, so add a "microblaze" prefix, and then sprinkle const over its definition & use.
2021-06-27 13:55:50 +08:00
2021-07-01 Mike Frysinger <vapier@gentoo.org>
* config/tc-microblaze.c (md_begin): Make opcode const. Rename
opcodes to microblaze_opcodes.
opcodes: constify aarch64_opcode_tables This table is huge (~350k), so stop putting it into writable .data since it's only const data.
2021-06-27 13:37:24 +08:00
2021-07-01 Mike Frysinger <vapier@gentoo.org>
* config/tc-aarch64.c (struct templates): Make opcode const.
(md_assemble): Likewise.
(fill_instruction_hash_table): Likewise.
gas: update csect alignment for PPC prefixed instructions on XCOFF Power10 prefixed instructions must not cross 64-byte boundaries. This is already handled. However, on XCOFF, the csect must be updated to match the new alignment. * config/tc-ppc.c (md_assemble): Update ppc_current_csect alignment when finding prefixed instructions.
2021-06-22 16:15:06 +08:00
2021-06-24 Clément Chigot <clement.chigot@atos.net>
* config/tc-ppc.c (md_assemble): Update ppc_current_csect
alignment when finding prefixed instructions.
picojava assembler and disassembler fixes Commit 54758c3e398d made changes to the picojava support based on https://sourceware.org/pipermail/binutils/2005-November/045136.html An update from picojava to picojava II, I think. Unfortunately the patch neglected any changes to the gas testsuite, resulting in "FAIL: pj" since that date. This patch makes a few relatively simple changes to cure the regression. gas/ * config/tc-pj.c (md_apply_fix): Apply PJ_CODE_REL32 relocs. * testsuite/gas/pj/ops.s: Update jsr, ret, getstatic, putstatic, getfield, putfield, invokevirtual, invokespecial, invokestatic, invokeinterface, goto_w, jsr_w assembly. Delete version 1 picojava opcodes. * testsuite/gas/pj/ops.d: Match expected output. opcodes/ * pj-dis.c (print_insn_pj): Don't print trailing tab. Do print separator for pcrel insns.
2021-06-21 15:37:05 +08:00
2021-06-22 Alan Modra <amodra@gmail.com>
* config/tc-pj.c (md_apply_fix): Apply PJ_CODE_REL32 relocs.
* testsuite/gas/pj/ops.s: Update jsr, ret, getstatic,
putstatic, getfield, putfield, invokevirtual, invokespecial,
invokestatic, invokeinterface, goto_w, jsr_w assembly. Delete
version 1 picojava opcodes.
* testsuite/gas/pj/ops.d: Match expected output.
ubsan errors when 32-bit bfd A shift count exceeding the size of the value is undefined behaviour, and so is negating a signed LONG_MIN. * config/tc-z80.c (signed_overflow, unsigned_overflow): Avoid UB.
2021-06-18 20:57:01 +08:00
2021-06-19 Alan Modra <amodra@gmail.com>
* config/tc-z80.c (signed_overflow, unsigned_overflow): Avoid UB.
ppc raw test failure when 32-bit bfd The test contained an expression that can't be evaluated unless expressions are 64-bit. * testsuite/gas/ppc/raw.s: Use 0 as pli constant. * testsuite/gas/ppc/raw.d: Update to suit.
2021-06-18 20:56:11 +08:00
2021-06-19 Alan Modra <amodra@gmail.com>
* testsuite/gas/ppc/raw.s: Use 0 as pli constant.
* testsuite/gas/ppc/raw.d: Update to suit.
gas: fold symbol table entries generated for .startof.() / .sizeof.() When the same such construct is used multiple times in a source file, there's still no need to emit a separate symbol each time. Under the assumption that there won't be many of these, use a simple array lookup method to record previously used symbols.
2021-06-18 19:51:52 +08:00
2021-06-18 Jan Beulich <jbeulich@suse.com>
* expr.c (symbol_lookup_or_make): New.
(operand): Use it.
* testsuite/gas/elf/startof.s, testsuite/gas/elf/startof.d: New.
* testsuite/gas/elf/elf.exp: Run new test.
Fix an assertion failure in the AArch64 assembler triggered by incorrect instruction syntax. PR 27904 * config/tc-aarch64.c (ldst_lo12_determine_real_reloc_type): Generate a syntax error message if the reloc qualifier does not match the instruction's size.
2021-06-17 23:19:20 +08:00
2021-06-17 Nick Clifton <nickc@redhat.com>
PR 27904
* config/tc-aarch64.c (ldst_lo12_determine_real_reloc_type):
Generate a syntax error message if the reloc qualifier does not
match the instruction's size.
gas: handle csect in bss section for XCOFF Latest gcc versions are now generating csects instead of .lcomm for bss symbols. Some adjustements are needed in order to handle them. * config/tc-ppc.c (md_begin): Create bss section with dummy symbol. (ppc_frob_symbol): Output XTY_CM for bss csects. (ppc_fix_adjustable): Adjust condition to avoid bss csects.
2021-06-15 17:06:52 +08:00
2021-06-17 Clément Chigot <clement.chigot@atos.net>
* config/tc-ppc.c (md_begin): Create bss section with dummy
symbol.
(ppc_frob_symbol): Output XTY_CM for bss csects.
(ppc_fix_adjustable): Adjust condition to avoid bss csects.
gas: ensure sections contents is zero for BFD_RELOC_PPC*_TLSM on XCOFF. AIX ld expects the section contents for relocations BFD_RELOC_PPC_TLSM or BFD_RELOC_PPC64_TLSM to be zero. Actually, it seems to be the case for all the TLS relocations generated by AIX assembly but only these two are mandatory. * config/tc-ppc.c (md_apply_fix): Adjust addend to nullify section contents for BFD_RELOC_PPC_TLSM or BFD_RELOC_PPC64_TLSM. * testsuite/gas/ppc/xcoff-tlsm-32.d: New test. * testsuite/gas/ppc/xcoff-tlsm-64.d: New test. * testsuite/gas/ppc/xcoff-tlsm.s: New test. * testsuite/gas/ppc/aix.exp: Run new tests.
2021-06-14 19:25:42 +08:00
2021-06-17 Clément Chigot <clement.chigot@atos.net>
* config/tc-ppc.c (md_apply_fix): Adjust addend to nullify
section contents for BFD_RELOC_PPC_TLSM or
BFD_RELOC_PPC64_TLSM.
* testsuite/gas/ppc/xcoff-tlsm-32.d: New test.
* testsuite/gas/ppc/xcoff-tlsm-64.d: New test.
* testsuite/gas/ppc/xcoff-tlsm.s: New test.
* testsuite/gas/ppc/aix.exp: Run new tests.
gas: fix hex float parsing from .dcb.? directives Unlike for .dc.? the parsing here failed to skip the colon before calling hex_float(). To avoid both variants of parsing going out of sync again, introduce a helper used by both.
2021-06-16 14:55:52 +08:00
2021-06-16 Jan Beulich <jbeulich@suse.com>
* read.c (parse_one_float): New.
(s_float_space, float_cons): Use it.
* testsuite/gas/all/float.s: Add .dc.*, .dcb.*, and .ds.* cases.
gas: fix overflow diagnostics While the logic in fixup_segment() so far was off by 1 for fixups dealing with quantities without known signedness, thus failing to report an overflow when e.g. a byte-sized resulting value is -0x100, the logic in emit_expr_with_reloc() reported an overflow even on large negative values when the respective positive ones would not be warned about, and when fixup_segment() wouldn't do so either. Such diagnostics all ought to follow a similar pattern of what value range is acceptable. (If expressions' X_unsigned was reliably set, emit_expr_with_reloc()'s checking might make sense to tighten based on that flag.) Note that with commit 80aab57939a0 ("Changes to let cons handle bignums like general expressions") having added handling of nbytes > sizeof(valueT) in the O_constant case, converting to O_big, the setting to zero of "hibit" had become dead. With "hibit" no longer used, this code now gets dropped altogether. But additionally a respective know() gets inserted.
2021-06-16 14:55:20 +08:00
2021-06-16 Jan Beulich <jbeulich@suse.com>
* read.c (emit_expr_with_reloc): Adjust overflow check. Drop
hibit local variable.
* write.c (fixup_segment): Differentiate signed and non-signed
relocs in overflow check.
* testsuite/gas/all/overflow.s,
testsuite/gas/all/overflow.l: New.
* testsuite/gas/all/gas.exp: Run new test.
x86: bring "gas --help" output for --32 etc in sync with reality The testsuite uses the output to determine whether BFD64 is in effect. --x32 is supported for ELF only; don't advertise it for PE/COFF. --64 is also supported for Mach-O; advertise it. Adjust the testsuite's BFD64 check accordingly. Also replace "code" by "object", since it's the object format that the options primarily control. It's also _initial_ code bitness, but this can be changed by directives.
2021-06-15 14:01:12 +08:00
2021-06-15 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (md_show_usage): Split ELF and PE/COFF parts
of object format controlling option. Add Mach-O to the latter.
* testsuite/gas/i386/i386.exp (gas_bfd64_check): Adjust
accordingly.
x86: simplify .dispNN setting First of all eliminate the disp{16,32,32s} static variables, which are used solely for setting a temporary variable in build_modrm_byte(). The effect there can be had without use of such a temporary and without operand_type_or(), by just setting the single bit each that needs setting. Then use operand_type_and_not(..., anydisp) when all dispNN bits want clearing together.
2021-06-15 14:00:45 +08:00
2021-06-15 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (disp16, disp32, disp32s): Delete.
(optimize_disp, i386_finalize_displacement): Use
operand_type_and_not.
(build_modrm_byte): Likewise. Eliminate local variable newdisp.
x86: slightly simplify offset_in_range() Applying a mask with all bits set (or its inverse, with hence all bits clear) won't alter the result (or won't trigger the warning). Re-arrange the code to eliminate two more of the somewhat odd (2 << width_minus_1) constructs.
2021-06-15 14:00:17 +08:00
2021-06-15 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (offset_in_range): Bail early when mask would
cover all bits anyway.
x86: harmonize disp with imm handling Certain disp values may trigger "... shortened to ..." warnings when equivalent imm ones don't. In some of the cases there are also differences (for non-64-bit code) between BFD64 and !BFD64 builds. The resulting encodings (i.e. use [or not] of the shorter disp8 / imm8 forms) are also different in some cases. Make this handling consistent. Note that using equivalent 16-bit mode displacements / immediates continues to expose entirely different behavior (see the disp-imm-16 testcase added by an earlier patch). This may want to be the subject of further changes, but it'll then quickly become obvious that e.g. keying use of extend_to_32bit_address() to non-64-bit mode isn't appropriate either: Once we allow wrapping operands, we would better do so consistently, in which case all of this would need to become dependent upon address or operand size instead of mode.
2021-06-15 13:59:44 +08:00
2021-06-15 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (optimize_disp): Generalize disp32 part of
the BFD64-only logic to also apply to non-64-bit code.
(i386_finalize_displacement): Use extend_to_32bit_address for
non-64-bit code. Drop now redundant O_constant checks.
* testsuite/gas/i386/disp-imm-32.s,
testsuite/gas/i386/disp-imm-32.d: New.
* testsuite/gas/i386/i386.exp: Run new test.
x86: make offset_in_range()'s warning contents useful (again) In case there is something which gets shortened (perhaps only on a BFD64 build targeting a 32-bit binary), seeing the full original value is often helpful to understand what's actually going wrong. Of course for non-64-bit binaries we better wouldn't be seeing such warnings at all, as they're often indicative of a behavioral difference between BFD64 and !BFD64 builds. Prior to "gas: drop sprint_value()", which introduced the use of bfd_sprintf_vma(), the output had other shortcomings.
2021-06-15 13:58:57 +08:00
2021-06-15 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (offset_in_range): Replace uses of
bfd_sprintf_vma.
x86: off-by-1 in offset_in_range() Just like e.g. 0x10000 triggers a warning for size 2, -0x10000 ought to as well. Note that some of the encodings produced aren't ones one would expect, and hence the generated code is not being checked for in the new testcases.
2021-06-15 13:58:18 +08:00
2021-06-15 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (offset_in_range): Adjust conditional.
* testsuite/gas/i386/disp-imm-16.s,
testsuite/gas/i386/disp-imm-16.l,
testsuite/gas/i386/disp-imm-64.s,
testsuite/gas/i386/disp-imm-64.l: New.
* testsuite/gas/i386/i386.exp: Run new tests.
x86: permit parenthesized expressions again as addressing scale factor The description of e68c3d59acd0 ("x86: better respect quotes in parse_operands()") wrongly states: "In i386_att_operand(), which needs adjustment to remain in sync, besides respecting double quotes now, also change the logic such that we don't count parentheses anymore: Finding any opening or closing parenthesis or any double quote means we're done, because the subsequent parsing code wouldn't accept (extra) instances of these anyway." I didn't pay attention to the possibility of the scale factor being specified as an expression, which may contain parentheses. Thanks to Martin for pointing this out. Restore prior behavior or matching parentheses (backwards), while giving the variable a more suitable name. Note that this simple and immediate fix is not ging to be enough: This expression could itself involve quoted symbols. However, to address this backwards parsing needs to be done away with altogether here (such that parentheses which are part of such a quoted symbol name can also properly be accounted for), which is going to be a more intrusive change.
2021-06-15 13:57:11 +08:00
2021-06-15 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (i386_att_operand): Re-introduce (now
properly named) parens_not_balanced.
* testsuite/gas/i386/sib.s: Add more cases.
* testsuite/gas/i386/sib.d, testsuite/gas/i386/sib-intel.d:
Adjust expectations.
gas: fold three as_warn() in emit_expr_with_reloc() Simply use the available abstraction instead of, effectively, trying to open-code it.
2021-06-14 14:18:58 +08:00
2021-06-14 Jan Beulich <jbeulich@suse.com>
* read.c (emit_expr_with_reloc): Fold three as_warn().
gas: drop TC_ADDRESS_BYTES conditionals I've been repeatedly confused by, in particular, the .dc.a potable[] entry being conditional. Grepping in gas/config/ reveals only very few targets actually #define-ing it. But as of 7be1c4891a20 the symbol is always defined, so #ifdef-s are pointless (and, as said, potentially confusing). Also adjust documentation to reflect this.
2021-06-14 14:18:07 +08:00
2021-06-14 Jan Beulich <jbeulich@suse.com>
* doc/internals.texi (TC_ADDRESS_BYTES): Mention generic default.
* read.c (potable, cons_worker): Drop TC_ADDRESS_BYTES
conditional.
x86: Always define TC_PARSE_CONS_EXPRESSION Always define TC_PARSE_CONS_EXPRESSION to properly wrap constants for all x86 targets. * config/tc-i386.c (x86_cons): Handle GOT/PLT relocations only if needed. * config/tc-i386.h (TC_PARSE_CONS_EXPRESSION): Always define.
2021-06-11 21:19:16 +08:00
2021-06-11 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (x86_cons): Handle GOT/PLT relocations only
if needed.
* config/tc-i386.h (TC_PARSE_CONS_EXPRESSION): Always define.
RISC-V: Update the riscv_opts.[rvc|rve] in the riscv_set_arch. We also need to update the riscv_opts.[rvc|rve] for elf attributes. Otherwise, the following case will fail, $ cat cadd.s .attribute arch, "rv64gc" c.add a0, a1 $ riscv64-unknown-elf-as cadd.s -o cadd.o cadd.s: Assembler messages: cadd.s:2: Error: illegal operands `c.add a0,a1 After applying this patch, $ riscv64-unknown-elf-as cadd.s -o cadd.o $ riscv64-unknown-elf-objdump -d cadd.o cadd.o: file format elf64-littleriscv Disassembly of section .text: 0000000000000000 <.text>: 0: 952e add a0,a0,a1 ... gas/ * config/tc-riscv.c (riscv_set_arch): Call riscv_set_rvc and riscv_set_rve both for -march and elf attributes. (riscv_after_parse_args): Likewise.
2021-06-11 17:23:43 +08:00
2021-06-11 Nelson Chu <nelson.chu@sifive.com>
* config/tc-riscv.c (riscv_set_arch): Call riscv_set_rvc
and riscv_set_rve both for -march and elf attributes.
(riscv_after_parse_args): Likewise.
arm: avoid "shadowing" of glibc function name Old enough glibc has an (unguarded) declaration of index() in string.h, which triggers a "shadows a global declaration" warning.
2021-06-10 18:40:11 +08:00
2021-06-10 Jan Beulich <jbeulich@suse.com>
* config/tc-arm.c (do_bfloat_vfma): Rename index to idx.
(do_vusdot): Likewise.
(do_vsudot): Likewise.
(check_cde_operand): Likewise.
(do_vdot): Likewise.
arm: fix array-out-of-bounds upon register parsing error Despite the comment ahead of the enum explicitly pointing out the need to also update the corresponding array, 1b8833198c0 ("Add support for MVE instructions: vcmp and vpt") failed to do so. Oddly enough the issue appears to be spotted only by rather old gcc (4.3-ish in my case).
2021-06-10 18:39:40 +08:00
2021-06-10 Jan Beulich <jbeulich@suse.com>
* config/tc-arm.c (reg_expected_msgs): Add REG_TYPE_ZR entry.
x86: suppress LEA optimization in a specific 16-bit case In 16-bit mode a 16-bit address size LEA with a 16-bit displacement and a 32-bit destination is shorter to encode than the corresponding MOV. Commit fe134c656991 ("x86: optimize LEA")'s promise was to only do the transformation when the encoding size wouldn't grow, i.e. it did go a little too far. Restrict this specific case of the transformation to -O2.
2021-06-10 18:39:08 +08:00
2021-06-10 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (optimize_encoding): Suppress LEA conversion
when it would grow code size in 16-bit mode.
* testsuite/gas/i386/lea16-optimize.d: Adjust expectations.
* testsuite/gas/i386/lea16-optimize2.d: New.
* testsuite/gas/i386/i386.exp: Run new test.
x86: cover a.out in recently added tests Follow the pattern found elsewhere when relocations are involved. For wrap32-data also drop a mistakenly left "ELF" from the test name. (Note that Darwin, for which the wrap32 tests are also failing, is left as-is, for there being numerous other failures already anyway, and it hence being questionable whether that target is actually properly maintained.)
2021-06-08 20:57:50 +08:00
2021-06-08 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/quoted.d, testsuite/gas/i386/wrap32-text.d:
Adjust expectations.
* testsuite/gas/i386/wrap32-data.d: Likewise. Correct name.
x86: minor improvements to optimize_imm() (part II) Don't kind-of-open-code fits_in_unsigned_{word,long}().
2021-06-08 20:57:18 +08:00
2021-06-08 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (optimize_imm): Use fits_in_unsigned_word
and fits_in_unsigned_long.
x86: minor improvements to optimize_disp() (part II) - Don't kind-of-open-code fits_in_unsigned_{word,long}(). - Fold two if()s both using fits_in_unsigned_long().
2021-06-08 20:56:39 +08:00
2021-06-08 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (optimize_disp): Use fits_in_unsigned_word
and fits_in_unsigned_long. Combine if()s.
x86-64: avoid bogus warnings with 32-bit addressing With optimize_disp() adjusting i.types[].bitfield.disp after adjusting the value to be used as displacement, it better also stores the updated value, to avoid subsequent "... shortened to ..." warnings. Note how optimize_imm() already does so. The -0xffffffff tests being added expose a separate issue: The encoding chosen should be 1 for ModR/M.mod, not 2. This will want to be taken care of, but not right here. This at the same time addresses a similar warning and demonstrates a similar encoding issue with 16-bit addressing. Since it was omitted when introducing the lea16-optimize test, add a plain lea16 one to also cover this.
2021-06-08 20:55:56 +08:00
2021-06-08 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (optimize_disp): Write back updated value.
* testsuite/gas/i386/lea16.s, testsuite/gas/i386/lea64.s: New
cases.
* testsuite/gas/i386/lea16-optimize.d,
testsuite/gas/i386/lea64.d, testsuite/gas/i386/lea64-optimize.d:
Adjust expectations.
* testsuite/gas/i386/lea16.d: New.
* testsuite/gas/i386/i386.exp: Run new test.
x86: minor improvements to optimize_disp() (part I) - Do the zero checking first - there's no point in doing anything else in this case. - Drop two pointless & where just before it was checked that the respective bits are clear already anyway.
2021-06-08 20:54:48 +08:00
2021-06-08 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (optimize_disp): Drop redundant masking.
Re-order.
x86: honor quoted figure braces in i386_att_operand() When AVX512 support was added, symbol quotation was not paid attention to. Just like the (base,index,scale) specifier gets parsed from the end of the expression, the {...} also wants parsing from the end; in no case is the first { found a guarantee of a masking or broadcasting specifier.
2021-06-07 18:05:35 +08:00
2021-06-07 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (i386_att_operand): Re-write handling of
vector operations operand suffix.
* testsuite/gas/i386/unary.s: Add more cases.
* testsuite/gas/i386/unary.d: Adjust expectations.
x86: better respect quotes in parse_operands() When d02603dc201f ("Allow symbol and label names to be enclosed in double quotes") added the check for a double quote to the loop body there, it didn't go quite far enough: Parentheses inside quotes shouldn't be counted, and character restrictions also shouldn't apply inside quoted regions. In i386_att_operand(), which needs adjustment to remain in sync, besides respecting double quotes now, also change the logic such that we don't count parentheses anymore: Finding any opening or closing parenthesis or any double quote means we're done, because the subsequent parsing code wouldn't accept (extra) instances of these anyway. Note that in parse_operands() this mimics get_symbol_name()'s questionable behavior of treating \ specially only when ahead of ". (The behavior is suspicious because the meaning of \\ then is ambiguous. It is in particular impossible to have a (quoted) symbol name end in a single \.) I would have used get_symbol_name() here, if that didn't require fiddling with input_line_pointer.
2021-06-07 18:05:02 +08:00
2021-06-07 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (parse_operands): Reduce scope of
paren_not_balanced, to match the new in_quotes. Skip over quoted
regions of operands.
(i386_att_operand): Remove (mis-named) parens_balanced. Respect
double quote.
* testsuite/gas/i386/unary.s: Add more cases.
* testsuite/gas/i386/unary.d: Adjust expectations.
x86: allow unary operators to start a memory operand So far only - was permitted, but +, !, and ~ ought to be treated the same. Rather than adding them to digit_chars[], which was at least odd to have held - so far, drop this array and its wrapper macro for being used just once. While adjusting this logic, also include [ in the characters which may start a displacement expression - gas generally treats [] as equivalent to ().
2021-06-07 18:04:24 +08:00
2021-06-07 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (digit_chars, is_digit_char): Delete.
(md_begin): Fold digit and lower-case letter handling.
(starts_memory_operand): Permit more characters.
* testsuite/gas/i386/unary.s, testsuite/gas/i386/unary.d: New.
* testsuite/gas/i386/i386.exp: Run new test.
x86: make symbol quotation check consistent in i386_att_operand() When d02603dc201f ("Allow symbol and label names to be enclosed in double quotes") added the check for a leading double quote to i386_att_operand(), it missed a second similar check after having found a segment override. To avoid the two checks going out of sync again, introduce an inline helper.
2021-06-07 18:03:32 +08:00
2021-06-07 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (starts_memory_operand): New.
(i386_att_operand): Use it.
* testsuite/gas/i386/quoted.s, testsuite/gas/i386/quoted.d: New.
* testsuite/gas/i386/i386.exp: Run new test.
x86: correct absolute branch check with segment override This needs to happen before checking of what may legitimately start a memory operand (like is done when there's no segment override). Plus a second '*' shouldn't be permitted when one was already found before the segment override.
2021-06-07 18:02:15 +08:00
2021-06-07 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (i386_att_operand): Flip checking for '*' and
start-of-expression. Don't permit '*' when one was already seen.
x86/Intel: drop unnecessary bracket matching from parse_operands() While subsequent processing in AT&T mode relies on this simplistic early checking, Intel mode hasn't been for quite a long time (or perhaps never really did).
2021-06-07 18:01:45 +08:00
2021-06-07 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (parse_operands): Don't check for matched
square brackets.
x86: remove pointless 2nd parameter from check_VecOperations() In the one case where non-NULL gets passed, passing NULL has the same effect. Hence the parameter is not needed at all.
2021-06-07 18:01:14 +08:00
2021-06-07 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (check_VecOperations): Remove 2nd parameter.
(i386_att_operand): Adjust calls to check_VecOperations.
* config/tc-i386-intel.c (i386_intel_operand): Likewise.
x86: immediate operands don't allow for vector operations Neither masking nor broadcast are possible here, and RC/SAE get dealt with elsewhere. This also fixes gas crashes (i.e. "Fatal error: unable to continue with assembly"), since the return path being removed failed to restore input_line_pointer from save_input_line_pointer.
2021-06-07 18:00:38 +08:00
2021-06-07 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (i386_immediate): Don't call check_VecOperations.
ix86: wrap constants Non-64-bit code should get handled the same with or without BFD64. This wasn't the case though in a number of situations (and quite likely there are more that I haven't spotted yet). It's not very nice to tie the check in md_apply_fix() to object_64bit, but afaict at that time we have no record anymore of the mode an insn was assembled in (it might also have been data). This doesn't look to be the first inconsistency of this kind, though. In x86_cons() it's even less clear what the right approach would be: flag_code shouldn't matter for data emission, but instead we'd need to know from which mode(s) the data actually gets accessed. On this basis, signed_cons() also gets adjusted.
2021-06-07 14:49:33 +08:00
2021-06-07 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (extend_to_32bit_address): New.
(x86_cons, i386_finalize_immediate, md_apply_fix): Use it.
(signed_cons): Use object_64bit.
* testsuite/gas/i386/wrap32.s, testsuite/gas/i386/wrap32-data.d,
testsuite/gas/i386/wrap32-text.d: New.
* testsuite/gas/i386/i386.exp: Run new tests.
PR1202, mcore disassembler: wrong address loopt Fixes a 16 year old bug report, which even came with a patch. opcodes/ PR 1202 * mcore-dis.c (print_insn_mcore): Correct loopt disassembly. Use unsigned int for inst. gas/ PR 1202 * testsuite/gas/mcore/allinsn.d: Correct loopt expected output.
2021-06-03 10:33:09 +08:00
2021-06-03 Alan Modra <amodra@gmail.com>
PR 1202
* testsuite/gas/mcore/allinsn.d: Correct loopt expected output.
PowerPC table driven -Mraw disassembly opcodes/ * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many. Don't special case PPC_OPCODE_RAW. (lookup_prefix): Likewise. (lookup_vle, lookup_spe2): Similarly. Add dialect parameter and.. (print_insn_powerpc): ..update caller. * ppc-opc.c (EXT): Define. (powerpc_opcodes): Mark extended mnemonics with EXT. (prefix_opcodes, vle_opcodes): Likewise. (XISEL, XISEL_MASK): Add cr field and simplify. (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort all isel variants to where the base mnemonic belongs. Sort dstt, dststt and dssall. gas/ * testsuite/gas/ppc/raw.s, * testsuite/gas/ppc/raw.d: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2021-05-28 11:54:16 +08:00
2021-05-29 Alan Modra <amodra@gmail.com>
* testsuite/gas/ppc/raw.s,
* testsuite/gas/ppc/raw.d: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
MIPS/GAS/testsuite: Add C0, C1, C2, C3 opcode tests Add tests for the generic C0, C1, C2, C3 coprocessor instructions. gas/ * testsuite/gas/mips/c0.d: New test. * testsuite/gas/mips/mips1@c0.d: New test. * testsuite/gas/mips/mips2@c0.d: New test. * testsuite/gas/mips/mips3@c0.d: New test. * testsuite/gas/mips/mips4@c0.d: New test. * testsuite/gas/mips/mips5@c0.d: New test. * testsuite/gas/mips/mips32@c0.d: New test. * testsuite/gas/mips/mips64@c0.d: New test. * testsuite/gas/mips/r3000@c0.d: New test. * testsuite/gas/mips/r3900@c0.d: New test. * testsuite/gas/mips/r4000@c0.d: New test. * testsuite/gas/mips/vr5400@c0.d: New test. * testsuite/gas/mips/r5900@c0.d: New test. * testsuite/gas/mips/sb1@c0.d: New test. * testsuite/gas/mips/interaptiv-mr2@c0.d: New test. * testsuite/gas/mips/octeon@c0.d: New test. * testsuite/gas/mips/xlr@c0.d: New test. * testsuite/gas/mips/c1.d: New test. * testsuite/gas/mips/mips1@c1.d: New test. * testsuite/gas/mips/mips2@c1.d: New test. * testsuite/gas/mips/mips3@c1.d: New test. * testsuite/gas/mips/mips4@c1.d: New test. * testsuite/gas/mips/mips5@c1.d: New test. * testsuite/gas/mips/mips32@c1.d: New test. * testsuite/gas/mips/mips64@c1.d: New test. * testsuite/gas/mips/mipsr6@c1.d: New test. * testsuite/gas/mips/r3000@c1.d: New test. * testsuite/gas/mips/r3900@c1.d: New test. * testsuite/gas/mips/r4000@c1.d: New test. * testsuite/gas/mips/vr5400@c1.d: New test. * testsuite/gas/mips/r5900@c1.d: New test. * testsuite/gas/mips/sb1@c1.d: New test. * testsuite/gas/mips/interaptiv-mr2@c1.d: New test. * testsuite/gas/mips/octeon@c1.d: New test. * testsuite/gas/mips/xlr@c1.d: New test. * testsuite/gas/mips/c2.d: New test. * testsuite/gas/mips/vr5400@c2.d: New test. * testsuite/gas/mips/r5900@c2.d: New test. * testsuite/gas/mips/octeon@c2.d: New test. * testsuite/gas/mips/c3.d: New test. * testsuite/gas/mips/mips1@c3.d: New test. * testsuite/gas/mips/mips2@c3.d: New test. * testsuite/gas/mips/mips32@c3.d: New test. * testsuite/gas/mips/r3000@c3.d: New test. * testsuite/gas/mips/r3900@c3.d: New test. * testsuite/gas/mips/c0.l: New test stderr output. * testsuite/gas/mips/c2.l: New test stderr output. * testsuite/gas/mips/c3.l: New test stderr output. * testsuite/gas/mips/c0.s: New test source. * testsuite/gas/mips/c1.s: New test source. * testsuite/gas/mips/c2.s: New test source. * testsuite/gas/mips/c3.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2021-05-29 09:26:33 +08:00
2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
* testsuite/gas/mips/c0.d: New test.
* testsuite/gas/mips/mips1@c0.d: New test.
* testsuite/gas/mips/mips2@c0.d: New test.
* testsuite/gas/mips/mips3@c0.d: New test.
* testsuite/gas/mips/mips4@c0.d: New test.
* testsuite/gas/mips/mips5@c0.d: New test.
* testsuite/gas/mips/mips32@c0.d: New test.
* testsuite/gas/mips/mips64@c0.d: New test.
* testsuite/gas/mips/r3000@c0.d: New test.
* testsuite/gas/mips/r3900@c0.d: New test.
* testsuite/gas/mips/r4000@c0.d: New test.
* testsuite/gas/mips/vr5400@c0.d: New test.
* testsuite/gas/mips/r5900@c0.d: New test.
* testsuite/gas/mips/sb1@c0.d: New test.
* testsuite/gas/mips/interaptiv-mr2@c0.d: New test.
* testsuite/gas/mips/octeon@c0.d: New test.
* testsuite/gas/mips/xlr@c0.d: New test.
* testsuite/gas/mips/c1.d: New test.
* testsuite/gas/mips/mips1@c1.d: New test.
* testsuite/gas/mips/mips2@c1.d: New test.
* testsuite/gas/mips/mips3@c1.d: New test.
* testsuite/gas/mips/mips4@c1.d: New test.
* testsuite/gas/mips/mips5@c1.d: New test.
* testsuite/gas/mips/mips32@c1.d: New test.
* testsuite/gas/mips/mips64@c1.d: New test.
* testsuite/gas/mips/mipsr6@c1.d: New test.
* testsuite/gas/mips/r3000@c1.d: New test.
* testsuite/gas/mips/r3900@c1.d: New test.
* testsuite/gas/mips/r4000@c1.d: New test.
* testsuite/gas/mips/vr5400@c1.d: New test.
* testsuite/gas/mips/r5900@c1.d: New test.
* testsuite/gas/mips/sb1@c1.d: New test.
* testsuite/gas/mips/interaptiv-mr2@c1.d: New test.
* testsuite/gas/mips/octeon@c1.d: New test.
* testsuite/gas/mips/xlr@c1.d: New test.
* testsuite/gas/mips/c2.d: New test.
* testsuite/gas/mips/vr5400@c2.d: New test.
* testsuite/gas/mips/r5900@c2.d: New test.
* testsuite/gas/mips/octeon@c2.d: New test.
* testsuite/gas/mips/c3.d: New test.
* testsuite/gas/mips/mips1@c3.d: New test.
* testsuite/gas/mips/mips2@c3.d: New test.
* testsuite/gas/mips/mips32@c3.d: New test.
* testsuite/gas/mips/r3000@c3.d: New test.
* testsuite/gas/mips/r3900@c3.d: New test.
* testsuite/gas/mips/c0.l: New test stderr output.
* testsuite/gas/mips/c2.l: New test stderr output.
* testsuite/gas/mips/c3.l: New test stderr output.
* testsuite/gas/mips/c0.s: New test source.
* testsuite/gas/mips/c1.s: New test source.
* testsuite/gas/mips/c2.s: New test source.
* testsuite/gas/mips/c3.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
MIPS/GAS/testsuite: Run RFE test across all ISAs Verify that the RFE instruction is not only accepted where supported, but rejected where it is not as well. gas/ * testsuite/gas/mips/mips.exp: Run RFE test across all ISAs. * testsuite/gas/mips/rfe.d: Update for ISA exclusions. * testsuite/gas/mips/mips1@rfe.d: New test. * testsuite/gas/mips/mips2@rfe.d: New test. * testsuite/gas/mips/r3000@rfe.d: New test. * testsuite/gas/mips/r3900@rfe.d: New test. * testsuite/gas/mips/rfe.l: New test stderr output.
2021-05-29 09:26:33 +08:00
2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
* testsuite/gas/mips/mips.exp: Run RFE test across all ISAs.
* testsuite/gas/mips/rfe.d: Update for ISA exclusions.
* testsuite/gas/mips/mips1@rfe.d: New test.
* testsuite/gas/mips/mips2@rfe.d: New test.
* testsuite/gas/mips/r3000@rfe.d: New test.
* testsuite/gas/mips/r3900@rfe.d: New test.
* testsuite/gas/mips/rfe.l: New test stderr output.
MIPS/GAS/testsuite: Run coprocessor tests across all ISAs Verify that individual coprocessor instructions are not only accepted where supported, but rejected where they are not as well. gas/ * testsuite/gas/mips/mips.exp: Run coprocessor tests across all ISAs. * testsuite/gas/mips/cp0b.d: Update for ISA exclusions. * testsuite/gas/mips/cp0bl.d: Update for ISA exclusions. * testsuite/gas/mips/cp0c.d: Update for ISA exclusions. * testsuite/gas/mips/cp0m.d: Update for ISA exclusions. * testsuite/gas/mips/cp3.d: Update for ISA exclusions. * testsuite/gas/mips/cp3b.d: Update for ISA exclusions. * testsuite/gas/mips/cp3bl.d: Update for ISA exclusions. * testsuite/gas/mips/cp3m.d: Update for ISA exclusions. * testsuite/gas/mips/cp3d.d: Update for ISA exclusions. * testsuite/gas/mips/mips1@cp0b.d: New test. * testsuite/gas/mips/mips2@cp0b.d: New test. * testsuite/gas/mips/mips3@cp0b.d: New test. * testsuite/gas/mips/r3000@cp0b.d: New test. * testsuite/gas/mips/r3900@cp0b.d: New test. * testsuite/gas/mips/r4000@cp0b.d: New test. * testsuite/gas/mips/r5900@cp0b.d: New test. * testsuite/gas/mips/mips2@cp0bl.d: New test. * testsuite/gas/mips/mips3@cp0bl.d: New test. * testsuite/gas/mips/r3900@cp0bl.d: New test. * testsuite/gas/mips/r4000@cp0bl.d: New test. * testsuite/gas/mips/r5900@cp0bl.d: New test. * testsuite/gas/mips/mips1@cp0c.d: New test. * testsuite/gas/mips/mips2@cp0c.d: New test. * testsuite/gas/mips/mips3@cp0c.d: New test. * testsuite/gas/mips/mips4@cp0c.d: New test. * testsuite/gas/mips/mips5@cp0c.d: New test. * testsuite/gas/mips/r3000@cp0c.d: New test. * testsuite/gas/mips/r3900@cp0c.d: New test. * testsuite/gas/mips/r4000@cp0c.d: New test. * testsuite/gas/mips/vr5400@cp0c.d: New test. * testsuite/gas/mips/r5900@cp0c.d: New test. * testsuite/gas/mips/mips1@cp0m.d: New test. * testsuite/gas/mips/r3000@cp0m.d: New test. * testsuite/gas/mips/octeon@cp2.d: New test. * testsuite/gas/mips/mipsr6@cp2b.d: New test. * testsuite/gas/mips/vr5400@cp2b.d: New test. * testsuite/gas/mips/octeon@cp2b.d: New test. * testsuite/gas/mips/mips1@cp2bl.d: New test. * testsuite/gas/mips/mipsr6@cp2bl.d: New test. * testsuite/gas/mips/r3000@cp2bl.d: New test. * testsuite/gas/mips/vr5400@cp2bl.d: New test. * testsuite/gas/mips/octeon@cp2bl.d: New test. * testsuite/gas/mips/vr5400@cp2m.d: New test. * testsuite/gas/mips/r5900@cp2m.d: New test. * testsuite/gas/mips/octeon@cp2m.d: New test. * testsuite/gas/mips/mips1@cp2d.d: New test. * testsuite/gas/mips/r3000@cp2d.d: New test. * testsuite/gas/mips/r3900@cp2d.d: New test. * testsuite/gas/mips/vr5400@cp2d.d: New test. * testsuite/gas/mips/r5900@cp2d.d: New test. * testsuite/gas/mips/octeon@cp2d.d: New test. * testsuite/gas/mips/mips1@cp2-64.d: New test. * testsuite/gas/mips/mips2@cp2-64.d: New test. * testsuite/gas/mips/mips32@cp2-64.d: New test. * testsuite/gas/mips/mips32r2@cp2-64.d: New test. * testsuite/gas/mips/mips32r3@cp2-64.d: New test. * testsuite/gas/mips/mips32r5@cp2-64.d: New test. * testsuite/gas/mips/mips32r6@cp2-64.d: New test. * testsuite/gas/mips/r3000@cp2-64.d: New test. * testsuite/gas/mips/r3900@cp2-64.d: New test. * testsuite/gas/mips/interaptiv-mr2@cp2-64.d: New test. * testsuite/gas/mips/mips1@cp3.d: New test. * testsuite/gas/mips/mips2@cp3.d: New test. * testsuite/gas/mips/mips32@cp3.d: New test. * testsuite/gas/mips/r3000@cp3.d: New test. * testsuite/gas/mips/r3900@cp3.d: New test. * testsuite/gas/mips/mips1@cp3b.d: New test. * testsuite/gas/mips/mips2@cp3b.d: New test. * testsuite/gas/mips/mips32@cp3b.d: New test. * testsuite/gas/mips/r3000@cp3b.d: New test. * testsuite/gas/mips/r3900@cp3b.d: New test. * testsuite/gas/mips/mips2@cp3bl.d: New test. * testsuite/gas/mips/mips32@cp3bl.d: New test. * testsuite/gas/mips/r3900@cp3bl.d: New test. * testsuite/gas/mips/mips1@cp3m.d: New test. * testsuite/gas/mips/mips2@cp3m.d: New test. * testsuite/gas/mips/r3000@cp3m.d: New test. * testsuite/gas/mips/r3900@cp3m.d: New test. * testsuite/gas/mips/mips2@cp3d.d: New test. * testsuite/gas/mips/cp0b.l: New test stderr output. * testsuite/gas/mips/cp0bl.l: New test stderr output. * testsuite/gas/mips/cp0c.l: New test stderr output. * testsuite/gas/mips/cp0m.l: New test stderr output. * testsuite/gas/mips/cp2.l: New test stderr output. * testsuite/gas/mips/cp2-64.l: New test stderr output. * testsuite/gas/mips/cp2b.l: New test stderr output. * testsuite/gas/mips/cp2bl.l: New test stderr output. * testsuite/gas/mips/cp2m.l: New test stderr output. * testsuite/gas/mips/cp2d.l: New test stderr output. * testsuite/gas/mips/cp3.l: New test stderr output. * testsuite/gas/mips/cp3b.l: New test stderr output. * testsuite/gas/mips/cp3bl.l: New test stderr output. * testsuite/gas/mips/cp3m.l: New test stderr output. * testsuite/gas/mips/cp3d.l: New test stderr output.
2021-05-29 09:26:33 +08:00
2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
* testsuite/gas/mips/mips.exp: Run coprocessor tests across all
ISAs.
* testsuite/gas/mips/cp0b.d: Update for ISA exclusions.
* testsuite/gas/mips/cp0bl.d: Update for ISA exclusions.
* testsuite/gas/mips/cp0c.d: Update for ISA exclusions.
* testsuite/gas/mips/cp0m.d: Update for ISA exclusions.
* testsuite/gas/mips/cp3.d: Update for ISA exclusions.
* testsuite/gas/mips/cp3b.d: Update for ISA exclusions.
* testsuite/gas/mips/cp3bl.d: Update for ISA exclusions.
* testsuite/gas/mips/cp3m.d: Update for ISA exclusions.
* testsuite/gas/mips/cp3d.d: Update for ISA exclusions.
* testsuite/gas/mips/mips1@cp0b.d: New test.
* testsuite/gas/mips/mips2@cp0b.d: New test.
* testsuite/gas/mips/mips3@cp0b.d: New test.
* testsuite/gas/mips/r3000@cp0b.d: New test.
* testsuite/gas/mips/r3900@cp0b.d: New test.
* testsuite/gas/mips/r4000@cp0b.d: New test.
* testsuite/gas/mips/r5900@cp0b.d: New test.
* testsuite/gas/mips/mips2@cp0bl.d: New test.
* testsuite/gas/mips/mips3@cp0bl.d: New test.
* testsuite/gas/mips/r3900@cp0bl.d: New test.
* testsuite/gas/mips/r4000@cp0bl.d: New test.
* testsuite/gas/mips/r5900@cp0bl.d: New test.
* testsuite/gas/mips/mips1@cp0c.d: New test.
* testsuite/gas/mips/mips2@cp0c.d: New test.
* testsuite/gas/mips/mips3@cp0c.d: New test.
* testsuite/gas/mips/mips4@cp0c.d: New test.
* testsuite/gas/mips/mips5@cp0c.d: New test.
* testsuite/gas/mips/r3000@cp0c.d: New test.
* testsuite/gas/mips/r3900@cp0c.d: New test.
* testsuite/gas/mips/r4000@cp0c.d: New test.
* testsuite/gas/mips/vr5400@cp0c.d: New test.
* testsuite/gas/mips/r5900@cp0c.d: New test.
* testsuite/gas/mips/mips1@cp0m.d: New test.
* testsuite/gas/mips/r3000@cp0m.d: New test.
* testsuite/gas/mips/octeon@cp2.d: New test.
* testsuite/gas/mips/mipsr6@cp2b.d: New test.
* testsuite/gas/mips/vr5400@cp2b.d: New test.
* testsuite/gas/mips/octeon@cp2b.d: New test.
* testsuite/gas/mips/mips1@cp2bl.d: New test.
* testsuite/gas/mips/mipsr6@cp2bl.d: New test.
* testsuite/gas/mips/r3000@cp2bl.d: New test.
* testsuite/gas/mips/vr5400@cp2bl.d: New test.
* testsuite/gas/mips/octeon@cp2bl.d: New test.
* testsuite/gas/mips/vr5400@cp2m.d: New test.
* testsuite/gas/mips/r5900@cp2m.d: New test.
* testsuite/gas/mips/octeon@cp2m.d: New test.
* testsuite/gas/mips/mips1@cp2d.d: New test.
* testsuite/gas/mips/r3000@cp2d.d: New test.
* testsuite/gas/mips/r3900@cp2d.d: New test.
* testsuite/gas/mips/vr5400@cp2d.d: New test.
* testsuite/gas/mips/r5900@cp2d.d: New test.
* testsuite/gas/mips/octeon@cp2d.d: New test.
* testsuite/gas/mips/mips1@cp2-64.d: New test.
* testsuite/gas/mips/mips2@cp2-64.d: New test.
* testsuite/gas/mips/mips32@cp2-64.d: New test.
* testsuite/gas/mips/mips32r2@cp2-64.d: New test.
* testsuite/gas/mips/mips32r3@cp2-64.d: New test.
* testsuite/gas/mips/mips32r5@cp2-64.d: New test.
* testsuite/gas/mips/mips32r6@cp2-64.d: New test.
* testsuite/gas/mips/r3000@cp2-64.d: New test.
* testsuite/gas/mips/r3900@cp2-64.d: New test.
* testsuite/gas/mips/interaptiv-mr2@cp2-64.d: New test.
* testsuite/gas/mips/mips1@cp3.d: New test.
* testsuite/gas/mips/mips2@cp3.d: New test.
* testsuite/gas/mips/mips32@cp3.d: New test.
* testsuite/gas/mips/r3000@cp3.d: New test.
* testsuite/gas/mips/r3900@cp3.d: New test.
* testsuite/gas/mips/mips1@cp3b.d: New test.
* testsuite/gas/mips/mips2@cp3b.d: New test.
* testsuite/gas/mips/mips32@cp3b.d: New test.
* testsuite/gas/mips/r3000@cp3b.d: New test.
* testsuite/gas/mips/r3900@cp3b.d: New test.
* testsuite/gas/mips/mips2@cp3bl.d: New test.
* testsuite/gas/mips/mips32@cp3bl.d: New test.
* testsuite/gas/mips/r3900@cp3bl.d: New test.
* testsuite/gas/mips/mips1@cp3m.d: New test.
* testsuite/gas/mips/mips2@cp3m.d: New test.
* testsuite/gas/mips/r3000@cp3m.d: New test.
* testsuite/gas/mips/r3900@cp3m.d: New test.
gas: default TC_VALIDATE_FIX_SUB to 0 gas/write.c provides a fallback TC_VALIDATE_FIX_SUB define that can be a problem for some targets, the problem being that a non-zero definition of TC_VALIDATE_FIX_SUB says that some uses of fx_subsy are OK, in effect that the target will handle fx_subsy in md_apply_fix and/or tc_gen_reloc. A lot of targets don't have the necessary md_apply_fix and tc_gen_reloc support. So a safer default is to disallow fx_subsy by default. I've had a good look over target usage of fx_subsy, and think I've caught all the cases where targets need TC_VALIDATE_FIX_SUB. Possible failures would be limited to alpha, microblaze, ppc and s390 (the targets that define UNDEFINED_DIFFERENCE_OK), or targets that generate fixups with BFD_RELOC_GPREL32/16 and use a syntax explicitly showing a difference expression. * write.c (TC_VALIDATE_FIX_SUB): Default to 0. * config/tc-hppa.h (TC_VALIDATE_FIX_SUB): Define. * config/tc-microblaze.h (TC_VALIDATE_FIX_SUB): Define. * config/tc-alpha.h (TC_VALIDATE_FIX_SUB): Define for ECOFF. * config/tc-ppc.h (TC_VALIDATE_FIX_SUB): Don't define for ELF. Do define for XCOFF.
2021-07-10 14:28:44 +08:00
* testsuite/gas/mips/mips2@cp3d.d: New test.
MIPS/GAS/testsuite: Run coprocessor tests across all ISAs Verify that individual coprocessor instructions are not only accepted where supported, but rejected where they are not as well. gas/ * testsuite/gas/mips/mips.exp: Run coprocessor tests across all ISAs. * testsuite/gas/mips/cp0b.d: Update for ISA exclusions. * testsuite/gas/mips/cp0bl.d: Update for ISA exclusions. * testsuite/gas/mips/cp0c.d: Update for ISA exclusions. * testsuite/gas/mips/cp0m.d: Update for ISA exclusions. * testsuite/gas/mips/cp3.d: Update for ISA exclusions. * testsuite/gas/mips/cp3b.d: Update for ISA exclusions. * testsuite/gas/mips/cp3bl.d: Update for ISA exclusions. * testsuite/gas/mips/cp3m.d: Update for ISA exclusions. * testsuite/gas/mips/cp3d.d: Update for ISA exclusions. * testsuite/gas/mips/mips1@cp0b.d: New test. * testsuite/gas/mips/mips2@cp0b.d: New test. * testsuite/gas/mips/mips3@cp0b.d: New test. * testsuite/gas/mips/r3000@cp0b.d: New test. * testsuite/gas/mips/r3900@cp0b.d: New test. * testsuite/gas/mips/r4000@cp0b.d: New test. * testsuite/gas/mips/r5900@cp0b.d: New test. * testsuite/gas/mips/mips2@cp0bl.d: New test. * testsuite/gas/mips/mips3@cp0bl.d: New test. * testsuite/gas/mips/r3900@cp0bl.d: New test. * testsuite/gas/mips/r4000@cp0bl.d: New test. * testsuite/gas/mips/r5900@cp0bl.d: New test. * testsuite/gas/mips/mips1@cp0c.d: New test. * testsuite/gas/mips/mips2@cp0c.d: New test. * testsuite/gas/mips/mips3@cp0c.d: New test. * testsuite/gas/mips/mips4@cp0c.d: New test. * testsuite/gas/mips/mips5@cp0c.d: New test. * testsuite/gas/mips/r3000@cp0c.d: New test. * testsuite/gas/mips/r3900@cp0c.d: New test. * testsuite/gas/mips/r4000@cp0c.d: New test. * testsuite/gas/mips/vr5400@cp0c.d: New test. * testsuite/gas/mips/r5900@cp0c.d: New test. * testsuite/gas/mips/mips1@cp0m.d: New test. * testsuite/gas/mips/r3000@cp0m.d: New test. * testsuite/gas/mips/octeon@cp2.d: New test. * testsuite/gas/mips/mipsr6@cp2b.d: New test. * testsuite/gas/mips/vr5400@cp2b.d: New test. * testsuite/gas/mips/octeon@cp2b.d: New test. * testsuite/gas/mips/mips1@cp2bl.d: New test. * testsuite/gas/mips/mipsr6@cp2bl.d: New test. * testsuite/gas/mips/r3000@cp2bl.d: New test. * testsuite/gas/mips/vr5400@cp2bl.d: New test. * testsuite/gas/mips/octeon@cp2bl.d: New test. * testsuite/gas/mips/vr5400@cp2m.d: New test. * testsuite/gas/mips/r5900@cp2m.d: New test. * testsuite/gas/mips/octeon@cp2m.d: New test. * testsuite/gas/mips/mips1@cp2d.d: New test. * testsuite/gas/mips/r3000@cp2d.d: New test. * testsuite/gas/mips/r3900@cp2d.d: New test. * testsuite/gas/mips/vr5400@cp2d.d: New test. * testsuite/gas/mips/r5900@cp2d.d: New test. * testsuite/gas/mips/octeon@cp2d.d: New test. * testsuite/gas/mips/mips1@cp2-64.d: New test. * testsuite/gas/mips/mips2@cp2-64.d: New test. * testsuite/gas/mips/mips32@cp2-64.d: New test. * testsuite/gas/mips/mips32r2@cp2-64.d: New test. * testsuite/gas/mips/mips32r3@cp2-64.d: New test. * testsuite/gas/mips/mips32r5@cp2-64.d: New test. * testsuite/gas/mips/mips32r6@cp2-64.d: New test. * testsuite/gas/mips/r3000@cp2-64.d: New test. * testsuite/gas/mips/r3900@cp2-64.d: New test. * testsuite/gas/mips/interaptiv-mr2@cp2-64.d: New test. * testsuite/gas/mips/mips1@cp3.d: New test. * testsuite/gas/mips/mips2@cp3.d: New test. * testsuite/gas/mips/mips32@cp3.d: New test. * testsuite/gas/mips/r3000@cp3.d: New test. * testsuite/gas/mips/r3900@cp3.d: New test. * testsuite/gas/mips/mips1@cp3b.d: New test. * testsuite/gas/mips/mips2@cp3b.d: New test. * testsuite/gas/mips/mips32@cp3b.d: New test. * testsuite/gas/mips/r3000@cp3b.d: New test. * testsuite/gas/mips/r3900@cp3b.d: New test. * testsuite/gas/mips/mips2@cp3bl.d: New test. * testsuite/gas/mips/mips32@cp3bl.d: New test. * testsuite/gas/mips/r3900@cp3bl.d: New test. * testsuite/gas/mips/mips1@cp3m.d: New test. * testsuite/gas/mips/mips2@cp3m.d: New test. * testsuite/gas/mips/r3000@cp3m.d: New test. * testsuite/gas/mips/r3900@cp3m.d: New test. * testsuite/gas/mips/mips2@cp3d.d: New test. * testsuite/gas/mips/cp0b.l: New test stderr output. * testsuite/gas/mips/cp0bl.l: New test stderr output. * testsuite/gas/mips/cp0c.l: New test stderr output. * testsuite/gas/mips/cp0m.l: New test stderr output. * testsuite/gas/mips/cp2.l: New test stderr output. * testsuite/gas/mips/cp2-64.l: New test stderr output. * testsuite/gas/mips/cp2b.l: New test stderr output. * testsuite/gas/mips/cp2bl.l: New test stderr output. * testsuite/gas/mips/cp2m.l: New test stderr output. * testsuite/gas/mips/cp2d.l: New test stderr output. * testsuite/gas/mips/cp3.l: New test stderr output. * testsuite/gas/mips/cp3b.l: New test stderr output. * testsuite/gas/mips/cp3bl.l: New test stderr output. * testsuite/gas/mips/cp3m.l: New test stderr output. * testsuite/gas/mips/cp3d.l: New test stderr output.
2021-05-29 09:26:33 +08:00
* testsuite/gas/mips/cp0b.l: New test stderr output.
* testsuite/gas/mips/cp0bl.l: New test stderr output.
* testsuite/gas/mips/cp0c.l: New test stderr output.
* testsuite/gas/mips/cp0m.l: New test stderr output.
* testsuite/gas/mips/cp2.l: New test stderr output.
* testsuite/gas/mips/cp2-64.l: New test stderr output.
* testsuite/gas/mips/cp2b.l: New test stderr output.
* testsuite/gas/mips/cp2bl.l: New test stderr output.
* testsuite/gas/mips/cp2m.l: New test stderr output.
* testsuite/gas/mips/cp2d.l: New test stderr output.
* testsuite/gas/mips/cp3.l: New test stderr output.
* testsuite/gas/mips/cp3b.l: New test stderr output.
* testsuite/gas/mips/cp3bl.l: New test stderr output.
* testsuite/gas/mips/cp3m.l: New test stderr output.
* testsuite/gas/mips/cp3d.l: New test stderr output.
MIPS/opcodes: Accurately record coprocessor opcode CPU/ISA membership Adjust opcode table entries for coprocessor instructions that have been removed from certain ISA levels or CPU implementations as follows: - remove CP0 memory access instructions from MIPS II up as the LWC0 and SWC0 opcodes have been reused for the LL and SC instructions respectively[1]; strictly speaking LWC0 and SWC0 have never really been defined in the first place[2], but let's keep them for now in case an odd implementation did, - remove CP0 branch instructions from MIPS IV[3] and MIPS32[4] up, as they have been removed as from those ISAs, - remove CP0 control register move instructions from MIPS32 up, as they have been removed as from that ISA[5], - remove the RFE instruction from MIPS III[6] and MIPS32[7] up, as it has been removed as from those ISAs in favour to ERET, - remove CP2 instructions from Vr5400 CPUs as their encodings have been reused for the multimedia instruction set extensions[8] and no CP2 registers exist[9], - remove CP3 memory access instructions from MIPS III up as coprocessor 3 has been removed as from that ISA[10][11] and from MIPS32 up as the LWC3 opcode has been reused for the PREF instruction and consequently all the four memory access instructions removed from the ISA (though the COP3 opcode has been retained)[12]. Update the testsuite accordingly. References: [1] Charles Price, "MIPS IV Instruction Set", MIPS Technologies, Inc., Revision 3.2, September, 1995, Table A-38 "CPU Instruction Encoding - MIPS II Architecture", p. A-178 [2] same, Section A.2.5.1 "Coprocessor Load and Store", p. A-12 [3] "MIPS R10000 Microprocessor User's Manual", Version 2.0, MIPS Technologies, Inc., January 29, 1997, Section 14.25 "CP0 Instructions", Subsection "Branch on Coprocessor 0", p. 285 [4] "MIPS32 Architecture For Programmers, Volume II: The MIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, Revision 1.00, June 9, 2003, Table A-9 "MIPS32 COP0 Encoding of rs Field", p. 242 [5] same [6] Joe Heinrich, "MIPS R4000 Microprocessor User's Manual", Second Edition, MIPS Technologies, Inc., April 1, 1994, Figure A-2 "R4000 Opcode Bit Encoding", p. A-182 [8] "Vr5432 64-bit MIPS RISC Microprocessor User's Manual, Volume 1", NEC Electronics Inc., Document No. U13751EU5V0UM00, May 2000, Section 1.2.3 "CPU Instruction Set Overview", p. 9 [9] "Vr5432 64-bit MIPS RISC Microprocessor User's Manual, Volume 2", NEC Electronics Inc., Document No. U13751EU5V0UM00, May 2000, Section 19.2 "Multimedia Instruction Format", p. 681 [10] Charles Price, "MIPS IV Instruction Set", MIPS Technologies, Inc., Revision 3.2, September, 1995, Section A 8.3.4 "Coprocessor 3 - COP3 and CP3 load/store", p. A-176 [11] same, Table A-39 "CPU Instruction Encoding - MIPS III Architecture", p. A-179 [12] "MIPS32 Architecture For Programmers, Volume II: The MIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, Revision 1.00, August 29, 2002, Table A-2 "MIPS32 Encoding of the Opcode Field", p. 241 opcodes/ * mips-opc.c (mips_builtin_opcodes): Update exclusion list for "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0", "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t", "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2", "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3", "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3", "cop2", and "cop3" entries. gas/ * testsuite/gas/mips/mips32@isa-override-1.d: Update for LDC3 instruction removal. * testsuite/gas/mips/mips32r2@isa-override-1.d: Likewise.
2021-05-29 09:26:32 +08:00
2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
* testsuite/gas/mips/mips32@isa-override-1.d: Update for LDC3
instruction removal.
* testsuite/gas/mips/mips32r2@isa-override-1.d: Likewise.
MIPS/GAS/testsuite: Add tests for coprocessor branch instructions Cover basic CP0, CP2, CP3 branch and branch-likely instructions across the relevant ISA levels. Omit CP1 branches, covered elsewhere. gas/ * testsuite/gas/mips/cp0b.d: New test. * testsuite/gas/mips/cp0bl.d: New test. * testsuite/gas/mips/cp2b.d: New test. * testsuite/gas/mips/micromips@cp2b.d: New test. * testsuite/gas/mips/cp2bl.d: New test. * testsuite/gas/mips/micromips@cp2bl.d: New test. * testsuite/gas/mips/cp3b.d: New test. * testsuite/gas/mips/cp3bl.d: New test. * testsuite/gas/mips/cp0b.s: New test source. * testsuite/gas/mips/cp0bl.s: New test source. * testsuite/gas/mips/cp2b.s: New test source. * testsuite/gas/mips/cp2bl.s: New test source. * testsuite/gas/mips/cp3b.s: New test source. * testsuite/gas/mips/cp3bl.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2021-05-29 09:26:32 +08:00
2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
* testsuite/gas/mips/cp0b.d: New test.
* testsuite/gas/mips/cp0bl.d: New test.
* testsuite/gas/mips/cp2b.d: New test.
* testsuite/gas/mips/micromips@cp2b.d: New test.
* testsuite/gas/mips/cp2bl.d: New test.
* testsuite/gas/mips/micromips@cp2bl.d: New test.
* testsuite/gas/mips/cp3b.d: New test.
* testsuite/gas/mips/cp3bl.d: New test.
* testsuite/gas/mips/cp0b.s: New test source.
* testsuite/gas/mips/cp0bl.s: New test source.
* testsuite/gas/mips/cp2b.s: New test source.
* testsuite/gas/mips/cp2bl.s: New test source.
* testsuite/gas/mips/cp3b.s: New test source.
* testsuite/gas/mips/cp3bl.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
MIPS/opcodes: Disassemble the RFE instruction Fix a commit b015e599c772 ("[MIPS] Add new virtualization instructions"), <https://sourceware.org/ml/binutils/2013-05/msg00118.html>, regression and bring the disassembly of the RFE instruction back for the relevant ISA levels. It is because the "rfe" opcode table entry was incorrectly moved behind the catch-all generic "c0" entry for CP0 instructions, causing output like: 00: 42000010 c0 0x10 to be produced rather than: 00: 42000010 rfe even for ISA levels that do include the RFE instruction. Move the "rfe" entry ahead of "c0" then, correcting the problem. Add a suitable test case. opcodes/ * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead of "c0". gas/ * testsuite/gas/mips/rfe.d: New test. * testsuite/gas/mips/rfe.s: New test source. * testsuite/gas/mips/mips.exp: Run the new test.
2021-05-29 09:26:32 +08:00
2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
* testsuite/gas/mips/rfe.d: New test.
* testsuite/gas/mips/rfe.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new test.
MIPS/opcodes: Add legacy CP1 control register names The two CP1 control registers defined by legacy ISAs used to be referred to by various names, such as FCR0, FCR31, FSR, however their documented full names have always been the Implementation and Revision, and Control and Status respectively, so the FIR and FCSR acronyms coming from modern ISA revisions will be just as unambiguous while improving the clarity of disassembly. Do not update the TX39 though as it did not have an FPU. opcodes/ * mips-dis.c (mips_cp1_names_mips): New variable. (mips_arch_choices): Use it rather than `mips_cp1_names_numeric' for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120", "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500", "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000", "r12000", "r14000", "r16000", "mips5", "loongson2e", and "loongson2f". gas/ * testsuite/gas/mips/cp1-names-r3900.d: New test. * testsuite/gas/mips/mips.exp: Run the new test. * testsuite/gas/mips/branch-misc-3.d: Update disassembly according to changes to opcodes. * testsuite/gas/mips/cp1-names-r3000.d: Likewise. * testsuite/gas/mips/cp1-names-r4000.d: Likewise. * testsuite/gas/mips/relax-swap1-mips1.d: Likewise. * testsuite/gas/mips/relax-swap1-mips2.d: Likewise. * testsuite/gas/mips/trunc.d: Likewise.
2021-05-29 09:26:32 +08:00
2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
* testsuite/gas/mips/cp1-names-r3900.d: New test.
* testsuite/gas/mips/mips.exp: Run the new test.
* testsuite/gas/mips/branch-misc-3.d: Update disassembly
according to changes to opcodes.
* testsuite/gas/mips/cp1-names-r3000.d: Likewise.
* testsuite/gas/mips/cp1-names-r4000.d: Likewise.
* testsuite/gas/mips/relax-swap1-mips1.d: Likewise.
* testsuite/gas/mips/relax-swap1-mips2.d: Likewise.
* testsuite/gas/mips/trunc.d: Likewise.
MIPS/GAS/testsuite: Add tests for coprocessor access instructions Cover basic CP0, CP2, CP3 move, load and store instructions across the relevant ISA levels. Omit CP0 move and CP1 instructions as they are covered elsewhere. gas/ * testsuite/gas/mips/cp0c.d: New test. * testsuite/gas/mips/cp0m.d: New test. * testsuite/gas/mips/r3900@cp0m.d: New test. * testsuite/gas/mips/cp2.d: New test. * testsuite/gas/mips/micromips@cp2.d: New test. * testsuite/gas/mips/cp2m.d: New test. * testsuite/gas/mips/mipsr6@cp2m.d: New test. * testsuite/gas/mips/micromips@cp2m.d: New test. * testsuite/gas/mips/cp2d.d: New test. * testsuite/gas/mips/mipsr6@cp2d.d: New test. * testsuite/gas/mips/micromips@cp2d.d: New test. * testsuite/gas/mips/cp2-64.d: New test. * testsuite/gas/mips/micromips@cp2-64.d: New test. * testsuite/gas/mips/cp3.d: New test. * testsuite/gas/mips/cp3m.d: New test. * testsuite/gas/mips/cp3d.d: New test. * testsuite/gas/mips/cp0c.s: New test source. * testsuite/gas/mips/cp0m.s: New test source. * testsuite/gas/mips/cp2.s: New test source. * testsuite/gas/mips/cp2m.s: New test source. * testsuite/gas/mips/cp2d.s: New test source. * testsuite/gas/mips/cp2-64.s: New test source. * testsuite/gas/mips/cp3.s: New test source. * testsuite/gas/mips/cp3m.s: New test source. * testsuite/gas/mips/cp3d.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
2021-05-29 09:26:32 +08:00
2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
* testsuite/gas/mips/cp0c.d: New test.
* testsuite/gas/mips/cp0m.d: New test.
* testsuite/gas/mips/r3900@cp0m.d: New test.
* testsuite/gas/mips/cp2.d: New test.
* testsuite/gas/mips/micromips@cp2.d: New test.
* testsuite/gas/mips/cp2m.d: New test.
* testsuite/gas/mips/mipsr6@cp2m.d: New test.
* testsuite/gas/mips/micromips@cp2m.d: New test.
* testsuite/gas/mips/cp2d.d: New test.
* testsuite/gas/mips/mipsr6@cp2d.d: New test.
* testsuite/gas/mips/micromips@cp2d.d: New test.
* testsuite/gas/mips/cp2-64.d: New test.
* testsuite/gas/mips/micromips@cp2-64.d: New test.
* testsuite/gas/mips/cp3.d: New test.
* testsuite/gas/mips/cp3m.d: New test.
* testsuite/gas/mips/cp3d.d: New test.
* testsuite/gas/mips/cp0c.s: New test source.
* testsuite/gas/mips/cp0m.s: New test source.
* testsuite/gas/mips/cp2.s: New test source.
* testsuite/gas/mips/cp2m.s: New test source.
* testsuite/gas/mips/cp2d.s: New test source.
* testsuite/gas/mips/cp2-64.s: New test source.
* testsuite/gas/mips/cp3.s: New test source.
* testsuite/gas/mips/cp3m.s: New test source.
* testsuite/gas/mips/cp3d.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
MIPS/opcodes: Do not use CP0 register names for control registers The CP0 control register set has never been defined, however encodings for the CFC0 and CTC0 instructions remained available for implementers up until the MIPS32 ISA declared them invalid and causing the Reserved Instruction exception[1]. Therefore we handle them for both assembly and disassembly, however in the latter case the names of CP0 registers from the regular set are incorrectly printed if named registers are requested. This is because we do not define separate operand classes for coprocessor regular and control registers respectively, which means the disassembler has no way to tell the two cases apart. Consequently nonsensical disassembly is produced like: cfc0 v0,c0_random Later the MIPSr5 ISA reused the encodings for XPA ASE MFHC0 and MTHC0 instructions[2] although it failed to document them in the relevant opcode table until MIPSr6 only. Correct the issue then by defining a new register class, OP_REG_CONTROL, and corresponding operand codes, `g' and `y' for the two positions in the machine instruction a control register operand can take. Adjust the test cases affected accordingly. While at it swap the regular MIPS opcode table "cfc0" and "ctc0" entries with each other so that they come in the alphabetical order. References: [1] "MIPS32 Architecture For Programmers, Volume II: The MIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, Revision 1.00, August 29, 2002, Table A-9 "MIPS32 COP0 Encoding of rs Field", p. 242 [2] "MIPS Architecture For Programmers, Volume II-A: The MIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, Revision 5.04, December 11, 2013, Section 3.2 "Alphabetical List of Instructions", pp. 195, 216 include/ * opcode/mips.h: Document `g' and `y' operand codes. (mips_reg_operand_type): Add OP_REG_CONTROL enumeration constant. gas/ * tc-mips.c (convert_reg_type) <OP_REG_CONTROL>: New case. (macro) <M_TRUNCWS, M_TRUNCWD>: Use the `g' rather than `G' operand code. opcodes/ * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register handling code over to... <OP_REG_CONTROL>: ... this new case. * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases. (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2", "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries replacing the `G' operand code with `g'. Update "cftc1" and "cftc2" entries replacing the `E' operand code with `y'. * micromips-opc.c (decode_micromips_operand) <'g'>: New case. (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2" entries replacing the `G' operand code with `g'. binutils/ * testsuite/binutils-all/mips/mips-xpa-virt-1.d: Correct CFC0 operand disassembly. * testsuite/binutils-all/mips/mips-xpa-virt-3.d: Likewise.
2021-05-29 09:26:32 +08:00
2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
* tc-mips.c (convert_reg_type) <OP_REG_CONTROL>: New case.
(macro) <M_TRUNCWS, M_TRUNCWD>: Use the `g' rather than `G'
operand code.
MIPS/opcodes: Add TX39 CP0 register names The TX39 core has its distinct set of CP0 registers[1], so it needs a separate table to hold their names. Add a test case accordingly. References: [1] "32-Bit RISC Microprocessor TX39 Family Core Architecture User's Manual", Toshiba, Jul. 27, 1995, Section 2.2.2 "System control coprocessor (CP0) registers", pp. 9-10 opcodes/ * mips-dis.c (mips_cp0_names_r3900): New variable. (mips_arch_choices): Use it rather than `mips_cp0_names_numeric' for "r3900". gas/ * testsuite/gas/mips/cp0-names-r3900.d: New test. * testsuite/gas/mips/mips.exp: Run it.
2021-05-29 09:26:32 +08:00
2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
* testsuite/gas/mips/cp0-names-r3900.d: New test.
* testsuite/gas/mips/mips.exp: Run it.
microMIPS/opcodes: Refer FPRs rather than FCRs with DMTC1 The DMTC1 instruction operates on a floating-point general register as its second operand, however in the disassembly of the microMIPS encoding a floating-point control register is shown instead. This is due to an incorrect ordering of the two "dmtc1" entries in the opcode table, which gives precedence to one using the `G' aka coprocessor format over one using the `S' or floating-point register format. The coprocessor format, or OP_REG_COPRO, is used so that GAS supports referring to FPRs by their numbers in assembly, such as $0, $1, etc. however in the case of CP1/FPU it is also used by the disassembler to decode those numbers to the names of corresponding control registers. This in turn causes nonsensical disassembly such as: dmtc1 a1,c1_fir in a reference to $f0. It has been like this ever since microMIPS ISA support has been added. Correct the ordering of the two entries then by swapping them with each other, making disassembly output consistent with the regular MIPS DMTC1 instruction as well all the remaining CP1 move instructions. Adjust all the test cases affected accordingly. opcodes/ * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1" entries with each other. gas/ * testsuite/gas/mips/micromips.d: Update disassembly according to "dmtc1" entry fix with opcodes. * testsuite/gas/mips/micromips-compact.d: Likewise. * testsuite/gas/mips/micromips-insn32.d: Likewise. * testsuite/gas/mips/micromips-noinsn32.d: Likewise. * testsuite/gas/mips/micromips-trap.d: Likewise. * testsuite/gas/mips/micromips@isa-override-1.d: Likewise.
2021-05-29 09:26:32 +08:00
2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
* testsuite/gas/mips/micromips.d: Update disassembly according
to "dmtc1" entry fix with opcodes.
* testsuite/gas/mips/micromips-compact.d: Likewise.
* testsuite/gas/mips/micromips-insn32.d: Likewise.
* testsuite/gas/mips/micromips-noinsn32.d: Likewise.
* testsuite/gas/mips/micromips-trap.d: Likewise.
* testsuite/gas/mips/micromips@isa-override-1.d: Likewise.
MIPS/GAS: Use FCSR rather than RA with CFC1/CTC1 Fix an issue caused by commit f9419b056fe2 ("MIPS gas: code cleanup"), <https://sourceware.org/ml/binutils/2002-05/msg00192.html>, and replace the incorrect use of RA with the CFC1 and CTC1 instructions with FCSR. While the register referred by its number is $31 in both cases, these instructions operate on the floating-point control register file rather than general-purpose registers. gas/ * config/tc-mips.c (FCSR): New macro. (macro) <M_TRUNCWS, M_TRUNCWD>: Use it in place of RA.
2021-05-29 09:26:32 +08:00
2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
* config/tc-mips.c (FCSR): New macro.
(macro) <M_TRUNCWS, M_TRUNCWD>: Use it in place of RA.
x86: Restore PC16 relocation overflow check The x86-64 psABI has --- A program or object file using R_X86_64_8, R_X86_64_16, R_X86_64_PC16 or R_X86_64_PC8 relocations is not conformant to this ABI, these relocations are only added for documentation purposes. --- Since x86 PC16 relocations have been used for 16-bit programs in an ELF32 or ELF64 container, PC16 relocation should wrap-around in 16-bit address space. Revert commit a7664973b24a242cd9ea17deb5eaf503065fc0bd Author: Jan Beulich <jbeulich@suse.com> Date: Mon Apr 26 10:41:35 2021 +0200 x86: correct overflow checking for 16-bit PC-relative relocs and xfail the related tests. Also revert commit 50c95a739c91ae70cf8481936611aa1f5397a384 Author: H.J. Lu <hjl.tools@gmail.com> Date: Wed May 26 12:13:13 2021 -0700 x86: Propery check PC16 reloc overflow in 16-bit mode instructions while keeping PR ld/27905 tests for PC16 relocation in 16-bit programs. bfd/ PR ld/27905 * elf32-i386.c: Don't include "libiberty.h". (elf_howto_table): Revert commits a7664973b24 and 50c95a739c9. (elf_i386_rtype_to_howto): Revert commit 50c95a739c9. (elf_i386_info_to_howto_rel): Likewise. (elf_i386_tls_transition): Likewise. (elf_i386_relocate_section): Likewise. * elf64-x86-64.c (x86_64_elf_howto_table): Revert commits a7664973b24 and 50c95a739c9. (elf_x86_64_rtype_to_howto): Revert commit 50c95a739c9. * elfxx-x86.c (_bfd_x86_elf_parse_gnu_properties): Likewise. * elfxx-x86.h (elf_x86_obj_tdata): Likewise. (elf_x86_has_code16): Likewise. binutils/ PR ld/27905 * readelf.c (decode_x86_feature_2): Revert commit 50c95a739c9. gas/ PR ld/27905 * config/tc-i386.c (set_code_flag): Revert commit 50c95a739c9. (set_16bit_gcc_code_flag): Likewise. (x86_cleanup): Likewise. * testsuite/gas/i386/code16-2.d: Updated. * testsuite/gas/i386/x86-64-code16-2.d: Likewise. include/ PR ld/27905 * elf/common.h (GNU_PROPERTY_X86_FEATURE_2_CODE16): Removed. ld/ PR ld/27905 * testsuite/ld-i386/pcrel16-2.d: xfail. * testsuite/ld-x86-64/pcrel16-2.d: Likewise.
2021-05-29 00:34:10 +08:00
2021-05-28 H.J. Lu <hongjiu.lu@intel.com>
PR ld/27905
* config/tc-i386.c (set_code_flag): Revert commit 50c95a739c9.
(set_16bit_gcc_code_flag): Likewise.
(x86_cleanup): Likewise.
* testsuite/gas/i386/code16-2.d: Updated.
* testsuite/gas/i386/x86-64-code16-2.d: Likewise.
PowerPC: Add new xxmr and xxlnot extended mnemonics opcodes/ * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics. gas/ * testsuite/gas/ppc/vsx.d <xxmr, xxlnot>: Add tests. * testsuite/gas/ppc/vsx.s: Likewise.
2021-05-28 05:59:15 +08:00
2021-05-27 Peter Bergner <bergner@linux.ibm.com>
* testsuite/gas/ppc/vsx.d <xxmr, xxlnot>: Add tests.
* testsuite/gas/ppc/vsx.s: Likewise.
nds32: __builtin_strncpy bound equals destination size * config/tc-nds32.c (do_pseudo_push_bhwd, do_pseudo_pop_bhwd), (do_pseudo_pusha, do_pseudo_pushi): Avoid fortify strncpy bound error.
2021-05-26 20:53:44 +08:00
2021-05-27 Alan Modra <amodra@gmail.com>
* config/tc-nds32.c (do_pseudo_push_bhwd, do_pseudo_pop_bhwd),
(do_pseudo_pusha, do_pseudo_pushi): Avoid fortify strncpy bound
error.
x86: Propery check PC16 reloc overflow in 16-bit mode instructions commit a7664973b24a242cd9ea17deb5eaf503065fc0bd Author: Jan Beulich <jbeulich@suse.com> Date: Mon Apr 26 10:41:35 2021 +0200 x86: correct overflow checking for 16-bit PC-relative relocs caused linker failure when building 16-bit program in a 32-bit ELF container. Update GNU_PROPERTY_X86_FEATURE_2_USED with #define GNU_PROPERTY_X86_FEATURE_2_CODE16 (1U << 12) to indicate that 16-bit mode instructions are used in the input object: https://groups.google.com/g/x86-64-abi/c/UvvXWeHIGMA to indicate that 16-bit mode instructions are used in the object to allow linker to properly perform relocation overflow check for 16-bit PC-relative relocations in 16-bit mode instructions. 1. Update x86 assembler to always generate the GNU property note with GNU_PROPERTY_X86_FEATURE_2_CODE16 for .code16 in ELF object. 2. Update i386 and x86-64 linkers to use 16-bit PC16 relocations if input object is marked with GNU_PROPERTY_X86_FEATURE_2_CODE16. bfd/ PR ld/27905 * elf32-i386.c: Include "libiberty.h". (elf_howto_table): Add 16-bit R_386_PC16 entry. (elf_i386_rtype_to_howto): Add a BFD argument. Use 16-bit R_386_PC16 if input has 16-bit mode instructions. (elf_i386_info_to_howto_rel): Update elf_i386_rtype_to_howto call. (elf_i386_tls_transition): Likewise. (elf_i386_relocate_section): Likewise. * elf64-x86-64.c (x86_64_elf_howto_table): Add 16-bit R_X86_64_PC16 entry. (elf_x86_64_rtype_to_howto): Use 16-bit R_X86_64_PC16 if input has 16-bit mode instructions. * elfxx-x86.c (_bfd_x86_elf_parse_gnu_properties): Set elf_x86_has_code16 if relocatable input is marked with GNU_PROPERTY_X86_FEATURE_2_CODE16. * elfxx-x86.h (elf_x86_obj_tdata): Add has_code16. (elf_x86_has_code16): New. binutils/ PR ld/27905 * readelf.c (decode_x86_feature_2): Support GNU_PROPERTY_X86_FEATURE_2_CODE16. gas/ PR ld/27905 * config/tc-i386.c (set_code_flag): Update x86_feature_2_used with GNU_PROPERTY_X86_FEATURE_2_CODE16 for .code16 in ELF object. (set_16bit_gcc_code_flag): Likewise. (x86_cleanup): Always generate the GNU property note if x86_feature_2_used isn't 0. * testsuite/gas/i386/code16-2.d: New file. * testsuite/gas/i386/code16-2.s: Likewise. * testsuite/gas/i386/x86-64-code16-2.d: Likewise. * testsuite/gas/i386/i386.exp: Run code16-2 and x86-64-code16-2. include/ PR ld/27905 * elf/common.h (GNU_PROPERTY_X86_FEATURE_2_CODE16): New. ld/ PR ld/27905 * testsuite/ld-i386/code16.d: New file. * testsuite/ld-i386/code16.t: Likewise. * testsuite/ld-x86-64/code16.d: Likewise. * testsuite/ld-x86-64/code16.t: Likewise. * testsuite/ld-i386/i386.exp: Run code16. * testsuite/ld-x86-64/x86-64.exp: Likewise.
2021-05-27 03:13:13 +08:00
2021-05-26 H.J. Lu <hongjiu.lu@intel.com>
PR ld/27905
* config/tc-i386.c (set_code_flag): Update x86_feature_2_used
with GNU_PROPERTY_X86_FEATURE_2_CODE16 for .code16 in ELF
object.
(set_16bit_gcc_code_flag): Likewise.
(x86_cleanup): Always generate the GNU property note if
x86_feature_2_used isn't 0.
* testsuite/gas/i386/code16-2.d: New file.
* testsuite/gas/i386/code16-2.s: Likewise.
* testsuite/gas/i386/x86-64-code16-2.d: Likewise.
* testsuite/gas/i386/i386.exp: Run code16-2 and x86-64-code16-2.
i386: Replace movsb with movsxb PR gas/27906 * doc/c-i386.texi: Replace movsb with movsxb as an alias for movsbq.
2021-05-26 20:53:23 +08:00
2021-05-26 Sebastien Villemot <sebastien@debian.org>
PR gas/27906
* doc/c-i386.texi: Replace movsb with movsxb as an alias for
movsbq.
RISC-V: Allow to link the objects with unknown prefixed extensions. Since the policies of GNU and llvm toolchain are different for now, current binutils mainline cannot accept any draft extensions, including rvv, zfh, .... The Clang/LLVM allows these draft stuff on mainline, but the GNU ld might be used with them, so this causes the link time problems. The patch allows ld to link the objects with unknown prefixed extensions, which are probably generated by LLVM or customized toolchains. bfd/ * elfxx-riscv.h (check_unknown_prefixed_ext): New bool. * elfxx-riscv.c (riscv_parse_prefixed_ext): Do not check the prefixed extension name if check_unknown_prefixed_ext is false. * elfnn-riscv.c (riscv_merge_arch_attr_info): Set check_unknown_prefixed_ext to false for linker. gas/ * config/tc-riscv.c (riscv_set_arch): Set check_unknown_prefixed_ext to true for assembler.
2021-05-26 10:34:13 +08:00
2021-05-26 Nelson Chu <nelson.chu@sifive.com>
* config/tc-riscv.c (riscv_set_arch): Set
check_unknown_prefixed_ext to true for assembler.
Arm: Fix forward thumb references [PR gas/25235] When assembling a forward reference the symbol will be unknown and so during do_t_adr we cannot set the thumb bit. The bit it set so early to prevent relaxations that are invalid. i.e. relaxing a Thumb2 to Thumb1 insn when the symbol is Thumb. But because it's done so early we miss the case for forward references. This patch changes it so that we additionally check the thumb bit during the internal relocation processing. In principle we should be able to only set the bit during reloc processing but that would require changes to the other relocations that the instruction could be relaxed to. This approach still allows early relaxations (which means that we have less iteration of internal reloc processing) while still fixing the forward reference case. gas/ChangeLog: 2021-05-24 Tamar Christina <tamar.christina@arm.com> PR gas/25235 * config/tc-arm.c (md_convert_frag): Set LSB when Thumb symbol. (relax_adr): Thumb symbols 4 bytes. * testsuite/gas/arm/pr25235.d: New test. * testsuite/gas/arm/pr25235.s: New test.
2021-05-25 23:04:04 +08:00
2021-05-25 Tamar Christina <tamar.christina@arm.com>
PR gas/25235
* config/tc-arm.c (md_convert_frag): Set LSB when Thumb symbol.
(relax_adr): Thumb symbols 4 bytes.
* testsuite/gas/arm/pr25235.d: New test.
* testsuite/gas/arm/pr25235.s: New test.
RISC-V: PR25212, Report errors for invalid march and mabi combinations. This patch clarify the following invalid combinations of march and mabi, * ilp32f/lp64f abi without f extension. * ilp32d/lp64d abi without d extension. * ilp32q/lp64q abi without q extension. * e extension with any abi except ilp32e GNU assembler reports errors when finding the above invalid combinations. But LLVM-MC reports warnings and ignores these invalid cases. It help to set the correct ilp32/lp64/ilp32e abi according to rv32/rv64/rve. This looks good and convenient, so perhaps we can do the same things. However, if you don't set the mabi, GNU assembler also try to set the suitable ABI according to march/elf-attribute. Compared to LLVM-MC, we will choose double/quad abi if d/f extension is set. gas/ PR 25212 * config/tc-riscv.c (riscv_set_abi_by_arch): If -mabi isn't set, we will choose ilp32e abi for rv32e. Besides, report errors for the invalid march and mabi combinations. * testsuite/gas/riscv/mabi-attr-rv32e.s: New testcase. Only accept ilp32e abi for rve extension. * testsuite/gas/riscv/mabi-fail-rv32e-lp64f.d: Likewise. * testsuite/gas/riscv/mabi-fail-rv32e-lp64f.l: Likewise. * testsuite/gas/riscv/mabi-fail-rv32e-lp64d.d: Likewise. * testsuite/gas/riscv/mabi-fail-rv32e-lp64d.l: Likewise. * testsuite/gas/riscv/mabi-fail-rv32e-lp64d.q: Likewise. * testsuite/gas/riscv/mabi-fail-rv32e-lp64d.q: Likewise. Renamed all mabi testcases to their march-mabi settings.
2021-05-21 15:40:33 +08:00
2021-05-24 Nelson Chu <nelson.chu@sifive.com>
PR 25212
* config/tc-riscv.c (riscv_set_abi_by_arch): If -mabi isn't set, we
will choose ilp32e abi for rv32e. Besides, report errors for the
invalid march and mabi combinations.
* testsuite/gas/riscv/mabi-attr-rv32e.s: New testcase. Only accept
ilp32e abi for rve extension.
* testsuite/gas/riscv/mabi-fail-rv32e-lp64f.d: Likewise.
* testsuite/gas/riscv/mabi-fail-rv32e-lp64f.l: Likewise.
* testsuite/gas/riscv/mabi-fail-rv32e-lp64d.d: Likewise.
* testsuite/gas/riscv/mabi-fail-rv32e-lp64d.l: Likewise.
* testsuite/gas/riscv/mabi-fail-rv32e-lp64d.q: Likewise.
* testsuite/gas/riscv/mabi-fail-rv32e-lp64d.q: Likewise.
Renamed all mabi testcases to their march-mabi settings.
Re: Fix offset for ia64 PCREL60B relocation on HP-UX PR 25599 * config/tc-ia64.c (emit_one_bundle): Expand comment for HP-UX adjustment. Add assertion. * testsuite/gas/ia64/reloc-mlx.d: Pass when slot 2 specified for PCREL60B.
2021-05-22 11:29:36 +08:00
2021-05-22 Alan Modra <amodra@gmail.com>
PR 25599
* config/tc-ia64.c (emit_one_bundle): Expand comment for HP-UX
adjustment. Add assertion.
* testsuite/gas/ia64/reloc-mlx.d: Pass when slot 2 specified
for PCREL60B.
Fix overflow detection in the Z80 assembler. * config/tc-z80.c (emit_data_val): Warn on constant overflow. (signed_overflow): New function. (unsigned_overflow): New function. (is_overflow): Use new functions. (md_apply_fix): Use signed_overflow. * testsuite/gas/z80/ez80_adl_suf.d: Fix test. * testsuite/gas/z80/ez80_isuf.s: Likewise. * testsuite/gas/z80/ez80_z80_suf.d: Likewise.
2021-05-20 23:14:10 +08:00
2021-05-20 Sergey Belyashov <sergey.belyashov@gmail.com>
* config/tc-z80.c (emit_data_val): Warn on constant overflow.
(signed_overflow): New function.
(unsigned_overflow): New function.
(is_overflow): Use new functions.
(md_apply_fix): Use signed_overflow.
* testsuite/gas/z80/ez80_adl_suf.d: Fix test.
* testsuite/gas/z80/ez80_isuf.s: Likewise.
* testsuite/gas/z80/ez80_z80_suf.d: Likewise.
PR27888, fix link of gas with zlib by libtool 2.4.6 PR 27888 * Makefile.am (ZLIB): Define. (as_new_LDADD): Add it. * Makefile.in: Regenerate.
2021-05-20 08:28:51 +08:00
2021-05-20 Nicolas Boulenguez <nicolas@debian.org>
PR 27888
* Makefile.am (ZLIB): Define.
(as_new_LDADD): Add it.
* Makefile.in: Regenerate.
arm: Fix bugs with MVE vmov from two GPRs to vector lanes The initial problem I wanted to fix here is that GAS was rejecting MVE instructions such as: vmov q3[2], q3[0], r2, r2 with: Error: General purpose registers may not be the same -- `vmov q3[2],q3[0],r2,r2' which is incorrect; such instructions are valid. Note that for moves in the other direction, e.g.: vmov r2, r2, q3[2], q3[0] GAS is correct in rejecting this as it does not make sense to move both lanes into the same register (the Arm ARM says this is CONSTRAINED UNPREDICTABLE). After fixing this issue, I added assembly/disassembly tests for these vmovs. This revealed several disassembly issues, including incorrectly marking the moves into vector lanes as UNPREDICTABLE, and disassembling many of the vmovs as vector loads. These are now fixed. gas/ChangeLog: * config/tc-arm.c (do_mve_mov): Only reject vmov if we're moving into the same GPR twice. * testsuite/gas/arm/mve-vmov-bad-2.l: Tweak error message. * testsuite/gas/arm/mve-vmov-3.d: New test. * testsuite/gas/arm/mve-vmov-3.s: New test. opcodes/ChangeLog: * arm-dis.c (mve_opcodes): Fix disassembly of MVE_VMOV2_GP_TO_VEC_LANE when idx == 1. (is_mve_encoding_conflict): MVE vector loads should not match when P = W = 0. (is_mve_unpredictable): It's not unpredictable to use the same source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
2021-05-17 22:12:39 +08:00
2021-05-17 Alex Coplan <alex.coplan@arm.com>
* config/tc-arm.c (do_mve_mov): Only reject vmov if we're moving
into the same GPR twice.
* testsuite/gas/arm/mve-vmov-bad-2.l: Tweak error message.
* testsuite/gas/arm/mve-vmov-3.d: New test.
* testsuite/gas/arm/mve-vmov-3.s: New test.
SAFE_BYTE_GET64 Functions dealing with lack of a 64-bit integer type can disappear now that we require C99. Printing using dwarf_vmatoa is better too. binutils/ * dwarf.c (dwarf_vmatoa64, SAFE_BYTE_GET64, add64): Delete. (skip_attr_bytes): Replace use of SAFE_BYTE_GET64 with SAFE_BYTE_GET_AND_INC. (read_and_display_attr_value): Likewise. Print using dwarf_vmatoa. (process_debug_info, process_cu_tu_index): Likewise. * elfcomm.c (byte_put, byte_put_little_endian, byte_put_big_endian), (byte_get, byte_get_little_endian, byte_get_big_endian), (byte_get_signed): Make size param unsigned. Remove code dealing with 4-byte elf_vma. (byte_get_64): Delete. * elfcomm.h (byte_put, byte_put_little_endian, byte_put_big_endian), (byte_get, byte_get_little_endian, byte_get_big_endian), (byte_get_signed): Update prototypes. (byte_get_64): Delete. gas/ * testsuite/gas/elf/dwarf-5-file0.d: Update. * testsuite/gas/i386/dwarf5-line-1.d: Update.
2021-05-12 16:18:13 +08:00
2021-05-12 Alan Modra <amodra@gmail.com>
* testsuite/gas/elf/dwarf-5-file0.d: Update.
* testsuite/gas/i386/dwarf5-line-1.d: Update.
Report illegal Z80 load instructions. PR 27823 * config/tc-z80.c (emit_ld_r_m): Report an illegal load instruction. * testsuite/gas/z80/ill_ops.s: New test source file. * testsuite/gas/z80/ill_ops.d: New test driver. * testsuite/gas/z80/ill_ops.l: New test error output.
2021-05-11 17:57:04 +08:00
2021-05-11 Sergey Belyashov <sergey.belyashov@gmail.com>
PR 27823
* config/tc-z80.c (emit_ld_r_m): Report an illegal load
instruction.
* testsuite/gas/z80/ill_ops.s: New test source file.
* testsuite/gas/z80/ill_ops.d: New test driver.
* testsuite/gas/z80/ill_ops.l: New test error output.
Add support for 8-bit and 24-bit shifts in the z80 assembler. PR 27415 * config/tc-z80.c (emit_data_val): Add support for 8-bit and 24-bit shifts. * testsuite/gas/z80/z80_reloc.a: Update tests. * testsuite/gas/z80/z80_reloc.d: Update expected disassembly.
2021-05-10 20:36:08 +08:00
2021-05-10 Sergey Belyashov <sergey.belyashov@gmail.com>
PR 27415
* config/tc-z80.c (emit_data_val): Add support for 8-bit and
24-bit shifts.
* testsuite/gas/z80/z80_reloc.a: Update tests.
* testsuite/gas/z80/z80_reloc.d: Update expected disassembly.
support generating multi-html pages in parallel Use the pattern from other projects where we generate the html pages in a dir named the same as the project. So now we have: gas/doc/gas.html - single html page gas/doc/gas/ - multiple html pages This works for projects that have a doc/ subdir already, but gprof & ld require a little tweaking since they generate their docs in their respective toplevels.
2021-05-03 00:50:39 +08:00
2021-05-08 Mike Frysinger <vapier@gentoo.org>
* doc/Makefile.am (html-local, as/index.html): New targets.
* doc/Makefile.in: Regenerate.
generate single html manual page by default This better matches other GNU projects like autoconf/automake where the html manual is the single page form. We'll support the multi-page form in a follow up change.
2021-05-03 00:09:00 +08:00
2021-05-08 Mike Frysinger <vapier@gentoo.org>
* doc/Makefile.am (AM_MAKEINFOFLAGS): Add --no-split.
* doc/Makefile.in: Regenerate.
Add a generic .bss directive for ELF based targets. PR 3136 * config/obj-elf.c (elf_pseudo_table): Add entry for .bss. (obj_elf_bss): New function. Change to the .bss section. Support an optional subsection number. (obj_elf_change_section): Call obj_elf_section_change_hook. (obj_elf_section): Likewise. (obj_elf_data): Likewise. (obj_elf_text): Likewise. (obj_elf_struct): Likewise. (obj_elf_subsection): Likewise. (obj_elf_previous): Likewise. * config/obj-elf.h (obj_elf_bss): Prototype. * doc/as.texi (Bss): New node.
2021-05-08 00:07:41 +08:00
2021-05-07 Nick Clifton <nickc@redhat.com>
PR 3136
* config/obj-elf.c (elf_pseudo_table): Add entry for .bss.
(obj_elf_bss): New function. Change to the .bss section.
Support an optional subsection number.
(obj_elf_change_section): Call obj_elf_section_change_hook.
(obj_elf_section): Likewise.
(obj_elf_data): Likewise.
(obj_elf_text): Likewise.
(obj_elf_struct): Likewise.
(obj_elf_subsection): Likewise.
(obj_elf_previous): Likewise.
* config/obj-elf.h (obj_elf_bss): Prototype.
* doc/as.texi (Bss): New node.
Fix .dwsect generation for XCOFF. Handle .function generated with DWARF on XCOFF. gas * config/tc-ppc.c (ppc_function): Update comment for fifth argument. (ppc_frob_symbol): Remove ppc_last_function check. Make sure coff_last_function is reset. Correctly set fsize when not provided in .function. * testsuite/gas/ppc/aix.exp: New tests. * testsuite/gas/ppc/xcoff-function-1-32.d: New test. * testsuite/gas/ppc/xcoff-function-1-64.d: New test. * testsuite/gas/ppc/xcoff-function-1.s: New test. bfd * coff-rs6000.c (xcoff_dwsect_names): Add new DWARF sections. * coffgen.c (coff_pointerize_aux): Handle C_DWARF. (coff_print_symbol): Likewise. * libxcoff.h (XCOFF_DWSECT_NBR_NAMES): Update. gas * config/obj-coff.c (coff_frob_symbol): Don't skip C_DWARF. (coff_adjust_section_syms): Use corrext auxent for C_DWARF. (coff_frob_section): Likewise. * config/obj-coff.h (SA_GET_SECT_SCNLEN, SA_GET_SECT_NRELOC, SA_SET_SECT_SCNLEN, SA_SET_SECT_NRELOC) New defines. (SET_SECTION_RELOCS): Adjust for C_DWARF. * config/tc-ppc.c (ppc_frob_symbol): Don't skip C_DWARF. (ppc_adjust_symtab): Reorder C_DWARF symbols. * testsuite/gas/ppc/aix.exp: New tests. * testsuite/gas/ppc/xcoff-dwsect-2-32.d: New test. * testsuite/gas/ppc/xcoff-dwsect-2-64.d: New test. * testsuite/gas/ppc/xcoff-dwsect-2.s: New test. include * coff/internal.h (C_DWARF): New define. * coff/xcoff.h (SSUBTYP_DWLOC, SSUBTYP_DWFRAME, SSUBTYP_DWMAC): New defines.
2021-05-07 22:29:49 +08:00
2021-05-07 Clément Chigot <clement.chigot@atos.net>
* config/obj-coff.c (coff_frob_symbol): Don't skip C_DWARF.
(coff_adjust_section_syms): Use corrext auxent for C_DWARF.
(coff_frob_section): Likewise.
* config/obj-coff.h (SA_GET_SECT_SCNLEN,
SA_GET_SECT_NRELOC, SA_SET_SECT_SCNLEN,
SA_SET_SECT_NRELOC) New defines.
(SET_SECTION_RELOCS): Adjust for C_DWARF.
* config/tc-ppc.c (ppc_frob_symbol): Don't skip C_DWARF.
(ppc_adjust_symtab): Reorder C_DWARF symbols.
* testsuite/gas/ppc/aix.exp: New tests.
* testsuite/gas/ppc/xcoff-dwsect-2-32.d: New test.
* testsuite/gas/ppc/xcoff-dwsect-2-64.d: New test.
* testsuite/gas/ppc/xcoff-dwsect-2.s: New test.
* config/tc-ppc.c (ppc_function): Update comment for
fifth argument.
(ppc_frob_symbol): Remove ppc_last_function check.
Make sure coff_last_function is reset.
Correctly set fsize when not provided in .function.
* testsuite/gas/ppc/aix.exp: New tests.
* testsuite/gas/ppc/xcoff-function-1-32.d: New test.
* testsuite/gas/ppc/xcoff-function-1-64.d: New test.
* testsuite/gas/ppc/xcoff-function-1.s: New test.
x86-64/ELF: clear src_mask for all reloc types x86-64 uses rela relocations. The comment next to the field's declaration says "Non-zero values for ELF USE_RELA targets should be viewed with suspicion ..." And indeed the fields being non-zero causes section contents to be accumulated into the final relocated values in addition to the relocations' addends, which is contrary to the ELF spec.
2021-05-07 18:05:12 +08:00
2021-05-07 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/rela.s, testsuite/gas/i386/rela.d: New.
* testsuite/gas/i386/i386.exp: Run new test.
x86: don't mix disp and imm processing Surely disp processing should access the disp operand, not an imm one. This is not an active issue only because imms and disps are, at the moment, overlapping fields of the same union.
2021-05-07 18:03:12 +08:00
2021-05-07 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (output_disp): Use disps field instead of
imms one.
x86: move register check in immediate operand parsing i386_finalize_immediate() is used for both AT&T and Intel immediate operand handling. Move an AT&T-only check to i386_immediate(), which at the same time allows it to cover other cases as well, giving an overall better / more consistent diagnostic.
2021-05-07 18:02:40 +08:00
2021-05-07 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (i386_finalize_immediate): Move register
check ...
(i386_immediate): ... here.
x86: minor improvements to optimize_imm() - Drop a pointless & where just before it was checked that the respective bits are clear already anyway. - Avoid a not really necessary operand_type_set() and a redundant operand_type_or() / operand_type_and() pair.
2021-05-07 18:02:07 +08:00
2021-05-07 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (optimize_imm): Drop redundant masking.
Re-arrange operand type accumulation.
or1k: Implement relocation R_OR1K_GOT_AHI16 for gotha() The gotha() relocation mnemonic will be outputted by OpenRISC GCC when using the -mcmodel=large option. This relocation is used along with got() to generate 32-bit GOT offsets. This increases the previous GOT offset limit from the previous 16-bit (64K) limit. This is needed on large binaries where the GOT grows larger than 64k. bfd/ChangeLog: PR 21464 * bfd-in2.h: Add BFD_RELOC_OR1K_GOT_AHI16 relocation. * elf32-or1k.c (or1k_elf_howto_table, or1k_reloc_map): Likewise. (or1k_final_link_relocate, or1k_elf_relocate_section, or1k_elf_check_relocs): Likewise. * libbfd.h (bfd_reloc_code_real_names): Likewise. * reloc.c: Likewise. cpu/ChangeLog: PR 21464 * or1k.opc (or1k_imm16_relocs, parse_reloc): Define parse logic for gotha() relocation. include/ChangeLog: PR 21464 * elf/or1k.h (elf_or1k_reloc_type): Define R_OR1K_GOT_AHI16 number. opcodes/ChangeLog: PR 21464 * or1k-asm.c: Regenerate. gas/ChangeLog: PR 21464 * testsuite/gas/or1k/reloc-1.s: Add test for new relocation. * testsuite/gas/or1k/reloc-1.d: Add test result for new relocation. Cc: Giulio Benetti <giulio.benetti@benettiengineering.com> fixup reloc, add tests
2021-05-06 19:51:24 +08:00
2021-05-06 Stafford Horne <shorne@gmail.com>
PR 21464
* testsuite/gas/or1k/reloc-1.s: Add test for new relocation.
* testsuite/gas/or1k/reloc-1.d: Add test result for new
relocation.
RISC-V: PR27764, Add tests for A extension ChangeLog entry for last patch.
2021-05-04 07:19:17 +08:00
2021-05-03 Christoph Muellner <cmuellner@gcc.gnu.org>
PR 27764
* testsuite/gas/riscv/a-ext-64.d: New testcase.
* testsuite/gas/riscv/a-ext-64.s: Likewise.
* testsuite/gas/riscv/a-ext.d: Likewise.
* testsuite/gas/riscv/a-ext.s: Likewise.
x86: allow @secrel32 also in data definitions Now that lex_got() is uniform for all targets using it, permit COFF targets to also use @secrel32 with, in particular, .long. This is more natural than the custom .secrel32 directive, and also allows more flexibility (the "+six" form of the two added test lines doesn't work with a .secrel32 equivalent, in that it silently produces an unintended relocation type). As an extra benefit this also makes sure that data definitions in Intel syntax mode would get treated like they do for e.g. ELF targets.
2021-05-03 19:28:30 +08:00
2021-05-03 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.h (TC_PARSE_CONS_EXPRESSION): Adjust surrounding
#if.
* testsuite/gas/i386/secrel.s: Convert some .secrel32 to .long.
Add two further .long and an .equ.
* testsuite/gas/i386/secrel.d: Adjust expecations.
x86: use UNIX EOL in secrel testcase For some reason these were using Windows EOL.
2021-05-03 19:27:47 +08:00
2021-05-03 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/secrel.d, testsuite/gas/i386/secrel.s:
Convert Windows to UNIX EOL.
x86: fold both instances of lex_got() I see no reason at all for us to carry two copies of almost identical code. The differences, apart from the table entries, are benign. And the #ifdef-ary doesn't really get any worse.
2021-05-03 19:26:41 +08:00
2021-05-03 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (lex_got): Adjust surrounding #if. Fold TE_PE
variant into ELF one.
testsuite: Don't start directives in first column Fixes fails on hppa64-hp-hpux11.23 * testsuite/gas/elf/section25.s: Don't start directives in first column. * testsuite/gas/elf/section26.s: Likewise.
2021-05-03 06:20:03 +08:00
2021-05-03 Alan Modra <amodra@gmail.com>
* testsuite/gas/elf/section25.s: Don't start directives in first
column.
* testsuite/gas/elf/section26.s: Likewise.
x86-64: adjust recently added tests Five of them fail for Cygwin and MingW. Adjust four and move one to the ELF-only section.
2021-04-29 21:02:25 +08:00
2021-04-29 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/i386.exp: Move x86-64-rip-2 invocation.
* testsuite/gas/i386/lea64.d,
testsuite/gas/i386/lea64-optimize.d: Allow for COFF relocs.
* testsuite/gas/i386/x86-64-rip-inval-1.s,
testsuite/gas/i386/x86-64-rip-inval-2.s. Add .end.
x86: relax when/how @size can be used Allow a few more expression forms when the entire expression can be resolved at assembly time. For this, i386_validate_fix() needs to arrange for all processing of the relocation to be deferred to tc_gen_reloc().
2021-04-29 17:45:10 +08:00
2021-04-29 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (i386_validate_fix): Change return type to
int. Short-circuit BFD_RELOC_SIZE* handling.
(tc_gen_reloc): New local variable sym. Extend logic when
processing BFD_RELOC_SIZE*.
* config/tc-i386.f (i386_validate_fix): Change return type to
int.
(TC_VALIDATE_FIX): Proceed to SKIP when i386_validate_fix()
returns zero.
* testsuite/gas/i386/size-5.s, testsuite/gas/i386/size-5a.d,
testsuite/gas/i386/size-5b.d: New.
* testsuite/gas/i386/i386.exp: Run new tests.
x86: allow @size to also (sensibly) apply to sections So far this (counter-intuitively) produced the size as recorded in the (section) symbol. Obtain the section's size instead for section symbols. (I wonder whether STT_SECTION symbols couldn't properly hold the section's size in their st_size field, which in turn would likely mean the internal symbol would also have its size properly updated.) Note that this is not the same as the .sizeof.() pseudo-operator: @size yields the local file's contribution to a section, while .sizeof.() gets resolved by the linker to produce the final full section's size. As to the 3rd each of the expected output lines in the changed testcase: I can't find justification for zzz to come after yyy despite them being defined in the opposite order in source. Therefore I think it's better to permit both possible outcomes.
2021-04-29 17:43:53 +08:00
2021-04-29 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (tc_gen_reloc): Use section size for section
symbols when resolving BFD_RELOC_SIZE*.
* testsuite/gas/i386/size-2.s: Add section size cases.
* testsuite/gas/i386/size-2.d,
testsuite/gas/i386/x86-64-size-2.d: Adjust expectations.
x86: honor signedness of PC-relative relocations PR gas/27763 While the comment in output_jump() was basically correct prior to the introduction of 64-bit mode, both that and the not-JMP-like behavior of XBEGIN require adjustments: Branches with 32-bit displacement do not wrap at 4G in 64-bit mode, and XBEGIN with 16-bit operand size doesn't wrap at 64k. Similarly %rip-relative addressing doesn't wrap at 4G. The new testcase points out that for PE/COFF object_64bit didn't get set so far, preventing in particular the check at the end of md_convert_frag() to take effect. For Mach-O the new testcase fails (bogusly), in that only the first two of the expected errors get raised. Since for Mach-O many testcases already fail, and since an x86_64-darwin target can't even be configured for, I didn't think I need to bother. Note that there are further issues in this area, in particular for branches with operand size overrides. Such branches, which truncate %rip / %eip, can't be correctly expressed with ordinary PC-relative relocations. It's not really clear what to do with them - perhaps the best we can do is to carry through all associated relocations, leaving it to the linker (or even loader) to decide (once the final address layout is known). Same perhaps goes for relocations associated with 32-bit addressing in 64-bit mode.
2021-04-28 16:53:00 +08:00
2021-04-28 Jan Beulich <jbeulich@suse.com>
H.J. Lu <hjl.tools@gmail.com>
PR gas/27763
* config/tc-i386.c (output_jump): Also mark 2-byte relocs as
signed for XBEGIN. Also mark 4-byte relocs as signed for 64-bit.
(output_disp): Also mark 4-byte relocs as signed for 64-bit.
(md_estimate_size_before_relax): Move local variable fixP. Set
it from fix_new() return values. Mark 4-byte relocs as signed
for 64-bit.
* testsuite/gas/i386/pcrel64.s, testsuite/gas/i386/pcrel64.l,
* testsuite/gas/i386/x86-64-rip-2.s,
* testsuite/gas/i386/x86-64-rip-2.d,
* testsuite/gas/i386/x86-64-rip-inval-1.s,
* testsuite/gas/i386/x86-64-rip-inval-1.l,
* testsuite/gas/i386/x86-64-rip-inval-2.s,
* testsuite/gas/i386/x86-64-rip-inval-2.l: New.
* testsuite/gas/i386/i386.exp: Run new tests.
x86: Add () to silence GCC 5 Add () to !i.prefix[ADDR_PREFIX] to silence GCC 5: gas/config/tc-i386.c:4152:31: error: logical not is only applied to the left hand side of comparison [-Werror=logical-not-parentheses] && !i.prefix[ADDR_PREFIX] != (flag_code == CODE_32BIT)) ^ * config/tc-i386.c (optimize_encoding): Add () to silence GCC 5.
2021-04-27 23:16:55 +08:00
2021-04-27 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (optimize_encoding): Add () to silence GCC 5.
x86: add IS_ELF to check whether to resolve @size reloc This may not be strictly needed, as BFD_RELOC_SIZE* shouldn't appear from elsewhere for non-ELF, but let's be on the safe side.
2021-04-26 16:39:45 +08:00
2021-04-26 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (tc_gen_reloc): Check IS_ELF for
BFD_RELOC_SIZE*.
x86: limit 32-bit @size overflow checks to 64-bit objects For 32-bit objects the behavior should not be dependent upon the build being a BFD64 one.
2021-04-26 16:39:11 +08:00
2021-04-26 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (tc_gen_reloc): Limit BFD_RELOC_SIZE32
overflow check to 64-bit objects.
x86: optimize LEA Over the years I've seen a number of instances where people used lea (%reg1), %reg2 or lea symbol, %reg despite the same thing being expressable via MOV. Since additionally LEA often has restrictions towards the ports it can be issued to, while MOV typically gets dealt with simply by register renaming, transform to MOV when possible (without growing opcode size and without altering involved relocation types). Note that for Mach-O the new 64-bit testcases would fail (for BFD_RELOC_X86_64_32S not having a representation), and hence get skipped there.
2021-04-26 16:37:30 +08:00
2021-04-26 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (want_disp32): Also check for SIZE32.
(optimize_encoding): Handle LEA.
* testsuite/gas/i386/lea.s, testsuite/gas/i386/lea.d,
testsuite/gas/i386/lea.e, testsuite/gas/i386/lea-optimize.d:
Add many more forms.
* testsuite/gas/i386/lea16.s, testsuite/gas/i386/lea16-optimize.d,
testsuite/gas/i386/lea64.s, testsuite/gas/i386/lea64.d,
testsuite/gas/i386/lea64.e, testsuite/gas/i386/lea64-optimize.d:
New.
* testsuite/gas/i386/i386.exp: Run new tests.
x86-64: have value properly checked when resolving fixup Constants not known at the time an individual insn gets assembled and going into a sign-extended field still shouldn't be silently truncated at the time the respective fixup gets resolved.
2021-04-26 16:35:51 +08:00
2021-04-26 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (md_apply_fix): Mark BFD_RELOC_X86_64_32S as
signed.
* testsuite/gas/i386/x86-64-addr32-bad.s,
testsuite/gas/i386/x86-64-addr32-bad.l: New.
* testsuite/gas/i386/i386.exp: Run new test.
Fix type of .persistent.bss section The change implementing the .persistent family of sections broke the existing support for the .persistent.bss section in the compiler: int a __attribute__ ((section (".persistent.bss"))); t.s: Assembler messages: t.s:4: Warning: setting incorrect section type for .persistent.bss The compiler encodes it as @nobits but the assembler expects @progbits. The assembler is incorrect and should treat the section like the compiler. bfd/ * elf.c (special_sections_p): Add .persistent.bss. gas/ * testsuite/gas/elf/section25.d: Run it everywhere. * testsuite/gas/elf/section26.d: Likewise. * testsuite/gas/elf/section26.s: Add test for .persistent.bss.
2021-04-24 01:07:59 +08:00
2021-04-23 Eric Botcazou<ebotcazou@adacore.com>
* testsuite/gas/elf/section25.d: Run it everywhere.
* testsuite/gas/elf/section26.d: Likewise.
* testsuite/gas/elf/section26.s: Add test for .persistent.bss.
Allow .seh_pushframe to take an optional [code] parameter * config/obj-coff-seh.c (obj_coff_seh_pushframe): Allow an optional "code" argument.
2021-04-23 23:33:47 +08:00
2021-04-23 Jérôme Gardou <jerome.gardou@gmail.com>
* config/obj-coff-seh.c (obj_coff_seh_pushframe): Allow an
optional "code" argument.
x86-64: special case LEA when determining signedness of displacement LEA behavior without a 64-bit destination is independent of address size - in particular LEA with 32-bit addressing and 64-bit destination is the same as LEA with 64-bit addressing and 32-bit destination. IOW checking merely i.prefix[ADDR_PREFIX] is insufficient. This also means wrong relocation types (R_X86_64_32S when R_X86_64_32 is needed) were used so far in such cases. Note that in one case in build_modrm_byte() the 64-bit check came too early altogether, and hence gets dropped in favor of the one included in the new helper. This is benign to non-64-bit code from all I can tell, but the failure to clear disp16 could have been a latent problem.
2021-04-23 15:18:06 +08:00
2021-04-23 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (want_disp32): New.
(md_assemble): Use it.
(optimize_disp): Likewise.
(build_modrm_byte): Likewise.
x86-64: defer 32-bit signed displacement check In preparation for extending the conditions here defer this check until operands have been parsed, as certain further attributes will need to be known for determinig applicability of this check to be correct to LEA.
2021-04-23 15:17:33 +08:00
2021-04-23 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (i386_finalize_displacement): Move Disp32S
check ...
(md_assemble): ... here.
x86: re-order optimize_disp() While I can't point out any specific case where things break, it looks wrong to have the consumer of a flag before its producer. Set .disp32 first, then do the possible conversion to signed 32-bit, and finally check whether the value fits in a signed long.
2021-04-23 15:16:57 +08:00
2021-04-23 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (optimize_disp): Move down BFD64 section.
Move up setting of disp32.
x86: don't truncate values in diagnostics and alike Truncating an expression's X_add_number to just "long" can result in confusing output (e.g. an apparently in-range number claimed to be out of range). Use the abstraction that bfd provides for this. Take the opportunity and also insert a missing "of".
2021-04-23 15:15:45 +08:00
2021-04-23 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (pe): Don't truncate expression value.
(i386_finalize_displacement): Likewise.
Adjust readelf's output so that section symbols without a name as shown with their section name. binutils* readelf.c (print_dynamic_symbol): Print the section name for section symbols without a name of their own. * testsuite/binutils-all/mips/global-local-symtab-sort-n64t.d: Adjust expected output to allow for named section symbols. * testsuite/binutils-all/mips/global-local-symtab-sort-o32t.d: Likewise. * testsuite/binutils-all/readelf.s-64: Likewise. * testsuite/binutils-all/readelf.ss-64-unused: Likewise. * testsuite/binutils-all/readelf.ss-tmips: Likewise. * testsuite/binutils-all/readelf.ss-unused: Likewise. ld * testsuite/ld-aarch64/variant_pcs-now.d: Adjust expected output to allow for named section symbols. * testsuite/ld-aarch64/variant_pcs-r.d: Likewise. * testsuite/ld-aarch64/variant_pcs-shared.d: Likewise. * testsuite/ld-alpha/tlsbin.rd: Likewise. * testsuite/ld-alpha/tlsbinr.rd: Likewise. * testsuite/ld-alpha/tlspic.rd: Likewise. * testsuite/ld-arm/rodata-merge-map.sym: Likewise. * testsuite/ld-arm/script-type.sym: Likewise. * testsuite/ld-cris/libdso-2.d: Likewise. * testsuite/ld-cris/pr16044.d: Likewise. * testsuite/ld-elf/sec64k.exp: Likewise. * testsuite/ld-ia64/tlsbin.rd: Likewise. * testsuite/ld-ia64/tlspic.rd: Likewise. * testsuite/ld-mips-elf/global-local-symtab-sort-n64t.d: Likewise. * testsuite/ld-mips-elf/global-local-symtab-sort-o32t.d: Likewise. * testsuite/ld-mmix/bspec1.d: Likewise. * testsuite/ld-mmix/bspec2.d: Likewise. * testsuite/ld-mmix/local1.d: Likewise. * testsuite/ld-mmix/local3.d: Likewise. * testsuite/ld-mmix/local5.d: Likewise. * testsuite/ld-mmix/local7.d: Likewise. * testsuite/ld-mmix/undef-3.d: Likewise. * testsuite/ld-powerpc/tlsso.r: Likewise. * testsuite/ld-powerpc/tlsso32.r: Likewise. * testsuite/ld-powerpc/tlstocso.r: Likewise. * testsuite/ld-s390/tlsbin.rd: Likewise. * testsuite/ld-s390/tlsbin_64.rd: Likewise. * testsuite/ld-s390/tlspic.rd: Likewise. * testsuite/ld-s390/tlspic_64.rd: Likewise. * testsuite/ld-sparc/gotop32.rd: Likewise. * testsuite/ld-sparc/gotop64.rd: Likewise. * testsuite/ld-sparc/tlssunbin32.rd: Likewise. * testsuite/ld-sparc/tlssunbin64.rd: Likewise. * testsuite/ld-sparc/tlssunnopic32.rd: Likewise. * testsuite/ld-sparc/tlssunnopic64.rd: Likewise. * testsuite/ld-sparc/tlssunpic32.rd: Likewise. * testsuite/ld-sparc/tlssunpic64.rd: Likewise. * testsuite/ld-tic6x/common.d: Likewise. * testsuite/ld-tic6x/shlib-1.rd: Likewise. * testsuite/ld-tic6x/shlib-1b.rd: Likewise. * testsuite/ld-tic6x/shlib-1r.rd: Likewise. * testsuite/ld-tic6x/shlib-1rb.rd: Likewise. * testsuite/ld-tic6x/shlib-app-1.rd: Likewise. * testsuite/ld-tic6x/shlib-app-1b.rd: Likewise. * testsuite/ld-tic6x/shlib-app-1r.rd: Likewise. * testsuite/ld-tic6x/shlib-app-1rb.rd: Likewise. * testsuite/ld-tic6x/shlib-noindex.rd: Likewise. * testsuite/ld-tic6x/static-app-1.rd: Likewise. * testsuite/ld-tic6x/static-app-1b.rd: Likewise. * testsuite/ld-tic6x/static-app-1r.rd: Likewise. * testsuite/ld-tic6x/static-app-1rb.rd: Likewise. gas * testsuite/gas/aarch64/dwarf.d: Adjust expected output to allow for named section symbols. * testsuite/gas/arm/thumbver.d: Likewise. * testsuite/gas/bfin/loop_temps.d: Likewise. * testsuite/gas/elf/section2.e-arc: Likewise. * testsuite/gas/elf/section2.e-arm: Likewise. * testsuite/gas/elf/section2.e-csky: Likewise. * testsuite/gas/elf/section2.e-m32r: Likewise. * testsuite/gas/elf/section2.e-mips: Likewise. * testsuite/gas/elf/section2.e-msp430: Likewise. * testsuite/gas/elf/section2.e-riscv: Likewise. * testsuite/gas/elf/section2.e-rl78: Likewise. * testsuite/gas/elf/section2.e-rx: Likewise. * testsuite/gas/elf/section2.e-score: Likewise. * testsuite/gas/elf/section2.e-tic6x: Likewise. * testsuite/gas/elf/section2.e-unused: Likewise. * testsuite/gas/elf/section2.e-v850: Likewise. * testsuite/gas/elf/section2.e-xtensa: Likewise. * testsuite/gas/ia64/alias-ilp32.d: Likewise. * testsuite/gas/ia64/alias.d: Likewise. * testsuite/gas/ia64/global.d: Likewise. * testsuite/gas/microblaze/relax_size.elf: Likewise. * testsuite/gas/microblaze/relax_size2.elf: Likewise. * testsuite/gas/mips/global-local-symtab-sort-n64t.d: Likewise. * testsuite/gas/mips/global-local-symtab-sort-o32t.d: Likewise. * testsuite/gas/mmix/bspec-1.d: Likewise. * testsuite/gas/mmix/byte-1.d: Likewise. * testsuite/gas/mmix/comment-1.d: Likewise. * testsuite/gas/mmix/loc-1.d: Likewise. * testsuite/gas/mmix/loc-2.d: Likewise. * testsuite/gas/mmix/loc-3.d: Likewise. * testsuite/gas/mmix/loc-4.d: Likewise. * testsuite/gas/mmix/loc-5.d: Likewise. * testsuite/gas/tic6x/scomm-directive-4.d: Likewise.
2021-04-21 17:34:32 +08:00
2021-04-21 Nick Clifton <nickc@redhat.com>
* testsuite/gas/aarch64/dwarf.d: Adjust expected output to allow
for named section symbols.
* testsuite/gas/arm/thumbver.d: Likewise.
* testsuite/gas/bfin/loop_temps.d: Likewise.
* testsuite/gas/elf/section2.e-arc: Likewise.
* testsuite/gas/elf/section2.e-arm: Likewise.
* testsuite/gas/elf/section2.e-csky: Likewise.
* testsuite/gas/elf/section2.e-m32r: Likewise.
* testsuite/gas/elf/section2.e-mips: Likewise.
* testsuite/gas/elf/section2.e-msp430: Likewise.
* testsuite/gas/elf/section2.e-riscv: Likewise.
* testsuite/gas/elf/section2.e-rl78: Likewise.
* testsuite/gas/elf/section2.e-rx: Likewise.
* testsuite/gas/elf/section2.e-score: Likewise.
* testsuite/gas/elf/section2.e-tic6x: Likewise.
* testsuite/gas/elf/section2.e-unused: Likewise.
* testsuite/gas/elf/section2.e-v850: Likewise.
* testsuite/gas/elf/section2.e-xtensa: Likewise.
* testsuite/gas/ia64/alias-ilp32.d: Likewise.
* testsuite/gas/ia64/alias.d: Likewise.
* testsuite/gas/ia64/global.d: Likewise.
* testsuite/gas/microblaze/relax_size.elf: Likewise.
* testsuite/gas/microblaze/relax_size2.elf: Likewise.
* testsuite/gas/mips/global-local-symtab-sort-n64t.d: Likewise.
* testsuite/gas/mips/global-local-symtab-sort-o32t.d: Likewise.
* testsuite/gas/mmix/bspec-1.d: Likewise.
* testsuite/gas/mmix/byte-1.d: Likewise.
* testsuite/gas/mmix/comment-1.d: Likewise.
* testsuite/gas/mmix/loc-1.d: Likewise.
* testsuite/gas/mmix/loc-2.d: Likewise.
* testsuite/gas/mmix/loc-3.d: Likewise.
* testsuite/gas/mmix/loc-4.d: Likewise.
* testsuite/gas/mmix/loc-5.d: Likewise.
* testsuite/gas/tic6x/scomm-directive-4.d: Likewise.
Rework the R_NEG support on both gas and ld for the PowerPC AIX targets, in order to manage C++ exceptions built with GCC. bfd PR binutils/21700 * reloc.c (BFD_RELOC_PPC_NEG): New relocation. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * coff-rs6000.c (_bfd_xcoff_reloc_type_lookup): Add BFD_RELOC_PPC_NEG handler. (xcoff_reloc_type_neg): Correctly substract addend. * coff64-rs6000.c (xcoff64_howto_table): Add R_NEG_32 howto. (xcoff64_rtype2howto): Add handler for R_NEG_32. (xcoff64_reloc_type_lookup): Add BFD_RELOC_PPC_NEG handler. * xcofflink.c (xcoff_need_ldrel_p): Check output section for R_POS-like relocations. New argument added. (xcoff_mark): Adapt to new xcoff_need_ldrel_p argument. (xcoff_link_input_bfd): Likewise. gas * config/tc-ppc.c (ppc_get_csect_to_adjust): New function. (ppc_fix_adjustable): Manage fx_subsy part. (tc_gen_reloc): Create second relocation when both fx_addsy and fx_subsy are provided. * config/tc-ppc.h (RELOC_EXPANSION_POSSIBLE): New define. (MAX_RELOC_EXPANSION): Likewise. (TC_FORCE_RELOCATION_SUB_SAME): Likewise (UNDEFINED_DIFFERENCE_OK): Likewise * testsuite/gas/all/gas.exp: Skip difference between two undefined symbols test. ld * testsuite/ld-powerpc/aix52.exp: Add new test. * testsuite/ld-powerpc/aix-neg-reloc-32.d: New test. * testsuite/ld-powerpc/aix-neg-reloc-64.d: New test. * testsuite/ld-powerpc/aix-neg-reloc.ex: New test. * testsuite/ld-powerpc/aix-neg-reloc.s: New test.
2021-04-20 21:40:43 +08:00
2021-04-20 Clément Chigot <clement.chigot@atos.net>
PR binutils/21700
* config/tc-ppc.c (ppc_get_csect_to_adjust): New function.
(ppc_fix_adjustable): Manage fx_subsy part.
(tc_gen_reloc): Create second relocation when both
fx_addsy and fx_subsy are provided.
* config/tc-ppc.h (RELOC_EXPANSION_POSSIBLE): New define.
(MAX_RELOC_EXPANSION): Likewise.
(TC_FORCE_RELOCATION_SUB_SAME): Likewise
(UNDEFINED_DIFFERENCE_OK): Likewise
* testsuite/gas/all/gas.exp: Skip difference between two
undefined symbols test.
Fix an assembler testuite failure when checking a toolchain configured with --target=rs6000-aix3.3. * testsuite/gas/all/gas.exp: Add rs6000*-*-aix* to the list of targets which should skip the undefined symbols test.
2021-04-20 00:36:43 +08:00
2021-04-19 Nick Clifton <nickc@redhat.com>
* testsuite/gas/all/gas.exp: Add rs6000*-*-aix* to the list of
targets which should skip the undefined symbols test.
aarch64: New instructions for maintenance of GPT entries cached in a TLB This patch adds support to four new system registers (RPAOS, RPALOS, PAALLOS, PAALL) in conjunction with TLBI instruction. This change is part of RME (Realm Management Extension). gas/ChangeLog: 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * NEWS: Update news. * testsuite/gas/aarch64/rme.d: Update test. * testsuite/gas/aarch64/rme.s: Update test. opcodes/ChangeLog: 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support for TLBI instruction.
2021-04-19 22:00:07 +08:00
2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* NEWS: Update news.
* testsuite/gas/aarch64/rme.d: Update test.
* testsuite/gas/aarch64/rme.s: Update test.
aarch64: Add new data cache maintenance operations This patch adds support to two new system registers (CIPAPA, CIGDPAPA) in conjunction with DC instruction. This change is part of RME (Realm Management Extension). gas/ChangeLog: 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * testsuite/gas/aarch64/rme.d: Update test. * testsuite/gas/aarch64/rme.s: Update test. opcodes/ChangeLog: 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for DC instruction.
2021-04-19 21:54:46 +08:00
2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* testsuite/gas/aarch64/rme.d: Update test.
* testsuite/gas/aarch64/rme.s: Update test.
gas: drop sprint_value() Its (documented) behavior is unhelpful in particular in 64-bit build environments: While printing large 32-bit numbers in decimal already isn't very meaningful to most people, this even more so goes for yet larger 64-bit numbers. bfd_sprintf_vma() still tries to limit the number of digits printed (without depending on a build system property), but uniformly produces hex output.
2021-04-19 19:28:35 +08:00
2021-04-19 Jan Beulich <jbeulich@suse.com>
* as.h (sprint_value): Delete.
* messages.c (sprint_value): Likewise.
* config/tc-i386.c (offset_in_range): Use bfd_sprintf_vma in
place of sprint_value.
* config/tc-s390.c (s390_insert_operand): Likewise.
* doc/internals.texi (sprint_value): Delete section.
* write.c (fixup_segment): Likewise.
(relax_segment): Likewise.
aarch64: Define RME system registers This patch introduces RME (Realm Management Extension) system registers. gas/ChangeLog: 2021-03-01 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * testsuite/gas/aarch64/rme-invalid.d: New test. * testsuite/gas/aarch64/rme-invalid.l: New test. * testsuite/gas/aarch64/rme-invalid.s: New test. * testsuite/gas/aarch64/rme.d: New test. * testsuite/gas/aarch64/rme.s: New test. opcodes/ChangeLog: 2021-03-01 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-opc.c: Add RME system registers.
2021-04-16 22:33:38 +08:00
2021-04-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* testsuite/gas/aarch64/rme-invalid.d: New test.
* testsuite/gas/aarch64/rme-invalid.l: New test.
* testsuite/gas/aarch64/rme-invalid.s: New test.
* testsuite/gas/aarch64/rme.d: New test.
* testsuite/gas/aarch64/rme.s: New test.
RISC-V: PR27436, make operand C> work the same as >. gas/ PR 27436 * config/tc-riscv.c (riscv_ip): make operand C> work the same as >. * testsuite/gas/riscv/shamt-32.d: New testcase. * testsuite/gas/riscv/shamt-32.l: Likewise. * testsuite/gas/riscv/shamt-32.s: Likewise. * testsuite/gas/riscv/shamt-64.d: Likewise. * testsuite/gas/riscv/shamt-64.l: Likewise. * testsuite/gas/riscv/shamt-64.s: Likewise.
2021-04-16 14:50:32 +08:00
2021-04-16 Nelson Chu <nelson.chu@sifive.com>
PR 27436
* config/tc-riscv.c (riscv_ip): make operand C> work the same as >.
* testsuite/gas/riscv/shamt-32.d: New testcase.
* testsuite/gas/riscv/shamt-32.l: Likewise.
* testsuite/gas/riscv/shamt-32.s: Likewise.
* testsuite/gas/riscv/shamt-64.d: Likewise.
* testsuite/gas/riscv/shamt-64.l: Likewise.
* testsuite/gas/riscv/shamt-64.s: Likewise.
Update the ChangeLog, and add the missing entries.
2021-04-16 16:48:27 +08:00
2021-04-16 Lifang Xia <lifang_xia@c-sky.com>
* testsuite/gas/riscv/c-zero-imm.d: Compress addi a4,a4,0 to
c.mv a4,a4.
* testsuite/gas/riscv/c-zero-imm.s: Likewise.
Re: PR27723, Internal error in select_cie_for_fde Let's make sure what we allow in the CIE initial instructions and what select_cie_for_fde compares for a match is always in sync. Also correct the previous patch that allowed DW_CFA_GNU_window_save to be part of the CIE initial instructions, which was likely a mistake. PR 27723 * dw2gencfi.c (initial_cie_insn): New function, extracted from.. (select_cie_for_fde): ..here. Simplify.
2021-04-14 07:53:12 +08:00
2021-04-14 Alan Modra <amodra@gmail.com>
PR 27723
* dw2gencfi.c (initial_cie_insn): New function, extracted from..
(select_cie_for_fde): ..here. Simplify.
PR27723, Internal error in select_cie_for_fde PR 27723 * dw2gencfi.c (select_cie_for_fde): Handle DW_CFA_val_offset, DW_CFA_GNU_window_save and DW_CFA_restore_state.
2021-04-13 21:51:04 +08:00
2021-04-14 Alan Modra <amodra@gmail.com>
PR 27723
* dw2gencfi.c (select_cie_for_fde): Handle DW_CFA_val_offset,
DW_CFA_GNU_window_save and DW_CFA_restore_state.
m68hc11 gas testsuite wart Writing to a potentially read-only source directory is not good. * testsuite/gas/m68hc11/m68hc11.exp (gas_m68hc11_message): Don't write to $srcdir. Use gas_host_run and read output file rather than gas_start/gas_finish.
2021-04-12 23:02:11 +08:00
2021-04-13 Alan Modra <amodra@gmail.com>
* testsuite/gas/m68hc11/m68hc11.exp (gas_m68hc11_message): Don't
write to $srcdir. Use gas_host_run and read output file rather
than gas_start/gas_finish.
Power10 bignum operands When built on a 32-bit host without --enable-64-bit-bfd, powerpc-linux and other 32-bit powerpc targeted binutils fail to assemble some power10 prefixed instructions with 34-bit fields. A typical error seen when running the testsuite is .../gas/testsuite/gas/ppc/prefix-pcrel.s:10: Error: bignum invalid In practice this doesn't matter for addresses: 32-bit programs don't need or use the top 2 bits of a d34 field when calculating addresses. However it may matter when loading or adding 64-bit constants with paddi. A power10 processor in 32-bit mode still has 64-bit wide GPRs. So this patch enables limited support for O_big PowerPC operands, and corrects sign extension of 32-bit constants using X_extrabit. * config/tc-ppc.c (insn_validate): Use uint64_t for operand values. (md_assemble): Likewise. Handle bignum operands. (ppc_elf_suffix): Handle O_big. Remove unnecessary input_line_pointer check. * expr.c: Delete unnecessary forward declarations. (generic_bignum_to_int32): Return uint32_t. (generic_bignum_to_int64): Return uint64_t. Compile always. (operand): Twiddle X_extrabit for unary '~'. Set X_unsigned and clear X_extrabit for unary '!'. * expr.h (generic_bignum_to_int32): Declare. (generic_bignum_to_int64): Declare. * testsuite/gas/ppc/prefix-pcrel.s, * testsuite/gas/ppc/prefix-pcrel.d: Add more instructions.
2021-04-12 07:32:46 +08:00
2021-04-12 Alan Modra <amodra@gmail.com>
* config/tc-ppc.c (insn_validate): Use uint64_t for operand values.
(md_assemble): Likewise. Handle bignum operands.
(ppc_elf_suffix): Handle O_big. Remove unnecessary input_line_pointer
check.
* expr.c: Delete unnecessary forward declarations.
(generic_bignum_to_int32): Return uint32_t.
(generic_bignum_to_int64): Return uint64_t. Compile always.
(operand): Twiddle X_extrabit for unary '~'. Set X_unsigned and
clear X_extrabit for unary '!'.
* expr.h (generic_bignum_to_int32): Declare.
(generic_bignum_to_int64): Declare.
* testsuite/gas/ppc/prefix-pcrel.s,
* testsuite/gas/ppc/prefix-pcrel.d: Add more instructions.
RISC-V: Support to parse the multi-letter prefix in the architecture string. The original discussion is as follows, https://github.com/riscv/riscv-isa-manual/issues/637 I never considered the prefixes may have multiple letters, like zxm. But the ISA spec has been updated for a long time that I haven't noticed. This patch rewrites the part of architecture parser to support parsing the multi-letter prefixes. Besides, I also improve the parser to report errors in details. One of the most obvious improvement is - Do not parse the prefixed extensions according to the orders in the parse_config. If we do so, then we used to get "unexpected ISA string at end" errors, but the message is a little bit hard to know what is happening. I Remove the confused message, and let riscv_parse_prefixed_ext to report the details. bfd/ * elfxx-riscv.c (riscv_std_z_ext_strtab): Moved forward. (riscv_std_s_ext_strtab): Likewise. (riscv_std_h_ext_strtab): Likewise. (riscv_std_zxm_ext_strtab): Added for the zxm prefix. (enum riscv_prefix_ext_class): Moved forward and renamed from riscv_isa_ext_class. Reorder them according to the parsing order, since the enum values are used to check the orders in the riscv_compare_subsets. (struct riscv_parse_prefix_config): Moved forward and renamed from riscv_parse_config_t. Also removed the ext_valid_p field, the related functions are replaced by riscv_valid_prefixed_ext. (parse_config): Moved forward and updated. The more letters of the prefix string, the more forward it must be defined. Otherwise, we will get the wrong mapping when using strncmp in riscv_get_prefix_class. (riscv_get_prefix_class): Moved forward. Support to parse the multi-letter prefix, like zxm. (riscv_known_prefixed_ext): New function, check if the prefixed extension is supported according to the right riscv_std_*_ext_strtab. (riscv_valid_prefixed_ext): New function, used to replace the riscv_ext_*_valid_p functions. (riscv_init_ext_order): Do not set the values for prefix keywords since they may have multiple letters for now. (riscv_compare_subsets): Set the order values of prefix keywords to negative numbers according to the riscv_prefix_ext_class. (riscv_parse_std_ext): Call riscv_get_prefix_class to see if we have parsed the prefixed extensions. (riscv_parse_prefixed_ext): Updated and removed the parameter config. Report error when the prefix is unknown. (riscv_parse_subset): Do not parse the prefixed extensions according to the orders in the parse_config. Remove the confused message and let riscv_parse_prefixed_ext to report the details. * elfxx-riscv.h (enum riscv_isa_ext_class): Moved to elfxx-riscv.c. (riscv_get_prefix_class): Removed to static. gas/ * testsuite/gas/riscv/march-fail-order-x-std.d: Renamed from march-fail-porder-x-std.d. * testsuite/gas/riscv/march-fail-order-z-std.d: Renamed from march-fail-porder-z-std.d. * testsuite/gas/riscv/march-fail-order-x-z.d: Renamed from march-fail-porder-x-z.d. * testsuite/gas/riscv/march-fail-order-zx-std.l: Added to replace march-fail-porder.l. * testsuite/gas/riscv/march-fail-order-x-z.l: Likewise. * testsuite/gas/riscv/march-fail-order-x.l: Updated. * testsuite/gas/riscv/march-fail-order-z.l: Likewise. * testsuite/gas/riscv/march-fail-single-prefix-h.d: Renamed from march-fail-single-char-h.d. * testsuite/gas/riscv/march-fail-single-prefix-s.d: Renamed from march-fail-single-char-s.d. * testsuite/gas/riscv/march-fail-single-prefix-x.d: Renamed from march-fail-single-char-x.d. * testsuite/gas/riscv/march-fail-single-prefix-z.d: Renamed from march-fail-single-char-z.d. * testsuite/gas/riscv/march-fail-single-prefix-zmx.d: Added. * testsuite/gas/riscv/march-fail-single-prefix.l: Added to replace march-fail-single-prefix.l. * testsuite/gas/riscv/march-fail-unknown-zxm.d: Added. * testsuite/gas/riscv/march-fail-unknown-std.l: Updated. * testsuite/gas/riscv/march-fail-unknown.l: Likewise.
2021-04-07 12:50:19 +08:00
2021-04-12 Nelson Chu <nelson.chu@sifive.com>
* testsuite/gas/riscv/march-fail-order-x-std.d: Renamed from
march-fail-porder-x-std.d.
* testsuite/gas/riscv/march-fail-order-z-std.d: Renamed from
march-fail-porder-z-std.d.
* testsuite/gas/riscv/march-fail-order-x-z.d: Renamed from
march-fail-porder-x-z.d.
* testsuite/gas/riscv/march-fail-order-zx-std.l: Added to replace
march-fail-porder.l.
* testsuite/gas/riscv/march-fail-order-x-z.l: Likewise.
* testsuite/gas/riscv/march-fail-order-x.l: Updated.
* testsuite/gas/riscv/march-fail-order-z.l: Likewise.
* testsuite/gas/riscv/march-fail-single-prefix-h.d: Renamed from
march-fail-single-char-h.d.
* testsuite/gas/riscv/march-fail-single-prefix-s.d: Renamed from
march-fail-single-char-s.d.
* testsuite/gas/riscv/march-fail-single-prefix-x.d: Renamed from
march-fail-single-char-x.d.
* testsuite/gas/riscv/march-fail-single-prefix-z.d: Renamed from
march-fail-single-char-z.d.
* testsuite/gas/riscv/march-fail-single-prefix-zmx.d: Added.
* testsuite/gas/riscv/march-fail-single-prefix.l: Added to replace
march-fail-single-prefix.l.
* testsuite/gas/riscv/march-fail-unknown-zxm.d: Added.
* testsuite/gas/riscv/march-fail-unknown-std.l: Updated.
* testsuite/gas/riscv/march-fail-unknown.l: Likewise.
AArch64: Fix Diagnostic messaging for LD/ST Exclusive. A summary of what this patch set fixes: For instructions STXR w0,x2,[x0] STLXR w0,x2,[x0] The warning we emit currently is misleading: Warning: unpredictable: identical transfer and status registers --`stlxr w0,x2,[x0]' Warning: unpredictable: identical transfer and status registers --`stxr w0,x2,[x0]' it ought to be: Warning: unpredictable: identical base and status registers --`stlxr w0,x2,[x0]' Warning: unpredictable: identical base and status registers --`stxr w0,x2,[x0]' For instructions: ldaxp x0,x0,[x0] ldxp x0,x0,[x0] The warning we emit is incorrect Warning: unpredictable: identical transfer and status registers --`ldaxp x0,x0,[x0]' Warning: unpredictable: identical transfer and status registers --`ldxp x0,x0,[x0]' it ought to be: Warning: unpredictable load of register pair -- `ldaxp x0,x0,[x0]' Warning: unpredictable load of register pair -- `ldxp x0,x0,[x0]' For instructions stlxp w0, x2, x2, [x0] stxp w0, x2, x2, [x0] We don't emit any warning when it ought to be: Warning: unpredictable: identical base and status registers --`stlxp w0,x2,x2,[x0]' Warning: unpredictable: identical base and status registers --`stxp w0,x2,x2,[x0]' gas/ChangeLog: 2021-04-09 Tejas Belagod <tejas.belagod@arm.com> * config/tc-aarch64.c (warn_unpredictable_ldst): Clean-up diagnostic messages for LD/ST Exclusive instructions. * testsuite/gas/aarch64/diagnostic.s: Add a diagnostic test for STLXP. * testsuite/gas/aarch64/diagnostic.l: Fix-up test after message clean-up.
2021-04-09 19:29:32 +08:00
2021-04-09 Tejas Belagod <tejas.belagod@arm.com>
Power10 bignum operands When built on a 32-bit host without --enable-64-bit-bfd, powerpc-linux and other 32-bit powerpc targeted binutils fail to assemble some power10 prefixed instructions with 34-bit fields. A typical error seen when running the testsuite is .../gas/testsuite/gas/ppc/prefix-pcrel.s:10: Error: bignum invalid In practice this doesn't matter for addresses: 32-bit programs don't need or use the top 2 bits of a d34 field when calculating addresses. However it may matter when loading or adding 64-bit constants with paddi. A power10 processor in 32-bit mode still has 64-bit wide GPRs. So this patch enables limited support for O_big PowerPC operands, and corrects sign extension of 32-bit constants using X_extrabit. * config/tc-ppc.c (insn_validate): Use uint64_t for operand values. (md_assemble): Likewise. Handle bignum operands. (ppc_elf_suffix): Handle O_big. Remove unnecessary input_line_pointer check. * expr.c: Delete unnecessary forward declarations. (generic_bignum_to_int32): Return uint32_t. (generic_bignum_to_int64): Return uint64_t. Compile always. (operand): Twiddle X_extrabit for unary '~'. Set X_unsigned and clear X_extrabit for unary '!'. * expr.h (generic_bignum_to_int32): Declare. (generic_bignum_to_int64): Declare. * testsuite/gas/ppc/prefix-pcrel.s, * testsuite/gas/ppc/prefix-pcrel.d: Add more instructions.
2021-04-12 07:32:46 +08:00
* config/tc-aarch64.c (warn_unpredictable_ldst): Clean-up
diagnostic messages for LD/ST Exclusive instructions.
AArch64: Fix Diagnostic messaging for LD/ST Exclusive. A summary of what this patch set fixes: For instructions STXR w0,x2,[x0] STLXR w0,x2,[x0] The warning we emit currently is misleading: Warning: unpredictable: identical transfer and status registers --`stlxr w0,x2,[x0]' Warning: unpredictable: identical transfer and status registers --`stxr w0,x2,[x0]' it ought to be: Warning: unpredictable: identical base and status registers --`stlxr w0,x2,[x0]' Warning: unpredictable: identical base and status registers --`stxr w0,x2,[x0]' For instructions: ldaxp x0,x0,[x0] ldxp x0,x0,[x0] The warning we emit is incorrect Warning: unpredictable: identical transfer and status registers --`ldaxp x0,x0,[x0]' Warning: unpredictable: identical transfer and status registers --`ldxp x0,x0,[x0]' it ought to be: Warning: unpredictable load of register pair -- `ldaxp x0,x0,[x0]' Warning: unpredictable load of register pair -- `ldxp x0,x0,[x0]' For instructions stlxp w0, x2, x2, [x0] stxp w0, x2, x2, [x0] We don't emit any warning when it ought to be: Warning: unpredictable: identical base and status registers --`stlxp w0,x2,x2,[x0]' Warning: unpredictable: identical base and status registers --`stxp w0,x2,x2,[x0]' gas/ChangeLog: 2021-04-09 Tejas Belagod <tejas.belagod@arm.com> * config/tc-aarch64.c (warn_unpredictable_ldst): Clean-up diagnostic messages for LD/ST Exclusive instructions. * testsuite/gas/aarch64/diagnostic.s: Add a diagnostic test for STLXP. * testsuite/gas/aarch64/diagnostic.l: Fix-up test after message clean-up.
2021-04-09 19:29:32 +08:00
* testsuite/gas/aarch64/diagnostic.s: Add a diagnostic test for STLXP.
Power10 bignum operands When built on a 32-bit host without --enable-64-bit-bfd, powerpc-linux and other 32-bit powerpc targeted binutils fail to assemble some power10 prefixed instructions with 34-bit fields. A typical error seen when running the testsuite is .../gas/testsuite/gas/ppc/prefix-pcrel.s:10: Error: bignum invalid In practice this doesn't matter for addresses: 32-bit programs don't need or use the top 2 bits of a d34 field when calculating addresses. However it may matter when loading or adding 64-bit constants with paddi. A power10 processor in 32-bit mode still has 64-bit wide GPRs. So this patch enables limited support for O_big PowerPC operands, and corrects sign extension of 32-bit constants using X_extrabit. * config/tc-ppc.c (insn_validate): Use uint64_t for operand values. (md_assemble): Likewise. Handle bignum operands. (ppc_elf_suffix): Handle O_big. Remove unnecessary input_line_pointer check. * expr.c: Delete unnecessary forward declarations. (generic_bignum_to_int32): Return uint32_t. (generic_bignum_to_int64): Return uint64_t. Compile always. (operand): Twiddle X_extrabit for unary '~'. Set X_unsigned and clear X_extrabit for unary '!'. * expr.h (generic_bignum_to_int32): Declare. (generic_bignum_to_int64): Declare. * testsuite/gas/ppc/prefix-pcrel.s, * testsuite/gas/ppc/prefix-pcrel.d: Add more instructions.
2021-04-12 07:32:46 +08:00
* testsuite/gas/aarch64/diagnostic.l: Fix-up test after message
clean-up.
AArch64: Fix Diagnostic messaging for LD/ST Exclusive. A summary of what this patch set fixes: For instructions STXR w0,x2,[x0] STLXR w0,x2,[x0] The warning we emit currently is misleading: Warning: unpredictable: identical transfer and status registers --`stlxr w0,x2,[x0]' Warning: unpredictable: identical transfer and status registers --`stxr w0,x2,[x0]' it ought to be: Warning: unpredictable: identical base and status registers --`stlxr w0,x2,[x0]' Warning: unpredictable: identical base and status registers --`stxr w0,x2,[x0]' For instructions: ldaxp x0,x0,[x0] ldxp x0,x0,[x0] The warning we emit is incorrect Warning: unpredictable: identical transfer and status registers --`ldaxp x0,x0,[x0]' Warning: unpredictable: identical transfer and status registers --`ldxp x0,x0,[x0]' it ought to be: Warning: unpredictable load of register pair -- `ldaxp x0,x0,[x0]' Warning: unpredictable load of register pair -- `ldxp x0,x0,[x0]' For instructions stlxp w0, x2, x2, [x0] stxp w0, x2, x2, [x0] We don't emit any warning when it ought to be: Warning: unpredictable: identical base and status registers --`stlxp w0,x2,x2,[x0]' Warning: unpredictable: identical base and status registers --`stxp w0,x2,x2,[x0]' gas/ChangeLog: 2021-04-09 Tejas Belagod <tejas.belagod@arm.com> * config/tc-aarch64.c (warn_unpredictable_ldst): Clean-up diagnostic messages for LD/ST Exclusive instructions. * testsuite/gas/aarch64/diagnostic.s: Add a diagnostic test for STLXP. * testsuite/gas/aarch64/diagnostic.l: Fix-up test after message clean-up.
2021-04-09 19:29:32 +08:00
PowerPC disassembly of pcrel references This adds some annotation to Power10 pcrel instructions, displaying the target address (ie. pc + D34 field) plus a symbol if there is one at exactly that target address. pld from the .got or .plt will also look up the entry and display it, symbolically if there is a dynamic relocation on the entry. include/ * dis-asm.h (struct disassemble_info): Add dynrelbuf and dynrelcount. binutils/ * objdump.c (struct objdump_disasm_info): Delete dynrelbuf and dynrelcount. (find_symbol_for_address): Adjust for dynrelbuf and dynrelcount move. (disassemble_section, disassemble_data): Likewise. opcodes/ * ppc-dis.c (struct dis_private): Add "special". (POWERPC_DIALECT): Delete. Replace uses with.. (private_data): ..this. New inline function. (disassemble_init_powerpc): Init "special" names. (skip_optional_operands): Add is_pcrel arg, set when detecting R field of prefix instructions. (bsearch_reloc, print_got_plt): New functions. (print_insn_powerpc): For pcrel instructions, print target address and symbol if known, and decode plt and got loads too. gas/ * testsuite/gas/ppc/prefix-pcrel.d: Update expected output. * testsuite/gas/ppc/prefix-reloc.d: Likewise. * gas/testsuite/gas/ppc/vsx_32byte.d: Likewise. ld/ * testsuite/ld-powerpc/inlinepcrel-1.d: Update expected output. * testsuite/ld-powerpc/inlinepcrel-2.d: Likewise. * testsuite/ld-powerpc/notoc2.d: Likewise. * testsuite/ld-powerpc/notoc3.d: Likewise. * testsuite/ld-powerpc/pcrelopt.d: Likewise. * testsuite/ld-powerpc/startstop.d: Likewise. * testsuite/ld-powerpc/tlsget.d: Likewise. * testsuite/ld-powerpc/tlsget2.d: Likewise. * testsuite/ld-powerpc/tlsld.d: Likewise. * testsuite/ld-powerpc/weak1.d: Likewise. * testsuite/ld-powerpc/weak1so.d: Likewise.
2021-04-06 17:33:35 +08:00
2021-04-09 Alan Modra <amodra@gmail.com>
* testsuite/gas/ppc/prefix-pcrel.d: Update expected output.
* testsuite/gas/ppc/prefix-reloc.d: Likewise.
* gas/testsuite/gas/ppc/vsx_32byte.d: Likewise.
PR27676, PowerPC missing extended dcbt, dcbtst mnemonics Note that this doesn't implement the ISA to the letter regarding dcbtds (and dcbtstds), which says that the TH field may be zero. That doesn't make sense because allowing TH=0 would mean you no long have a dcbtds but rather a dcbtct instruction. I'm interpreting the ISA wording about allowing TH=0 to mean that the TH field of dcbtds is optional (in which case the TH value is 0b1000). opcodes/ PR 27676 * ppc-opc.c (DCBT_EO): Move earlier. (insert_thct, extract_thct, insert_thds, extract_thds): New functions. (powerpc_operands): Add THCT and THDS entries. (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds. gas/ * testsuite/gas/ppc/pr27676.d, * testsuite/gas/ppc/pr27676.s: New test. * testsuite/gas/ppc/ppc.exp: Run it. * testsuite/gas/ppc/dcbt.d: Update. * testsuite/gas/ppc/power4_32.d: Update.
2021-04-05 06:47:06 +08:00
2021-04-08 Alan Modra <amodra@gmail.com>
* testsuite/gas/ppc/pr27676.d,
* testsuite/gas/ppc/pr27676.s: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
* testsuite/gas/ppc/dcbt.d: Update.
* testsuite/gas/ppc/power4_32.d: Update.
Fix pr27217 testcase failure aarch64_be-linux-gnu_ilp32 +FAIL: PR27212 PR 27217 * testsuite/gas/aarch64/pr27217.d: Correct name. Accept ilp32 relocs.
2021-04-07 16:42:38 +08:00
2021-04-07 Alan Modra <amodra@gmail.com>
PR 27217
* testsuite/gas/aarch64/pr27217.d: Correct name. Accept ilp32 relocs.
Fix a problem assembling AArch64 sources when a relocation is generated against a symbol that has a defined value. PR 27217 * config/tc-aarch64.c (my_get_expression): Rename to aarch64_get_expression. Add a fifth argument to enable deferring of expression resolution. (parse_typed_reg): Update calls to my_get_expression. (parse_vector_reg_list): Likewise. (parse_immediate_expression): Likewise. (parse_big_immediate): Likewise. (parse_shift): Likewise. (parse_shifter_operand_imm): Likewise. (parse_operands): Likewise. (parse_shifter_operand_reloc): Update calls to my_get_expression and call aarch64_force_reloc to determine the value of the new fifth argument. (parse_address_main): Likewise. (parse_half): Likewise. (parse_adrp): Likewise. (aarch64_force_reloc): New function. Contains code extracted from... (aarch64_force_relocation): ... here. * testsuite/gas/aarch64/pr27217.s: New test case. * testsuite/gas/aarch64/pr27217.d: New test driver.
2021-04-06 20:27:50 +08:00
2021-04-06 Nick Clifton <nickc@redhat.com>
PR 27217
* config/tc-aarch64.c (my_get_expression): Rename to
aarch64_get_expression. Add a fifth argument to enable deferring
of expression resolution.
(parse_typed_reg): Update calls to my_get_expression.
(parse_vector_reg_list): Likewise.
(parse_immediate_expression): Likewise.
(parse_big_immediate): Likewise.
(parse_shift): Likewise.
(parse_shifter_operand_imm): Likewise.
(parse_operands): Likewise.
(parse_shifter_operand_reloc): Update calls to my_get_expression
and call aarch64_force_reloc to determine the value of the new
fifth argument.
(parse_address_main): Likewise.
(parse_half): Likewise.
(parse_adrp): Likewise.
(aarch64_force_reloc): New function. Contains code extracted from...
(aarch64_force_relocation): ... here.
* testsuite/gas/aarch64/pr27217.s: New test case.
* testsuite/gas/aarch64/pr27217.d: New test driver.
gas: missing (re-)initialization of local variable in fixup_segment() At the very least this has been causing bogus diagnostics, e.g. .text .data .long .bss - . .long -.text .bss yielding Error: can't resolve `0' {.bss section} - `.text' {.text section} instead of Error: can't resolve `0' {*ABS* section} - `.text' {.text section} In particular for targets overriding any of TC_FORCE_RELOCATION_* & Co or for ones setting md_register_arithmetic to true the problems may be worse.
2021-04-06 16:56:30 +08:00
2021-04-06 Jan Beulich <jbeulich@suse.com>
* write.c (fixup_segment): Move add_symbol_segment declaration
into main loop.
C99 gas configury Also remove alloca stuff since we don't use alloca in gas nowadays. * configure.ac: Don't check for string.h, strings.h, stdlib.h, errno.h, limits.h, locale.h or time.h. Don't check for unlink, remove, sbrk (unused) or setlocale. Adjust gas_test_headers. Don't check for errno, free, malloc, realoc, sbrk, strstr, getenv strstr, or vsnprintf declarations. (AC_ISC_POSIX, AC_FUNC_ALLOCA, AC_C_INLINE): Don't invoke. * as.h: Don't include alloca-conf.h, include config.h instead. Include string.h, stdlib.h, errno.h unconditionally. Remove various fallback declarations. * asintl.h: Don't test HAVE_LOCALE_H. * as.c: Don't test HAVE_SETLOCALE. * dwarf2dbg.c: Include limits.h unconditionally. * expr.c: Likewise. * sb.c: Likewise. * symbols.c: Likewise. * config/tc-cr16.c: Likewise. * config/tc-d30v.c: Likewise. * config/tc-i386.c: Likewise. * config/tc-ia64.c: Likewise. * config/tc-tic54x.c (tic54x_mlib): Call remove rather than unlink. * config.in: Regenerate. * configure: Regenerate. * Makefile.in: Regenerate. * doc/Makefile.in: Regenerate.
2021-04-05 14:01:25 +08:00
2021-04-05 Alan Modra <amodra@gmail.com>
* configure.ac: Don't check for string.h, strings.h, stdlib.h,
errno.h, limits.h, locale.h or time.h. Don't check for unlink,
remove, sbrk (unused) or setlocale. Adjust gas_test_headers.
Don't check for errno, free, malloc, realoc, sbrk, strstr, getenv
strstr, or vsnprintf declarations.
(AC_ISC_POSIX, AC_FUNC_ALLOCA, AC_C_INLINE): Don't invoke.
* as.h: Don't include alloca-conf.h, include config.h instead.
Include string.h, stdlib.h, errno.h unconditionally. Remove
various fallback declarations.
* asintl.h: Don't test HAVE_LOCALE_H.
* as.c: Don't test HAVE_SETLOCALE.
* dwarf2dbg.c: Include limits.h unconditionally.
* expr.c: Likewise.
* sb.c: Likewise.
* symbols.c: Likewise.
* config/tc-cr16.c: Likewise.
* config/tc-d30v.c: Likewise.
* config/tc-i386.c: Likewise.
* config/tc-ia64.c: Likewise.
* config/tc-tic54x.c (tic54x_mlib): Call remove rather than unlink.
* config.in: Regenerate.
* configure: Regenerate.
* Makefile.in: Regenerate.
* doc/Makefile.in: Regenerate.
Remove strneq macro and use startswith. bfd/ChangeLog: * ecoff.c (strneq): Remove strneq and use startswith. (_bfd_ecoff_slurp_armap): Likewise. binutils/ChangeLog: * elfcomm.h (strneq): Remove strneq and use startswith. * readelf.c (ia64_process_unwind): Likewise. (process_note): Likewise. gas/ChangeLog: * config/obj-coff.c (strneq): Remove strneq and use startswith. (weak_is_altname): Likewise. (obj_coff_section): Likewise. * config/tc-cr16.c (process_label_constant): Likewise. * config/tc-crx.c (strneq): Likewise. include/ChangeLog: * opcode/cr16.h (strneq): Remove strneq and use startswith. ld/ChangeLog: * ldbuildid.c (strneq): Remove strneq and use startswith. (validate_build_id_style): Likewise. (compute_build_id_size): Likewise. opcodes/ChangeLog: * arm-dis.c (strneq): Remove strneq and use startswith. * cr16-dis.c (print_insn_cr16): Likewise. * score-dis.c (streq): Likewise. (strneq): Likewise. * score7-dis.c (strneq): Likewise.
2021-03-22 21:56:16 +08:00
2021-04-01 Martin Liska <mliska@suse.cz>
* config/obj-coff.c (strneq): Remove strneq and use startswith.
(weak_is_altname): Likewise.
(obj_coff_section): Likewise.
* config/tc-cr16.c (process_label_constant): Likewise.
* config/tc-crx.c (strneq): Likewise.
Use startswith in gas subfolder. gas/ChangeLog: * as.c (select_emulation_mode): Use startswith. * config/m68k-parse.y: Likewise. * config/obj-aout.c (obj_aout_type): Likewise. * config/obj-elf.c (elf_common_parse): Likewise. (obj_elf_section_type): Likewise. (obj_elf_section_word): Likewise. (obj_elf_section): Likewise. (obj_elf_symver): Likewise. (adjust_stab_sections): Likewise. * config/obj-evax.c (evax_shorten_name): Likewise. * config/obj-macho.c (obj_mach_o_is_frame_section): Likewise. * config/tc-aarch64.c (parse_aarch64_imm_float): Likewise. (aarch64_parse_features): Likewise. (create_register_alias): Likewise. (aarch64_data_in_code): Likewise. (md_parse_option): Likewise. * config/tc-alpha.c (s_alpha_section_word): Likewise. (s_alpha_pdesc): Likewise. * config/tc-arc.c (tokenize_extregister): Likewise. * config/tc-arm.c (create_register_alias): Likewise. (create_neon_reg_alias): Likewise. (parse_ifimm_zero): Likewise. (parse_qfloat_immediate): Likewise. (arm_elf_section_type): Likewise. (arm_parse_extension): Likewise. (aeabi_set_public_attributes): Likewise. (s_arm_arch_extension): Likewise. (arm_data_in_code): Likewise. (start_unwind_section): Likewise. * config/tc-avr.c (avr_ldi_expression): Likewise. * config/tc-csky.c (is_freglist_legal): Likewise. (csky_s_section): Likewise. * config/tc-d30v.c (do_assemble): Likewise. * config/tc-dlx.c (parse_operand): Likewise. * config/tc-epiphany.c (md_assemble): Likewise. * config/tc-h8300.c (h8300_elf_section): Likewise. (get_operand): Likewise. * config/tc-hppa.c (pa_ip): Likewise. (pa_level): Likewise. (pa_space): Likewise. * config/tc-i386.c (i386_mach): Likewise. (md_assemble): Likewise. (check_VecOperations): Likewise. (i386_target_format): Likewise. (i386_elf_section_type): Likewise. * config/tc-ia64.c (start_unwind_section): Likewise. (md_parse_option): Likewise. (is_taken_branch): Likewise. (idesc->name,): Likewise. (note_register_values): Likewise. (do_alias): Likewise. * config/tc-m32c.c (insn_to_subtype): Likewise. * config/tc-m68hc11.c (get_operand): Likewise. (md_assemble): Likewise. * config/tc-m68k.c (m68k_ip): Likewise. (m68k_elf_suffix): Likewise. * config/tc-mcore.c (mcore_s_section): Likewise. * config/tc-metag.c (parse_get_set): Likewise. (md_parse_option): Likewise. * config/tc-microblaze.c (parse_imm): Likewise. (check_got): Likewise. (md_apply_fix): Likewise. * config/tc-mips.c (CPU_HAS_MIPS16): Likewise. (md_begin): Likewise. (s_is_linkonce): Likewise. (check_regno): Likewise. (match_float_constant): Likewise. (classify_vr4120_insn): Likewise. (match_insn): Likewise. (mips_after_parse_args): Likewise. (s_change_sec): Likewise. (s_option): Likewise. (parse_code_option): Likewise. (md_section_align): Likewise. (nopic_need_relax): Likewise. * config/tc-mmix.c (mmix_handle_mmixal): Likewise. * config/tc-mn10300.c (mn10300_fix_adjustable): Likewise. (mn10300_end_of_match): Likewise. * config/tc-msp430.c (msp430_make_init_symbols): Likewise. * config/tc-nds32.c (nds32_parse_option): Likewise. * config/tc-nds32.h (md_do_align): Likewise. * config/tc-nios2.c (strprefix): Likewise. (nios2_special_relocation_p): Likewise. (nios2_parse_base_register): Likewise. (nios2_cons): Likewise. * config/tc-ns32k.c (addr_mode): Likewise. * config/tc-pdp11.c (set_option): Likewise. (parse_reg): Likewise. (parse_ac5): Likewise. (parse_op_no_deferred): Likewise. (set_cpu_model): Likewise. (set_machine_model): Likewise. * config/tc-pj.c (md_operand): Likewise. * config/tc-ppc.c (ppc_set_cpu): Likewise. (ppc_arch): Likewise. (ppc_section_type): Likewise. * config/tc-s12z.c (tb_reg_rel): Likewise. (tb_opr_rel): Likewise. * config/tc-s390.c (s390_parse_cpu): Likewise. (md_parse_option): Likewise. * config/tc-score.c (s3_nopic_need_relax): Likewise. (s3_pic_need_relax): Likewise. * config/tc-score7.c (s7_nopic_need_relax): Likewise. (s7_pic_need_relax): Likewise. * config/tc-sh.h (SUB_SEGMENT_ALIGN): Likewise. * config/tc-sparc.c (md_parse_option): Likewise. (sparc_ip): Likewise. (s_reserve): Likewise. (s_common): Likewise. (s_seg): Likewise. (sparc_cons): Likewise. * config/tc-tic54x.c (stag_add_field): Likewise. (tic54x_endstruct): Likewise. * config/tc-tic6x.c (tic6x_start_unwind_section): Likewise. * config/tc-v850.c (v850_comm): Likewise. (md_begin): Likewise. (md_assemble): Likewise. * config/tc-vax.c (vax_cons): Likewise. * config/tc-wasm32.c (wasm32_leb128): Likewise. * config/tc-xstormy16.c (md_operand): Likewise. * config/tc-xtensa.c (get_directive): Likewise. (xg_instruction_matches_option_term): Likewise. (is_unaligned_label): Likewise. (cache_literal_section): Likewise. * config/xtensa-relax.c (parse_precond): Likewise. (parse_option_cond): Likewise. (transition_applies): Likewise. (wide_branch_opcode): Likewise. * dw2gencfi.c: Likewise. * dwarf2dbg.c (dwarf2_directive_filename): Likewise. * ehopt.c (get_cie_info): Likewise. * input-file.c (input_file_open): Likewise. * listing.c (listing_newline): Likewise. (debugging_pseudo): Likewise. * read.c (read_a_source_file): Likewise. * write.c (adjust_reloc_syms): Likewise. (compress_debug): Likewise. (maybe_generate_build_notes): Likewise.
2021-03-22 20:33:04 +08:00
2021-04-01 Martin Liska <mliska@suse.cz>
* as.c (select_emulation_mode): Use startswith.
* config/m68k-parse.y: Likewise.
* config/obj-aout.c (obj_aout_type): Likewise.
* config/obj-elf.c (elf_common_parse): Likewise.
(obj_elf_section_type): Likewise.
(obj_elf_section_word): Likewise.
(obj_elf_section): Likewise.
(obj_elf_symver): Likewise.
(adjust_stab_sections): Likewise.
* config/obj-evax.c (evax_shorten_name): Likewise.
* config/obj-macho.c (obj_mach_o_is_frame_section): Likewise.
* config/tc-aarch64.c (parse_aarch64_imm_float): Likewise.
(aarch64_parse_features): Likewise.
(create_register_alias): Likewise.
(aarch64_data_in_code): Likewise.
(md_parse_option): Likewise.
* config/tc-alpha.c (s_alpha_section_word): Likewise.
(s_alpha_pdesc): Likewise.
* config/tc-arc.c (tokenize_extregister): Likewise.
* config/tc-arm.c (create_register_alias): Likewise.
(create_neon_reg_alias): Likewise.
(parse_ifimm_zero): Likewise.
(parse_qfloat_immediate): Likewise.
(arm_elf_section_type): Likewise.
(arm_parse_extension): Likewise.
(aeabi_set_public_attributes): Likewise.
(s_arm_arch_extension): Likewise.
(arm_data_in_code): Likewise.
(start_unwind_section): Likewise.
* config/tc-avr.c (avr_ldi_expression): Likewise.
* config/tc-csky.c (is_freglist_legal): Likewise.
(csky_s_section): Likewise.
* config/tc-d30v.c (do_assemble): Likewise.
* config/tc-dlx.c (parse_operand): Likewise.
* config/tc-epiphany.c (md_assemble): Likewise.
* config/tc-h8300.c (h8300_elf_section): Likewise.
(get_operand): Likewise.
* config/tc-hppa.c (pa_ip): Likewise.
(pa_level): Likewise.
(pa_space): Likewise.
* config/tc-i386.c (i386_mach): Likewise.
(md_assemble): Likewise.
(check_VecOperations): Likewise.
(i386_target_format): Likewise.
(i386_elf_section_type): Likewise.
* config/tc-ia64.c (start_unwind_section): Likewise.
(md_parse_option): Likewise.
(is_taken_branch): Likewise.
(idesc->name,): Likewise.
(note_register_values): Likewise.
(do_alias): Likewise.
* config/tc-m32c.c (insn_to_subtype): Likewise.
* config/tc-m68hc11.c (get_operand): Likewise.
(md_assemble): Likewise.
* config/tc-m68k.c (m68k_ip): Likewise.
(m68k_elf_suffix): Likewise.
* config/tc-mcore.c (mcore_s_section): Likewise.
* config/tc-metag.c (parse_get_set): Likewise.
(md_parse_option): Likewise.
* config/tc-microblaze.c (parse_imm): Likewise.
(check_got): Likewise.
(md_apply_fix): Likewise.
* config/tc-mips.c (CPU_HAS_MIPS16): Likewise.
(md_begin): Likewise.
(s_is_linkonce): Likewise.
(check_regno): Likewise.
(match_float_constant): Likewise.
(classify_vr4120_insn): Likewise.
(match_insn): Likewise.
(mips_after_parse_args): Likewise.
(s_change_sec): Likewise.
(s_option): Likewise.
(parse_code_option): Likewise.
(md_section_align): Likewise.
(nopic_need_relax): Likewise.
* config/tc-mmix.c (mmix_handle_mmixal): Likewise.
* config/tc-mn10300.c (mn10300_fix_adjustable): Likewise.
(mn10300_end_of_match): Likewise.
* config/tc-msp430.c (msp430_make_init_symbols): Likewise.
* config/tc-nds32.c (nds32_parse_option): Likewise.
* config/tc-nds32.h (md_do_align): Likewise.
* config/tc-nios2.c (strprefix): Likewise.
(nios2_special_relocation_p): Likewise.
(nios2_parse_base_register): Likewise.
(nios2_cons): Likewise.
* config/tc-ns32k.c (addr_mode): Likewise.
* config/tc-pdp11.c (set_option): Likewise.
(parse_reg): Likewise.
(parse_ac5): Likewise.
(parse_op_no_deferred): Likewise.
(set_cpu_model): Likewise.
(set_machine_model): Likewise.
* config/tc-pj.c (md_operand): Likewise.
* config/tc-ppc.c (ppc_set_cpu): Likewise.
(ppc_arch): Likewise.
(ppc_section_type): Likewise.
* config/tc-s12z.c (tb_reg_rel): Likewise.
(tb_opr_rel): Likewise.
* config/tc-s390.c (s390_parse_cpu): Likewise.
(md_parse_option): Likewise.
* config/tc-score.c (s3_nopic_need_relax): Likewise.
(s3_pic_need_relax): Likewise.
* config/tc-score7.c (s7_nopic_need_relax): Likewise.
(s7_pic_need_relax): Likewise.
* config/tc-sh.h (SUB_SEGMENT_ALIGN): Likewise.
* config/tc-sparc.c (md_parse_option): Likewise.
(sparc_ip): Likewise.
(s_reserve): Likewise.
(s_common): Likewise.
(s_seg): Likewise.
(sparc_cons): Likewise.
* config/tc-tic54x.c (stag_add_field): Likewise.
(tic54x_endstruct): Likewise.
* config/tc-tic6x.c (tic6x_start_unwind_section): Likewise.
* config/tc-v850.c (v850_comm): Likewise.
(md_begin): Likewise.
(md_assemble): Likewise.
* config/tc-vax.c (vax_cons): Likewise.
* config/tc-wasm32.c (wasm32_leb128): Likewise.
* config/tc-xstormy16.c (md_operand): Likewise.
* config/tc-xtensa.c (get_directive): Likewise.
(xg_instruction_matches_option_term): Likewise.
(is_unaligned_label): Likewise.
(cache_literal_section): Likewise.
* config/xtensa-relax.c (parse_precond): Likewise.
(parse_option_cond): Likewise.
(transition_applies): Likewise.
(wide_branch_opcode): Likewise.
* dw2gencfi.c: Likewise.
* dwarf2dbg.c (dwarf2_directive_filename): Likewise.
* ehopt.c (get_cie_info): Likewise.
* input-file.c (input_file_open): Likewise.
* listing.c (listing_newline): Likewise.
(debugging_pseudo): Likewise.
* read.c (read_a_source_file): Likewise.
* write.c (adjust_reloc_syms): Likewise.
(compress_debug): Likewise.
(maybe_generate_build_notes): Likewise.
Don't include bfd/sysdep.h for gas files * itbl-lex-wrapper.c: Include as.h not sysdep.h. * config/bfin-lex-wrapper.c: Likewise. * itbl-lex.l: Don't include as.h. * config/bfin-lex.l: Likewise.
2021-03-31 15:45:46 +08:00
2021-03-31 Alan Modra <amodra@gmail.com>
* itbl-lex-wrapper.c: Include as.h not sysdep.h.
* config/bfin-lex-wrapper.c: Likewise.
* itbl-lex.l: Don't include as.h.
* config/bfin-lex.l: Likewise.
Use bool in gas * as.h (POISON_BFD_BOOLEAN): Define. * as.c, * as.h, * atof-generic.c, * config/atof-ieee.c, * config/bfin-aux.h, * config/obj-coff.c, * config/obj-ecoff.c, * config/obj-elf.c, * config/obj-elf.h, * config/obj-som.c, * config/tc-aarch64.c, * config/tc-alpha.c, * config/tc-arc.c, * config/tc-arc.h, * config/tc-arm.c, * config/tc-arm.h, * config/tc-avr.c, * config/tc-avr.h, * config/tc-bfin.c, * config/tc-bfin.h, * config/tc-bpf.c, * config/tc-cris.c, * config/tc-csky.c, * config/tc-csky.h, * config/tc-d10v.c, * config/tc-d10v.h, * config/tc-d30v.c, * config/tc-d30v.h, * config/tc-dlx.c, * config/tc-dlx.h, * config/tc-epiphany.c, * config/tc-epiphany.h, * config/tc-fr30.c, * config/tc-fr30.h, * config/tc-frv.c, * config/tc-frv.h, * config/tc-ft32.c, * config/tc-ft32.h, * config/tc-h8300.c, * config/tc-hppa.c, * config/tc-i386-intel.c, * config/tc-i386.c, * config/tc-ia64.c, * config/tc-ip2k.c, * config/tc-iq2000.c, * config/tc-iq2000.h, * config/tc-lm32.c, * config/tc-lm32.h, * config/tc-m32c.c, * config/tc-m32c.h, * config/tc-m32r.c, * config/tc-m32r.h, * config/tc-m68hc11.c, * config/tc-m68k.c, * config/tc-mcore.c, * config/tc-mcore.h, * config/tc-mep.c, * config/tc-mep.h, * config/tc-metag.c, * config/tc-metag.h, * config/tc-microblaze.c, * config/tc-mips.c, * config/tc-mips.h, * config/tc-mmix.c, * config/tc-mn10200.c, * config/tc-mn10300.c, * config/tc-mn10300.h, * config/tc-moxie.c, * config/tc-msp430.c, * config/tc-msp430.h, * config/tc-mt.c, * config/tc-mt.h, * config/tc-nds32.c, * config/tc-nds32.h, * config/tc-nios2.c, * config/tc-ns32k.c, * config/tc-or1k.c, * config/tc-or1k.h, * config/tc-pdp11.c, * config/tc-ppc.c, * config/tc-pru.c, * config/tc-pru.h, * config/tc-riscv.c, * config/tc-riscv.h, * config/tc-rx.c, * config/tc-rx.h, * config/tc-s12z.c, * config/tc-s12z.h, * config/tc-s390.c, * config/tc-score.c, * config/tc-score.h, * config/tc-score7.c, * config/tc-sh.c, * config/tc-sh.h, * config/tc-spu.c, * config/tc-tic54x.c, * config/tc-tic6x.c, * config/tc-tic6x.h, * config/tc-tilegx.c, * config/tc-tilepro.c, * config/tc-v850.c, * config/tc-v850.h, * config/tc-visium.c, * config/tc-visium.h, * config/tc-wasm32.c, * config/tc-wasm32.h, * config/tc-xc16x.c, * config/tc-xgate.c, * config/tc-xstormy16.c, * config/tc-xstormy16.h, * config/tc-xtensa.c, * config/tc-xtensa.h, * config/tc-z80.c, * config/tc-z8k.c, * config/xtensa-istack.h, * config/xtensa-relax.c, * config/xtensa-relax.h, * dw2gencfi.c, * dwarf2dbg.c, * dwarf2dbg.h, * expr.c, * expr.h, * frags.c, * frags.h, * listing.c, * macro.c, * output-file.c, * read.c, * read.h, * stabs.c, * symbols.c, * write.c: Replace bfd_boolean with bool, FALSE with false, and TRUE with true.
2021-03-31 08:12:05 +08:00
2021-03-31 Alan Modra <amodra@gmail.com>
* as.h (POISON_BFD_BOOLEAN): Define.
* as.c, * as.h, * atof-generic.c, * config/atof-ieee.c,
* config/bfin-aux.h, * config/obj-coff.c, * config/obj-ecoff.c,
* config/obj-elf.c, * config/obj-elf.h, * config/obj-som.c,
* config/tc-aarch64.c, * config/tc-alpha.c, * config/tc-arc.c,
* config/tc-arc.h, * config/tc-arm.c, * config/tc-arm.h,
* config/tc-avr.c, * config/tc-avr.h, * config/tc-bfin.c,
* config/tc-bfin.h, * config/tc-bpf.c, * config/tc-cris.c,
* config/tc-csky.c, * config/tc-csky.h, * config/tc-d10v.c,
* config/tc-d10v.h, * config/tc-d30v.c, * config/tc-d30v.h,
* config/tc-dlx.c, * config/tc-dlx.h, * config/tc-epiphany.c,
* config/tc-epiphany.h, * config/tc-fr30.c, * config/tc-fr30.h,
* config/tc-frv.c, * config/tc-frv.h, * config/tc-ft32.c,
* config/tc-ft32.h, * config/tc-h8300.c, * config/tc-hppa.c,
* config/tc-i386-intel.c, * config/tc-i386.c, * config/tc-ia64.c,
* config/tc-ip2k.c, * config/tc-iq2000.c, * config/tc-iq2000.h,
* config/tc-lm32.c, * config/tc-lm32.h, * config/tc-m32c.c,
* config/tc-m32c.h, * config/tc-m32r.c, * config/tc-m32r.h,
* config/tc-m68hc11.c, * config/tc-m68k.c, * config/tc-mcore.c,
* config/tc-mcore.h, * config/tc-mep.c, * config/tc-mep.h,
* config/tc-metag.c, * config/tc-metag.h,
* config/tc-microblaze.c, * config/tc-mips.c, * config/tc-mips.h,
* config/tc-mmix.c, * config/tc-mn10200.c, * config/tc-mn10300.c,
* config/tc-mn10300.h, * config/tc-moxie.c, * config/tc-msp430.c,
* config/tc-msp430.h, * config/tc-mt.c, * config/tc-mt.h,
* config/tc-nds32.c, * config/tc-nds32.h, * config/tc-nios2.c,
* config/tc-ns32k.c, * config/tc-or1k.c, * config/tc-or1k.h,
* config/tc-pdp11.c, * config/tc-ppc.c, * config/tc-pru.c,
* config/tc-pru.h, * config/tc-riscv.c, * config/tc-riscv.h,
* config/tc-rx.c, * config/tc-rx.h, * config/tc-s12z.c,
* config/tc-s12z.h, * config/tc-s390.c, * config/tc-score.c,
* config/tc-score.h, * config/tc-score7.c, * config/tc-sh.c,
* config/tc-sh.h, * config/tc-spu.c, * config/tc-tic54x.c,
* config/tc-tic6x.c, * config/tc-tic6x.h, * config/tc-tilegx.c,
* config/tc-tilepro.c, * config/tc-v850.c, * config/tc-v850.h,
* config/tc-visium.c, * config/tc-visium.h, * config/tc-wasm32.c,
* config/tc-wasm32.h, * config/tc-xc16x.c, * config/tc-xgate.c,
* config/tc-xstormy16.c, * config/tc-xstormy16.h,
* config/tc-xtensa.c, * config/tc-xtensa.h, * config/tc-z80.c,
* config/tc-z8k.c, * config/xtensa-istack.h,
* config/xtensa-relax.c, * config/xtensa-relax.h, * dw2gencfi.c,
* dwarf2dbg.c, * dwarf2dbg.h, * expr.c, * expr.h, * frags.c,
* frags.h, * listing.c, * macro.c, * output-file.c, * read.c,
* read.h, * stabs.c, * symbols.c, * write.c: Replace bfd_boolean
with bool, FALSE with false, and TRUE with true.
Remove bfd_stdint.h If we require C99 for binutils then stdint.h is available. bfd/ * .gitignore: Delete bfd_stdint.h entry. * Makefile.am (bfdinclude_HEADERS): Delete bfd_stdint.h. (BUILD_HFILES, LOCAL_H_DEPS): Likewise. * bfd-in.h: Include stdint.h in place of bfd_stdint.h. * configure.ac: Don't invoke GCC_HEADER_STDINT. * configure.com: Don't create bfd_stdint.h. * Makefile.in: Regenerate. * aclocal.m4: Regenerate. * bfd-in2.h: Regenerate. * config.in: Regenerate. * configure: Regenerate. * doc/Makefile.in: Regenerate. * po/BLD-POTFILES.in: Regenerate. binutils/ * coffdump.c: Include stdint.h in place of bfd_stdint.h. * dwarf.c: Likewise. gas/ * config/tc-aarch64.c: Include stdint.h in place of bfd_stdint.h. * config/tc-crx.c: Likewise. * config/tc-nds32.h: Likewise. include/ * cgen/basic-modes.h: Include stdint.h in place of bfd_stdint.h. * elf/nfp.h: Likewise. * opcode/aarch64.h: Likewise. * opcode/cgen.h: Likewise. * opcode/nfp.h: Likewise. * opcode/ppc.h: Likewise. ld/ * elf-hints-local.h: Include stdint.h in place of bfd_stdint.h. * emultempl/nds32elf.em: Likewise. * testsuite/ld-elf/mbind2b.c: Likewise. * testsuite/ld-elf/pr18718.c: Likewise. * testsuite/ld-elf/pr18720a.c: Likewise. * testsuite/ld-elf/pr25749-1.c: Likewise. * testsuite/ld-elf/pr25749-1a.c: Likewise. * testsuite/ld-elf/pr25749-1b.c: Likewise. * testsuite/ld-elf/pr25749-1c.c: Likewise. * testsuite/ld-elf/pr25749-1d.c: Likewise. * testsuite/ld-elf/pr25749-2.c: Likewise. * testsuite/ld-elf/pr25754-1a.c: Likewise. * testsuite/ld-elf/pr25754-2a.c: Likewise. * testsuite/ld-elf/pr25754-3a.c: Likewise. * testsuite/ld-elf/pr25754-4a.c: Likewise. * testsuite/ld-elf/pr25754-5a.c: Likewise. * testsuite/ld-elf/pr25754-6a.c: Likewise. opcodes/ * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h. * aarch64-dis.h: Likewise. * aarch64-opc.c: Likewise. * avr-dis.c: Likewise. * csky-dis.c: Likewise. * nds32-asm.c: Likewise. * nds32-dis.c: Likewise. * nfp-dis.c: Likewise. * riscv-dis.c: Likewise. * s12z-dis.c: Likewise. * wasm32-dis.c: Likewise.
2021-03-31 07:37:02 +08:00
2021-03-31 Alan Modra <amodra@gmail.com>
* config/tc-aarch64.c: Include stdint.h in place of bfd_stdint.h.
* config/tc-crx.c: Likewise.
* config/tc-nds32.h: Likewise.
x86: drop seg_entry Use struct reg_entry instead for most purposes, with a separate array holding just the respective opcode prefix bytes.
2021-03-30 20:09:41 +08:00
2021-03-30 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (build_modrm_byte): Change return type.
Change type of "default_seg". Use NULL. Adjust setting of
"default_seg".
(reg_ds, reg_es, reg_ss): New.
(struct _i386_insn): Change type of seg[].
(md_begin): Initialize reg_ds, reg_es, and reg_ss.
(swap_operands): Change type of "temp_seg".
(check_string): Adjust %es check.
(process_operands): Change type of "default_seg". Use NULL.
Adjust segment override processing..
(i386_att_operand): Adjust segment override handling.
* config/tc-i386-intel.c (i386_intel_operand): Likewise.
x86: drop REGNAM_{AL,AX,EAX} The former two are unused anyway. And having such constants isn't very helpful either, when they live in a place where updating the register table wouldn't even allow noticing the need to adjust these constants.
2021-03-30 20:08:48 +08:00
2021-03-30 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (reg_eax): New.
(md_begin): Initialize reg_eax.
* config/tc-i386-intel.c (i386_intel_simplify_register): Use
reg_eax.
(i386_intel_simplify): Likewise.
x86: adjust st(<N>) parsing st(1) ... st(7) will never be looked up in the hash table, so there's no point inserting the entries. It's also not really necessary to do a 2nd hash lookup after parsing the register number, nor is there a real reason for having both st and st(0) entries. Plus we can easily do away with the need for st to be first in the table.
2021-03-30 20:08:11 +08:00
2021-03-30 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (reg_st0): New.
(md_begin): Convert to switch(). Initialize reg_st0. Don't
insert other st(N).
(parse_real_register): Adjust st(N) processing.
x86: integrate rc_op into struct _i386_insn There's no need for the extra level of indirection and the extra storage needed for the pointer, pointing from one piece of static data to another. Key checking of rounding being in effect off of the type field of the structure instead.
2021-03-30 20:06:37 +08:00
2021-03-30 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (rc_op): Delete.
(struct Rounding_Operation): Move ...
(struct _i386_insn): ... here. Change field "rounding".
(build_evex_prefix): Adjust rounding processing.
(swap_2_operands): Likewise.
(check_VecOperands): Likewise.
(RC_SAE_immediate): Likewise.
(optimize_encoding): Adjust check for rounding.
(build_modrm_byte): Likewise.
(output_imm): Likewise.
(md_assemble): Initialize rounding type.
x86: integrate broadcast_op into struct _i386_insn There's no need for the extra level of indirection and the extra storage needed for the pointer, pointing from one piece of static data to another. Key checking of broadcast being in effect off of the type field of the structure instead.
2021-03-30 20:06:09 +08:00
2021-03-30 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (broadcast_op): Delete.
(struct Broadcast_Operation): Move ...
(struct _i386_insn): ... here. Change field "broadcast".
(match_mem_size): Adjust check for broadcast.
(optimize_encoding): Likewise.
(process_suffix): Likewise.
(build_evex_prefix): Adjust broadcast processing.
(swap_2_operands): Likewise.
(check_VecOperations): Likewise.
(match_template): Likewise.
(check_VecOperands): Likewise.
x86: integrate mask_op into struct _i386_insn There's no need for the extra level of indirection and the extra storage needed for the pointer, pointing from one piece of static data to another. Key checking of masking being in effect off of the register field of the structure instead.
2021-03-30 20:05:42 +08:00
2021-03-30 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (reg_k0): New.
(mask_op): Delete.
(struct Mask_Operation): Move ...
(struct _i386_insn): ... here. Change field "mask".
(md_begin): Initialize reg_k0.
(build_evex_prefix): Adjust mask processing.
(swap_2_operands): Likewise.
(check_VecOperands): Likewise.
(check_VecOperations): Likewise.
(optimize_encoding): Adjust checks for masking.
(output_insn): Likewise.
x86: make swap_2_operands() have unsigned parameters All callers pass unsigned values (in some cases by virtue of passing non-negative literal numbers). This in turn requires struct {Mask,RC,Broadcast}_Operation's "operand" fields to become unsigned, in turn allowing to reduce the amount of casting needed (the two new casts that are necessary cast _to_ "unsigned" instead of _from_, as that's the form that'll never case undefined behavior).
2021-03-30 20:05:10 +08:00
2021-03-30 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (swap_2_operands): Switch parameters to
unsigned.
(struct RC_Operation): Switch operand field to unsigned.
(struct Mask_Operation): Likewise.
(struct Broadcast_Operation): Likewise.
(build_evex_prefix): Drop cast.
(check_VecOperands): Likewise.
(build_modrm_byte): Likewise.
(output_imm): Likewise.
(check_VecOperations): Add casts to unsigned.
x86: VPSADBW's source operands are also commutative In commit 79dec6b7baa2 ("x86-64: optimize certain commutative VEX-encoded insns") I missed the fact that there being subtraction involved here doesn't matter, as absolute differences get summed up.
2021-03-29 18:06:09 +08:00
2021-03-29 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/x86-64-sse2avx.s: Add vpsadbw case.
* testsuite/gas/i386/x86-64-avx-swap-2.d.
testsuite/gas/i386/x86-64-sse2avx.d: Adjust expectations.
x86: derive opcode encoding space attribute from base opcode Just like is already done for VEX/XOP/EVEX encoded insns, record the encoding space information in the respective opcode modifier field. Do this again without changing the source table, but rather by deriving the values from their existing source representation.
2021-03-29 18:02:50 +08:00
2021-03-29 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (optimize_encoding): Replace VEX-encoding
checks by opcodespace ones.
(insert_lfence_before): Likewise.
(maybe_fused_with_jcc_p): Likewise.
(add_branch_padding_frag_p): Likewise.
(output_disp): Likewise.
(load_insn_p): Re-arrange checks to key applicable ones off of
an opcodespace check.
(md_assemble): Adjust opcode checks.
(check_byte_reg): Likewise.
(process_operands): Likewise.
(i386_index_check): Likewise.
(process_suffix): Likewise. New local variable is_movx. Adjust
movsx/movzx and crc32 handling.
(output_insn): Adjust opcode checks. Drop no longer reachable
case labels. Output legacy encoding prefixes in addition to the
base_opcode byte(s). Rework counting of prefixes for extended
opcode maps.
* config/tc-i386-intel.c (i386_intel_simplify_register): Adjust
opcode checks.
TRUE/FALSE simplification There is really no need to write code like "foo != 0 ? TRUE : FALSE" unless we had stupidly defined FALSE as something other than 0 or TRUE as something other than 1. The simpler "foo != 0" does just as well. Similarly "(condition == TRUE)" or "(condition == FALSE) can be simplified to "(condition)" and "(!condition)" respectively. I'll note that there is reason to use "integer_expression != 0" when assigning a bfd_boolean rather than the simpler "integer_expression", if you expect the variable to have 0 or 1 value. It's probably even a good idea to not rely on implicit conversion if bfd_boolean were _Bool. bfd/ * aoutx.h (aout_link_write_symbols): Don't cast boolean expression to bfd_boolean. * elf32-or1k.c (or1k_set_got_and_rela_sizes): Dont compare booleans against FALSE. * elf32-arc.c (name_for_global_symbol): Don't compare boolean to TRUE. (is_reloc_PC_relative): Don't use "boolean_condition ? TRUE : FALSE". (is_reloc_SDA_relative, is_reloc_for_GOT): Likewise. (is_reloc_for_PLT, is_reloc_for_TLS): Likewise. * elf32-arm.c (stm32l4xx_need_create_replacing_stub): Likewise. * elf32-nds32.c (insert_nds32_elf_blank): Likewise. * elf32-rx.c (rx_set_section_contents): Likewise. * elfnn-aarch64.c (elfNN_aarch64_final_link_relocate): Likewise. * elfxx-mips.c (_bfd_mips_elf_ignore_undef_symbol): Likewise. * mach-o.c (bfd_mach_o_read_command): Likewise. * targets.c (bfd_get_target_info): Likewise. binutils/ * dlltool.c (main): Don't use "boolean_condition ? TRUE : FALSE". * dwarf.c (read_and_display_attr_value): Likewise. (display_debug_str_offsets): Likewise. * objdump.c (dump_bfd): Likewise. * readelf.c (dump_section_as_strings): Likewise. (dump_section_as_bytes): Likewise. gas/ * atof-generic.c (FALSE, TRUE): Don't define. * config/obj-elf.h (FALSE, TRUE): Don't define. * config/obj-som.h (FALSE, TRUE): Don't define. * config/tc-hppa.h (FALSE, TRUE): Don't define. * config/tc-pdp11.c (FALSE, TRUE): Don't define. * config/tc-iq2000.h (obj_fix_adjustable): Delete. * config/tc-m32r.h (TC_FIX_ADJUSTABLE): Delete. * config/tc-mt.h (obj_fix_adjustable): Delete. * config/tc-nds32.h (TC_FIX_ADJUSTABLE): Delete. * config/tc-arc.c (parse_opcode_flags): Simplify boolean expression. (relaxable_flag, relaxable_operand, assemble_insn): Likewise. (tokenize_extregister): Likewise. * config/tc-csky.c (parse_opcode, get_operand_value): Likewise. (parse_operands_op, parse_operands, md_assemble): Likewise. * config/tc-d10v.c (build_insn): Likewise. * config/tc-score.c (s3_gen_insn_frag): Likewise. * config/tc-score7.c (s7_gen_insn_frag, s7_relax_frag): Likewise. * config/tc-tic6x.c (tic6x_update_features, md_assemble): Likewise. * config/tc-z80.c (emit_byte): Likewise. include/ * opcode/aarch64.h (alias_opcode_p): Simplify boolean expression. (opcode_has_alias, pseudo_opcode_p, optional_operand_p): Likewise. (opcode_has_special_coder): Likewise. ld/ * emultempl/aix.em (gld${EMULATION_NAME}_before_allocation): Simplify boolean expression. * lexsup.c (parse_args): Likewise. * pe-dll.c (pe_dll_id_target): Likewise. opcodes/ * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression. (fp_qualifier_p, get_data_pattern): Likewise. (aarch64_get_operand_modifier_from_value): Likewise. (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise. (operand_variant_qualifier_p): Likewise. (qualifier_value_in_range_constraint_p): Likewise. (aarch64_get_qualifier_esize): Likewise. (aarch64_get_qualifier_nelem): Likewise. (aarch64_get_qualifier_standard_value): Likewise. (get_lower_bound, get_upper_bound): Likewise. (aarch64_find_best_match, match_operands_qualifier): Likewise. (aarch64_print_operand): Likewise. * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise. (operand_need_sign_extension, operand_need_shift_by_two): Likewise. (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise. * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise. * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise. (print_insn_tic6x): Likewise.
2021-03-29 07:22:56 +08:00
2021-03-29 Alan Modra <amodra@gmail.com>
* atof-generic.c (FALSE, TRUE): Don't define.
* config/obj-elf.h (FALSE, TRUE): Don't define.
* config/obj-som.h (FALSE, TRUE): Don't define.
* config/tc-hppa.h (FALSE, TRUE): Don't define.
* config/tc-pdp11.c (FALSE, TRUE): Don't define.
* config/tc-iq2000.h (obj_fix_adjustable): Delete.
* config/tc-m32r.h (TC_FIX_ADJUSTABLE): Delete.
* config/tc-mt.h (obj_fix_adjustable): Delete.
* config/tc-nds32.h (TC_FIX_ADJUSTABLE): Delete.
* config/tc-arc.c (parse_opcode_flags): Simplify boolean expression.
(relaxable_flag, relaxable_operand, assemble_insn): Likewise.
(tokenize_extregister): Likewise.
* config/tc-csky.c (parse_opcode, get_operand_value): Likewise.
(parse_operands_op, parse_operands, md_assemble): Likewise.
* config/tc-d10v.c (build_insn): Likewise.
* config/tc-score.c (s3_gen_insn_frag): Likewise.
* config/tc-score7.c (s7_gen_insn_frag, s7_relax_frag): Likewise.
* config/tc-tic6x.c (tic6x_update_features, md_assemble): Likewise.
* config/tc-z80.c (emit_byte): Likewise.
gas int vs bfd_boolean fixes * config/tc-arm.c (struct arm_long_option_table <func>): Return bfd_boolean. * config/tc-arm.h (arm_optimize_expr, arm_data_in_code): Likewise. * config/tc-metag.c (parse_mov_port): Replace unsigned int variable with bfd_boolean. (parse_mmov, parse_mov_ct, parse_alu, parse_shift, parse_bitop), (parse_cmp, parse_fmmov, parse_fmov_data, parse_fearith), (parse_dget_set, parse_dalu): Likewise, ensuring assignment from logical expressions. (struct metag_long_option <func>): Return bfd_boolean. (metag_parse_cpu, metag_parse_fpu, metag_parse_dsp): Likewise. * config/tc-msp430.c (msp430_dstoperand): Correct dummy type. * config/tc-s12z.c (parse_operand_func): Return bfd_boolean. (no_operands, lex_force_match, lex_reg_list): Likewise. (size_from_suffix): Return int. (s12z_relax_frag, md_estimate_size_before_relax): Return 0. * config/tc-s12z.h (tc_s12z_fix_adjustable): Likewise.
2021-03-29 07:19:35 +08:00
2021-03-29 Alan Modra <amodra@gmail.com>
* config/tc-arm.c (struct arm_long_option_table <func>): Return
bfd_boolean.
* config/tc-arm.h (arm_optimize_expr, arm_data_in_code): Likewise.
* config/tc-metag.c (parse_mov_port): Replace unsigned int variable
with bfd_boolean.
(parse_mmov, parse_mov_ct, parse_alu, parse_shift, parse_bitop),
(parse_cmp, parse_fmmov, parse_fmov_data, parse_fearith),
(parse_dget_set, parse_dalu): Likewise, ensuring assignment from
logical expressions.
(struct metag_long_option <func>): Return bfd_boolean.
(metag_parse_cpu, metag_parse_fpu, metag_parse_dsp): Likewise.
* config/tc-msp430.c (msp430_dstoperand): Correct dummy type.
* config/tc-s12z.c (parse_operand_func): Return bfd_boolean.
(no_operands, lex_force_match, lex_reg_list): Likewise.
(size_from_suffix): Return int.
(s12z_relax_frag, md_estimate_size_before_relax): Return 0.
* config/tc-s12z.h (tc_s12z_fix_adjustable): Likewise.
x86-64: don't accept supposedly disabled MOVQ forms While all of MMX, SSE, and SSE2 are included in "generic64", they can be individually disabled. There are two MOVQ forms lacking respective attributes. While the MMX one would get refused anyway (due to MMX registers not recognized with .nommx), the assembler did happily accept the SSE2 form. Add respective CPU settings to both, paralleling what the MOVD counterparts have.
2021-03-26 18:43:19 +08:00
2021-03-26 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/x86-64-nosse2.s,
testsuite/gas/i386/x86-64-nosse2.l: New.
* testsuite/gas/i386/i386.exp: Run new test.
[NIOS2] Fix disassembly of br.n instruction. The code was checking wrong bit for sign extension. It caused it to zero-extend instead of sign-extend the immediate value. 2021-03-25 Abid Qadeer <abidh@codesourcery.com> opcodes/ * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of immediate in br.n instruction. gas/ * testsuite/gas/nios2/brn.s: New. * testsuite/gas/nios2/brn.d: New.
2021-03-25 05:24:35 +08:00
2021-03-25 Abid Qadeer <abidh@codesourcery.com>
* testsuite/gas/nios2/brn.d: New.
* testsuite/gas/nios2/brn.d: New.
x86: fix CMPXCHG8B special case when disallowing q suffix outside of 64-bit mode In match_template() i.tm hasn't been filled yet, so it is necessarily t which needs checking. This is only a latent issue as no other templates with the same base_opcode have an extension_opcode of 1.
2021-03-25 15:20:55 +08:00
2021-03-25 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (match_template): Use t instead of i.tm.
x86: flag bad S/G insn operand combinations For VEX-encoded ones, all three involved vector registers have to be distinct. For EVEX-encoded ones an actual mask register has to be in use and zeroing-masking cannot be used (violation of either will #UD). Additionally both involved vector registers have to be distinct for EVEX-encoded gathers.
2021-03-25 15:20:19 +08:00
2021-03-25 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/avx512f-nondef.s: Add vgather cases.
* testsuite/gas/i386/x86-64-vgather-check.s: Add cases with
colliding registers in the upper half of the space.
* testsuite/gas/i386/avx512f-nondef.d,
testsuite/gas/i386/vgather-check.d,
testsuite/gas/i386/x86-64-vgather-check.d,
testsuite/gas/i386/x86-64-vgather-check-error.l,
testsuite/gas/i386/x86-64-vgather-check-warn.e: Adjust
expecations.
* testsuite/gas/i386/vgather-check-none.d,
testsuite/gas/i386/vgather-check-warn.d,
testsuite/gas/i386/x86-64-vgather-check-none.d,
testsuite/gas/i386/x86-64-vgather-check-warn.d: Refer to "base"
tests for expected dump output.
x86: flag as bad AVX512 insns with EVEX.z set but EVEX.aaa clear This combination makes no sense and is documented to cause #UD.
2021-03-25 15:19:21 +08:00
2021-03-25 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/avx512f-nondef.s: Add case for EVEX.z
without mask register.
* testsuite/gas/i386/avx512f-nondef.d: Adjust expectations.
x86: fix AMD Zen3 insns For INVLPGB the operand count was wrong (besides %edx there's also %ecx which is an input to the insn). In this case I see little sense in retaining the bogus 2-operand template. Plus swapping of the operands wasn't properly suppressed for Intel syntax. For PVALIDATE, RMPADJUST, and RMPUPDATE bogus single operand templates were specified. These get retained, as the address operand is the only one really needed to expressed non-default address size, but only for compatibility reasons. Proper multi-operand insn get introduced and the testcases get adjusted / extended accordingly. While at it also drop the redundant definition of __amd64__ - we already have x86_64 defined (or not) to distinguish 64-bit and non-64-bit cases.
2021-03-25 15:18:41 +08:00
2021-03-25 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (md_assemble): Widen set of insns to avoid
swapping operands for.
* testsuite/gas/i386/invlpgb.s: Fix, re-arrange, and add Intel
syntax tests.
* testsuite/gas/i386/snp.s: Re-arrange and add multi-operand as
well as Intel syntax tests.
* testsuite/gas/i386/invlpgb.d, testsuite/gas/i386/snp.d: Adjust
expectations.
Power10 bignum operands When built on a 32-bit host without --enable-64-bit-bfd, powerpc-linux and other 32-bit powerpc targeted binutils fail to assemble some power10 prefixed instructions with 34-bit fields. A typical error seen when running the testsuite is .../gas/testsuite/gas/ppc/prefix-pcrel.s:10: Error: bignum invalid In practice this doesn't matter for addresses: 32-bit programs don't need or use the top 2 bits of a d34 field when calculating addresses. However it may matter when loading or adding 64-bit constants with paddi. A power10 processor in 32-bit mode still has 64-bit wide GPRs. So this patch enables limited support for O_big PowerPC operands, and corrects sign extension of 32-bit constants using X_extrabit. * config/tc-ppc.c (insn_validate): Use uint64_t for operand values. (md_assemble): Likewise. Handle bignum operands. (ppc_elf_suffix): Handle O_big. Remove unnecessary input_line_pointer check. * expr.c: Delete unnecessary forward declarations. (generic_bignum_to_int32): Return uint32_t. (generic_bignum_to_int64): Return uint64_t. Compile always. (operand): Twiddle X_extrabit for unary '~'. Set X_unsigned and clear X_extrabit for unary '!'. * expr.h (generic_bignum_to_int32): Declare. (generic_bignum_to_int64): Declare. * testsuite/gas/ppc/prefix-pcrel.s, * testsuite/gas/ppc/prefix-pcrel.d: Add more instructions.
2021-04-12 07:32:46 +08:00
* testsuite/gas/i386/invlpgb64.d, testsuite/gas/i386/snp64.d:
x86: fix AMD Zen3 insns For INVLPGB the operand count was wrong (besides %edx there's also %ecx which is an input to the insn). In this case I see little sense in retaining the bogus 2-operand template. Plus swapping of the operands wasn't properly suppressed for Intel syntax. For PVALIDATE, RMPADJUST, and RMPUPDATE bogus single operand templates were specified. These get retained, as the address operand is the only one really needed to expressed non-default address size, but only for compatibility reasons. Proper multi-operand insn get introduced and the testcases get adjusted / extended accordingly. While at it also drop the redundant definition of __amd64__ - we already have x86_64 defined (or not) to distinguish 64-bit and non-64-bit cases.
2021-03-25 15:18:41 +08:00
Likewise. Drop passing --def-sym to as.
x86-64: limit breakage from gcc movdir64b et al workaround This is only a partial fix for PR/gas 27419, in that it limits the bad behavior of accepting mismatched operands to just x32 mode. The full fix would be to revert commits 27f134698ac5 and b3a3496f83a1, and to address the issue in gcc instead.
2021-03-25 15:17:45 +08:00
2021-03-25 Jan Beulich <jbeulich@suse.com>
PR/gas 27419
* config/tc-i386.c (process_suffix): Restrict (%rip) -> (%eip)
conversion to x32 mode.
* testsuite/gas/i386/ilp32/enqcmd.s,
testsuite/gas/i386/ilp32/enqcmd.d,
testsuite/gas/i386/ilp32/movdir.s,
testsuite/gas/i386/ilp32/movdir.d: New.
* testsuite/gas/i386/x86-64-enqcmd.s,
testsuite/gas/i386/x86-64-movdir.s: Drop mismatched operand
cases.
* testsuite/gas/i386/x86-64-enqcmd-inval.s: Add (%rip) and
(%eip) cases.
* testsuite/gas/i386/x86-64-movdir64b-reg.s Add (%eip) case.
* testsuite/gas/i386/x86-64-enqcmd.d,
testsuite/gas/i386/x86-64-enqcmd-intel.d,
testsuite/gas/i386/x86-64-enqcmd-inval.l,
testsuite/gas/i386/x86-64-movdir.d,
testsuite/gas/i386/x86-64-movdir-intel.d,
testsuite/gas/i386/x86-64-movdir64b-reg.l: Adjust expectations.
PR27647 PowerPC extended conditional branch mnemonics opcodes/ PR 27647 * ppc-opc.c (XLOCB_MASK): Delete. (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using XLBH_MASK. (powerpc_opcodes): Accept a BH field on all extended forms of bclr, bclrl, bcctr, bcctrl, bctar, bctarl. gas/ PR 27647 * testsuite/gas/ppc/a2.d: Update expected output. * testsuite/gas/ppc/power8.d: Likewise.
2021-03-25 08:59:34 +08:00
2021-03-25 Alan Modra <amodra@gmail.com>
PR 27647
* testsuite/gas/ppc/a2.d: Update expected output.
* testsuite/gas/ppc/power8.d: Likewise.
x86: derive opcode length from opcode value In the majority of cases we can easily determine the length from the encoding, irrespective of whether a prefix is specified there as well. We further don't even need to record the value in the table entries, as it's easy enough to determine it (without any guesswork, unless an insn with major opcode 00 appeared that requires a 2nd opcode byte to be specified explicitly) when installing the chosen template for further processing. Should an encoding appear which - has a major opcode byte of 66, F3, or F2, - requires a 2nd opcode byte to be specified explicitly, - doesn't have a mandatory prefix we'd need to convert all templates presently encoding a mandatory prefix this way to the Prefix_0X<nn> model to eliminate the respective guessing i386-gen does.
2021-03-24 15:33:33 +08:00
2021-03-24 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (struct _i386_insn): New field
opcode_length.
(md_begin): Drop assertion.
(install_template): New.
(build_vex_prefix): Call install_template.
(match_template): Likewise.
(process_operands): Use new opcode_length field.
(output_jump): Likewise.
(output_insn): Likewise. Adjust psedo prefix check.
x86: derive mandatory prefix attribute from base opcode Just like is already done for legacy encoded insns, record the mandatory prefix information in the respective opcode modifier field. Do this without changing the source table, but rather by deriving the values from their existing source representation.
2021-03-24 15:32:32 +08:00
2021-03-24 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (md_begin): Add assertion.
(build_vex_prefix): Drop implied prefix calculation.
(build_evex_prefix): Likewise.
(optimize_encoding): Adjust opcode checks.
(load_insn_p): Also check opcodeprefix.
(match_template): Also check opcodespace.
(process_suffix): Likewise.
(process_operands): Likewise.
(output_insn): Likewise. Also check isprefix when discaring
standalone LOCK.
* config/tc-i386-intel.c (i386_intel_operand): Also check
opcodespace.
x86: don't use opcode_length to identify pseudo prefixes This is in preparation of opcode_length going away as a field in the templates. Identify pseudo prefixes by a base opcode of zero instead: No real prefix has an opcode of zero. This at the same time allows dropping a curious special case from i386-gen. Since most attributes are identical for all pseudo prefixes, take the opportunity and also template them.
2021-03-24 15:31:41 +08:00
2021-03-24 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (parse_insn): Recognize pseudo prefixes by
base_opcode and extension_opcode.
x86: re-number PREFIX_0X<nn> In preparation to use PREFIX_0X<nn> attributes also in VEX/XOP/EVEX encoding templates, renumber the pseudo-enumerators such that their values can then also be used directly in the respective prefix bit fields.
2021-03-24 00:09:53 +08:00
2021-03-23 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (pte): Re-order opc_pfx[] entries.
x86: re-order two fields of struct insn_template To facilitate a subsequent table parser change, re-order CPU flags and opcode modifier fields. No functional change intended.
2021-03-24 00:09:11 +08:00
2021-03-23 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (output_i386_opcode): Invoke
process_i386_cpu_flag() slightly later.
(process_i386_opcodes): Likewise.
x86: split opcode prefix and opcode space representation Commit 8b65b8953af2 ("x86: Remove the prefix byte from non-VEX/EVEX base_opcode") used the opcodeprefix field for two distinct purposes. In preparation of having VEX/XOP/EVEX and non-VEX templates become similar in the representatioon of both encoding space and opcode prefixes, split the field to have a separate one holding an insn's opcode space.
2021-03-24 00:08:39 +08:00
2021-03-23 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (pte): Print prefix and encoding space.
(build_vex_prefix): Check opcodespace instead of opcodeprefix.
(build_evex_prefix): Likewise.
(load_insn_p): Likewise.
x86: don't open-code PREFIX_NONE Use the constant rather than literal zero. While at it fold two conditionals (using the same base opcode and prefix) in load_insn_p().
2021-03-23 15:44:35 +08:00
2021-03-23 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (load_insn_p): Use PREFIX_NONE. Fold two
if()-s.
(match_template, output_insn): Use PREFIX_NONE.
x86: unbreak certain MPX insn operand forms Commit 8b65b8953af2 ("x86: Remove the prefix byte from non-VEX/EVEX base_opcode") dropped the mandatory prefix bytes from legacy encoded insn templates, but failed to also adjust affected MPX-specific checks in two places. For the expressions to remain halfway readable, introduce local variables to hold current_templates->start.
2021-03-23 15:44:03 +08:00
2021-03-23 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (i386_index_check): New local variable t.
Correct MPX insn check.
* config/tc-i386-intel.c (i386_intel_simplify_register): Correct
MPX insn check.
* testsuite/gas/i386/x86-64-mpx.s: Add RIP-relative cases. Test
index scaling by other than 1.
* testsuite/gas/i386/x86-64-mpx.d: Adjust expectations.
Add startswith function and use it instead of CONST_STRNEQ. bfd/ChangeLog: * bfd-in.h (startswith): Add startswith function. (CONST_STRNEQ): Remove. * bfd-in2.h (startswith): Regenerate with make headers. * archive.c (bfd_slurp_armap): Replace usage of CONST_STRNEQ with startswith. (_bfd_slurp_extended_name_table): Likewise. * archive64.c (_bfd_archive_64_bit_slurp_armap): Likewise. * bfd.c (bfd_get_sign_extend_vma): Likewise. (bfd_convert_section_size): Likewise. (bfd_convert_section_contents): Likewise. * coff-stgo32.c (go32exe_create_stub): Likewise. (go32exe_check_format): Likewise. * coffcode.h (styp_to_sec_flags): Likewise. (GNU_DEBUGALTLINK): Likewise. * coffgen.c (_bfd_coff_section_already_linked): Likewise. (coff_gc_sweep): Likewise. (bfd_coff_gc_sections): Likewise. * cofflink.c (coff_link_add_symbols): Likewise. (process_embedded_commands): Likewise. * compress.c (bfd_is_section_compressed_with_header): Likewise. (bfd_init_section_decompress_status): Likewise. * dwarf2.c (find_debug_info): Likewise. (place_sections): Likewise. * ecoff.c (_bfd_ecoff_slurp_armap): Likewise. * elf-m10300.c (_bfd_mn10300_elf_size_dynamic_sections): Likewise. * elf.c (_bfd_elf_make_section_from_shdr): Likewise. (assign_section_numbers): Likewise. (elfcore_grok_win32pstatus): Likewise. * elf32-arm.c (cmse_scan): Likewise. (elf32_arm_gc_mark_extra_sections): Likewise. (elf32_arm_size_dynamic_sections): Likewise. (is_arm_elf_unwind_section_name): Likewise. * elf32-bfin.c (bfin_size_dynamic_sections): Likewise. * elf32-cr16.c (_bfd_cr16_elf_size_dynamic_sections): Likewise. * elf32-cris.c (elf_cris_size_dynamic_sections): Likewise. * elf32-csky.c (csky_elf_size_dynamic_sections): Likewise. * elf32-hppa.c (elf32_hppa_size_dynamic_sections): Likewise. * elf32-iq2000.c (iq2000_elf_check_relocs): Likewise. * elf32-lm32.c (lm32_elf_size_dynamic_sections): Likewise. * elf32-m32r.c (m32r_elf_size_dynamic_sections): Likewise. * elf32-m68k.c (elf_m68k_size_dynamic_sections): Likewise. * elf32-metag.c (elf_metag_size_dynamic_sections): Likewise. * elf32-msp430.c (msp430_elf_relax_delete_bytes): Likewise. * elf32-nios2.c (nios2_elf32_size_dynamic_sections): Likewise. * elf32-or1k.c (or1k_elf_size_dynamic_sections): Likewise. * elf32-ppc.c (ppc_elf_size_dynamic_sections): Likewise. * elf32-s390.c (elf_s390_size_dynamic_sections): Likewise. * elf32-score.c (s3_bfd_score_elf_size_dynamic_sections): Likewise. * elf32-score7.c (s7_bfd_score_elf_size_dynamic_sections): Likewise. * elf32-sh.c (sh_elf_size_dynamic_sections): Likewise. * elf32-tic6x.c (is_tic6x_elf_unwind_section_name): Likewise. (elf32_tic6x_size_dynamic_sections): Likewise. * elf32-vax.c (elf_vax_size_dynamic_sections): Likewise. * elf32-xtensa.c (elf_xtensa_size_dynamic_sections): Likewise. (xtensa_is_insntable_section): Likewise. (xtensa_is_littable_section): Likewise. (xtensa_is_proptable_section): Likewise. (xtensa_property_section_name): Likewise. (xtensa_callback_required_dependence): Likewise. * elf64-alpha.c (elf64_alpha_size_dynamic_sections): Likewise. * elf64-hppa.c (elf64_hppa_size_dynamic_sections): Likewise. * elf64-ia64-vms.c (is_unwind_section_name): Likewise. (get_reloc_section): Likewise. (elf64_ia64_size_dynamic_sections): Likewise. (elf64_ia64_object_p): Likewise. * elf64-mmix.c (mmix_elf_add_symbol_hook): Likewise. * elf64-ppc.c (ppc64_elf_size_dynamic_sections): Likewise. * elf64-s390.c (elf_s390_size_dynamic_sections): Likewise. * elflink.c (elf_link_add_object_symbols): Likewise. (_bfd_elf_gc_mark_extra_sections): Likewise. (bfd_elf_parse_eh_frame_entries): Likewise. (_bfd_elf_section_already_linked): Likewise. * elfnn-aarch64.c (elfNN_aarch64_size_dynamic_sections): Likewise. * elfnn-ia64.c (is_unwind_section_name): Likewise. (elfNN_ia64_size_dynamic_sections): Likewise. (elfNN_ia64_object_p): Likewise. * elfxx-mips.c (FN_STUB_P): Likewise. (CALL_STUB_P): Likewise. (CALL_FP_STUB_P): Likewise. (_bfd_mips_elf_section_from_shdr): Likewise. (_bfd_mips_elf_fake_sections): Likewise. (_bfd_mips_elf_size_dynamic_sections): Likewise. (_bfd_mips_final_write_processing): Likewise. (_bfd_mips_elf_final_link): Likewise. * elfxx-sparc.c (_bfd_sparc_elf_size_dynamic_sections): Likewise. * elfxx-x86.c (elf_i386_is_reloc_section): Likewise. (elf_x86_64_is_reloc_section): Likewise. * hpux-core.c (thread_section_p): Likewise. * libcoff.h (bfd_pei_p): Likewise. * linker.c (REAL): Likewise. (unwrap_hash_lookup): Likewise. (_bfd_generic_link_add_one_symbol): Likewise. * mmo.c (mmo_internal_write_section): Likewise. * osf-core.c (osf_core_core_file_p): Likewise. * pef.c (bfd_pef_print_symbol): Likewise. * pei-x86_64.c (pex64_print_all_pdata_sections): Likewise. * som.c (som_slurp_symbol_table): Likewise. (som_slurp_armap): Likewise. * wasm-module.c (wasm_compute_custom_section_file_position): Likewise. binutils/ChangeLog: * dlltool.c (scan_drectve_symbols): Replace usage of CONST_STRNEQ with startswith. * emul_aix.c (ar_emul_aix_parse_arg): Likewise. * objcopy.c (is_mergeable_note_section): Likewise. * objdump.c (dump_dwarf_section): Likewise. * prdbg.c (pr_method_type): Likewise. (pr_class_baseclass): Likewise. (tg_class_baseclass): Likewise. * readelf.c (process_lto_symbol_tables): Likewise. * stabs.c (ULLHIGH): Likewise. (parse_stab_argtypes): Likewise. (stab_demangle_function_name): Likewise. gas/ChangeLog: * config/tc-i386.c (md_parse_option): Replace usage of CONST_STRNEQ with startswith. (x86_64_section_word): Likewise. * config/tc-sparc.c (md_parse_option): Likewise. gdb/ChangeLog: * arm-tdep.c (show_disassembly_style_sfunc): Replace usage of CONST_STRNEQ with startswith. (_initialize_arm_tdep): Likewise. ld/ChangeLog: * emultempl/aix.em: Replace usage of CONST_STRNEQ with startswith. * emultempl/beos.em: Likewise. * emultempl/elf.em: Likewise. * emultempl/pe.em: Likewise. * emultempl/pep.em: Likewise. * emultempl/xtensaelf.em: Likewise. * ldctor.c (ctor_prio): Likewise. * ldelf.c (ldelf_try_needed): Likewise. (ldelf_parse_ld_so_conf): Likewise. (ldelf_after_open): Likewise. (output_rel_find): Likewise. (ldelf_place_orphan): Likewise. * ldfile.c (ldfile_add_library_path): Likewise. * ldlang.c (lang_add_input_file): Likewise. * ldmain.c (get_sysroot): Likewise. (get_emulation): Likewise. (add_archive_element): Likewise. * ldwrite.c (unsplittable_name): Likewise. (clone_section): Likewise. * lexsup.c (parse_args): Likewise. * pe-dll.c (is_import): Likewise. (pe_implied_import_dll): Likewise. opcodes/ChangeLog: * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith. * arc-dis.c (parse_option): Likewise. * arm-dis.c (parse_arm_disassembler_options): Likewise. * cris-dis.c (print_with_operands): Likewise. * h8300-dis.c (bfd_h8_disassemble): Likewise. * i386-dis.c (print_insn): Likewise. * ia64-gen.c (fetch_insn_class): Likewise. (parse_resource_users): Likewise. (in_iclass): Likewise. (lookup_specifier): Likewise. (insert_opcode_dependencies): Likewise. * mips-dis.c (parse_mips_ase_option): Likewise. (parse_mips_dis_option): Likewise. * s390-dis.c (disassemble_init_s390): Likewise. * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
2021-03-19 18:50:26 +08:00
2021-03-22 Martin Liska <mliska@suse.cz>
* config/tc-i386.c (md_parse_option): Replace usage of CONST_STRNEQ with startswith.
(x86_64_section_word): Likewise.
* config/tc-sparc.c (md_parse_option): Likewise.
gas/app.c don't throw away spaces before slash I don't know really why we should lose a space before a '/'. Possibly it would make sense if '/' started a comment, but otherwise no. * app.c (do_scrub_chars): Don't lose spaces before a slash.
2021-03-19 11:54:05 +08:00
2021-03-19 Alan Modra <amodra@gmail.com>
* app.c (do_scrub_chars): Don't lose spaces before a slash.
2021-03-18 Christian Groessler <chris@groessler.org> * config/tc-z8k.c (apply_fix): Handle 7-bit relocations correctly. Problem found by Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>.
2021-03-19 04:33:51 +08:00
2021-03-18 Christian Groessler <chris@groessler.org>
* config/tc-z8k.c (apply_fix): Handle 7-bit relocations correctly.
Problem found by Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>.
RISC-V : Support bitmanip-0.93 ZBA/ZBB/ZBC instructions bfd/ * elfxx-riscv.c (riscv_std_z_ext_strtab): Add zba, zbb and zbc. gas/ * config/tc-riscv.c (ext_version_table): Add b, zba, zbb and zbc. (riscv_multi_subset_supports): Add INSN_CLASS_ZB*. * testsuite/gas/riscv/b-ext-64.s: Bitmanip test case. * testsuite/gas/riscv/b-ext-64.d: Likewise. * testsuite/gas/riscv/b-ext.s: Likewise. * testsuite/gas/riscv/b-ext.d: Likewise. include/ * opcode/riscv-opc.h: Support zba, zbb and zbc extensions. * opcode/riscv.h (riscv_insn_class): Add INSN_CLASS_ZB*. opcodes/ * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
2021-02-24 13:26:29 +08:00
2021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
* config/tc-riscv.c (ext_version_table): Add b, zba, zbb and zbc.
(riscv_multi_subset_supports): Add INSN_CLASS_ZB*.
* testsuite/gas/riscv/b-ext-64.s: Bitmanip test case.
* testsuite/gas/riscv/b-ext-64.d: Likewise.
* testsuite/gas/riscv/b-ext.s: Likewise.
* testsuite/gas/riscv/b-ext.d: Likewise.
aarch64: Add few missing system registers This patch adds few missing system registers to GAS: LORC_EL1, LOREA_EL1, LORN_EL1, LORSA_EL1, ICC_CTLR_EL3, ICC_SRE_ELX, ICH_VTR_EL2. gas/ChangeLog: 2021-03-02 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * testsuite/gas/aarch64/illegal-sysreg-7.d: New test. * testsuite/gas/aarch64/illegal-sysreg-7.l: New test. * testsuite/gas/aarch64/illegal-sysreg-7.s: New test. * testsuite/gas/aarch64/sysreg-7.d: New test. * testsuite/gas/aarch64/sysreg-7.s: New test. opcodes/ChangeLog: 2021-03-02 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1, icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
2021-03-12 22:18:59 +08:00
2021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* testsuite/gas/aarch64/illegal-sysreg-7.d: New test.
* testsuite/gas/aarch64/illegal-sysreg-7.l: New test.
* testsuite/gas/aarch64/illegal-sysreg-7.s: New test.
* testsuite/gas/aarch64/sysreg-7.d: New test.
* testsuite/gas/aarch64/sysreg-7.s: New test.
aix: implement TLS relocation for gas and ld Add support for TLS in XCOFF. Amongst the things done by this commit: - Update XCOFF auxialiary header to match new version and allow TLS sections. - Add TLS sections (.tdata and .tbss) support in gas and ld. - Add support for the TLS relocations in gas and ld. Two different types BFD_RELOC are created for PPC and PPC64 as the size is a pointer, thus distinct in 32 or 64bit. The addresses given by ld to .tdata and .tbss is a bit special. In XCOFF, these addresses are actually offsets from the TLS pointer computed at runtime. AIX assembly and linker does the same. In top of that, the .tdata must be before .data (this is mandatory for AIX loader). Thus, the aix ld script is recomputing "." before .data to restore its original value. There might be a simpler way, but this one is working. Optimisation linked to TLS relocations aren't yet implemented. bfd/ * reloc.c (BFD_RELOC_PPC_TLS_LE, BFD_RELOC_PPC_TLS_IE, BFD_RELOC_PPC_TLS_M, BFD_RELOC_PPC_TLS_ML, BFD_RELOC_PPC64_TLS_GD, BFD_RELOC_PPC64_TLS_LD, BFD_RELOC_PPC64_TLS_LE, BFD_RELOC_PPC64_TLS_IE, BFD_RELOC_PPC64_TLS_M, BFD_RELOC_PPC64_TLS_ML): New relocations. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * coff-rs6000.c (xcoff_calculate_relocation): Call xcoff_reloc_type_tls for TLS relocations. (xcoff_howto_table): Implement TLS relocations. (_bfd_xcoff_reloc_type_lookup): Add cases TLS relocations. (xcoff_reloc_type_tls): New function. * coff64-rs6000.c (xcoff_calculate_relocation): Likewise. (xcoff_howto_table): Likewise. (_bfd_xcoff_reloc_type_lookup): Likewise. * coffcode.h (sec_to_styp_flags): Handle TLS sections. (styp_to_sec_flags): Likewise. (coff_compute_section_file_positions): Avoid file offset optimisation for .data when the previous section is .tdata. (coff_write_object_contents): Handle TLS sections. * coffswap.h (coff_swap_aouthdr_out): Add support for new fields in aouthdr. * libxcoff.h (xcoff_reloc_type_tls): Add prototype. * xcofflink.c (xcoff_link_add_symbols): Handle XMC_UL. (xcoff_need_ldrel_p): Add cases for TLS relocations. (xcoff_create_ldrel): Add l_symndx for TLS sections. gas/ * config/tc-ppc.c (ppc_xcoff_text_section, ppc_xcoff_data_section, (ppc_xcoff_bss_section, ppc_xcoff_tdata_section, (ppc_xcoff_tbss_section): New variables. (ppc_text_subsegment, ppc_text_csects, ppc_data_subgments, (ppc_data_csects): Removed. (ppc_xcoff_section_is_initialized, ppc_init_xcoff_section, ppc_xcoff_parse_cons): New functions. (md_being): Initialize XCOFF sections. (ppc_xcoff_suffix): Add support for TLS relocations (fixup_size, md_apply_fix): Add support for new BFD_RELOC. (ppc_change_csect): Handle XMC_TL, XMC_UL. Correctly, add XMC_BS to .bss section. Handle new XCOFF section variables. (ppc_comm): Likewise. (ppc_toc): Likewise. (ppc_symbol_new_hook): Likewise. (ppc_frob_symbol): Likewise. (ppc_fix_adjustable): Add tbss support. * config/tc-ppc.h (TC_PARSE_CONS_EXPRESSION): New define. (ppc_xcoff_parse_cons): Add prototype. (struct ppc_xcoff_section): New structure. ld/ * emultempl/aix.em: Ensure .tdata section is removed if empty, even with -r flag. * scripttempl/aix.sc: Handle TLS sections. * testsuite/ld-powerpc/aix52.exp: Add new tests. * testsuite/ld-powerpc/aix-tls-reloc-32.d: New test. * testsuite/ld-powerpc/aix-tls-reloc-64.d: New test. * testsuite/ld-powerpc/aix-tls-reloc.ex: New test. * testsuite/ld-powerpc/aix-tls-reloc.s: New test. * testsuite/ld-powerpc/aix-tls-section-32.d: New test. * testsuite/ld-powerpc/aix-tls-section-64.d: New test. * testsuite/ld-powerpc/aix-tls-section.ex: New test. * testsuite/ld-powerpc/aix-tls-section.s: New test. include/ * coff/internal.h (struct internal_aouthdr): Add new fields. * coff/rs6000.h (AOUTHDRÃ): Add new fields. * coff/rs6k64.h (struct external_filehdr): Likewise. * coff/xcoff.h (_TDATA), _TBSS): New defines (RS6K_AOUTHDR_TLS_LE, RS6K_AOUTHDR_RAS, RS6K_AOUTHDR_ALGNTDATA, RS6K_AOUTHDR_SHR_SYMTAB, RS6K_AOUTHDR_FORK_POLICY, RS6K_AOUTHDR_FORK_COR): New defines. (XMC_TU): Removed. (XMC_UL): New define.
2021-03-11 18:08:19 +08:00
2021-03-12 Clément Chigot <clement.chigot@atos.net>
* config/tc-ppc.c (ppc_xcoff_text_section, ppc_xcoff_data_section,
(ppc_xcoff_bss_section, ppc_xcoff_tdata_section,
(ppc_xcoff_tbss_section): New variables.
(ppc_text_subsegment, ppc_text_csects, ppc_data_subgments,
(ppc_data_csects): Removed.
(ppc_xcoff_section_is_initialized, ppc_init_xcoff_section,
ppc_xcoff_parse_cons): New functions.
(md_being): Initialize XCOFF sections.
(ppc_xcoff_suffix): Add support for TLS relocations
(fixup_size, md_apply_fix): Add support for new BFD_RELOC.
(ppc_change_csect): Handle XMC_TL, XMC_UL. Correctly, add XMC_BS
to .bss section. Handle new XCOFF section variables.
(ppc_comm): Likewise.
(ppc_toc): Likewise.
(ppc_symbol_new_hook): Likewise.
(ppc_frob_symbol): Likewise.
(ppc_fix_adjustable): Add tbss support.
* config/tc-ppc.h (TC_PARSE_CONS_EXPRESSION): New define.
(ppc_xcoff_parse_cons): Add prototype.
(struct ppc_xcoff_section): New structure.
aix: implement R_TOCU and R_TOCL relocations Implement support for largetoc on XCOFF. R_TOCU and R_TOCL are referenced by the new BFD defines: BFD_RELOC_PPC_TOC16_HI and BFD_RELOC_PPC_TOC16_LO. A new toc storage class is added XMC_TE. In order to correctly handle R_TOCU, the logic behind xcoff_reloc_type_toc is changed to compute the whole TOC offset instead of just the difference between the "link" offset and the "assembly" offset. In gas, add a function to transform addis format used by AIX "addis RT, D(RA)" into the ELF format "addis RT, RA, SI". bfd/ * reloc.c (BFD_RELOC_PPC_TOC16_HI, BFD_RELOC_PPC_TOC16_LO): New relocations. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * coff-rs6000.c (xcoff_calculate_relocation): Call xcoff_reloc_type_toc for R_TOCU and R_TOCL. (xcoff_howto_table): Remove src_mask for TOC relocations. Add R_TOCU and R_TOCL howtos. (_bfd_xcoff_reloc_type_lookup): Add cases for BFD_RELOC_PPC_TOC16_HI and BFD_RELOC_PPC_TOC16_LO. (xcoff_reloc_type_toc): Compute the whole offset. Implement R_TOCU and R_TOCL. * coff64-rs6000.c (xcoff64_calculate_relocation): Likewise. (xcoff64_howto_table): Likewise. (xcoff64_reloc_type_lookup): Likewise. gas/ * config/tc-ppc.c (ppc_xcoff_suffix): New function. (MAP, MAP32, MAP64): New macros for XCOFF. (ppc_xcoff_fixup_addis): New function. (ppc_is_toc_sym): Handle XMC_TE. (fixup_size): Add cases for BFD_RELOC_PPC_TOC16_HI and BFD_RELOC_PPC_TOC16_LO. (md_assemble): Call ppc_xcoff_fixup_addis for XCOFF. (ppc_change_csect): Handle XMC_TE. (ppc_tc): Enable .tc symbols to have only a XMC_TC or XMC_TE storage class. (ppc_symbol_new_hook): Handle XMC_TE. (ppc_frob_symbol): Likewise. (ppc_fix_adjustable): Likewise. (md_apply_fix): Handle BFD_RELOC_PPC_TOC16_HI and BFD_RELOC_PPC_TOC16_LO. ld/ * scripttempl/aix.sc: Add .te to .data section. * testsuite/ld-powerpc/aix52.exp: Add test structure for AIX7+. Add aix-largetoc-1 test. * testsuite/ld-powerpc/aix-largetoc-1-32.d: New test. * testsuite/ld-powerpc/aix-largetoc-1-64.d: New test. * testsuite/ld-powerpc/aix-largetoc-1.ex: New test. * testsuite/ld-powerpc/aix-largetoc-1.s: New test.
2021-03-11 18:08:19 +08:00
2021-03-12 Clément Chigot <clement.chigot@atos.net>
* config/tc-ppc.c (ppc_xcoff_suffix): New function.
(MAP, MAP32, MAP64): New macros for XCOFF.
(ppc_xcoff_fixup_addis): New function.
(ppc_is_toc_sym): Handle XMC_TE.
(fixup_size): Add cases for BFD_RELOC_PPC_TOC16_HI and
BFD_RELOC_PPC_TOC16_LO.
(md_assemble): Call ppc_xcoff_fixup_addis for XCOFF.
(ppc_change_csect): Handle XMC_TE.
(ppc_tc): Enable .tc symbols to have only a XMC_TC or XMC_TE
storage class.
(ppc_symbol_new_hook): Handle XMC_TE.
(ppc_frob_symbol): Likewise.
(ppc_fix_adjustable): Likewise.
(md_apply_fix): Handle BFD_RELOC_PPC_TOC16_HI and
BFD_RELOC_PPC_TOC16_LO.
x86/Intel: correct AVX512 S/G disassembly Commit 6ff00b5e12e7 ("x86/Intel: correct permitted operand sizes for AVX512 scatter/gather") brought the assembler side of AVX512 S/G insn handling in line with AVX2's, but the disassembler side was forgotten. This has the benefit of - allowing to fold a number of table entries, - rendering a few #define-s and enumerators unused.
2021-03-10 15:20:29 +08:00
2021-03-10 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/avx512f-intel.d,
testsuite/gas/i386/avx512f_vl-intel.d,
testsuite/gas/i386/avx512pf-intel.d,
testsuite/gas/i386/x86-64-avx512f-intel.d,
testsuite/gas/i386/x86-64-avx512f_vl-intel.d,
testsuite/gas/i386/x86-64-avx512pf-intel.d: Adjust expectations.
x86: correct decoding of nop/reserved space (0f18 ... 0x1f) All encodings not used in this range are (reserved) NOPs. Hence their decoding should be fully consistent. For this to work the PREFIX_IGNORED logic needs slightly extending, such that the attribute will also - have an effect when used inside prefix_table[], yet without always falling back to using slot 0, - cause prefixes marked as ignored while decoding through prefix_table[] to no longer be considered decoded, when encountered in a subsequent decoding step. In adjacent code also drop meaningless PREFIX_OPCODE.
2021-03-10 15:14:11 +08:00
2021-03-10 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/prefetch.d,
testsuite/gas/i386/prefetch-intel.d,
testsuite/gas/i386/x86-64-prefetch.d,
testsuite/gas/i386/x86-64-prefetch-intel.d: Adjust expectations.
* testsuite/gas/i386/nops-8.s, testsuite/gas/i386/nops-8.d: New.
* testsuite/gas/i386/i386.exp: Run new test.
x86: fold some prefix related attributes into a single one RepPrefixOk, HLEPrefixOk, and NoTrackPrefixOk can't be specified together, so can share an enum-like field. IsLockable can be inferred from HLE setting and hence only needs specifying when neither of them is present.
2021-03-09 15:54:32 +08:00
2021-03-09 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (check_hle): Replace HLEPrefix* by Prefix*.
(md_assemble): Replace use of repprefixok, islockable, and
notrackprefixok.
(i386_index_check): Replace use of repprefixok.
x86-64: make SYSEXIT handling similar to SYSRET's Despite SYSEXIT being an Intel-only insn in long mode, its behavior there is similar to SYSRET's: Depending on REX.W execution continues in either 64-bit or compatibility mode. Hence distinguishing by suffix is as necessary here as it is there.
2021-03-09 15:53:38 +08:00
2021-03-09 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/noreg64.s: Add sysexit.
* testsuite/gas/i386/x86-64-sysenter-amd.s: Split sysexit into
sysexitl and sysexitq.
* testsuite/gas/i386/noreg-intel64.l,
testsuite/gas/i386/noreg64-data16.d,
testsuite/gas/i386/noreg64-data16.e,
testsuite/gas/i386/noreg64-rex64.d,
testsuite/gas/i386/noreg64.d,
testsuite/gas/i386/noreg64.l,
testsuite/gas/i386/x86-64-sysenter-amd.d,
testsuite/gas/i386/x86-64-sysenter-amd.l,
testsuite/gas/i386/x86-64-sysenter-intel.d: Adjust expectations.
Correct an error message in the ARM assembler. PR 27411 * config/tc-arm.c (do_t_add_sub): Correct error message. * testsuite/gas/arm/pr27411.s: New test. * testsuite/gas/arm/pr27411.d: New test driver. * testsuite/gas/arm/pr27411.l: Expected error output for new test.
2021-02-27 00:37:30 +08:00
2021-02-26 Nick Clifton <nickc@redhat.com>
PR 27411
* config/tc-arm.c (do_t_add_sub): Correct error message.
* testsuite/gas/arm/pr27411.s: New test.
* testsuite/gas/arm/pr27411.d: New test driver.
* testsuite/gas/arm/pr27411.l: Expected error output for new test.
PR23691, gas .y files vs. automatic make dependencies A number of targets, bfin, rl78, rx, can show odd failures when bfd/reloc.c changes BFD_RELOC_* enum values, if recompiling over a build dir with existing objects. The problem is caused by bfin-parse.o and similar not being recompiled and so using stale BFD_RELOC_* values. This isn't fixed by making bfin-parse.c depend on bfd/reloc.c, which isn't necessary anyway. bfin-parse.o should have been recompiled due to bfd/bfd.h changing when extracted bfd/reloc.c BFD_RELOC_* values change, but that wasn't happening. The problem is that automake generates a makefile that loads gas/config/.deps/ dependency file for objects with corresponding sources mentioned in EXTRA_as_new_SOURCES. Unless we want to mess around generating explicit dependencies, I think that mean moving some object files to the build gas/config/. This patch does that, removing some hacks for m68k-parse.c that should no longer be necessary, and removes some rules that catered to old bison producing code that triggers compiler warnings. PR 23691 * Makefile.am (TARGET_CPU_CFILES): Split off config/xtensa-relax.c.. (TARGET_CPU_HFILES): ..and config/xtensa-relax.h.. (TARGET_EXTRA_FILES): ..to here. Add config/bfin-lex-wrapper.c, and use alongside TARGET_CPU_CFILES. (EXTRA_DIST): Update location of generated .c files. (config/m68k-parse.c): New rule replacing m68k-parse.c rule. (config/bfin-parse.c, config/rl78-parse.cm config/rx-parse.c), (config/bfin-lex.c, config/bfin-lex-wrapper.@OBJEXT@): Similarly. (itbl-lex-wrapper.@OBJEXT@): Simplify to just the needed dependencies. (itbl-parse.@OBJEXT@): Delete rule using NO_WERROR. (itbl-parse.c, itbl-parse.h): Tidy. * config/bfin-lex-wrapper.c: Include config/bfin-lex.c. * config/bfin-lex.l: Include config/bfin-parse.h. * configure.ac (extra_objects): Move object files corresponding to .y and .l files now in config/ to config/. * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate.
2021-02-23 19:24:25 +08:00
2021-02-24 Alan Modra <amodra@gmail.com>
PR 23691
* Makefile.am (TARGET_CPU_CFILES): Split off config/xtensa-relax.c..
(TARGET_CPU_HFILES): ..and config/xtensa-relax.h..
(TARGET_EXTRA_FILES): ..to here. Add config/bfin-lex-wrapper.c,
and use alongside TARGET_CPU_CFILES.
(EXTRA_DIST): Update location of generated .c files.
(config/m68k-parse.c): New rule replacing m68k-parse.c rule.
(config/bfin-parse.c, config/rl78-parse.cm config/rx-parse.c),
(config/bfin-lex.c, config/bfin-lex-wrapper.@OBJEXT@): Similarly.
(itbl-lex-wrapper.@OBJEXT@): Simplify to just the needed
dependencies.
(itbl-parse.@OBJEXT@): Delete rule using NO_WERROR.
(itbl-parse.c, itbl-parse.h): Tidy.
* config/bfin-lex-wrapper.c: Include config/bfin-lex.c.
* config/bfin-lex.l: Include config/bfin-parse.h.
* configure.ac (extra_objects): Move object files corresponding
to .y and .l files now in config/ to config/.
* Makefile.in: Regenerate.
* configure: Regenerate.
* po/POTFILES.in: Regenerate.
Fix compile time warnings when building riscv assembler. * config/tc-riscv.c (riscv_ip): Fix compile time warnings about misleading indentation.
2021-02-19 18:14:09 +08:00
2021-02-19 Nick Clifton <nickc@redhat.com>
* config/tc-riscv.c (riscv_ip): Fix compile time warnings about
misleading indentation.
RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn. * Renamed obsolete UJ/SB types and RVC types, also added CSS/CL(CS) types, [VALID/EXTRACT/ENCODE macros] BTYPE_IMM: Renamed from SBTYPE_IMM. JTYPE_IMM: Renamed from UJTYPE_IMM. CITYPE_IMM: Renamed from RVC_IMM. CITYPE_LUI_IMM: Renamed from RVC_LUI_IMM. CITYPE_ADDI16SP_IMM: Renamed from RVC_ADDI16SP_IMM. CITYPE_LWSP_IMM: Renamed from RVC_LWSP_IMM. CITYPE_LDSP_IMM: Renamed from RVC_LDSP_IMM. CIWTYPE_IMM: Renamed from RVC_UIMM8. CIWTYPE_ADDI4SPN_IMM: Renamed from RVC_ADDI4SPN_IMM. CSSTYPE_IMM: Added for .insn without special encoding. CSSTYPE_SWSP_IMM: Renamed from RVC_SWSP_IMM. CSSTYPE_SDSP_IMM: Renamed from RVC_SDSP_IMM. CLTYPE_IMM: Added for .insn without special encoding. CLTYPE_LW_IMM: Renamed from RVC_LW_IMM. CLTYPE_LD_IMM: Renamed from RVC_LD_IMM. RVC_SIMM3: Unused and removed. CBTYPE_IMM: Renamed from RVC_B_IMM. CJTYPE_IMM: Renamed from RVC_J_IMM. * Added new operands and removed the unused ones, C5: Unsigned CL(CS) immediate, added for .insn directive. C6: Unsigned CSS immediate, added for .insn directive. Ci: Unused and removed. C<: Unused and removed. bfd/ PR 27158 * elfnn-riscv.c (perform_relocation): Updated encoding macros. (_bfd_riscv_relax_call): Likewise. (_bfd_riscv_relax_lui): Likewise. * elfxx-riscv.c (howto_table): Likewise. gas/ PR 27158 * config/tc-riscv.c (riscv_ip): Updated encoding macros. (md_apply_fix): Likewise. (md_convert_frag_branch): Likewise. (validate_riscv_insn): Likewise. Also arranged operands, including added C5 and C6 operands, and removed unused Ci and C< operands. * doc/c-riscv.texi: Updated and added CSS/CL/CS types. * testsuite/gas/riscv/insn.d: Added CSS/CL/CS instructions. * testsuite/gas/riscv/insn.s: Likewise. gdb/ PR 27158 * riscv-tdep.c (decode_ci_type_insn): Updated encoding macros. (decode_j_type_insn): Likewise. (decode_cj_type_insn): Likewise. (decode_b_type_insn): Likewise. (decode): Likewise. include/ PR 27158 * opcode/riscv.h: Updated encoding macros. opcodes/ PR 27158 * riscv-dis.c (print_insn_args): Updated encoding macros. * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM. (match_c_addi16sp): Updated encoding macros. (match_c_lui): Likewise. (match_c_lui_with_hint): Likewise. (match_c_addi4spn): Likewise. (match_c_slli): Likewise. (match_slli_as_c_slli): Likewise. (match_c_slli64): Likewise. (match_srxi_as_c_srxi): Likewise. (riscv_insn_types): Added .insn css/cl/cs. sim/ PR 27158 * riscv/sim-main.c (execute_i): Updated encoding macros.
2021-01-26 18:02:38 +08:00
2021-02-19 Nelson Chu <nelson.chu@sifive.com>
PR 27158
* config/tc-riscv.c (riscv_ip): Updated encoding macros.
(md_apply_fix): Likewise.
(md_convert_frag_branch): Likewise.
(validate_riscv_insn): Likewise. Also arranged operands, including
added C5 and C6 operands, and removed unused Ci and C< operands.
* doc/c-riscv.texi: Updated and added CSS/CL/CS types.
* testsuite/gas/riscv/insn.d: Added CSS/CL/CS instructions.
* testsuite/gas/riscv/insn.s: Likewise.
RISC-V: Add bfd/cpu-riscv.h to support all spec versions controlling. Make the opcode/riscv-opc.c and include/opcode/riscv.h tidy, move the spec versions stuff to bfd/cpu-riscv.h. Also move the csr stuff and ext_version_table to gas/config/tc-riscv.c for internal use. To avoid too many repeated code, define general RISCV_GET_SPEC_NAME/SPEC_CLASS macros. Therefore, assembler/dis-assembler/linker/gdb can get all spec versions related stuff from cpu-riscv.h and cpu-riscv.c, since the stuff are defined there uniformly. bfd/ * Makefile.am: Added cpu-riscv.h. * Makefile.in: Regenerated. * po/SRC-POTFILES.in: Regenerated. * cpu-riscv.h: Added to support spec versions controlling. Also added extern arrays and functions for cpu-riscv.c. (enum riscv_spec_class): Define all spec classes here uniformly. (struct riscv_spec): Added for all specs. (RISCV_GET_SPEC_CLASS): Added to reduce repeated code. (RISCV_GET_SPEC_NAME): Likewise. (RISCV_GET_ISA_SPEC_CLASS): Added to get ISA spec class. (RISCV_GET_PRIV_SPEC_CLASS): Added to get privileged spec class. (RISCV_GET_PRIV_SPEC_NAME): Added to get privileged spec name. * cpu-riscv.c (struct priv_spec_t): Replaced with struct riscv_spec. (riscv_get_priv_spec_class): Replaced with RISCV_GET_PRIV_SPEC_CLASS. (riscv_get_priv_spec_name): Replaced with RISCV_GET_PRIV_SPEC_NAME. (riscv_priv_specs): Moved below. (riscv_get_priv_spec_class_from_numbers): Likewise, updated. (riscv_isa_specs): Moved from include/opcode/riscv.h. * elfnn-riscv.c: Included cpu-riscv.h. (riscv_merge_attributes): Initialize in_priv_spec and out_priv_spec. * elfxx-riscv.c: Included cpu-riscv.h and opcode/riscv.h. (RISCV_UNKNOWN_VERSION): Moved from include/opcode/riscv.h. * elfxx-riscv.h: Removed extern functions to cpu-riscv.h. gas/ * config/tc-riscv.c: Included cpu-riscv.h. (enum riscv_csr_clas): Moved from include/opcode/riscv.h. (struct riscv_csr_extra): Likewise. (struct riscv_ext_version): Likewise. (ext_version_table): Moved from opcodes/riscv-opc.c. (default_isa_spec): Updated type to riscv_spec_class. (default_priv_spec): Likewise. (riscv_set_default_isa_spec): Updated. (init_ext_version_hash): Likewise. (riscv_init_csr_hash): Likewise, also fixed indent. include/ * opcode/riscv.h: Moved stuff and make the file tidy. opcodes/ * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h. (default_priv_spec): Updated type to riscv_spec_class. (parse_riscv_dis_option): Updated. * riscv-opc.c: Moved stuff and make the file tidy.
2021-01-28 10:45:56 +08:00
2021-02-18 Nelson Chu <nelson.chu@sifive.com>
* config/tc-riscv.c: Included cpu-riscv.h.
(enum riscv_csr_clas): Moved from include/opcode/riscv.h.
(struct riscv_csr_extra): Likewise.
(struct riscv_ext_version): Likewise.
(ext_version_table): Moved from opcodes/riscv-opc.c.
(default_isa_spec): Updated type to riscv_spec_class.
(default_priv_spec): Likewise.
(riscv_set_default_isa_spec): Updated.
(init_ext_version_hash): Likewise.
(riscv_init_csr_hash): Likewise, also fixed indent.
h8300 complains about new section defined without attributes * testsuite/gas/elf/section28.d: xfail h8300.
2021-02-17 14:18:41 +08:00
2021-02-17 Alan Modra <amodra@gmail.com>
* testsuite/gas/elf/section28.d: xfail h8300.
gas: Allow SHF_GNU_RETAIN on all sections Since SHF_GNU_RETAIN is allowed on all sections, strip SHF_GNU_RETAIN when checking incorrect section attributes. PR gas/27412 * config/obj-elf.c (obj_elf_change_section): Strip SHF_GNU_RETAIN when checking incorrect section attributes. * testsuite/gas/elf/elf.exp: Run section28 and section29. * testsuite/gas/elf/section28.d: New file. * testsuite/gas/elf/section28.s: Likewise. * testsuite/gas/elf/section29.d: Likewise. * testsuite/gas/elf/section29.s: Likewise.
2021-02-16 20:55:42 +08:00
2021-02-16 H.J. Lu <hongjiu.lu@intel.com>
PR gas/27412
* config/obj-elf.c (obj_elf_change_section): Strip SHF_GNU_RETAIN
when checking incorrect section attributes.
* testsuite/gas/elf/elf.exp: Run section28 and section29.
* testsuite/gas/elf/section28.d: New file.
* testsuite/gas/elf/section28.s: Likewise.
* testsuite/gas/elf/section29.d: Likewise.
* testsuite/gas/elf/section29.s: Likewise.
x86: CVTPI2PD has special behavior CVTPI2PD with a memory operand, unlike CVTPI2PS, doesn't engage MMX logic. Therefore it - has a proper AVX equivalent (CVTDQ2PD) and hence can be subject to SSE2AVX translation and SSE checking, - should not record MMX use in the respective ELF note.
2021-02-16 18:34:25 +08:00
2021-02-16 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/sse-check.s,
testsuite/gas/i386/sse2avx.s,
testsuite/gas/i386/x86-64-sse2avx.s: Add CVTPI2PD cases.
* testsuite/gas/i386/sse-check-error.l,
testsuite/gas/i386/sse-check-warn.e,
testsuite/gas/i386/sse-check.d,
testsuite/gas/i386/sse2avx.d,
testsuite/gas/i386/x86-64-sse-check-error.l,
testsuite/gas/i386/x86-64-sse2avx.d: Adjust expecations.
* testsuite/gas/i386/property-cvtpi2pd.s,
testsuite/gas/i386/property-cvtpi2pd.d,
testsuite/gas/i386/property-cvtpi2ps.s,
testsuite/gas/i386/property-cvtpi2ps.d: New.
* testsuite/gas/i386/i386.exp: Run new tests.
x86: honor template rather than actual operands when updating i.xstate This undoes a change to md_assemble() that 32930e4edbc0 ("x86: Support GNU_PROPERTY_X86_ISA_1_V[234] marker") did without any explanation. This broke a CVTPI2PS property test that a subsequent test will add, and the updates to existing tests also demonstrate what was wrong: For example, AVX insns update the full YMM, even if a Vex128 variant is in use.
2021-02-16 18:33:04 +08:00
2021-02-16 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (md_assemble): Use template rather than
actuals when updating i.xstate.
* testsuite/gas/i386/property-4.d,
testsuite/gas/i386/property-5.d,
testsuite/gas/i386/property-12.d: Adjust expectations.
x86: record register use for SIMD insns without respective explicit operands VZERO{ALL,UPPER} modify YMM registers despite having no operands. While {,V}{LD,ST}MXCSR don't modify XMM registers, MXCSR and XMMn collectively form underlying machine state.
2021-02-16 18:32:18 +08:00
2021-02-16 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (output_insn): Handle ldmxcsr, stmxcsr,
vldmxcsr, vstmxcsr, vzeroall, and vzeroupper.
* testsuite/gas/i386/property-ldmxcsr.s,
testsuite/gas/i386/property-ldmxcsr.d,
testsuite/gas/i386/property-vldmxcsr.s,
testsuite/gas/i386/property-vldmxcsr.d,
testsuite/gas/i386/property-vzeroall.s,
testsuite/gas/i386/property-vzeroall.d: New.
* testsuite/gas/i386/i386.exp: Run new tests.
x86: make common property tests common There's no need to run the exact same test twice. Move the tests which don't differ between 32- and 64-bit to the "Common tests" section.
2021-02-16 18:30:49 +08:00
2021-02-16 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/i386.exp: Move bitness-independent property
tests to bitness independent section.
* testsuite/gas/i386/x86-64-property-2.d,
testsuite/gas/i386/x86-64-property-3.d,
testsuite/gas/i386/x86-64-property-4.d,
testsuite/gas/i386/x86-64-property-5.d,
testsuite/gas/i386/x86-64-property-6.d,
testsuite/gas/i386/x86-64-property-10.d,
testsuite/gas/i386/x86-64-property-11.d,
testsuite/gas/i386/x86-64-property-12.d,
testsuite/gas/i386/x86-64-property-13.d: Delete.
x86: make 16-bit ENQCMD test actually test ENQCMD
2021-02-16 18:26:58 +08:00
2021-02-16 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/enqcmd-16bit.s: Include enqcmd.s, not
movdir.s.
* testsuite/gas/i386/enqcmd-16bit.d: Adjust expectations.
PR27426, More bugs in dwarf2dbg.c PR 27426 * dwarf2dbg.c (allocate_filename_to_slot): Allocate the dirs array in another place.
2021-02-16 12:09:04 +08:00
2021-02-16 Alan Modra <amodra@gmail.com>
PR 27426
* dwarf2dbg.c (allocate_filename_to_slot): Allocate the dirs array
in another place.
demand_copy_C_string NUL check * read.c (demand_copy_C_string): Really check for embedded zeros.
2021-02-16 12:02:36 +08:00
2021-02-16 Alan Modra <amodra@gmail.com>
* read.c (demand_copy_C_string): Really check for embedded zeros.
IBM Z: Implement instruction set extensions opcodes/ * s390-mkopc.c (main): Accept arch14 as cpu string. * s390-opc.txt: Add new arch14 instructions. include/ * opcode/s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_ARCH14. gas/ * config/tc-s390.c (s390_parse_cpu): New entry for arch14. * doc/c-s390.texi: Document arch14 march option. * testsuite/gas/s390/s390.exp: Run the arch14 related tests. * testsuite/gas/s390/zarch-arch14.d: New test. * testsuite/gas/s390/zarch-arch14.s: New test.
2021-02-15 21:20:00 +08:00
2021-02-15 Andreas Krebbel <krebbel@linux.ibm.com>
* config/tc-s390.c (s390_parse_cpu): New entry for arch14.
* doc/c-s390.texi: Document arch14 march option.
* testsuite/gas/s390/s390.exp: Run the arch14 related tests.
* testsuite/gas/s390/zarch-arch14.d: New test.
* testsuite/gas/s390/zarch-arch14.s: New test.
Change the readelf and objdump programs so that they will automatically follow links to separate debug info files. * configure.ac (follow-debug-links): Add option to enable or disable the following of debug links by default. Set the default for the option to be 'follow'. * dwarf.c (do_follow_links): Initialise with DEFAULT_FOR_FOLLOW_LINKS. (dwarf_select_sections_by_names): Add no-follow-links option. (dwarf_select_sections_by_letter): Add 'N' option. * objdump.c (usage): Add conditional text describing the follow links option. (slurp_symtab): Ensure that there is a NULL entry at the end of the symbol table. (slurp_dynamic_symtab): Likewise. (dump_bfd): When extending the symbol table, ensure that there is still a NULL entry at the end. * readelf.c (usage): Add conditional text describing the follow links option. * doc/binutils.texi: Update documentation for objcopy and readelf. * doc/debug.options.texi: Update documentation of the follow-links option. * config.in: Regenerate. * configure: Regenerate. * testsuite/binutils-all/compress.exp: Add the -WN option to objdump command lines that are not expecting to follow links. * testsuite/binutils-all/readelf.exp: Add the --debug-dump=no-follow-links option to tests that are not expecting to follow debug links. gas * testsuite/gas/mach-o/sections-1.d: Stop automatic debug link following. * testsuite/gas/xgate/insns-dwarf2.d: Likewise. ld * testsuite/ld-elf/sec64k.exp: Stop readelf from automatically following debug links.
2021-02-12 22:52:22 +08:00
2021-02-12 Nick Clifton <nickc@redhat.com>
* testsuite/gas/mach-o/sections-1.d: Stop automatic debug link
Power10 bignum operands When built on a 32-bit host without --enable-64-bit-bfd, powerpc-linux and other 32-bit powerpc targeted binutils fail to assemble some power10 prefixed instructions with 34-bit fields. A typical error seen when running the testsuite is .../gas/testsuite/gas/ppc/prefix-pcrel.s:10: Error: bignum invalid In practice this doesn't matter for addresses: 32-bit programs don't need or use the top 2 bits of a d34 field when calculating addresses. However it may matter when loading or adding 64-bit constants with paddi. A power10 processor in 32-bit mode still has 64-bit wide GPRs. So this patch enables limited support for O_big PowerPC operands, and corrects sign extension of 32-bit constants using X_extrabit. * config/tc-ppc.c (insn_validate): Use uint64_t for operand values. (md_assemble): Likewise. Handle bignum operands. (ppc_elf_suffix): Handle O_big. Remove unnecessary input_line_pointer check. * expr.c: Delete unnecessary forward declarations. (generic_bignum_to_int32): Return uint32_t. (generic_bignum_to_int64): Return uint64_t. Compile always. (operand): Twiddle X_extrabit for unary '~'. Set X_unsigned and clear X_extrabit for unary '!'. * expr.h (generic_bignum_to_int32): Declare. (generic_bignum_to_int64): Declare. * testsuite/gas/ppc/prefix-pcrel.s, * testsuite/gas/ppc/prefix-pcrel.d: Add more instructions.
2021-04-12 07:32:46 +08:00
following.
Change the readelf and objdump programs so that they will automatically follow links to separate debug info files. * configure.ac (follow-debug-links): Add option to enable or disable the following of debug links by default. Set the default for the option to be 'follow'. * dwarf.c (do_follow_links): Initialise with DEFAULT_FOR_FOLLOW_LINKS. (dwarf_select_sections_by_names): Add no-follow-links option. (dwarf_select_sections_by_letter): Add 'N' option. * objdump.c (usage): Add conditional text describing the follow links option. (slurp_symtab): Ensure that there is a NULL entry at the end of the symbol table. (slurp_dynamic_symtab): Likewise. (dump_bfd): When extending the symbol table, ensure that there is still a NULL entry at the end. * readelf.c (usage): Add conditional text describing the follow links option. * doc/binutils.texi: Update documentation for objcopy and readelf. * doc/debug.options.texi: Update documentation of the follow-links option. * config.in: Regenerate. * configure: Regenerate. * testsuite/binutils-all/compress.exp: Add the -WN option to objdump command lines that are not expecting to follow links. * testsuite/binutils-all/readelf.exp: Add the --debug-dump=no-follow-links option to tests that are not expecting to follow debug links. gas * testsuite/gas/mach-o/sections-1.d: Stop automatic debug link following. * testsuite/gas/xgate/insns-dwarf2.d: Likewise. ld * testsuite/ld-elf/sec64k.exp: Stop readelf from automatically following debug links.
2021-02-12 22:52:22 +08:00
* testsuite/gas/xgate/insns-dwarf2.d: Likewise.
gas testsuite: adjust recently added tests for hppa Some hppa gas targets treat anything starting in the first column as a label, so directives can't start there. Also, binutils_assemble and run_dump_test cleverly edit test source to suit the hppa .comm directive which has a different syntax to most targets. The editing means we can't match source file names in dumps. Finally, hppa gas complains if instructions are emitted without a ".text" or similar directive. * testsuite/gas/all/pr27381.err: Don't match source file name. * testsuite/gas/all/pr27381.s: Don't start directive in first column. * testsuite/gas/all/pr27384.err: Don't match source file name. Adjust line number. * testsuite/gas/all/pr27384.s: Add ".text" directive. * testsuite/gas/elf/pr27355.err: Don't match source file name.
2021-02-12 09:11:16 +08:00
2021-02-12 Alan Modra <amodra@gmail.com>
* testsuite/gas/all/pr27381.err: Don't match source file name.
* testsuite/gas/all/pr27381.s: Don't start directive in first column.
* testsuite/gas/all/pr27384.err: Don't match source file name.
Adjust line number.
* testsuite/gas/all/pr27384.s: Add ".text" directive.
* testsuite/gas/elf/pr27355.err: Don't match source file name.
Re: Remove arm-symbianelf gas/ * NEWS: Mention arm-symbianelf removal. ld/ * NEWS: Mention arm-symbianelf removal.
2021-02-10 10:06:52 +08:00
2021-02-11 Alan Modra <amodra@gmail.com>
* NEWS: Mention arm-symbianelf removal.
Remove debugging code accidentally included with the fix for PR 27384 * listing.c (buffer_line): Remove debugging code accidentally included with the fix for PR 27384.
2021-02-10 17:56:33 +08:00
2021-02-10 Nick Clifton <nickc@redhat.com>
* listing.c (buffer_line): Remove debugging code accidentally
included with the fix for PR 27384.
Add a sanity check of files include by .incbin. PR 27381 * read.c (s_incbin): Check that the file to be included is a regular, non-directory file. * testsuite/gas/all/pr27381.s: New test source file. * testsuite/gas/all/pr27381.d: New test control file. * testsuite/gas/all/pr27381.err: Expected error output for the new test. * testsuite/gas/all/gas.exp: Run the new test.
2021-02-09 22:22:23 +08:00
2021-02-09 Nick Clifton <nickc@redhat.com>
PR 27381
* read.c (s_incbin): Check that the file to be included is a
regular, non-directory file.
* testsuite/gas/all/pr27381.s: New test source file.
* testsuite/gas/all/pr27381.d: New test control file.
* testsuite/gas/all/pr27381.err: Expected error output for the new test.
* testsuite/gas/all/gas.exp: Run the new test.
Remove arm-symbianelf * configure.ac: Delete arm*-*-symbianelf* entry. * configure: Regenerate. bfd/ * config.bfd (arm*-*-symbianelf*): Move from obsolete to removed. * configure.ac: Delete symbian entries. * elf-bfd.h (enum elf_target_os): Delete is_symbian. * elf32-arm.c: Remove symbian support. Formatting. * targets.c: Delete symbian entries. * configure: Regenerate. binutils/ * testsuite/lib/binutils-common.exp (supports_gnu_osabi): Remove symbianelf. gas/ * Makefile.am (TARG_ENV_HFILES): Remove config/te-symbian.h. * config/tc-arm.c (elf32_arm_target_format): Remove TE_SYMBIAN support. * config/te-symbian.h: Delete. * configure.tgt: Remove arm-*-symbianelf*. * testsuite/gas/arm/arch4t-eabi.d: Don't mention symbianelf in target selection. * testsuite/gas/arm/arch4t.d: Likewise. * testsuite/gas/arm/got_prel.d: Likewise. * testsuite/gas/arm/mapdir.d: Likewise. * testsuite/gas/arm/mapmisc.d: Likewise. * testsuite/gas/arm/mapsecs.d: Likewise. * testsuite/gas/arm/mapshort-eabi.d: Likewise. * testsuite/gas/arm/thumb-eabi.d: Likewise. * testsuite/gas/arm/thumb.d: Likewise. * testsuite/gas/arm/thumbrel.d: Likewise. * Makefile.in: Regenerate. * po/POTFILES.in: Regenerate. ld/ * Makefile.am (ALL_EMULATION_SOURCES): Remove earmsymbian.c. Don't include symbian dep file. * configure.tgt: Remove arm*-*-symbianelf* entry. * emulparams/armsymbian.sh: Delete. * ld.texi: Don't mention symbian. * scripttempl/armbpabi.sc: Delete. * testsuite/ld-arm/symbian-seg1.d: Delete. * testsuite/ld-arm/symbian-seg1.s: Delete. * testsuite/ld-arm/arm-elf.exp: Don't run symbian-seg1. * Makefile.in: Regenerate. * po/BLD-POTFILES.in: Regenerate.
2021-02-08 18:36:17 +08:00
2021-02-09 Alan Modra <amodra@gmail.com>
* Makefile.am (TARG_ENV_HFILES): Remove config/te-symbian.h.
* config/tc-arm.c (elf32_arm_target_format): Remove TE_SYMBIAN
support.
* config/te-symbian.h: Delete.
* configure.tgt: Remove arm-*-symbianelf*.
* testsuite/gas/arm/arch4t-eabi.d: Don't mention symbianelf in
target selection.
* testsuite/gas/arm/arch4t.d: Likewise.
* testsuite/gas/arm/got_prel.d: Likewise.
* testsuite/gas/arm/mapdir.d: Likewise.
* testsuite/gas/arm/mapmisc.d: Likewise.
* testsuite/gas/arm/mapsecs.d: Likewise.
* testsuite/gas/arm/mapshort-eabi.d: Likewise.
* testsuite/gas/arm/thumb-eabi.d: Likewise.
* testsuite/gas/arm/thumb.d: Likewise.
* testsuite/gas/arm/thumbrel.d: Likewise.
* Makefile.in: Regenerate.
* po/POTFILES.in: Regenerate.
Prevent a bad .Psize expression from triggering a memory access violation. PR 27384 * listing.c (listing_psize): Check the result of the width expression before assigning it to paper_width. * testsuite/gas/all/pr27384.s: New test source file. * testsuite/gas/all/pr27384.d: New test control file. * testsuite/gas/all/pr27384.err: Expected errors from new test. * testsuite/gas/all/gas.exp: Run the new test.
2021-02-09 20:53:32 +08:00
2021-02-09 Nick Clifton <nickc@redhat.com>
PR 27384
* listing.c (listing_psize): Check the result of the width
expression before assigning it to paper_width.
* testsuite/gas/all/pr27384.s: New test source file.
* testsuite/gas/all/pr27384.d: New test control file.
* testsuite/gas/all/pr27384.err: Expected errors from new test.
* testsuite/gas/all/gas.exp: Run the new test.
Add a test for PR 27355 - where corrupt assembler .file directives could trigger a segmentation fault. PR 27355 * testsuite/gas/elf/pr27355.s: New test source file. * testsuite/gas/elf/pr27355.d: New test control file. * testsuite/gas/elf/pr27355.err: Expected errors from new test. * testsuite/gas/elf/elf.exp: Run the new test.
2021-02-09 18:51:40 +08:00
2021-02-09 Nick Clifton <nickc@redhat.com>
PR 27355
* testsuite/gas/elf/pr27355.s: New test source file.
* testsuite/gas/elf/pr27355.d: New test control file.
* testsuite/gas/elf/pr27355.err: Expected errors from new test.
* testsuite/gas/elf/elf.exp: Run the new test.
opcodes: tic54x: namespace exported variables The tic54x exports some fairly generic variable names that can conflict with programs that use them, so put proper tic54x_ prefixes on all of them.
2021-01-16 14:00:45 +08:00
2021-02-08 Mike Frysinger <vapier@gentoo.org>
* config/tc-tic54x (tic54x_mmregs): Rename to ...
(tic54x_register_mmregs): ... this. Change mmregs to tic54x_mmregs.
(md_pseudo_table): Change tic54x_mmregs to tic54x_register_mmregs.
(md_begin): Add tic54x_ prefix to regs, mmregs, condition_codes,
cc2_codes, cc3_codes, status_bits, and misc_symbols.
Fix an illegal memory access when parsing a corrupt assembler file. PR 27355 * dwarf2dbg.c (allocate_filename_to_slot): Allocate the dirs array if it has not already been created.
2021-02-09 02:31:21 +08:00
2021-02-08 Nick Clifton <nickc@redhat.com>
PR 27355
* dwarf2dbg.c (allocate_filename_to_slot): Allocate the dirs array
if it has not already been created.
RISC-V: Removed the v0.93 bitmanip ZBA/ZBB/ZBC instructions. bfd/ * elfxx-riscv.c (riscv_parse_prefixed_ext): Removed zb*. gas/ * config/tc-riscv.c (riscv_multi_subset_supports): Removed INSN_CLASS_ZB*. * testsuite/gas/riscv/bitmanip-insns-32.d: Removed. * testsuite/gas/riscv/bitmanip-insns-64.d: Removed. * testsuite/gas/riscv/bitmanip-insns.s: Removed. include/ * opcode/riscv-opc.h: Removed macros for zb* extensions. * opcode/riscv.h (riscv_insn_class): Removed INSN_CLASS_ZB*. opcodes/ * riscv-opc.c (MASK_RVB_IMM): Removed. (riscv_opcodes): Removed zb* instructions. (riscv_ext_version_table): Removed versions for zb*.
2021-02-04 16:15:03 +08:00
2021-02-04 Nelson Chu <nelson.chu@sifive.com>
* config/tc-riscv.c (riscv_multi_subset_supports): Removed
INSN_CLASS_ZB*.
* testsuite/gas/riscv/bitmanip-insns-32.d: Removed.
* testsuite/gas/riscv/bitmanip-insns-64.d: Removed.
* testsuite/gas/riscv/bitmanip-insns.s: Removed.
IBM Z: Add missing vector formats to .insn docs gas/ * doc/c-s390.texi: Document vector instruction formats.
2021-02-03 19:01:12 +08:00
2021-02-03 Andreas Krebbel <krebbel@linux.ibm.com>
* doc/c-s390.texi: Document vector instruction formats.
Add Genode target support * configure.tgt: Add *-*-genode* as a target for AArch64 and x86.
2021-02-02 01:31:47 +08:00
2021-02-01 Emery Hemingway <ehmry@posteo.net>
* configure.tgt: Add *-*-genode* as a target for AArch64 and x86.
PR27283 gas for alpha fails to build with gcc 11 PR 27283 * config/tc-alpha.c (insert_operand): Delete dead code.
2021-01-31 09:32:54 +08:00
2021-02-01 Alan Modra <amodra@gmail.com>
PR 27283
* config/tc-alpha.c (insert_operand): Delete dead code.
nios2: Don't disable relaxation with --gdwarf-N GCC 11 passes --gdwarf-5 to assembler to enable DWARF5 debug info. Don't disable relaxation when --gdwarf-N is specified. The assembler generated debug information will treat the sequence of the relaxed instructions as a single instruction. PR gas/27243 * config/tc-nios2.c (md_begin): Don't disable relaxation with --gdwarf-N. * testsuite/gas/nios2/relax.d: New file. * testsuite/gas/nios2/relax.s: Likewise.
2021-01-27 00:18:39 +08:00
2021-01-26 H.J. Lu <hongjiu.lu@intel.com>
PR gas/27243
* config/tc-nios2.c (md_begin): Don't disable relaxation with
--gdwarf-N.
* testsuite/gas/nios2/relax.d: New file.
* testsuite/gas/nios2/relax.s: Likewise.
gas testsuite tidy This replaces skip and notarget in a number of gas tests with xfail, the idea being that running tests might expose segmentation faults or other serious errors even when we don't expect a test to pass. Doing so showed a number of cases where tests now pass, which is another reason to avoid profligate use of notarget and skip. * testsuite/gas/all/local-label-overflow.d: Use xfail rather than notarget all except hppa. Comment. * testsuite/gas/all/sleb128-2.d: Use xfail rather than notarget. * testsuite/gas/all/sleb128-4.d: Likewise. Don't skip msp430. * testsuite/gas/all/sleb128-5.d: Use xfail rather than notarget. * testsuite/gas/all/sleb128-7.d: Likewise. * testsuite/gas/all/sleb128-9.d: Likewise. * testsuite/gas/elf/bignums.d: Likewise. * testsuite/gas/elf/group0c.d: Likewise. * testsuite/gas/elf/group1a.d: Likewise. * testsuite/gas/elf/section-symbol-redef.d: Likewise. * testsuite/gas/elf/section15.d: Likewise. * testsuite/gas/elf/section4.d: Likewise. * testsuite/gas/elf/section7.d: Likewise. * testsuite/gas/macros/irp.d: Likewise. * testsuite/gas/macros/repeat.d: Likewise. * testsuite/gas/macros/rept.d: Likewise. * testsuite/gas/macros/test2.d: Likewise. * testsuite/gas/macros/vararg.d: Likewise. * testsuite/gas/all/string.d: Use xfail rather than skip. * testsuite/gas/elf/missing-build-notes.d: Likewise. * testsuite/gas/elf/section0.d: Likewise. * testsuite/gas/elf/section1.d: Likewise. * testsuite/gas/elf/section10.d: Likewise. * testsuite/gas/elf/section11.d: Likewise. * testsuite/gas/elf/section6.d: Likewise. * testsuite/gas/elf/symtab.d: Use xfail rather than skip, adjust hppa. * testsuite/gas/elf/symtab.s: Don't start directives in first column. * testsuite/gas/macros/test3.d: Don't notarget nds32.
2021-01-25 20:23:31 +08:00
2021-01-26 Alan Modra <amodra@gmail.com>
* testsuite/gas/all/local-label-overflow.d: Use xfail rather than
notarget all except hppa. Comment.
* testsuite/gas/all/sleb128-2.d: Use xfail rather than notarget.
* testsuite/gas/all/sleb128-4.d: Likewise. Don't skip msp430.
* testsuite/gas/all/sleb128-5.d: Use xfail rather than notarget.
* testsuite/gas/all/sleb128-7.d: Likewise.
* testsuite/gas/all/sleb128-9.d: Likewise.
* testsuite/gas/elf/bignums.d: Likewise.
* testsuite/gas/elf/group0c.d: Likewise.
* testsuite/gas/elf/group1a.d: Likewise.
* testsuite/gas/elf/section-symbol-redef.d: Likewise.
* testsuite/gas/elf/section15.d: Likewise.
* testsuite/gas/elf/section4.d: Likewise.
* testsuite/gas/elf/section7.d: Likewise.
* testsuite/gas/macros/irp.d: Likewise.
* testsuite/gas/macros/repeat.d: Likewise.
* testsuite/gas/macros/rept.d: Likewise.
* testsuite/gas/macros/test2.d: Likewise.
* testsuite/gas/macros/vararg.d: Likewise.
* testsuite/gas/all/string.d: Use xfail rather than skip.
* testsuite/gas/elf/missing-build-notes.d: Likewise.
* testsuite/gas/elf/section0.d: Likewise.
* testsuite/gas/elf/section1.d: Likewise.
* testsuite/gas/elf/section10.d: Likewise.
* testsuite/gas/elf/section11.d: Likewise.
* testsuite/gas/elf/section6.d: Likewise.
* testsuite/gas/elf/symtab.d: Use xfail rather than skip, adjust hppa.
* testsuite/gas/elf/symtab.s: Don't start directives in first column.
* testsuite/gas/macros/test3.d: Don't notarget nds32.
gas byte test skip *-*-* is a little silly, delete the test. * testsuite/gas/all/byte.d, * testsuite/gas/all/byte.l, * testsuite/gas/all/byte.s: Delete. * testsuite/gas/all/gas.exp: Don't run byte test.
2021-01-25 12:48:55 +08:00
2021-01-26 Alan Modra <amodra@gmail.com>
* testsuite/gas/all/byte.d,
* testsuite/gas/all/byte.l,
* testsuite/gas/all/byte.s: Delete.
* testsuite/gas/all/gas.exp: Don't run byte test.
pr27228 testcase This failed on ft32, hppa, and mips-irix targets. In the case of ft32 the problem was iterating over an array in reverse and not using the proper condition, so BFD_RELOC_NONE was not recognised. bfd/ * elf32-ft32.c (ft32_reloc_type_lookup): Don't miss ft32_reloc_map[0]. gas/ PR 27282 * testsuite/gas/all/none.d: Replace skip with xfail, don't xfail ft32. * testsuite/gas/elf/pr27228.d: xfail hppa and allow OBJECT match.
2021-01-25 12:47:15 +08:00
2021-01-26 Alan Modra <amodra@gmail.com>
PR 27282
* testsuite/gas/all/none.d: Replace skip with xfail, don't xfail ft32.
* testsuite/gas/elf/pr27228.d: xfail hppa and allow OBJECT match.
gas: Add a testcase for PR gas/27228 PR gas/27228 * testsuite/gas/elf/elf.exp: Run pr27228. * testsuite/gas/elf/pr27228.d: New file. * testsuite/gas/elf/pr27228.s: Likewise.
2021-01-24 20:14:30 +08:00
2021-01-24 H.J. Lu <hongjiu.lu@intel.com>
PR gas/27228
* testsuite/gas/elf/elf.exp: Run pr27228.
* testsuite/gas/elf/pr27228.d: New file.
* testsuite/gas/elf/pr27228.s: Likewise.
PR27228, .reloc wrong symbol emitted for undefined local symbol Local symbols are of course supposed to be defined by their object file, but in other cases a local symbol is promoted to global by gas if undefined and referenced. This patch stops gas wrongly replacing a local undefined symbol with the undefined section symbol, resulting in a .reloc undefined local symbol being emitted as global. PR 27228 * write.c (resolve_reloc_expr_symbols): Don't assume local symbol is defined.
2021-01-24 10:09:07 +08:00
2021-01-24 Alan Modra <amodra@gmail.com>
PR 27228
* write.c (resolve_reloc_expr_symbols): Don't assume local symbol
is defined.
PR27221, 058430b4a1 warnings while assembling the Linux kernel PR 27221 * dwarf2dbg.c (dwarf2_gen_line_info_1): Don't warn about ignored line number info when gas is generating it. * testsuite/gas/elf/dwarf2-20.d: Adjust to not expect warnings. * testsuite/gas/m68hc11/indexed12.d: Likewise. * testsuite/gas/elf/elf.exp: Don't run warn-2. * gas/testsuite/gas/elf/warn-2.s: Delete.
2021-01-21 14:20:02 +08:00
2021-01-21 Alan Modra <amodra@gmail.com>
PR 27221
* dwarf2dbg.c (dwarf2_gen_line_info_1): Don't warn about ignored
line number info when gas is generating it.
* testsuite/gas/elf/dwarf2-20.d: Adjust to not expect warnings.
* testsuite/gas/m68hc11/indexed12.d: Likewise.
* testsuite/gas/elf/elf.exp: Don't run warn-2.
* gas/testsuite/gas/elf/warn-2.s: Delete.
PR27218, memory access violation in dwarf2dbg.c PR 27218 * dwarf2dbg.c (dwarf2_gen_line_info): Correct setting of dwarf_level. (dwarf2_directive_filename, dwarf2_directive_loc): Likewise, and error for negative file numbers.
2021-01-21 14:16:20 +08:00
2021-01-21 Alan Modra <amodra@gmail.com>
PR 27218
* dwarf2dbg.c (dwarf2_gen_line_info): Correct setting of dwarf_level.
(dwarf2_directive_filename, dwarf2_directive_loc): Likewise, and
error for negative file numbers.
PowerPC: Don't generate unused section symbols PowerPC version of git commit d1bcae833b. bfd/ * elf32-ppc.c: Delete outdated comment. (TARGET_KEEP_UNUSED_SECTION_SYMBOLS): Define. * elf64-ppc.c (TARGET_KEEP_UNUSED_SECTION_SYMBOLS): Define. gas/ * testsuite/gas/ppc/power4.d: Adjust for removal of section sym. * testsuite/gas/ppc/test1elf32.d: Likewise. * testsuite/gas/ppc/test1elf64.d: Likewise. ld/ * testsuite/ld-powerpc/relbrlt.s: Make symbols global. * testsuite/ld-powerpc/relbrlt.d: Adjust to suit. * testsuite/ld-powerpc/tlsget.d: Adjust for reordered stubs. * testsuite/ld-powerpc/tlsget.wf: Likewise. * testsuite/ld-powerpc/tlsget2.d: Likewise. * testsuite/ld-powerpc/tlsget2.wf: Likewise. * testsuite/ld-powerpc/tlsexe.r: Adjust for removed section syms. * testsuite/ld-powerpc/tlsexe32.r: Likewise. * testsuite/ld-powerpc/tlsexe32no.r: Likewise. * testsuite/ld-powerpc/tlsexeno.r: Likewise. * testsuite/ld-powerpc/tlsexenors.r: Likewise. * testsuite/ld-powerpc/tlsexers.r: Likewise. * testsuite/ld-powerpc/tlsexetoc.r: Likewise. * testsuite/ld-powerpc/tlsexetocrs.r: Likewise. * testsuite/ld-powerpc/tlsso.r: Likewise. * testsuite/ld-powerpc/tlsso32.r: Likewise. * testsuite/ld-powerpc/tlstocso.r: Likewise.
2021-01-20 13:25:46 +08:00
2021-01-20 Alan Modra <amodra@gmail.com>
* testsuite/gas/ppc/power4.d: Adjust for removal of section sym.
* testsuite/gas/ppc/test1elf32.d: Likewise.
* testsuite/gas/ppc/test1elf64.d: Likewise.
as: Automatically enable DWARF5 support Currently $ as -o x.o x.s fails when x.s contains DWARF5 ".file 0" or ".loc 0" directives. Update assembler to automatically enable DWARF5 support so that $ gcc -S -g -c x.c $ gcc -c x.s works. PR gas/27195 * dwarf2dbg.c (dwarf2_gen_line_info): Set dwarf_level to 5 if needed. (dwarf2_directive_filename): Likewise. (dwarf2_directive_loc): Likewise. * testsuite/gas/elf/dwarf-5-file0.d: Pass --gdwarf-3. * testsuite/gas/lns/lns-diag-1.l: Remove the "Error: file number less than one" errors.
2021-01-18 22:25:05 +08:00
2021-01-18 H.J. Lu <hongjiu.lu@intel.com>
PR gas/27195
* dwarf2dbg.c (dwarf2_gen_line_info): Set dwarf_level to 5 if
needed.
(dwarf2_directive_filename): Likewise.
(dwarf2_directive_loc): Likewise.
* testsuite/gas/elf/dwarf-5-file0.d: Pass --gdwarf-3.
* testsuite/gas/lns/lns-diag-1.l: Remove the
"Error: file number less than one" errors.
PR27198, segv in S_IS_WEAK Fix a NULL dereference seen when assembling invalid input. PR 27198 * config/tc-i386.c (need_plt32_p): Return FALSE for NULL symbol. * testsuite/gas/i386/pr27198.d, * gas/testsuite/gas/i386/pr27198.err, * gas/testsuite/gas/i386/pr27198.s: New test. * gas/testsuite/gas/i386/i386.exp: Run it.
2021-01-18 07:08:22 +08:00
2021-01-18 Alan Modra <amodra@gmail.com>
PR 27198
* config/tc-i386.c (need_plt32_p): Return FALSE for NULL symbol.
* testsuite/gas/i386/pr27198.d,
* gas/testsuite/gas/i386/pr27198.err,
* gas/testsuite/gas/i386/pr27198.s: New test.
* gas/testsuite/gas/i386/i386.exp: Run it.
RISC-V: Indent and GNU coding standards tidy, also aligned the code. bfd/ * elfnn-riscv.c: Indent, labels and GNU coding standards tidy, also aligned the code. gas/ * config/tc-riscv.c: Indent and GNU coding standards tidy, also aligned the code. * config/tc-riscv.h: Likewise. include/ * opcode/riscv.h: Indent and GNU coding standards tidy, also aligned the code. opcodes/ * riscv-opc.c (riscv_gpr_names_abi): Aligned the code. (riscv_fpr_names_abi): Likewise. (riscv_opcodes): Likewise. (riscv_insn_types): Likewise.
2021-01-15 09:36:51 +08:00
2021-01-15 Nelson Chu <nelson.chu@sifive.com>
* config/tc-riscv.c: Indent and GNU coding standards tidy,
also aligned the code.
* config/tc-riscv.h: Likewise.
RISC-V: Error and warning messages tidy. Error and warning messages usually starting with lower case letter, and without the period at the end. Besides, add the prefixed "internel:" at the beginning of the messages when they are caused internally. Also fix indents and typos. bfd/ * elfnn-riscv.c (riscv_merge_attributes): Fix typos of messages. gas/ * config/tc-riscv.c: Error and warning messages tidy. * testsuite/gas/riscv/priv-reg-fail-fext.l: Updated. * testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-read-only-02.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise. ld/ * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-01.d: Updated. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-04.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-05.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-06.d: Likewise. opcodes/ * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
2021-01-13 16:52:14 +08:00
2021-01-15 Nelson Chu <nelson.chu@sifive.com>
* config/tc-riscv.c: Error and warning messages tidy.
* testsuite/gas/riscv/priv-reg-fail-fext.l: Updated.
* testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-read-only-02.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise.
RISC-V: Comments tidy and improvement. The GNU coding standards said the comments should be complete sentences and end with a period and two spaces. But sometimes it should be more cleaner when the comments only include a word or codes. Therefore, I made the following changes after referring to other target/generic codes, * Try to write sentences in comments, must end with a period and two spaces. * End with two spaces without a period for codes/instructions only. * End with one space without a period for a single word/variable only. Besids, also rewrite/remove some comments which are obsolete or too long, and fix indents for comments. bfd/ * elfnn-riscv.c: Comments tidy and improvement. * elfxx-riscv.c: Likewise. * elfxx-riscv.h: Likewise. gas/ * config/tc-riscv.c: Comments tidy and improvement. Also update comment "fallthru" to "Fall through" that end with a period and two spaces. include/ * elf/riscv.h: Comments tidy and improvement. * opcode/riscv-opc.h: Likewise. * opcode/riscv.h: Likewise. opcodes/ * riscv-dis.c: Comments tidy and improvement. * riscv-opc.c: Likewise.
2021-01-13 10:05:48 +08:00
2021-01-15 Nelson Chu <nelson.chu@sifive.com>
* config/tc-riscv.c: Comments tidy and improvement. Also update
comment "fallthru" to "Fall through" that end with a period and
two spaces.
gas: make [248]byte directives available everywhere These aren't specific to ELF at all, and seem generally useful. So pull them out of the ELF backend and into the common core.
2021-01-14 11:14:10 +08:00
2021-01-14 Mike Frysinger <vapier@gentoo.org>
* doc/as.texi: Delete @ifset ELF wrapping around [248]byte entries.
Delete warning that these are only available with ELF targets.
* obj-elf.c (elf_pseudo_table): Move 2byte/4byte/8byte entries ...
* read.c (potable): ... here.
gas: bfin: build lexer with -Werror The makefile has comments about old versions of bison/yacc generating warnings, but that doesn't apply to the lexer which comes from flex. As far as I can tell, the warnings in the Blackfin lexer can be fixed with defines that have been supported back through flex in 2002. So lets turn on -Werror for it and see if anyone notices. If they do, they can report their exact tool versions so we can record that here.
2021-01-14 14:03:54 +08:00
2021-01-14 Mike Frysinger <vapier@gentoo.org>
* Makefile.am (bfin-lex-wrapper.@OBJEXT@): Delete $(NO_WERROR).
* Makefile.in: Regenerated.
gas: bfin: fix build time warnings
2021-01-14 13:51:59 +08:00
2021-01-14 Mike Frysinger <vapier@gentoo.org>
* bfin-lex.l (YY_NO_INPUT, YY_NO_UNPUT): Define.
(parse_int): Mark char_bag const.
x86: Don't generate GOT_symbol for PLT relocations Don't generate the _GLOBAL_OFFSET_TABLE_ symbol for PLT relocations since it isn't needed. PR gas/27178 * config/tc-i386.c (lex_got::gotrel): Add need_GOT_symbol. Don't generate GOT_symbol for PLT relocations. * testsuite/gas/i386/i386.exp: Run PR gas/27178 tests. * testsuite/gas/i386/no-got.d: New file. * testsuite/gas/i386/no-got.s: Likewise. * testsuite/gas/i386/x86-64-no-got.d: Likewise. * testsuite/gas/i386/x86-64-no-got.s: Likewise.
2021-01-13 21:42:11 +08:00
2021-01-13 H.J. Lu <hongjiu.lu@intel.com>
PR gas/27178
* config/tc-i386.c (lex_got::gotrel): Add need_GOT_symbol.
Don't generate GOT_symbol for PLT relocations.
* testsuite/gas/i386/i386.exp: Run PR gas/27178 tests.
* testsuite/gas/i386/no-got.d: New file.
* testsuite/gas/i386/no-got.s: Likewise.
* testsuite/gas/i386/x86-64-no-got.d: Likewise.
* testsuite/gas/i386/x86-64-no-got.s: Likewise.
Regen Makefile.in for jobserver.m4 aclocal.m4 dependency bfd/ * Makefile.in: Regenerate. * doc/Makefile.in: Regenerate. binutils/ * Makefile.in: Regenerate. * doc/Makefile.in: Regenerate. gas/ * Makefile.in: Regenerate. * Makefile.in: Regenerate. gprof/ * Makefile.in: Regenerate. ld/ * Makefile.in: Regenerate. libctf/ * Makefile.in: Regenerate. opcodes/ * Makefile.in: Regenerate.
2021-01-13 16:43:23 +08:00
2021-01-13 Alan Modra <amodra@gmail.com>
* Makefile.in: Regenerate.
* Makefile.in: Regenerate.
Implement a workaround for GNU mak jobserver Compiling binutils using -flto=jobserver with GCC 11 leads to libtool: link: gcc -W -Wall -Wstrict-prototypes -Wmissing-prototypes -Wshadow -Wstack-usage=262144 -Wwrite-strings -I../../gas/../zlib -g -O2 -fprofile-generate -flto=jobserver -o as-new app.o as.o atof-generic.o compress-debug.o cond.o depend.o dwarf2dbg.o dw2gencfi.o ecoff.o ehopt.o expr.o flonum-copy.o flonum-konst.o flonum-mult.o frags.o hash.o input-file.o input-scrub.o listing.o literal.o macro.o messages.o output-file.o read.o remap.o sb.o stabs.o subsegs.o symbols.o write.o config/tc-i386.o config/obj-elf.o config/atof-ieee.o ../opcodes/.libs/libopcodes.a ../bfd/.libs/libbfd.a -L/tmp/binutils-gdb/objdir/zlib -lz ../libiberty/libiberty.a -ldl lto-wrapper: warning: jobserver is not available: '--jobserver-auth=' is not present in 'MAKEFLAGS' since the '+' is missing on the recipe line in Makefiles generated by automake. Add the '+' to the recipe line by hand. bfd/ PR binutils/26792 * configure.ac: Use GNU_MAKE_JOBSERVER. * aclocal.m4: Regenerated. * configure: Likewise. binutils/ PR binutils/26792 * configure.ac: Use GNU_MAKE_JOBSERVER. * aclocal.m4: Regenerated. * configure: Likewise. config/ PR binutils/26792 * jobserver.m4: New file. gas/ PR binutils/26792 * configure.ac: Use GNU_MAKE_JOBSERVER. * aclocal.m4: Regenerated. * configure: Likewise. gprof/ PR binutils/26792 * configure.ac: Use GNU_MAKE_JOBSERVER. * aclocal.m4: Regenerated. * configure: Likewise. ld/ PR binutils/26792 * configure.ac: Use GNU_MAKE_JOBSERVER. * aclocal.m4: Regenerated. * configure: Likewise. libctf/ PR binutils/26792 * configure.ac: Use GNU_MAKE_JOBSERVER. * aclocal.m4: Regenerated. * configure: Likewise. opcodes/ PR binutils/26792 * configure.ac: Use GNU_MAKE_JOBSERVER. * aclocal.m4: Regenerated. * configure: Likewise.
2021-01-12 21:45:28 +08:00
2021-01-12 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/26792
* configure.ac: Use GNU_MAKE_JOBSERVER.
* aclocal.m4: Regenerated.
* configure: Likewise.
Updated translations for some subdirectories
2021-01-12 21:18:50 +08:00
2021-01-12 Nick Clifton <nickc@redhat.com>
* po/fr.po: Updated French translation.
Binutils: Check if AR works with --plugin and rc Check if AR works with --plugin and rc before passing --plugin to AR and RANLIB. bfd/ PR ld/27173 binutils/ PR ld/27173 * configure: Regenerated. gas/ PR ld/27173 * configure: Regenerated. gprof/ PR ld/27173 * configure: Regenerated. ld/ PR ld/27173 * configure: Regenerated. libctf/ PR ld/27173 * configure: Regenerated. opcodes/ PR ld/27173 * configure: Regenerated.
2021-01-12 08:29:31 +08:00
2021-01-11 H.J. Lu <hongjiu.lu@intel.com>
PR ld/27173
* configure: Regenerated.
aarch64: Remove support for CSRE This patch removes support for the CSRE extension from aarch64 gas/objdump. CSRE (FEAT_CSRE) is part of the Future Architecture Technologies program and at this time Arm is withdrawing this particular feature. The patch removes the system registers and the CSR PDEC instruction. gas/ChangeLog * NEWS: Remove CSRE. * config/tc-aarch64.c (parse_csr_operand): Delete. (parse_operands): Delete handling of AARCH64_OPND_CSRE_CSR. (aarch64_features): Remove csre. * doc/c-aarch64.texi: Remove CSRE. * testsuite/gas/aarch64/csre.d: Delete. * testsuite/gas/aarch64/csre-invalid.s: Likewise. * testsuite/gas/aarch64/csre-invalid.d: Likewise. * testsuite/gas/aarch64/csre_csr.s: Likewise. * testsuite/gas/aarch64/csre_csr.d: Likewise. * testsuite/gas/aarch64/csre_csr-invalid.s: Likewise. * testsuite/gas/aarch64/csre_csr-invalid.l: Likewise. * testsuite/gas/aarch64/csre_csr-invalid.d: Likewise. include/ChangeLog * opcode/aarch64.h (AARCH64_FEATURE_CSRE): Delete. (aarch64_opnd): Delete AARCH64_OPND_CSRE_CSR. opcodes/ChangeLog * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. * aarch64-opc.c (aarch64_print_operand): Delete handling of AARCH64_OPND_CSRE_CSR. * aarch64-tbl.h (aarch64_feature_csre): Delete. (CSRE): Likewise. (_CSRE_INSN): Likewise. (aarch64_opcode_table): Delete csr.
2021-01-06 01:39:04 +08:00
2021-10-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* NEWS: Remove CSRE.
* config/tc-aarch64.c (parse_csr_operand): Delete.
(parse_operands): Delete handling of
AARCH64_OPND_CSRE_CSR.
(aarch64_features): Remove csre.
* doc/c-aarch64.texi: Remove CSRE.
* testsuite/gas/aarch64/csre.d: Delete.
* testsuite/gas/aarch64/csre-invalid.s: Likewise.
* testsuite/gas/aarch64/csre-invalid.d: Likewise.
* testsuite/gas/aarch64/csre_csr.s: Likewise.
* testsuite/gas/aarch64/csre_csr.d: Likewise.
* testsuite/gas/aarch64/csre_csr-invalid.s: Likewise.
* testsuite/gas/aarch64/csre_csr-invalid.l: Likewise.
* testsuite/gas/aarch64/csre_csr-invalid.d: Likewise.
Updated translations for multiple subdirectories
2021-01-11 20:55:33 +08:00
2021-01-11 Nick Clifton <nickc@redhat.com>
* po/uk.po: Updated Ukranian translation.
Binutils: Pass --plugin to AR and RANLIB Detect GCC LTO plugin. Pass --plugin to AR and RANLIB to support LTO build. bfd/ * configure: Regenerated. binutils/ * configure: Regenerated. gas/ * configure: Regenerated. gprof/ * configure: Regenerated. ld/ * configure: Regenerated. libctf/ * configure: Regenerated. opcodes/ * configure: Regenerated.
2021-01-09 22:47:58 +08:00
2021-01-09 H.J. Lu <hongjiu.lu@intel.com>
* configure: Regenerated.
Change version number to 2.36.50 and regenerate files
2021-01-09 19:01:01 +08:00
2021-01-09 Nick Clifton <nickc@redhat.com>
* configure: Regenerate.
* po/gas.pot: Regenerate.
Add Changelog entries and NEWS entries for 2.36 branch
2021-01-09 18:40:28 +08:00
2021-01-09 Nick Clifton <nickc@redhat.com>
* 2.36 release branch crated.
POWER10: Add Return-Oriented Programming instructions POWER10 adds some return-oriented programming (ROP) instructions and this patch adds support for them. You will notice that they are enabled for POWER8 and later, not just POWER10 and later. This is on purpose. This allows the instructions to be added to POWER8 binaries that can be run on POWER8, POWER9 and POWER10 cpus. On POWER8 and POWER9, these instructions just act as nop's. opcodes/ * ppc-opc.c (insert_dw, (extract_dw): New functions. (DW, (XRC_MASK): Define. (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics. gas/ * testsuite/gas/ppc/rop-checks.d, * testsuite/gas/ppc/rop-checks.l, * testsuite/gas/ppc/rop-checks.s, * testsuite/gas/ppc/rop.d, * testsuite/gas/ppc/rop.s: New tests. * testsuite/gas/ppc/ppc.exp: Run them.
2021-01-09 06:07:12 +08:00
2021-01-08 Peter Bergner <bergner@linux.ibm.com>
* testsuite/gas/ppc/rop-checks.d,
* testsuite/gas/ppc/rop-checks.l,
* testsuite/gas/ppc/rop-checks.s,
* testsuite/gas/ppc/rop.d,
* testsuite/gas/ppc/rop.s: New tests.
* testsuite/gas/ppc/ppc.exp: Run them.
configure regen commit f478212851 did the regen by hand, missed a change in ld/configure and didn't update line numbers. Fix that, and an old regen of ld/Makefile.in with the wrong automake. bfd/ * configure: Regenerate. binutils/ * configure: Regenerate. gas/ * configure: Regenerate. gprof/ * configure: Regenerate. ld/ * Makefile.in: Regenerate. * configure: Regenerate. libctf/ * configure: Regenerate. opcodes/ * configure: Regenerate. zlib/ * configure: Regenerate.
2021-01-09 08:33:29 +08:00
2021-01-09 Alan Modra <amodra@gmail.com>
* configure: Regenerate.
libtool.m4: update GNU/Hurd test from upstream. In upstream libtool, 47a889a4ca20 ("Improve GNU/Hurd support.") fixed detection of shlibpath_overrides_runpath, thus avoiding unnecessary relink. This backports it. . * libtool.m4: Match gnu* along other GNU systems. */ChangeLog: * configure: Re-generate.
2021-01-08 00:47:36 +08:00
2021-01-07 Samuel Thibault <samuel.thibault@gnu.org>
* configure: Regenerate.
ELF: Don't generate unused section symbols For ELF targets, section symbols are required only for relocations. With -ffunction-sections -fdata-sections, there can be many unused section symbols. Sizes of libstdc++.a on Linux/x86-64 in GCC 11 are With unused section symbols : 39411698 bytes Without unused section symbols: 39227002 bytes The unused section symbols in libstdc++.a occupy more than 180 KB. Add BSF_SECTION_SYM_USED to indicate if a section symbol should be included in the symbol table. The BSF_SECTION_SYM_USED should be set if the section symbol is used for relocation or the section symbol is always included in the symbol table. Add keep_unused_section_symbols to bfd_target to indicate if unused section symbols should be kept. If TARGET_KEEP_UNUSED_SECTION_SYMBOLS is defined as FALSE, unused ection symbols will be removed. Tested on Linux/x86. Other ELF backends need to: 1. Define TARGET_KEEP_UNUSED_SECTION_SYMBOLS to FALSE. 2. Mark used section symbols in assembler backend. 3. Remove unused section symbols from expected assembler and linker outputs. bfd/ PR 27109 * aix386-core.c (core_aix386_vec): Initialize keep_unused_section_symbol to TARGET_KEEP_UNUSED_SECTION_SYMBOLS. * aout-target.h (MY (vec)): Likewise. * binary.c (binary_vec): Likewise. * cisco-core.c (core_cisco_be_vec): Likewise. (core_cisco_le_vec): Likewise. * coff-alpha.c (alpha_ecoff_le_vec): Likewise. * coff-i386.c (TARGET_SYM): Likewise. (TARGET_SYM_BIG): Likewise. * coff-ia64.c (TARGET_SYM): Likewise. * coff-mips.c (mips_ecoff_le_vec): Likewise. (mips_ecoff_be_vec): Likewise. (mips_ecoff_bele_vec): Likewise. * coff-rs6000.c (rs6000_xcoff_vec): Likewise. (powerpc_xcoff_vec): Likewise. * coff-sh.c (sh_coff_small_vec): Likewise. (sh_coff_small_le_vec): Likewise. * coff-tic30.c (tic30_coff_vec): Likewise. * coff-tic54x.c (tic54x_coff0_vec): Likewise. (tic54x_coff0_beh_vec): Likewise. (tic54x_coff1_vec): Likewise. (tic54x_coff1_beh_vec): Likewise. (tic54x_coff2_vec): Likewise. (tic54x_coff2_beh_vec): Likewise. * coff-x86_64.c (TARGET_SYM): Likewise. (TARGET_SYM_BIG): Likewise. * coff64-rs6000.c (rs6000_xcoff64_vec): Likewise. (rs6000_xcoff64_aix_vec): Likewise. * coffcode.h (CREATE_BIG_COFF_TARGET_VEC): Likewise. (CREATE_BIGHDR_COFF_TARGET_VEC): Likewise. (CREATE_LITTLE_COFF_TARGET_VEC): Likewise. * elfxx-target.h (TARGET_BIG_SYM): Likewise. (TARGET_LITTLE_SYM): Likewise. * hppabsd-core.c (core_hppabsd_vec): Likewise. * hpux-core.c (core_hpux_vec): Likewise. * i386msdos.c (i386_msdos_vec): Likewise. * ihex.c (ihex_vec): Likewise. * irix-core.c (core_irix_vec): Likewise. * mach-o-target.c (TARGET_NAME): Likewise. * mmo.c (mmix_mmo_vec): Likewise. * netbsd-core.c (core_netbsd_vec): Likewise. * osf-core.c (core_osf_vec): Likewise. * pdp11.c (MY (vec)): Likewise. * pef.c (pef_vec): Likewise. (pef_xlib_vec): Likewise. * plugin.c (plugin_vec): Likewise. * ppcboot.c (powerpc_boot_vec): Likewise. * ptrace-core.c (core_ptrace_vec): Likewise. * sco5-core.c (core_sco5_vec): Likewise. * som.c (hppa_som_vec): Likewise. * srec.c (srec_vec): Likewise. (symbolsrec_vec): Likewise. * tekhex.c (tekhex_vec): Likewise. * trad-core.c (core_trad_vec): Likewise. * verilog.c (verilog_vec): Likewise. * vms-alpha.c (alpha_vms_vec): Likewise. * vms-lib.c (alpha_vms_lib_txt_vec): Likewise. * wasm-module.c (wasm_vec): Likewise. * xsym.c (sym_vec): Likewise. * elf.c (ignore_section_sym): Return TRUE if BSF_SECTION_SYM_USED isn't set. (elf_map_symbols): Don't include ignored section symbols. * elfcode.h (elf_slurp_symbol_table): Also set BSF_SECTION_SYM_USED on STT_SECTION symbols. * elflink.c (bfd_elf_final_link): Generated section symbols only when emitting relocations or reqired. * elfxx-x86.h (TARGET_KEEP_UNUSED_SECTION_SYMBOLS): New. * syms.c (BSF_SECTION_SYM_USED): New. * targets.c (TARGET_KEEP_UNUSED_SECTION_SYMBOLS): New. (bfd_target): Add keep_unused_section_symbols. (bfd_keep_unused_section_symbols): New. * bfd-in2.h: Regenerated. binutils/ PR 27109 * objcopy.c (copy_object): Handle section symbols for non-relocatable inputs. * testsuite/binutils-all/readelf.exp (readelf_test): Check is_elf_unused_section_symbols. * testsuite/binutils-all/readelf.s-64: Updated. * testsuite/binutils-all/readelf.ss: Likewise. * testsuite/binutils-all/readelf.ss-64: Likewise. * testsuite/binutils-all/readelf.s-64-unused: New file. * testsuite/binutils-all/readelf.ss-64-unused: Likewise. * testsuite/binutils-all/readelf.ss-unused: Likewise. * testsuite/lib/binutils-common.exp (is_elf_unused_section_symbols): New proc. gas/ChangeLog: PR 27109 * read.c (s_reloc): Call symbol_mark_used_in_reloc on the section symbol. * subsegs.c (subseg_set_rest): Set BSF_SECTION_SYM_USED if needed. * write.c (adjust_reloc_syms): Call symbol_mark_used_in_reloc on the section symbol. (set_symtab): Don't generate unused section symbols. (maybe_generate_build_notes): Call symbol_mark_used_in_reloc on the section symbol. * config/obj-elf.c (elf_adjust_symtab): Call symbol_mark_used_in_reloc on the group signature symbol. * testsuite/gas/cfi/cfi-label.d: Remove unused section symbols from expected output. * testsuite/gas/elf/elf.exp (run_elf_list_test): Check is_elf_unused_section_symbols. * testsuite/gas/elf/section2.e: Updated. * testsuite/gas/elf/section2.e-unused: New file. * testsuite/gas/elf/symver.d: Remove unused section symbols. * testsuite/gas/i386/ilp32/elf/symver.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-size-1.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-size-3.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-size-5.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-unwind.d: Likewise. * testsuite/gas/i386/size-1.d: Likewise. * testsuite/gas/i386/size-3.d: Likewise. * testsuite/gas/i386/svr4.d: Likewise. * testsuite/gas/i386/x86-64-size-1.d: Likewise. * testsuite/gas/i386/x86-64-size-3.d: Likewise. * testsuite/gas/i386/x86-64-size-5.d: Likewise. * testsuite/gas/i386/x86-64-unwind.d: Likewise. ld/ PR 27109 * testsuite/ld-elf/export-class.sd: Adjust the expected output. * testsuite/ld-elf/loadaddr3b.d: Likewise. * testsuite/ld-i386/ibt-plt-1.d: Likewise. * testsuite/ld-i386/ibt-plt-2a.d: Likewise. * testsuite/ld-i386/ibt-plt-2c.d: Likewise. * testsuite/ld-i386/ibt-plt-3a.d: Likewise. * testsuite/ld-i386/ibt-plt-3c.d: Likewise. * testsuite/ld-i386/pr19636-1d.d: Likewise. * testsuite/ld-i386/pr19636-1l.d: Likewise. * testsuite/ld-i386/pr19636-2c.d: Likewise. * testsuite/ld-ifunc/ifunc-2-i386-now.d: Likewise. * testsuite/ld-ifunc/ifunc-2-local-i386-now.d: Likewise. * testsuite/ld-ifunc/ifunc-2-local-x86-64-now.d: Likewise. * testsuite/ld-ifunc/ifunc-2-x86-64-now.d: Likewise. * testsuite/ld-ifunc/ifunc-21-x86-64.d: Likewise. * testsuite/ld-ifunc/ifunc-22-x86-64.d: Likewise. * testsuite/ld-ifunc/pr17154-i386-now.d: Likewise. * testsuite/ld-ifunc/pr17154-i386.d: Likewise. * testsuite/ld-ifunc/pr17154-x86-64-now.d: Likewise. * testsuite/ld-ifunc/pr17154-x86-64.d: Likewise. * testsuite/ld-x86-64/bnd-branch-1-now.d: Likewise. * testsuite/ld-x86-64/bnd-ifunc-1-now.d: Likewise. * testsuite/ld-x86-64/bnd-ifunc-2-now.d: Likewise. * testsuite/ld-x86-64/bnd-ifunc-2.d: Likewise. * testsuite/ld-x86-64/bnd-plt-1-now.d: Likewise. * testsuite/ld-x86-64/bnd-plt-1.d: Likewise. * testsuite/ld-x86-64/ibt-plt-1-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-1.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2a-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2a.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2c-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-2c.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3a-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3a.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3c-x32.d: Likewise. * testsuite/ld-x86-64/ibt-plt-3c.d: Likewise. * testsuite/ld-x86-64/pr19609-4e.d: Likewise. * testsuite/ld-x86-64/pr19609-6a.d: Likewise. * testsuite/ld-x86-64/pr19609-6b.d: Likewise. * testsuite/ld-x86-64/pr19609-7b.d: Likewise. * testsuite/ld-x86-64/pr19609-7d.d: Likewise. * testsuite/ld-x86-64/pr19636-2l.d: Likewise. * testsuite/ld-x86-64/pr20253-1d.d: Likewise. * testsuite/ld-x86-64/pr20253-1h.d: Likewise. * testsuite/ld-x86-64/pr21038b-now.d: Likewise. * testsuite/ld-x86-64/pr21038b.d: Likewise. * testsuite/ld-x86-64/pr21038c-now.d: Likewise. * testsuite/ld-x86-64/pr21038c.d: Likewise. * testsuite/ld-x86-64/pr23854.d: Likewise. * testsuite/ld-x86-64/pr25416-3.d: Likewise. * testsuite/ld-x86-64/pr25416-4.d: Likewise. * testsuite/ld-i386/plt-pic.pd: Likewise. * testsuite/ld-i386/plt-pic2.dd: Likewise. * testsuite/ld-i386/plt.pd: Likewise. * testsuite/ld-i386/plt2.dd: Likewise. * testsuite/ld-i386/tlsbin.rd: Likewise. * testsuite/ld-i386/tlsbin2.rd: Likewise. * testsuite/ld-i386/tlsbindesc.rd: Likewise. * testsuite/ld-i386/tlsdesc.rd: Likewise. * testsuite/ld-i386/tlsgdesc.rd: Likewise. * testsuite/ld-i386/tlsnopic.rd: Likewise. * testsuite/ld-i386/tlspic.rd: Likewise. * testsuite/ld-i386/tlspic2.rd: Likewise. * testsuite/ld-x86-64/mpx3.dd: Likewise. * testsuite/ld-x86-64/mpx3n.dd: Likewise. * testsuite/ld-x86-64/mpx4.dd: Likewise. * testsuite/ld-x86-64/mpx4n.dd: Likewise. * testsuite/ld-x86-64/pe-x86-64-1.od: Likewise. * testsuite/ld-x86-64/pe-x86-64-2.od: Likewise. * testsuite/ld-x86-64/pe-x86-64-3.od: Likewise. * testsuite/ld-x86-64/pe-x86-64-4.od: Likewise. * testsuite/ld-x86-64/plt.pd: Likewise. * testsuite/ld-x86-64/plt2.dd: Likewise. * testsuite/ld-x86-64/tlsbin.rd: Likewise. * testsuite/ld-x86-64/tlsbin2.rd: Likewise. * testsuite/ld-x86-64/tlsbindesc.rd: Likewise. * testsuite/ld-x86-64/tlsdesc.rd: Likewise. * testsuite/ld-x86-64/tlsgdesc.rd: Likewise. * testsuite/ld-x86-64/tlspic.rd: Likewise. * testsuite/ld-x86-64/tlspic2.rd: Likewise. * testsuite/ld-elf/sec64k.exp: Check is_elf_unused_section_symbols.
2021-01-07 22:42:00 +08:00
2021-01-07 H.J. Lu <hongjiu.lu@intel.com>
PR 27109
* read.c (s_reloc): Call symbol_mark_used_in_reloc on the
section symbol.
* subsegs.c (subseg_set_rest): Set BSF_SECTION_SYM_USED if needed.
* write.c (adjust_reloc_syms): Call symbol_mark_used_in_reloc
on the section symbol.
(set_symtab): Don't generate unused section symbols.
(maybe_generate_build_notes): Call symbol_mark_used_in_reloc
on the section symbol.
* config/obj-elf.c (elf_adjust_symtab): Call
symbol_mark_used_in_reloc on the group signature symbol.
* testsuite/gas/cfi/cfi-label.d: Remove unused section symbols
from expected output.
* testsuite/gas/elf/elf.exp (run_elf_list_test): Check
is_elf_unused_section_symbols.
* testsuite/gas/elf/section2.e: Updated.
* testsuite/gas/elf/section2.e-unused: New file.
* testsuite/gas/elf/symver.d: Remove unused section symbols.
* testsuite/gas/i386/ilp32/elf/symver.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-size-1.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-size-3.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-size-5.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-unwind.d: Likewise.
* testsuite/gas/i386/size-1.d: Likewise.
* testsuite/gas/i386/size-3.d: Likewise.
* testsuite/gas/i386/svr4.d: Likewise.
* testsuite/gas/i386/x86-64-size-1.d: Likewise.
* testsuite/gas/i386/x86-64-size-3.d: Likewise.
* testsuite/gas/i386/x86-64-size-5.d: Likewise.
* testsuite/gas/i386/x86-64-unwind.d: Likewise.
RISC-V: Add pause hint instruction. Add support for the pause hint instruction, as specified in the Zihintpause extension. The pause instruction is encoded as a special form of a memory fence (which is available as part of the base instruction set). The chosen encoding does not mandate any particular memory ordering and therefore is a true hint. bfd/ * elfxx-riscv.c (riscv_std_z_ext_strtab): Added zihintpause. gas/ * config/tc-riscv.c (riscv_multi_subset_supports): Added INSN_CLASS_ZIHINTPAUSE. * testsuite/gas/riscv/pause.d: New testcase. Adding coverage for the pause hint instruction. * testsuite/gas/riscv/pause.s: Likewise. include/ * opcode/riscv-opc.h: Added MATCH_PAUSE, MASK_PAUSE and DECLARE_INSN for pause hint instruction. * opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_ZIHINTPAUSE. opcodes/ * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
2021-01-07 15:53:25 +08:00
2021-01-07 Philipp Tomsich <prt@gnu.org>
* config/tc-riscv.c (riscv_multi_subset_supports): Added
INSN_CLASS_ZIHINTPAUSE.
* testsuite/gas/riscv/pause.d: New testcase. Adding coverage for
the pause hint instruction.
* testsuite/gas/riscv/pause.s: Likewise.
RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93). In fact rev8/orc.b/zext.h are the aliases of grevi/gorci/pack[w], so we should update them to INSN_ALIAS when we have supported their true instruction in the future. Though we still use the [MATCH|MAKS]_[GREVI|GORCI|PACK|PACKW] to encode them. Besides, the orc.b has the same encoding both in rv32 and rv64, so we just keep one of them in the opcode table. This patch is implemented according to the following link, https://github.com/riscv/riscv-bitmanip/pull/101 2021-01-07 Claire Xenia Wolf <claire@symbioticeda.com> Jim Wilson <jimw@sifive.com> Andrew Waterman <andrew@sifive.com> Maxim Blinov <maxim.blinov@embecosm.com> Kito Cheng <kito.cheng@sifive.com> Nelson Chu <nelson.chu@sifive.com> bfd/ * elfxx-riscv.c (riscv_std_z_ext_strtab): Added zba, zbb and zbc. gas/ * config/tc-riscv.c (riscv_multi_subset_supports): Handle INSN_CLASS_ZB*. (riscv_get_default_ext_version): Do not check the default_isa_spec when the version defined in the riscv_opcodes table is ISA_SPEC_CLASS_DRAFT. * testsuite/gas/riscv/bitmanip-insns-32.d: New testcase. * testsuite/gas/riscv/bitmanip-insns-64.d: Likewise. * testsuite/gas/riscv/bitmanip-insns.s: Likewise. include/ * opcode/riscv-opc.h: Added MASK/MATCH/DECLARE_INSN for ZBA/ZBB/ZBC. * opcode/riscv.h (riscv_insn_class): Added INSN_CLASS_ZB*. (enum riscv_isa_spec_class): Added ISA_SPEC_CLASS_DRAFT for the frozen extensions. opcodes/ * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions. (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
2020-12-15 23:11:03 +08:00
2021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
Jim Wilson <jimw@sifive.com>
Andrew Waterman <andrew@sifive.com>
Maxim Blinov <maxim.blinov@embecosm.com>
Kito Cheng <kito.cheng@sifive.com>
Nelson Chu <nelson.chu@sifive.com>
* config/tc-riscv.c (riscv_multi_subset_supports): Handle INSN_CLASS_ZB*.
(riscv_get_default_ext_version): Do not check the default_isa_spec when
the version defined in the riscv_opcodes table is ISA_SPEC_CLASS_DRAFT.
* testsuite/gas/riscv/bitmanip-insns-32.d: New testcase.
* testsuite/gas/riscv/bitmanip-insns-64.d: Likewise.
* testsuite/gas/riscv/bitmanip-insns.s: Likewise.
sparc-elf ld test fails * testsuite/gas/sparc/sparc.exp: Move 64-bit tests inside gas_64_check.
2021-01-06 10:06:31 +08:00
2021-01-06 Alan Modra <amodra@gmail.com>
* testsuite/gas/sparc/sparc.exp: Move 64-bit tests inside gas_64_check.
gas APP macro tests These fail on tic30 due to that target using a different comment char. * testsuite/gas/macros/app1.d: xfail tic30. * testsuite/gas/macros/app2.d: Likewise. * testsuite/gas/macros/app3.d: Likewise. * testsuite/gas/macros/app4.d: Likewise.
2021-01-06 09:23:33 +08:00
2021-01-06 Alan Modra <amodra@gmail.com>
* testsuite/gas/macros/app1.d: xfail tic30.
* testsuite/gas/macros/app2.d: Likewise.
* testsuite/gas/macros/app3.d: Likewise.
* testsuite/gas/macros/app4.d: Likewise.
RISC-V: Mention -mbig-endian and -mlittle-endian in doc gas/ * doc/as.texi: Add -mlittle-endian and -mbig-endian to docs. * doc/c-riscv.texi: Likewise.
2021-01-06 05:50:37 +08:00
2021-01-06 Marcus Comstedt <marcus@mc.pp.se>
* doc/as.texi: Add -mlittle-endian and -mbig-endian to docs.
* doc/c-riscv.texi: Likewise.
RISC-V: Fix riscv gas/ld testsuites failures for big endian. Add riscv_choose_[ilp32|lp64]_emul, and use them to choose the correct linker script rather than set elf[32|64]lriscv directly. gas/ * testsuite/gas/riscv/li32.d: Accept bigriscv in addition to littleriscv. * testsuite/gas/riscv/li64.d: Likewise. * testsuite/gas/riscv/lla32.d: Likewise. * testsuite/gas/riscv/lla64.d: Likewise. * testsuite/gas/riscv/march-ok-g2.d: Likewise. * testsuite/gas/riscv/march-ok-g2_p1.d: Likewise. * testsuite/gas/riscv/march-ok-g2p0.d: Likewise. * testsuite/gas/riscv/march-ok-i2p0.d: Likewise. * testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d: Likewise. * testsuite/gas/riscv/march-ok-nse-with-version.d: Likewise. * testsuite/gas/riscv/march-ok-two-nse.d: Likewise. ld/ * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Added riscv_choose_[ilp32|lp64]_emul to choose the correct linker script. * testsuite/ld-riscv-elf/attr-merge-arch-01.d: Call riscv_choose_[ilp32|lp64]_emul instead of hardcoding elf[32|64]lriscv. * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d: Likewise. * testsuite/ld-riscv-elf/c-lui-2.d: Likewise. * testsuite/ld-riscv-elf/c-lui.d: Likewise. * testsuite/ld-riscv-elf/call-relax.d: Likewise. * testsuite/ld-riscv-elf/pcrel-lo-addend-2.d: Likewise. * testsuite/ld-riscv-elf/pcrel-lo-addend.d: Likewise. * testsuite/ld-riscv-elf/weakref32.d: Accept bigriscv in addition to littleriscv. * testsuite/ld-riscv-elf/weakref64.d: Likewise.
2021-01-06 05:50:39 +08:00
2021-01-06 Marcus Comstedt <marcus@mc.pp.se>
* testsuite/gas/riscv/li32.d: Accept bigriscv in addition
to littleriscv.
* testsuite/gas/riscv/li64.d: Likewise.
* testsuite/gas/riscv/lla32.d: Likewise.
* testsuite/gas/riscv/lla64.d: Likewise.
* testsuite/gas/riscv/march-ok-g2.d: Likewise.
* testsuite/gas/riscv/march-ok-g2_p1.d: Likewise.
* testsuite/gas/riscv/march-ok-g2p0.d: Likewise.
* testsuite/gas/riscv/march-ok-i2p0.d: Likewise.
* testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d: Likewise.
* testsuite/gas/riscv/march-ok-nse-with-version.d: Likewise.
* testsuite/gas/riscv/march-ok-two-nse.d: Likewise.
RISC-V: Implement support for big endian targets. RISC-V instruction/code is always little endian, but data might be big-endian. Therefore, we can not use the original bfd_get/bfd_put to get/put the code for big endian targets. Add new riscv_get_insn and riscv_put_insn to always get/put code as little endian can resolve the problem. Just remember to update them once we have supported the 48-bit/128-bit instructions in the future patches. bfd/ * config.bfd: Added targets riscv64be*-*-*, riscv32be*-*-* and riscvbe*-*-*. Also added riscv_elf[32|64]_be_vec. * configure.ac: Handle riscv_elf[32|64]_be_vec. * configure: Regenerate. * elfnn-riscv.c: Include <limits.h> and define CHAR_BIT for riscv_is_insn_reloc. (riscv_get_insn): RISC-V instructions are always little endian, but bfd_get may be used for big-endian, so add new riscv_get_insn to handle the insturctions. (riscv_put_insn): Likewsie. (riscv_is_insn_reloc): Check if we are relocaing an instruction. (perform_relocation): Call riscv_is_insn_reloc to decide if we should use riscv_[get|put]_insn or bfd_[get|put]. (riscv_zero_pcrel_hi_reloc): Use riscv_[get|put]_insn, bfd_[get|put]l32 or bfd_[get|put]l16 for code. (riscv_elf_relocate_section): Likewise. (riscv_elf_finish_dynamic_symbol): Likewise. (riscv_elf_finish_dynamic_sections): Likewise. (_bfd_riscv_relax_call): Likewise. (_bfd_riscv_relax_lui): Likewise. (_bfd_riscv_relax_align): Likewise. (_bfd_riscv_relax_pc): Likewise. (riscv_elf_object_p): Handled for big endian. (TARGET_BIG_SYM, TARGET_BIG_NAME): Defined. * targets.c: Add riscv_elf[32|64]_be_vec. (_bfd_target_vector): Likewise. gas/ * config/tc-riscv.c (riscv_target_format): Add elf64-bigriscv and elf32-bigriscv. (install_insn): Always write instructions as little endian. (riscv_make_nops): Likewise. (md_convert_frag_branch): Likewise. (md_number_to_chars): Write data in target endianness. (options, md_longopts): Add -mbig-endian and -mlittle-endian options. (md_parse_option): Handle the endian options. * config/tc-riscv.h: Only define TARGET_BYTES_BIG_ENDIAN if not already defined. * configure.tgt: Added riscv64be*, riscv32be*, riscvbe*. ld/ * configure.tgt: Added riscvbe-*-*, riscv32be*-*-*, riscv64be*-*-*, riscv32be*-*-linux*, and riscv64be*-*-linux*. * Makefile.am: Added eelf32briscv.c, eelf32briscv_ilp32f.c and eelf32briscv_ilp32.c. * Makefile.in: Regenerate. * emulparams/elf32briscv.sh: Added. * emulparams/elf32briscv_ilp32.sh: Likewise. * emulparams/elf32briscv_ilp32f.sh: Likewise. * emulparams/elf64briscv.sh: Likewise. * emulparams/elf64briscv_lp64.sh: Likewise. * emulparams/elf64briscv_lp64f.sh: Likewise.
2021-01-06 05:50:32 +08:00
2021-01-06 Marcus Comstedt <marcus@mc.pp.se>
* config/tc-riscv.c (riscv_target_format): Add elf64-bigriscv and
elf32-bigriscv.
(install_insn): Always write instructions as little endian.
(riscv_make_nops): Likewise.
(md_convert_frag_branch): Likewise.
(md_number_to_chars): Write data in target endianness.
(options, md_longopts): Add -mbig-endian and -mlittle-endian options.
(md_parse_option): Handle the endian options.
* config/tc-riscv.h: Only define TARGET_BYTES_BIG_ENDIAN if not
already defined.
* configure.tgt: Added riscv64be*, riscv32be*, riscvbe*.
elf: Allow mixed ordered/unordered inputs for non-relocatable link For non-relocatable link with SHF_LINK_ORDER inputs, allow mixed indirect and data inputs with ordered and unordered inputs: 1. Add pattern to bfd_section for the matching section name pattern in linker script and update BFD_FAKE_SECTION. 2. Sort the consecutive bfd_indirect_link_order sections with the same pattern to allow linker script to overdide input section order. 3. Place unordered sections before ordered sections. 4. Change the offsets of the indirect input sections only. bfd/ PR ld/26256 * elflink.c (compare_link_order): Place unordered sections before ordered sections. (elf_fixup_link_order): Add a link info argument. Allow mixed ordered and unordered input sections for non-relocatable link. Sort the consecutive bfd_indirect_link_order sections with the same pattern. Change the offsets of the bfd_indirect_link_order sections only. (bfd_elf_final_link): Pass info to elf_fixup_link_order. * section.c (bfd_section): Add pattern. (BFD_FAKE_SECTION): Initialize pattern to NULL. * bfd-in2.h: Regenerated. gas/ PR ld/26256 * config/obj-elf.c (obj_elf_change_section): Also filter out SHF_LINK_ORDER. ld/ PR ld/26256 * ldlang.c (gc_section_callback): Set pattern. * testsuite/ld-elf/pr26256-1.s: New file. * testsuite/ld-elf/pr26256-1.t: Likewise. * testsuite/ld-elf/pr26256-1a.d: Likewise. * testsuite/ld-elf/pr26256-1b.d: Likewise. * testsuite/ld-elf/pr26256-2.s: Likewise. * testsuite/ld-elf/pr26256-2.t: Likewise. * testsuite/ld-elf/pr26256-2a.d: Likewise. * testsuite/ld-elf/pr26256-2b-alt.d: Likewise. * testsuite/ld-elf/pr26256-2b.d: Likewise. * testsuite/ld-elf/pr26256-3.s: Likewise. * testsuite/ld-elf/pr26256-3a.d: Likewise. * testsuite/ld-elf/pr26256-3a.t: Likewise. * testsuite/ld-elf/pr26256-3b.d: Likewise. * testsuite/ld-elf/pr26256-3b.t: Likewise.
2021-01-05 04:37:49 +08:00
2021-01-04 H.J. Lu <hongjiu.lu@intel.com>
PR ld/26256
* config/obj-elf.c (obj_elf_change_section): Also filter out
SHF_LINK_ORDER.
PR27102, gas: "section symbols are already global" PR 27102 * symbols.c (S_SET_EXTERNAL): Revise section symbol warning message and register symbol error message.
2021-01-04 08:46:21 +08:00
2021-01-04 Alan Modra <amodra@gmail.com>
PR 27102
* symbols.c (S_SET_EXTERNAL): Revise section symbol warning
message and register symbol error message.
PR27101, as: Reject (byte) .align 0x100000000 This allows alignments up to 2**TC_ALIGN_LIMIT, which might be larger than an unsigned int can hold. PR 27101 * read.c (s_align): Use a large enough type for "align" to hold the result of get_absolute_expression.
2021-01-04 06:23:37 +08:00
2021-01-04 Alan Modra <amodra@gmail.com>
PR 27101
* read.c (s_align): Use a large enough type for "align" to hold
the result of get_absolute_expression.
PR27116, Spelling errors found by Debian style checker PR 27116 bfd/ * xcofflink.c: Correct spelling in comments. binutils/ * coffgrok.c (do_type): Correct spelling of auxiliary in errors. * doc/binutils.texi: Correct grammar. * readelf.c (process_version_sections): Correct spelling of auxiliary in warning. * testsuite/binutils-all/vax/objdump.exp: Comment grammar fix. config/ * override.m4: Correct comment grammar. gas/ * config/tc-i386.c: Correct comment spelling. * config/tc-riscv.c: Likewise. * config/tc-s390.c: Correct comment grammar. * doc/c-i386.texi: Correct spelling. * doc/c-s390.texi: Correct grammar. gold/ * tilegx.cc: Correct comment spelling. gprof/ * README: Correct grammar. * gprof.texi: Likewise. include/ * coff/internal.h: Correct comment spelling. * coff/sym.h: Likewise. * opcode/aarch64.h: Likewise. ld/ * configure.tgt: Correct comment grammar. * emultempl/m68hc1xelf.em: Likewise. * ld.texi: Correct grammar.
2021-01-01 11:51:52 +08:00
2021-01-01 Nicolas Boulenguez <nicolas@debian.org>
* config/tc-i386.c: Correct comment spelling.
* config/tc-riscv.c: Likewise.
* config/tc-s390.c: Correct comment grammar.
* doc/c-i386.texi: Correct spelling.
* doc/c-s390.texi: Correct grammar.
Update year range in copyright notice of binutils files
2021-01-01 06:58:58 +08:00
2021-01-01 Alan Modra <amodra@gmail.com>
Update year range in copyright notice of all files.
gas: Change to "swym 0" as canonical nop insn for MMIX While "set $0, $0" works, that's not the documented instruction to do nothing for MMIX. However, I'm not changing it for "nop_type 5" as seen in gas.exp and org-1.s, because "set $0, $0" seems like it could be re-used there, for some future ISA. gas/ * config/tc-mmix.h (md_single_noop_insn): Change to "swym 0".
2021-01-01 07:47:36 +08:00
2021-01-01 Hans-Peter Nilsson <hp@bitrange.com>
* config/tc-mmix.h (md_single_noop_insn): Change to "swym 0".
ChangeLog rotation
2021-01-01 06:47:13 +08:00
For older changes see ChangeLog-2020
New 2016 binutils ChangeLog files Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog and include/*/ChangeLog files.
2016-01-01 18:44:31 +08:00
Update year range in copyright notice of binutils files Adds two new external authors to etc/update-copyright.py to cover bfd/ax_tls.m4, and adds gprofng to dirs handled automatically, then updates copyright messages as follows: 1) Update cgen/utils.scm emitted copyrights. 2) Run "etc/update-copyright.py --this-year" with an extra external author I haven't committed, 'Kalray SA.', to cover gas testsuite files (which should have their copyright message removed). 3) Build with --enable-maintainer-mode --enable-cgen-maint=yes. 4) Check out */po/*.pot which we don't update frequently.
2024-01-04 19:52:08 +08:00
Copyright (C) 2021-2024 Free Software Foundation, Inc.
New 2016 binutils ChangeLog files Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog and include/*/ChangeLog files.
2016-01-01 18:44:31 +08:00
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