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128 lines
3.1 KiB
ArmAsm
128 lines
3.1 KiB
ArmAsm
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//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1/c_dsp32mac_pair_a1.dsp
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// Spec Reference: dsp32mac pair a1
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# mach: bfin
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.include "testutils.inc"
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start
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A1 = A0 = 0;
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// The result accumulated in A1 , and stored to a reg half
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imm32 r0, 0x63545abd;
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imm32 r1, 0x86bcfec7;
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imm32 r2, 0xa8645679;
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imm32 r3, 0x00860007;
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imm32 r4, 0xefb86569;
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imm32 r5, 0x1235860b;
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imm32 r6, 0x000c086d;
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imm32 r7, 0x678e0086;
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R7 = ( A1 += R1.L * R0.L ), A0 = R1.L * R0.L;
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P1 = A1.w;
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R1 = ( A1 = R2.L * R3.L ), A0 += R2.H * R3.L;
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P2 = A1.w;
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R3 = ( A1 -= R7.L * R4.L ), A0 += R7.H * R4.H;
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P3 = A1.w;
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R5 = ( A1 -= R6.L * R5.L ), A0 -= R6.L * R5.H;
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P4 = A1.w;
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CHECKREG r0, 0x63545ABD;
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CHECKREG r1, 0x0004BA9E;
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CHECKREG r2, 0xA8645679;
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CHECKREG r3, 0xE8616512;
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CHECKREG r4, 0xEFB86569;
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CHECKREG r5, 0xF0688FB4;
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CHECKREG r6, 0x000C086D;
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CHECKREG r7, 0xFF221DD6;
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CHECKREG p1, 0xFF221DD6;
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CHECKREG p2, 0x0004BA9E;
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CHECKREG p3, 0xE8616512;
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CHECKREG p4, 0xF0688FB4;
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imm32 r0, 0x98764abd;
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imm32 r1, 0xa1bcf4c7;
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imm32 r2, 0xa1145649;
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imm32 r3, 0x00010005;
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imm32 r4, 0xefbc1569;
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imm32 r5, 0x1235010b;
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imm32 r6, 0x000c001d;
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imm32 r7, 0x678e0001;
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R5 = ( A1 += R1.L * R0.H ), A0 -= R1.L * R0.L;
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P1 = A1.w;
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R1 = ( A1 = R2.L * R3.H ), A0 -= R2.H * R3.L;
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P2 = A1.w;
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R3 = ( A1 -= R4.L * R5.H ), A0 += R4.H * R5.H;
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P3 = A1.w;
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R1 = ( A1 += R6.L * R7.H ), A0 += R6.L * R7.H;
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P4 = A1.w;
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CHECKREG r0, 0x98764ABD;
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CHECKREG r1, 0x012F2306;
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CHECKREG r2, 0xA1145649;
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CHECKREG r3, 0x0117ACDA;
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CHECKREG r4, 0xEFBC1569;
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CHECKREG r5, 0xF97C8728;
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CHECKREG r6, 0x000C001D;
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CHECKREG r7, 0x678E0001;
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CHECKREG p1, 0xF97C8728;
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CHECKREG p2, 0x0000AC92;
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CHECKREG p3, 0x0117ACDA;
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CHECKREG p4, 0x012F2306;
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imm32 r0, 0x7136459d;
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imm32 r1, 0xabd69ec7;
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imm32 r2, 0x71145679;
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imm32 r3, 0x08010007;
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imm32 r4, 0xef9c1569;
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imm32 r5, 0x1225010b;
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imm32 r6, 0x0003401d;
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imm32 r7, 0x678e0561;
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R5 = ( A1 += R1.H * R0.L ), A0 = R1.L * R0.L;
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P1 = A1.w;
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R7 = ( A1 -= R2.H * R3.L ), A0 -= R2.H * R3.L;
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P2 = A1.w;
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R1 = ( A1 += R4.H * R5.L ), A0 -= R4.H * R5.H;
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P3 = A1.w;
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R5 = ( A1 += R6.H * R7.L ), A0 += R6.L * R7.H;
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P4 = A1.w;
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CHECKREG r0, 0x7136459D;
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CHECKREG r1, 0xCABE16DA;
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CHECKREG r2, 0x71145679;
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CHECKREG r3, 0x08010007;
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CHECKREG r4, 0xEF9C1569;
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CHECKREG r5, 0xCABE9156;
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CHECKREG r6, 0x0003401D;
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CHECKREG r7, 0xD363146A;
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CHECKREG p1, 0xD3694382;
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CHECKREG p2, 0xD363146A;
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CHECKREG p3, 0xCABE16DA;
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CHECKREG p4, 0xCABE9156;
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imm32 r0, 0x123489bd;
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imm32 r1, 0x91bcfec7;
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imm32 r2, 0xa9145679;
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imm32 r3, 0xd0910007;
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imm32 r4, 0xedb91569;
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imm32 r5, 0xd235910b;
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imm32 r6, 0x0d0c0999;
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imm32 r7, 0x67de0009;
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R1 = ( A1 += R5.H * R3.H ), A0 = R5.L * R3.L;
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P1 = A1.w;
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R3 = ( A1 = R2.H * R1.H ), A0 -= R2.H * R1.L;
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P2 = A1.w;
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R5 = ( A1 -= R7.H * R0.H ), A0 += R7.H * R0.H;
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P3 = A1.w;
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R7 = ( A1 += R4.H * R6.H ), A0 += R4.L * R6.H;
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P4 = A1.w;
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CHECKREG r0, 0x123489BD;
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CHECKREG r1, 0xDBB6D160;
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CHECKREG r2, 0xA9145679;
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CHECKREG r3, 0x18A4A070;
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CHECKREG r4, 0xEDB91569;
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CHECKREG r5, 0x09DF3640;
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CHECKREG r6, 0x0D0C0999;
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CHECKREG r7, 0x08024998;
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CHECKREG p1, 0xDBB6D160;
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CHECKREG p2, 0x18A4A070;
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CHECKREG p3, 0x09DF3640;
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CHECKREG p4, 0x08024998;
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pass
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