mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2025-01-06 12:09:26 +08:00
540 lines
8.3 KiB
ArmAsm
540 lines
8.3 KiB
ArmAsm
|
//Original:/testcases/core/c_regmv_dr_imlb/c_regmv_dr_imlb.dsp
|
||
|
// Spec Reference: regmv dreg-to-imlb
|
||
|
# mach: bfin
|
||
|
|
||
|
.include "testutils.inc"
|
||
|
start
|
||
|
|
||
|
// check DR-reg to imlb-reg move
|
||
|
imm32 r0, 0x00000001;
|
||
|
imm32 r1, 0x00020003;
|
||
|
imm32 r2, 0x00040005;
|
||
|
imm32 r3, 0x00060007;
|
||
|
imm32 r4, 0x00080009;
|
||
|
imm32 r5, 0x000a000b;
|
||
|
imm32 r6, 0x000c000d;
|
||
|
imm32 r7, 0x000e000f;
|
||
|
I0 = R0;
|
||
|
I1 = R0;
|
||
|
I2 = R0;
|
||
|
I3 = R0;
|
||
|
M0 = R0;
|
||
|
M1 = R0;
|
||
|
M2 = R0;
|
||
|
M3 = R0;
|
||
|
|
||
|
R0 = I0;
|
||
|
R1 = I1;
|
||
|
R2 = I2;
|
||
|
R3 = I3;
|
||
|
R4 = M0;
|
||
|
R5 = M1;
|
||
|
R6 = M2;
|
||
|
R7 = M3;
|
||
|
CHECKREG r0, 0x00000001;
|
||
|
CHECKREG r1, 0x00000001;
|
||
|
CHECKREG r2, 0x00000001;
|
||
|
CHECKREG r3, 0x00000001;
|
||
|
CHECKREG r4, 0x00000001;
|
||
|
CHECKREG r5, 0x00000001;
|
||
|
CHECKREG r6, 0x00000001;
|
||
|
CHECKREG r7, 0x00000001;
|
||
|
|
||
|
imm32 r0, 0x00000001;
|
||
|
imm32 r1, 0x00020003;
|
||
|
imm32 r2, 0x00040005;
|
||
|
imm32 r3, 0x00060007;
|
||
|
imm32 r4, 0x00080009;
|
||
|
imm32 r5, 0x000a000b;
|
||
|
imm32 r6, 0x000c000d;
|
||
|
imm32 r7, 0x000e000f;
|
||
|
I0 = R1;
|
||
|
I1 = R1;
|
||
|
I2 = R1;
|
||
|
I3 = R1;
|
||
|
M0 = R1;
|
||
|
M1 = R1;
|
||
|
M2 = R1;
|
||
|
M3 = R1;
|
||
|
R0 = I0;
|
||
|
R1 = I1;
|
||
|
R2 = I2;
|
||
|
R3 = I3;
|
||
|
R4 = M0;
|
||
|
R5 = M1;
|
||
|
R6 = M2;
|
||
|
R7 = M3;
|
||
|
CHECKREG r0, 0x00020003;
|
||
|
CHECKREG r1, 0x00020003;
|
||
|
CHECKREG r2, 0x00020003;
|
||
|
CHECKREG r3, 0x00020003;
|
||
|
CHECKREG r4, 0x00020003;
|
||
|
CHECKREG r5, 0x00020003;
|
||
|
CHECKREG r6, 0x00020003;
|
||
|
CHECKREG r7, 0x00020003;
|
||
|
|
||
|
imm32 r0, 0x00000001;
|
||
|
imm32 r1, 0x00020003;
|
||
|
imm32 r2, 0x00040005;
|
||
|
imm32 r3, 0x00060007;
|
||
|
imm32 r4, 0x00080009;
|
||
|
imm32 r5, 0x000a000b;
|
||
|
imm32 r6, 0x000c000d;
|
||
|
imm32 r7, 0x000e000f;
|
||
|
I0 = R2;
|
||
|
I1 = R2;
|
||
|
I2 = R2;
|
||
|
I3 = R2;
|
||
|
M0 = R2;
|
||
|
M1 = R2;
|
||
|
M2 = R2;
|
||
|
M3 = R2;
|
||
|
R0 = I0;
|
||
|
R1 = I1;
|
||
|
R2 = I2;
|
||
|
R3 = I3;
|
||
|
R4 = M0;
|
||
|
R5 = M1;
|
||
|
R6 = M2;
|
||
|
R7 = M3;
|
||
|
CHECKREG r0, 0x00040005;
|
||
|
CHECKREG r1, 0x00040005;
|
||
|
CHECKREG r2, 0x00040005;
|
||
|
CHECKREG r3, 0x00040005;
|
||
|
CHECKREG r4, 0x00040005;
|
||
|
CHECKREG r5, 0x00040005;
|
||
|
CHECKREG r6, 0x00040005;
|
||
|
CHECKREG r7, 0x00040005;
|
||
|
|
||
|
imm32 r0, 0x00000001;
|
||
|
imm32 r1, 0x00020003;
|
||
|
imm32 r2, 0x00040005;
|
||
|
imm32 r3, 0x00060007;
|
||
|
imm32 r4, 0x00080009;
|
||
|
imm32 r5, 0x000a000b;
|
||
|
imm32 r6, 0x000c000d;
|
||
|
imm32 r7, 0x000e000f;
|
||
|
I0 = R3;
|
||
|
I1 = R3;
|
||
|
I2 = R3;
|
||
|
I3 = R3;
|
||
|
M0 = R3;
|
||
|
M1 = R3;
|
||
|
M2 = R3;
|
||
|
M3 = R3;
|
||
|
R0 = I0;
|
||
|
R1 = I1;
|
||
|
R2 = I2;
|
||
|
R3 = I3;
|
||
|
R4 = M0;
|
||
|
R5 = M1;
|
||
|
R6 = M2;
|
||
|
R7 = M3;
|
||
|
CHECKREG r0, 0x00060007;
|
||
|
CHECKREG r1, 0x00060007;
|
||
|
CHECKREG r2, 0x00060007;
|
||
|
CHECKREG r3, 0x00060007;
|
||
|
CHECKREG r4, 0x00060007;
|
||
|
CHECKREG r5, 0x00060007;
|
||
|
CHECKREG r6, 0x00060007;
|
||
|
CHECKREG r7, 0x00060007;
|
||
|
|
||
|
imm32 r0, 0x00000001;
|
||
|
imm32 r1, 0x00020003;
|
||
|
imm32 r2, 0x00040005;
|
||
|
imm32 r3, 0x00060007;
|
||
|
imm32 r4, 0x00080009;
|
||
|
imm32 r5, 0x000a000b;
|
||
|
imm32 r6, 0x000c000d;
|
||
|
imm32 r7, 0x000e000f;
|
||
|
I0 = R4;
|
||
|
I1 = R4;
|
||
|
I2 = R4;
|
||
|
I3 = R4;
|
||
|
M0 = R4;
|
||
|
M1 = R4;
|
||
|
M2 = R4;
|
||
|
M3 = R4;
|
||
|
R0 = I0;
|
||
|
R1 = I1;
|
||
|
R2 = I2;
|
||
|
R3 = I3;
|
||
|
R4 = M0;
|
||
|
R5 = M1;
|
||
|
R6 = M2;
|
||
|
R7 = M3;
|
||
|
CHECKREG r0, 0x00080009;
|
||
|
CHECKREG r1, 0x00080009;
|
||
|
CHECKREG r2, 0x00080009;
|
||
|
CHECKREG r3, 0x00080009;
|
||
|
CHECKREG r4, 0x00080009;
|
||
|
CHECKREG r5, 0x00080009;
|
||
|
CHECKREG r6, 0x00080009;
|
||
|
CHECKREG r7, 0x00080009;
|
||
|
|
||
|
imm32 r0, 0x00000001;
|
||
|
imm32 r1, 0x00020003;
|
||
|
imm32 r2, 0x00040005;
|
||
|
imm32 r3, 0x00060007;
|
||
|
imm32 r4, 0x00080009;
|
||
|
imm32 r5, 0x000a000b;
|
||
|
imm32 r6, 0x000c000d;
|
||
|
imm32 r7, 0x000e000f;
|
||
|
I0 = R5;
|
||
|
I1 = R5;
|
||
|
I2 = R5;
|
||
|
I3 = R5;
|
||
|
M0 = R5;
|
||
|
M1 = R5;
|
||
|
M2 = R5;
|
||
|
M3 = R5;
|
||
|
R0 = I0;
|
||
|
R1 = I1;
|
||
|
R2 = I2;
|
||
|
R3 = I3;
|
||
|
R4 = M0;
|
||
|
R5 = M1;
|
||
|
R6 = M2;
|
||
|
R7 = M3;
|
||
|
CHECKREG r0, 0x000a000b;
|
||
|
CHECKREG r1, 0x000a000b;
|
||
|
CHECKREG r2, 0x000a000b;
|
||
|
CHECKREG r3, 0x000a000b;
|
||
|
CHECKREG r4, 0x000a000b;
|
||
|
CHECKREG r5, 0x000a000b;
|
||
|
CHECKREG r6, 0x000a000b;
|
||
|
CHECKREG r7, 0x000a000b;
|
||
|
|
||
|
imm32 r0, 0x00000001;
|
||
|
imm32 r1, 0x00020003;
|
||
|
imm32 r2, 0x00040005;
|
||
|
imm32 r3, 0x00060007;
|
||
|
imm32 r4, 0x00080009;
|
||
|
imm32 r5, 0x000a000b;
|
||
|
imm32 r6, 0x000c000d;
|
||
|
imm32 r7, 0x000e000f;
|
||
|
I0 = R6;
|
||
|
I1 = R6;
|
||
|
I2 = R6;
|
||
|
I3 = R6;
|
||
|
M0 = R6;
|
||
|
M1 = R6;
|
||
|
M2 = R6;
|
||
|
M3 = R6;
|
||
|
R0 = I0;
|
||
|
R1 = I1;
|
||
|
R2 = I2;
|
||
|
R3 = I3;
|
||
|
R4 = M0;
|
||
|
R5 = M1;
|
||
|
R6 = M2;
|
||
|
R7 = M3;
|
||
|
CHECKREG r0, 0x000c000d;
|
||
|
CHECKREG r1, 0x000c000d;
|
||
|
CHECKREG r2, 0x000c000d;
|
||
|
CHECKREG r3, 0x000c000d;
|
||
|
CHECKREG r4, 0x000c000d;
|
||
|
CHECKREG r5, 0x000c000d;
|
||
|
CHECKREG r6, 0x000c000d;
|
||
|
CHECKREG r7, 0x000c000d;
|
||
|
|
||
|
imm32 r0, 0x00000001;
|
||
|
imm32 r1, 0x00020003;
|
||
|
imm32 r2, 0x00040005;
|
||
|
imm32 r3, 0x00060007;
|
||
|
imm32 r4, 0x00080009;
|
||
|
imm32 r5, 0x000a000b;
|
||
|
imm32 r6, 0x000c000d;
|
||
|
imm32 r7, 0x000e000f;
|
||
|
I0 = R7;
|
||
|
I1 = R7;
|
||
|
I2 = R7;
|
||
|
I3 = R7;
|
||
|
M0 = R7;
|
||
|
M1 = R7;
|
||
|
M2 = R7;
|
||
|
M3 = R7;
|
||
|
R0 = I0;
|
||
|
R1 = I1;
|
||
|
R2 = I2;
|
||
|
R3 = I3;
|
||
|
R4 = M0;
|
||
|
R5 = M1;
|
||
|
R6 = M2;
|
||
|
R7 = M3;
|
||
|
CHECKREG r0, 0x000e000f;
|
||
|
CHECKREG r1, 0x000e000f;
|
||
|
CHECKREG r2, 0x000e000f;
|
||
|
CHECKREG r3, 0x000e000f;
|
||
|
CHECKREG r4, 0x000e000f;
|
||
|
CHECKREG r5, 0x000e000f;
|
||
|
CHECKREG r6, 0x000e000f;
|
||
|
CHECKREG r7, 0x000e000f;
|
||
|
|
||
|
imm32 r0, 0x00000001;
|
||
|
imm32 r1, 0x00020003;
|
||
|
imm32 r2, 0x00040005;
|
||
|
imm32 r3, 0x00060007;
|
||
|
imm32 r4, 0x00080009;
|
||
|
imm32 r5, 0x000a000b;
|
||
|
imm32 r6, 0x000c000d;
|
||
|
imm32 r7, 0x000e000f;
|
||
|
L0 = R0;
|
||
|
L1 = R0;
|
||
|
L2 = R0;
|
||
|
L3 = R0;
|
||
|
B0 = R0;
|
||
|
B1 = R0;
|
||
|
B2 = R0;
|
||
|
B3 = R0;
|
||
|
|
||
|
R0 = L0;
|
||
|
R1 = L1;
|
||
|
R2 = L2;
|
||
|
R3 = L3;
|
||
|
R4 = B0;
|
||
|
R5 = B1;
|
||
|
R6 = B2;
|
||
|
R7 = B3;
|
||
|
CHECKREG r0, 0x00000001;
|
||
|
CHECKREG r1, 0x00000001;
|
||
|
CHECKREG r2, 0x00000001;
|
||
|
CHECKREG r3, 0x00000001;
|
||
|
CHECKREG r4, 0x00000001;
|
||
|
CHECKREG r5, 0x00000001;
|
||
|
CHECKREG r6, 0x00000001;
|
||
|
CHECKREG r7, 0x00000001;
|
||
|
|
||
|
imm32 r0, 0x00000001;
|
||
|
imm32 r1, 0x00020003;
|
||
|
imm32 r2, 0x00040005;
|
||
|
imm32 r3, 0x00060007;
|
||
|
imm32 r4, 0x00080009;
|
||
|
imm32 r5, 0x000a000b;
|
||
|
imm32 r6, 0x000c000d;
|
||
|
imm32 r7, 0x000e000f;
|
||
|
L0 = R1;
|
||
|
L1 = R1;
|
||
|
L2 = R1;
|
||
|
L3 = R1;
|
||
|
B0 = R1;
|
||
|
B1 = R1;
|
||
|
B2 = R1;
|
||
|
B3 = R1;
|
||
|
R0 = L0;
|
||
|
R1 = L1;
|
||
|
R2 = L2;
|
||
|
R3 = L3;
|
||
|
R4 = B0;
|
||
|
R5 = B1;
|
||
|
R6 = B2;
|
||
|
R7 = B3;
|
||
|
CHECKREG r0, 0x00020003;
|
||
|
CHECKREG r1, 0x00020003;
|
||
|
CHECKREG r2, 0x00020003;
|
||
|
CHECKREG r3, 0x00020003;
|
||
|
CHECKREG r4, 0x00020003;
|
||
|
CHECKREG r5, 0x00020003;
|
||
|
CHECKREG r6, 0x00020003;
|
||
|
CHECKREG r7, 0x00020003;
|
||
|
|
||
|
imm32 r0, 0x00000001;
|
||
|
imm32 r1, 0x00020003;
|
||
|
imm32 r2, 0x00040005;
|
||
|
imm32 r3, 0x00060007;
|
||
|
imm32 r4, 0x00080009;
|
||
|
imm32 r5, 0x000a000b;
|
||
|
imm32 r6, 0x000c000d;
|
||
|
imm32 r7, 0x000e000f;
|
||
|
L0 = R2;
|
||
|
L1 = R2;
|
||
|
L2 = R2;
|
||
|
L3 = R2;
|
||
|
B0 = R2;
|
||
|
B1 = R2;
|
||
|
B2 = R2;
|
||
|
B3 = R2;
|
||
|
R0 = L0;
|
||
|
R1 = L1;
|
||
|
R2 = L2;
|
||
|
R3 = L3;
|
||
|
R4 = B0;
|
||
|
R5 = B1;
|
||
|
R6 = B2;
|
||
|
R7 = B3;
|
||
|
CHECKREG r0, 0x00040005;
|
||
|
CHECKREG r1, 0x00040005;
|
||
|
CHECKREG r2, 0x00040005;
|
||
|
CHECKREG r3, 0x00040005;
|
||
|
CHECKREG r4, 0x00040005;
|
||
|
CHECKREG r5, 0x00040005;
|
||
|
CHECKREG r6, 0x00040005;
|
||
|
CHECKREG r7, 0x00040005;
|
||
|
|
||
|
imm32 r0, 0x00000001;
|
||
|
imm32 r1, 0x00020003;
|
||
|
imm32 r2, 0x00040005;
|
||
|
imm32 r3, 0x00060007;
|
||
|
imm32 r4, 0x00080009;
|
||
|
imm32 r5, 0x000a000b;
|
||
|
imm32 r6, 0x000c000d;
|
||
|
imm32 r7, 0x000e000f;
|
||
|
L0 = R3;
|
||
|
L1 = R3;
|
||
|
L2 = R3;
|
||
|
L3 = R3;
|
||
|
B0 = R3;
|
||
|
B1 = R3;
|
||
|
B2 = R3;
|
||
|
B3 = R3;
|
||
|
R0 = L0;
|
||
|
R1 = L1;
|
||
|
R2 = L2;
|
||
|
R3 = L3;
|
||
|
R4 = B0;
|
||
|
R5 = B1;
|
||
|
R6 = B2;
|
||
|
R7 = B3;
|
||
|
CHECKREG r0, 0x00060007;
|
||
|
CHECKREG r1, 0x00060007;
|
||
|
CHECKREG r2, 0x00060007;
|
||
|
CHECKREG r3, 0x00060007;
|
||
|
CHECKREG r4, 0x00060007;
|
||
|
CHECKREG r5, 0x00060007;
|
||
|
CHECKREG r6, 0x00060007;
|
||
|
CHECKREG r7, 0x00060007;
|
||
|
|
||
|
imm32 r0, 0x00000001;
|
||
|
imm32 r1, 0x00020003;
|
||
|
imm32 r2, 0x00040005;
|
||
|
imm32 r3, 0x00060007;
|
||
|
imm32 r4, 0x00080009;
|
||
|
imm32 r5, 0x000a000b;
|
||
|
imm32 r6, 0x000c000d;
|
||
|
imm32 r7, 0x000e000f;
|
||
|
L0 = R4;
|
||
|
L1 = R4;
|
||
|
L2 = R4;
|
||
|
L3 = R4;
|
||
|
B0 = R4;
|
||
|
B1 = R4;
|
||
|
B2 = R4;
|
||
|
B3 = R4;
|
||
|
R0 = L0;
|
||
|
R1 = L1;
|
||
|
R2 = L2;
|
||
|
R3 = L3;
|
||
|
R4 = B0;
|
||
|
R5 = B1;
|
||
|
R6 = B2;
|
||
|
R7 = B3;
|
||
|
CHECKREG r0, 0x00080009;
|
||
|
CHECKREG r1, 0x00080009;
|
||
|
CHECKREG r2, 0x00080009;
|
||
|
CHECKREG r3, 0x00080009;
|
||
|
CHECKREG r4, 0x00080009;
|
||
|
CHECKREG r5, 0x00080009;
|
||
|
CHECKREG r6, 0x00080009;
|
||
|
CHECKREG r7, 0x00080009;
|
||
|
|
||
|
imm32 r0, 0x00000001;
|
||
|
imm32 r1, 0x00020003;
|
||
|
imm32 r2, 0x00040005;
|
||
|
imm32 r3, 0x00060007;
|
||
|
imm32 r4, 0x00080009;
|
||
|
imm32 r5, 0x000a000b;
|
||
|
imm32 r6, 0x000c000d;
|
||
|
imm32 r7, 0x000e000f;
|
||
|
L0 = R5;
|
||
|
L1 = R5;
|
||
|
L2 = R5;
|
||
|
L3 = R5;
|
||
|
B0 = R5;
|
||
|
B1 = R5;
|
||
|
B2 = R5;
|
||
|
B3 = R5;
|
||
|
R0 = L0;
|
||
|
R1 = L1;
|
||
|
R2 = L2;
|
||
|
R3 = L3;
|
||
|
R4 = B0;
|
||
|
R5 = B1;
|
||
|
R6 = B2;
|
||
|
R7 = B3;
|
||
|
CHECKREG r0, 0x000a000b;
|
||
|
CHECKREG r1, 0x000a000b;
|
||
|
CHECKREG r2, 0x000a000b;
|
||
|
CHECKREG r3, 0x000a000b;
|
||
|
CHECKREG r4, 0x000a000b;
|
||
|
CHECKREG r5, 0x000a000b;
|
||
|
CHECKREG r6, 0x000a000b;
|
||
|
CHECKREG r7, 0x000a000b;
|
||
|
|
||
|
imm32 r0, 0x00000001;
|
||
|
imm32 r1, 0x00020003;
|
||
|
imm32 r2, 0x00040005;
|
||
|
imm32 r3, 0x00060007;
|
||
|
imm32 r4, 0x00080009;
|
||
|
imm32 r5, 0x000a000b;
|
||
|
imm32 r6, 0x000c000d;
|
||
|
imm32 r7, 0x000e000f;
|
||
|
L0 = R6;
|
||
|
L1 = R6;
|
||
|
L2 = R6;
|
||
|
L3 = R6;
|
||
|
B0 = R6;
|
||
|
B1 = R6;
|
||
|
B2 = R6;
|
||
|
B3 = R6;
|
||
|
R0 = L0;
|
||
|
R1 = L1;
|
||
|
R2 = L2;
|
||
|
R3 = L3;
|
||
|
R4 = B0;
|
||
|
R5 = B1;
|
||
|
R6 = B2;
|
||
|
R7 = B3;
|
||
|
CHECKREG r0, 0x000c000d;
|
||
|
CHECKREG r1, 0x000c000d;
|
||
|
CHECKREG r2, 0x000c000d;
|
||
|
CHECKREG r3, 0x000c000d;
|
||
|
CHECKREG r4, 0x000c000d;
|
||
|
CHECKREG r5, 0x000c000d;
|
||
|
CHECKREG r6, 0x000c000d;
|
||
|
CHECKREG r7, 0x000c000d;
|
||
|
|
||
|
imm32 r0, 0x00000001;
|
||
|
imm32 r1, 0x00020003;
|
||
|
imm32 r2, 0x00040005;
|
||
|
imm32 r3, 0x00060007;
|
||
|
imm32 r4, 0x00080009;
|
||
|
imm32 r5, 0x000a000b;
|
||
|
imm32 r6, 0x000c000d;
|
||
|
imm32 r7, 0x000e000f;
|
||
|
L0 = R7;
|
||
|
L1 = R7;
|
||
|
L2 = R7;
|
||
|
L3 = R7;
|
||
|
B0 = R7;
|
||
|
B1 = R7;
|
||
|
B2 = R7;
|
||
|
B3 = R7;
|
||
|
R0 = L0;
|
||
|
R1 = L1;
|
||
|
R2 = L2;
|
||
|
R3 = L3;
|
||
|
R4 = B0;
|
||
|
R5 = B1;
|
||
|
R6 = B2;
|
||
|
R7 = B3;
|
||
|
CHECKREG r0, 0x000e000f;
|
||
|
CHECKREG r1, 0x000e000f;
|
||
|
CHECKREG r2, 0x000e000f;
|
||
|
CHECKREG r3, 0x000e000f;
|
||
|
CHECKREG r4, 0x000e000f;
|
||
|
CHECKREG r5, 0x000e000f;
|
||
|
CHECKREG r6, 0x000e000f;
|
||
|
CHECKREG r7, 0x000e000f;
|
||
|
|
||
|
pass
|