mirror of
https://sourceware.org/git/binutils-gdb.git
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275 lines
6.5 KiB
ArmAsm
275 lines
6.5 KiB
ArmAsm
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//Original:/testcases/core/c_dsp32mac_dr_a1_t/c_dsp32mac_dr_a1_t.dsp
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// Spec Reference: dsp32mac dr a1 t (truncation)
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# mach: bfin
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.include "testutils.inc"
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start
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A1 = A0 = 0;
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// The result accumulated in A , and stored to a reg half
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imm32 r0, 0xa3545abd;
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imm32 r1, 0xbdbcfec7;
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imm32 r2, 0xc1248679;
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imm32 r3, 0xd0069007;
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imm32 r4, 0xefbc4569;
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imm32 r5, 0xcd35500b;
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imm32 r6, 0xe00c800d;
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imm32 r7, 0xf78e900f;
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R0.H = ( A1 = R1.L * R0.L ), A0 = R1.L * R0.L (T);
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R1 = A1.w;
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R2.H = ( A1 = R2.L * R3.H ), A0 = R2.H * R3.L (T);
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R3 = A1.w;
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R4.H = ( A1 = R4.H * R5.L ), A0 += R4.H * R5.H (T);
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R5 = A1.w;
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R6.H = ( A1 = R6.H * R7.H ), A0 += R6.L * R7.H (T);
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R7 = A1.w;
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CHECKREG r0, 0xFF225ABD;
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CHECKREG r1, 0xFF221DD6;
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CHECKREG r2, 0x2D8C8679;
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CHECKREG r3, 0x2D8CEDAC;
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CHECKREG r4, 0xF5D44569;
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CHECKREG r5, 0xF5D41A28;
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CHECKREG r6, 0x021B800D;
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CHECKREG r7, 0x021BB550;
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// The result accumulated in A , and stored to a reg half (MNOP)
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imm32 r0, 0x63548abd;
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imm32 r1, 0x7dbcfec7;
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imm32 r2, 0xa1245679;
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imm32 r3, 0xb0069007;
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imm32 r4, 0xcfbc4569;
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imm32 r5, 0xd235c00b;
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imm32 r6, 0xe00ca00d;
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imm32 r7, 0x678e700f;
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R0.H = ( A1 = R1.L * R0.L ) (T);
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R1 = A1.w;
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R2.H = ( A1 += R2.L * R3.H ) (T);
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R3 = A1.w;
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R4.H = ( A1 = R4.H * R5.L ) (T);
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R5 = A1.w;
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R6.H = ( A1 = R6.H * R7.H ) (T);
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R7 = A1.w;
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CHECKREG r0, 0x011E8ABD;
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CHECKREG r1, 0x011EBDD6;
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CHECKREG r2, 0xCB175679;
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CHECKREG r3, 0xCB172B82;
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CHECKREG r4, 0x181D4569;
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CHECKREG r5, 0x181DDA28;
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CHECKREG r6, 0xE626A00D;
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CHECKREG r7, 0xE6263550;
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// The result accumulated in A , and stored to a reg half (MNOP)
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imm32 r0, 0x5354babd;
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imm32 r1, 0x6dbcdec7;
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imm32 r2, 0x7124e679;
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imm32 r3, 0x80067007;
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imm32 r4, 0x9fbc4569;
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imm32 r5, 0xa235900b;
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imm32 r6, 0xb00c300d;
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imm32 r7, 0xc78ea00f;
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R0.H = A1 , A0 = R1.L * R0.L (T);
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R1 = A1.w;
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R2.H = A1 , A0 = R2.H * R3.L (T);
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R3 = A1.w;
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R4.H = A1 , A0 = R4.H * R5.H (T);
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R5 = A1.w;
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R6.H = A1 , A0 += R6.L * R7.H (T);
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R7 = A1.w;
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CHECKREG r0, 0xE626BABD;
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CHECKREG r1, 0xE6263550;
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CHECKREG r2, 0xE626E679;
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CHECKREG r3, 0xE6263550;
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CHECKREG r4, 0xE6264569;
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CHECKREG r5, 0xE6263550;
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CHECKREG r6, 0xE626300D;
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CHECKREG r7, 0xE6263550;
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// The result accumulated in A , and stored to a reg half
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imm32 r0, 0x33545abd;
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imm32 r1, 0x5dbcfec7;
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imm32 r2, 0x71245679;
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imm32 r3, 0x90060007;
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imm32 r4, 0xafbc4569;
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imm32 r5, 0xd235900b;
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imm32 r6, 0xc00ca00d;
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imm32 r7, 0x678ed00f;
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R0.H = ( A1 = R1.L * R0.L ) (M), A0 += R1.L * R0.L (T);
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R1 = A1.w;
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R2.H = ( A1 += R2.L * R3.H ) (M), A0 = R2.H * R3.L (T);
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R3 = A0.w;
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R4.H = ( A1 += R4.H * R5.L ) (M), A0 = R4.H * R5.H (T);
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R5 = A1.w;
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R6.H = ( A1 = R6.H * R7.H ) (M), A0 += R6.L * R7.H (T);
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R7 = A0.w;
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CHECKREG r0, 0xFF915ABD;
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CHECKREG r1, 0xFF910EEB;
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CHECKREG r2, 0x30375679;
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CHECKREG r3, 0x00062FF8;
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CHECKREG r4, 0x030D4569;
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CHECKREG r5, 0x030D72D5;
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CHECKREG r6, 0xE621A00D;
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CHECKREG r7, 0xCF173844;
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// The result accumulated in A1 MM=0, and stored to a reg half (MNOP)
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imm32 r0, 0x83545abd;
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imm32 r1, 0xa8bcfec7;
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imm32 r2, 0xc1845679;
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imm32 r3, 0x1c080007;
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imm32 r4, 0xe1cc8569;
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imm32 r5, 0x921c080b;
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imm32 r6, 0x7901908d;
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imm32 r7, 0x679e9008;
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R0.H = ( A1 += R1.L * R0.L ) (M,T);
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R1 = A1.w;
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R2.H = ( A1 = R2.L * R3.H ) (M,T);
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R3 = A1.w;
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R4.H = ( A1 += R4.H * R5.L ) (M,T);
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R5 = A1.w;
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R6.H = ( A1 = R6.H * R7.H ) (M,T);
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R7 = A1.w;
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CHECKREG r0, 0xE5B25ABD;
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CHECKREG r1, 0xE5B26993;
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CHECKREG r2, 0x09775679;
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CHECKREG r3, 0x0977EFC8;
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CHECKREG r4, 0x08858569;
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CHECKREG r5, 0x0885038C;
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CHECKREG r6, 0x30FA908D;
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CHECKREG r7, 0x30FA159E;
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imm32 r0, 0x03545abd;
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imm32 r1, 0xb0bcfec7;
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imm32 r2, 0xc1048679;
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imm32 r3, 0xd0009007;
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imm32 r4, 0xefbc0569;
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imm32 r5, 0xcd35510b;
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imm32 r6, 0xe00c802d;
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imm32 r7, 0xf78e9003;
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R0.H = ( A1 -= R1.L * R0.L ), A0 = R1.L * R0.L (T);
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R1 = A1.w;
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R2.H = ( A1 = R2.L * R3.H ), A0 -= R2.H * R3.L (T);
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R3 = A1.w;
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R4.H = ( A1 -= R4.H * R5.L ), A0 += R4.H * R5.H (T);
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R5 = A1.w;
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R6.H = ( A1 += R6.H * R7.H ), A0 -= R6.L * R7.H (T);
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R7 = A1.w;
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CHECKREG r0, 0x31D75ABD;
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CHECKREG r1, 0x31D7F7C8;
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CHECKREG r2, 0x2D928679;
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CHECKREG r3, 0x2D92A000;
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CHECKREG r4, 0x37DF0569;
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CHECKREG r5, 0x37DF0DD8;
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CHECKREG r6, 0x39FA802D;
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CHECKREG r7, 0x39FAC328;
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// The result accumulated in A , and stored to a reg half (MNOP)
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imm32 r0, 0x63548abd;
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imm32 r1, 0x7dbcfec7;
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imm32 r2, 0xa1245679;
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imm32 r3, 0xb0069007;
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imm32 r4, 0xcfbc4569;
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imm32 r5, 0xd235c00b;
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imm32 r6, 0xe00ca00d;
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imm32 r7, 0x678e700f;
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R0.H = ( A1 -= R1.L * R0.L ) (T);
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R1 = A1.w;
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R2.H = ( A1 -= R2.L * R3.H ) (T);
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R3 = A1.w;
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R4.H = ( A1 -= R4.H * R5.L ) (T);
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R5 = A1.w;
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R6.H = ( A1 -= R6.H * R7.H ) (T);
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R7 = A1.w;
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CHECKREG r0, 0x38DC8ABD;
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CHECKREG r1, 0x38DC0552;
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CHECKREG r2, 0x6EE35679;
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CHECKREG r3, 0x6EE397A6;
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CHECKREG r4, 0x56C54569;
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CHECKREG r5, 0x56C5BD7E;
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CHECKREG r6, 0x709FA00D;
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CHECKREG r7, 0x709F882E;
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// The result accumulated in A , and stored to a reg half (MNOP)
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imm32 r0, 0x5354babd;
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imm32 r1, 0x6dbcdec7;
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imm32 r2, 0x7124e679;
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imm32 r3, 0x80067007;
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imm32 r4, 0x9fbc4569;
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imm32 r5, 0xa235900b;
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imm32 r6, 0xb00c300d;
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imm32 r7, 0xc78ea00f;
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R0.H = A1 , A0 -= R1.L * R0.L (T);
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R1 = A1.w;
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R2.H = A1 , A0 -= R2.H * R3.L (T);
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R3 = A1.w;
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R4.H = A1 , A0 -= R4.H * R5.H (T);
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R5 = A1.w;
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R6.H = A1 , A0 -= R6.L * R7.H (T);
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R7 = A1.w;
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CHECKREG r0, 0x709FBABD;
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CHECKREG r1, 0x709F882E;
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CHECKREG r2, 0x709FE679;
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CHECKREG r3, 0x709F882E;
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CHECKREG r4, 0x709F4569;
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CHECKREG r5, 0x709F882E;
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CHECKREG r6, 0x709F300D;
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CHECKREG r7, 0x709F882E;
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// The result accumulated in A , and stored to a reg half
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imm32 r0, 0x33545abd;
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imm32 r1, 0x5dbcfec7;
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imm32 r2, 0x71245679;
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imm32 r3, 0x90060007;
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imm32 r4, 0xafbc4569;
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imm32 r5, 0xd235900b;
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imm32 r6, 0xc00ca00d;
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imm32 r7, 0x678ed00f;
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R0.H = ( A1 -= R1.L * R0.L ) (M), A0 += R1.L * R0.L (T);
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R1 = A1.w;
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R2.H = ( A1 -= R2.L * R3.H ) (M), A0 -= R2.H * R3.L (T);
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R3 = A0.w;
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R4.H = ( A1 += R4.H * R5.L ) (M), A0 -= R4.H * R5.H (T);
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R5 = A1.w;
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R6.H = ( A1 += R6.H * R7.H ) (M), A0 -= R6.L * R7.H (T);
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R7 = A0.w;
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CHECKREG r0, 0x710E5ABD;
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CHECKREG r1, 0x710E7943;
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CHECKREG r2, 0x40685679;
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CHECKREG r3, 0x1ED0EB56;
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CHECKREG r4, 0x133E4569;
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CHECKREG r5, 0x133EAF81;
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CHECKREG r6, 0xF960A00D;
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CHECKREG r7, 0x4FB9B312;
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// The result accumulated in A1 MM=0, and stored to a reg half (MNOP)
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imm32 r0, 0x83545abd;
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imm32 r1, 0xa8bcfec7;
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imm32 r2, 0xc1845679;
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imm32 r3, 0x1c080007;
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imm32 r4, 0xe1cc8569;
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imm32 r5, 0x921c080b;
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imm32 r6, 0x7901908d;
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imm32 r7, 0x679e9008;
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R0.H = ( A1 -= R1.L * R0.L ) (M,T);
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R1 = A1.w;
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R2.H = ( A1 -= R2.L * R3.H ) (M,T);
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R3 = A1.w;
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R4.H = ( A1 -= R4.H * R5.L ) (M,T);
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R5 = A1.w;
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R6.H = ( A1 -= R6.H * R7.H ) (M,T);
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R7 = A1.w;
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CHECKREG r0, 0xF9CE5ABD;
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CHECKREG r1, 0xF9CEFB3E;
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CHECKREG r2, 0xF0575679;
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CHECKREG r3, 0xF0570B76;
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CHECKREG r4, 0xF1498569;
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CHECKREG r5, 0xF149F7B2;
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CHECKREG r6, 0xC04F908D;
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CHECKREG r7, 0xC04FE214;
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pass
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