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166 lines
2.7 KiB
ArmAsm
166 lines
2.7 KiB
ArmAsm
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//Original:/proj/frio/dv/testcases/core/c_ldimmhalf_l_ibml/c_ldimmhalf_l_ibml.dsp
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// Spec Reference: ldimmhalf l ibml
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# mach: bfin
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.include "testutils.inc"
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start
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INIT_I_REGS -1;
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INIT_L_REGS -1;
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INIT_M_REGS -1;
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INIT_B_REGS -1;
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I0.L = 0x2001;
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I1.L = 0x2003;
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I2.L = 0x2005;
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I3.L = 0x2007;
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L0.L = 0x2009;
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L1.L = 0x200b;
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L2.L = 0x200d;
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L3.L = 0x200f;
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R0 = I0;
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R1 = I1;
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R2 = I2;
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R3 = I3;
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R4 = L0;
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R5 = L1;
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R6 = L2;
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R7 = L3;
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CHECKREG r0, 0xffff2001;
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CHECKREG r1, 0xffff2003;
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CHECKREG r2, 0xffff2005;
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CHECKREG r3, 0xffff2007;
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CHECKREG r4, 0xffff2009;
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CHECKREG r5, 0xffff200b;
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CHECKREG r6, 0xffff200d;
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CHECKREG r7, 0xffff200f;
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I0.L = 0x0111;
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I1.L = 0x1111;
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I2.L = 0x2222;
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I3.L = 0x3333;
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L0.L = 0x4444;
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L1.L = 0x5555;
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L2.L = 0x6666;
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L3.L = 0x7777;
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R0 = I0;
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R1 = I1;
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R2 = I2;
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R3 = I3;
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R4 = L0;
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R5 = L1;
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R6 = L2;
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R7 = L3;
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CHECKREG r0, 0xffff0111;
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CHECKREG r1, 0xffff1111;
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CHECKREG r2, 0xffff2222;
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CHECKREG r3, 0xffff3333;
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CHECKREG r4, 0xffff4444;
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CHECKREG r5, 0xffff5555;
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CHECKREG r6, 0xffff6666;
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CHECKREG r7, 0xffff7777;
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I0.L = 0x8888;
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I1.L = 0x9aaa;
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I2.L = 0xabbb;
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I3.L = 0xbccc;
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L0.L = 0xcddd;
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L1.L = 0xdeee;
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L2.L = 0xefff;
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L3.L = 0xf111;
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R0 = I0;
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R1 = I1;
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R2 = I2;
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R3 = I3;
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R4 = L0;
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R5 = L1;
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R6 = L2;
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R7 = L3;
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CHECKREG r0, 0xffff8888;
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CHECKREG r1, 0xffff9aaa;
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CHECKREG r2, 0xffffabbb;
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CHECKREG r3, 0xffffbccc;
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CHECKREG r4, 0xffffcddd;
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CHECKREG r5, 0xffffdeee;
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CHECKREG r6, 0xffffefff;
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CHECKREG r7, 0xfffff111;
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B0.L = 0x3001;
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B1.L = 0x3003;
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B2.L = 0x3005;
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B3.L = 0x3007;
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M0.L = 0x3009;
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M1.L = 0x300b;
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M2.L = 0x300d;
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M3.L = 0x300f;
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R0 = B0;
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R1 = B1;
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R2 = B2;
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R3 = B3;
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R4 = M0;
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R5 = M1;
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R6 = M2;
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R7 = M3;
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CHECKREG r0, 0xffff3001;
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CHECKREG r1, 0xffff3003;
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CHECKREG r2, 0xffff3005;
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CHECKREG r3, 0xffff3007;
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CHECKREG r4, 0xffff3009;
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CHECKREG r5, 0xffff300B;
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CHECKREG r6, 0xffff300d;
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CHECKREG r7, 0xffff300f;
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B0.L = 0x0110;
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B1.L = 0x1110;
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B2.L = 0x2220;
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B3.L = 0x3330;
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M0.L = 0x4440;
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M1.L = 0x5550;
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M2.L = 0x6660;
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M3.L = 0x7770;
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R0 = B0;
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R1 = B1;
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R2 = B2;
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R3 = B3;
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R4 = M0;
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R5 = M1;
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R6 = M2;
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R7 = M3;
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CHECKREG r0, 0xffff0110;
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CHECKREG r1, 0xffff1110;
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CHECKREG r2, 0xffff2220;
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CHECKREG r3, 0xffff3330;
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CHECKREG r4, 0xffff4440;
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CHECKREG r5, 0xffff5550;
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CHECKREG r6, 0xffff6660;
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CHECKREG r7, 0xffff7770;
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B0.L = 0xf880;
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B1.L = 0xfaa0;
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B2.L = 0xfbb0;
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B3.L = 0xfcc0;
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M0.L = 0xfdd0;
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M1.L = 0xfee0;
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M2.L = 0xfff0;
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M3.L = 0xf110;
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R0 = B0;
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R1 = B1;
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R2 = B2;
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R3 = B3;
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R4 = M0;
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R5 = M1;
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R6 = M2;
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R7 = M3;
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CHECKREG r0, 0xfffff880;
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CHECKREG r1, 0xfffffaa0;
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CHECKREG r2, 0xfffffbb0;
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CHECKREG r3, 0xfffffcc0;
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CHECKREG r4, 0xfffffdd0;
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CHECKREG r5, 0xfffffee0;
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CHECKREG r6, 0xfffffff0;
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CHECKREG r7, 0xfffff110;
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pass
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