mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-12-27 04:52:05 +08:00
213 lines
6.0 KiB
ArmAsm
213 lines
6.0 KiB
ArmAsm
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//Original:/testcases/core/c_dsp32mult_dr_tu/c_dsp32mult_dr_tu.dsp
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// Spec Reference: dsp32mult single dr tu
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# mach: bfin
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.include "testutils.inc"
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start
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imm32 r0, 0x8b235625;
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imm32 r1, 0x98ba5127;
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imm32 r2, 0xa3846725;
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imm32 r3, 0x00080027;
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imm32 r4, 0xb0ab8d29;
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imm32 r5, 0x10ace82b;
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imm32 r6, 0xc00c008d;
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imm32 r7, 0xd2467028;
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R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (TFU);
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R5.H = R0.L * R1.L, R5.L = R0.L * R1.H (TFU);
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R6.H = R1.L * R0.L, R6.L = R1.H * R0.L (TFU);
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R7.H = R1.L * R1.L, R7.L = R1.H * R1.H (TFU);
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R0.H = R0.L * R0.L, R0.L = R0.L * R0.L (TFU);
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R1.H = R0.L * R1.L, R1.L = R0.L * R1.H (TFU);
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R2.H = R1.L * R0.L, R2.L = R1.H * R0.L (TFU);
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R3.H = R1.L * R1.L, R3.L = R1.H * R1.H (TFU);
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CHECKREG r0, 0x1CFC1CFC;
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CHECKREG r1, 0x0930114A;
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CHECKREG r2, 0x01F5010A;
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CHECKREG r3, 0x012A0054;
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CHECKREG r4, 0x1CFC1CFC;
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CHECKREG r5, 0x1B4E3364;
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CHECKREG r6, 0x1B4E3364;
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CHECKREG r7, 0x19B95B1D;
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imm32 r0, 0x9923a635;
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imm32 r1, 0x6f995137;
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imm32 r2, 0x1324b735;
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imm32 r3, 0x99060037;
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imm32 r4, 0x809bcd39;
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imm32 r5, 0xb0a99f3b;
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imm32 r6, 0xa00c093d;
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imm32 r7, 0x12467093;
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R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (TFU);
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R5.H = R2.L * R3.H, R5.L = R2.H * R3.H (TFU);
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R6.H = R3.L * R2.L, R6.L = R3.L * R2.H (TFU);
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R7.H = R3.L * R3.H, R7.L = R3.L * R3.H (TFU);
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R2.H = R2.L * R2.H, R2.L = R2.H * R2.L (TFU);
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R3.H = R2.L * R3.H, R3.L = R2.H * R3.H (TFU);
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R0.H = R3.L * R2.H, R0.L = R3.L * R2.L (TFU);
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R1.H = R3.L * R3.H, R1.L = R3.L * R3.H (TFU);
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CHECKREG r0, 0x00700070;
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CHECKREG r1, 0x00420042;
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CHECKREG r2, 0x0DB20DB2;
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CHECKREG r3, 0x082F082F;
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CHECKREG r4, 0x0DB20DB2;
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CHECKREG r5, 0x6D820B70;
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CHECKREG r6, 0x00270004;
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CHECKREG r7, 0x00200020;
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imm32 r0, 0x19235655;
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imm32 r1, 0xc9ba5157;
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imm32 r2, 0x63246755;
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imm32 r3, 0x0a060055;
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imm32 r4, 0x90abc509;
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imm32 r5, 0x10acef5b;
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imm32 r6, 0xb00a005d;
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imm32 r7, 0x1246a05f;
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R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (TFU);
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R1.H = R4.H * R5.L, R1.L = R4.L * R5.H (TFU);
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R2.H = R5.H * R4.L, R2.L = R5.H * R4.L (TFU);
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R3.H = R5.L * R5.L, R3.L = R5.H * R5.H (TFU);
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R4.H = R4.H * R4.L, R4.L = R4.L * R4.L (TFU);
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R5.H = R4.H * R5.L, R5.L = R4.L * R5.L (TFU);
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R6.H = R5.L * R4.L, R6.L = R5.H * R4.L (TFU);
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R7.H = R5.H * R5.L, R7.L = R5.H * R5.H (TFU);
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CHECKREG r0, 0x6F5897A6;
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CHECKREG r1, 0x87430CD4;
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CHECKREG r2, 0x0CD40CD4;
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CHECKREG r3, 0xDFCB0115;
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CHECKREG r4, 0x6F5897A6;
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CHECKREG r5, 0x681A8DC9;
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CHECKREG r6, 0x53FD3DAA;
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CHECKREG r7, 0x39A82A55;
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imm32 r0, 0xbb235666;
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imm32 r1, 0xefba5166;
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imm32 r2, 0x13248766;
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imm32 r3, 0xe0060066;
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imm32 r4, 0x9eab9d69;
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imm32 r5, 0x10ecef6b;
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imm32 r6, 0x800ee06d;
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imm32 r7, 0x12467e6f;
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// test the unsigned U=1
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R0.H = R6.H * R6.H, R0.L = R6.L * R6.L (TFU);
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R1.H = R6.H * R7.H, R1.L = R6.L * R7.H (TFU);
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R2.H = R7.H * R6.H, R2.L = R7.H * R6.L (TFU);
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R3.H = R7.H * R7.H, R3.L = R7.H * R7.H (TFU);
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R6.H = R6.H * R6.H, R6.L = R6.L * R6.L (TFU);
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R7.H = R6.H * R7.H, R7.L = R6.L * R7.H (TFU);
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R4.H = R7.H * R6.H, R4.L = R7.H * R6.L (TFU);
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R5.H = R7.H * R7.H, R5.L = R7.H * R7.H (TFU);
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CHECKREG r0, 0x400EC4BE;
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CHECKREG r1, 0x09231005;
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CHECKREG r2, 0x09231005;
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CHECKREG r3, 0x014D014D;
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CHECKREG r4, 0x01240383;
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CHECKREG r5, 0x00140014;
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CHECKREG r6, 0x400EC4BE;
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CHECKREG r7, 0x04920E0B;
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// mix order
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imm32 r0, 0xac23a675;
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imm32 r1, 0xcfba5127;
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imm32 r2, 0x13c46705;
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imm32 r3, 0x00060007;
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imm32 r4, 0x90accd09;
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imm32 r5, 0x10acdfdb;
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imm32 r6, 0x000cc00d;
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imm32 r7, 0x1246fc0f;
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R2.H = R0.L * R7.L, R2.L = R0.H * R7.H (TFU);
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R5.H = R1.L * R6.L, R5.L = R1.L * R6.H (TFU);
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R6.H = R2.H * R5.L, R6.L = R2.H * R5.L (TFU);
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R7.H = R3.L * R4.L, R7.L = R3.L * R4.L (TFU);
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R0.H = R4.L * R3.L, R0.L = R4.L * R3.L (TFU);
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R1.H = R5.H * R2.L, R1.L = R5.H * R2.L (TFU);
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R3.H = R6.L * R1.L, R3.L = R6.L * R1.L (TFU);
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R4.H = R7.H * R0.L, R4.L = R7.H * R0.H (TFU);
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CHECKREG r0, 0x00050005;
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CHECKREG r1, 0x02EB02EB;
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CHECKREG r2, 0xA3E40C49;
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CHECKREG r3, 0x00000000;
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CHECKREG r4, 0x00000000;
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CHECKREG r5, 0x3CE10003;
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CHECKREG r6, 0x00010001;
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CHECKREG r7, 0x00050005;
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imm32 r0, 0xab235a75;
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imm32 r1, 0xcfba5127;
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imm32 r2, 0xdd246905;
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imm32 r3, 0x00d6d007;
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imm32 r4, 0x90abcd09;
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imm32 r5, 0x10aceddb;
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imm32 r6, 0x000c0d0d;
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imm32 r7, 0x1246700f;
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R0.H = R7.H * R0.H, R0.L = R7.H * R0.L (TFU);
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R1.H = R6.H * R1.H, R1.L = R6.L * R1.L (TFU);
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R2.H = R5.H * R2.H, R2.L = R5.H * R2.L (TFU);
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R3.H = R4.H * R3.H, R3.L = R4.H * R3.L (TFU);
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R4.H = R3.H * R4.H, R4.L = R3.H * R4.L (TFU);
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R5.H = R2.H * R5.H, R5.L = R2.H * R5.L (TFU);
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R6.H = R1.H * R6.H, R6.L = R1.H * R6.L (TFU);
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R7.H = R0.L * R7.H, R7.L = R0.H * R7.H (TFU);
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CHECKREG r0, 0x0C370674;
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CHECKREG r1, 0x00090423;
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CHECKREG r2, 0x0E6606D6;
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CHECKREG r3, 0x0078758E;
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CHECKREG r4, 0x00430060;
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CHECKREG r5, 0x00F00D60;
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CHECKREG r6, 0x00000000;
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CHECKREG r7, 0x007500DF;
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imm32 r0, 0xfb235675;
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imm32 r1, 0xcfba5127;
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imm32 r2, 0x13f46705;
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imm32 r3, 0x000f0007;
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imm32 r4, 0x90abfd09;
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imm32 r5, 0x10acefdb;
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imm32 r6, 0x000c00fd;
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imm32 r7, 0x1246700f;
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R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (TFU);
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R3.H = R2.H * R7.H, R3.L = R2.H * R7.L (TFU);
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R0.H = R1.L * R0.L, R0.L = R1.H * R0.H (TFU);
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R1.H = R3.L * R0.L, R1.L = R3.H * R0.H (TFU);
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R4.H = R4.L * R2.L, R4.L = R4.H * R2.H (TFU);
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R5.H = R5.L * R3.H, R5.L = R5.H * R3.L (TFU);
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R6.H = R6.H * R4.L, R6.L = R6.L * R4.H (TFU);
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R7.H = R7.L * R6.L, R7.L = R7.H * R6.H (TFU);
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CHECKREG r0, 0x1B68CBC7;
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CHECKREG r1, 0x001D0000;
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CHECKREG r2, 0x00550004;
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CHECKREG r3, 0x00060025;
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CHECKREG r4, 0x00030030;
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CHECKREG r5, 0x00050002;
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CHECKREG r6, 0x00000000;
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CHECKREG r7, 0x00000000;
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imm32 r0, 0xab2d5675;
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imm32 r1, 0xcfbad127;
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imm32 r2, 0x13246d05;
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imm32 r3, 0x000600d7;
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imm32 r4, 0x908bcd09;
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imm32 r5, 0x10a9efdb;
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imm32 r6, 0x000c500d;
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imm32 r7, 0x1246760f;
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R4.H = R5.L * R2.L, R4.L = R5.L * R2.H (TFU);
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R6.H = R6.H * R3.L, R6.L = R6.H * R3.L (TFU);
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R0.H = R7.L * R4.L, R0.L = R7.L * R4.H (TFU);
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R1.H = R0.L * R5.H, R1.L = R0.L * R5.L (TFU);
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R2.H = R1.L * R6.L, R2.L = R1.H * R6.H (TFU);
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R5.H = R2.L * R7.H, R5.L = R2.H * R7.L (TFU);
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R3.H = R3.L * R0.L, R3.L = R3.L * R0.L (TFU);
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R7.H = R4.H * R1.L, R7.L = R4.H * R1.L (TFU);
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CHECKREG r0, 0x08442F1A;
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CHECKREG r1, 0x03102C21;
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CHECKREG r2, 0x00000000;
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CHECKREG r3, 0x00270027;
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CHECKREG r4, 0x662411EE;
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CHECKREG r5, 0x00000000;
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CHECKREG r6, 0x00000000;
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CHECKREG r7, 0x119B119B;
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pass
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