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binutils-gdb/sim/testsuite/mips/r6-branch.s

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sim: mips: Add simulator support for mips32r6/mips64r6 2022-02-01 Ali Lown <ali.lown@imgtec.com> Andrew Bennett <andrew.bennett@imgtec.com> Dragan Mladjenovic <dragan.mladjenovic@rt-rk.com> Faraz Shahbazker <fshahbazker@wavecomp.com> sim/common/ChangeLog: * sim-bits.h (EXTEND9, EXTEND18 ,EXTEND19, EXTEND21, EXTEND26): New macros. sim/mips/ChangeLog: * Makefile.in (IGEN_INCLUDE): Add mips3264r6.igen. * configure: Regenerate. * configure.ac: Support mipsisa32r6 and mipsisa64r6. (sim_engine_run): Pick simulator model from processor specified in e_flags. * cp1.c (value_fpr): Handle fmt_dc32. (fp_unary, fp_binary): Zero initialize locals. (update_fcsr, fp_classify, fp_rint, fp_r6_cmp, inner_fmac, fp_fmac, fp_min, fp_max, fp_mina, fp_maxa, fp_fmadd, fp_fmsub): New functions. (sim_fpu_class_mips_mapping): New. * cp1.h (fcsr_ABS2008_mask, fcsr_ABS2008_shift): New define. * interp.c (MIPSR6_P): New. (load_word): Allow unaligned memory access for MIPSR6. * micromips.igen (sc, scd): Adapt to new do_sc* helper signature. * mips.igen: Add *r6 models. (signal_if_cti, forbiddenslot32): New helpers. (delayslot32): Use signal_if_cti. (do_sc, do_scd); Add store_ll_bit parameter. (sc, scd): Adapt to previous change. (nal, beq, bal): New definitions for *r6. (sll): Split nop and ssnop cases into ... (nop, ssnop): New definitions. (loadstore_ea): Use the 32-bit compatibility adressing. (cache): Split logic into ... (do_cache): New helper. (check_fpu): Select IEEE 754-2008 mode for R6. (not_word_value, unpredictable, check_mt_hilo, check_mf_hilo, check_multi_hilo, check_div_hilo, check_u64, do_dmfc1b, add, li, addu, and, andi, bgez, bgtz, blez, bltz, bne, break, dadd, daddiu, daddu, dror, dror32, drorv, dsll, dsll32, dsllv, dsra, dsra32, dsrav, dsrl, dsrl32, dsub, dsubu, j, jal, jalr, jalr.hb, lb, lbu, ld, lh, lhu, lui, lw, lwu, nor, or, ori, ror, rorv, sb, sd, sh, sll, sllv, slt, slti, sltiu, sltu, sra, srav, srl, srlv, sub, subu, sw, sync, syscall, teq, tge, tgeu, tlt, tltu, tne, xor, xori, check_fmt_p, do_load_double, do_store_double, abs.FMT, add.FMT, ceil.l.FMT, ceil.w.FMT, cfc1, ctc1, cvt.d.FMT, cvt.l.FMT, cvt.w.FMT, div.FMT, dfmc1, dmtc1, floor.l.FMT, floor.w.FMT, ldc1, lwc1, mfc1, mov.FMT, mtc1, mul.FMT, recip.FMT, round.l.FMT, round.w.FMT, rsqrt.FMT, sdc1, sqrt.FMT, sub.FMT, swc1, trunc.l.FMT, trunc.w.FMT, bc0f, bc0fl, bc0t, bc0tl, dmfc0, dmtc0, eret, mfc0, mtc0, cop, tlbp, tlbr, tlbwi, tlbwr): Enable on *r6 models. * mips3264r2.igen (dext, dextm, dextu, di, dins, dinsm, dinsu, dsbh, dshd, ei, ext, mfhc1, mthc1, ins, seb, seh, synci, rdhwr, wsbh): Likewise. * mips3264r6.igen: New file. * sim-main.h (FP_formats): Add fmt_dc32. (FORBIDDEN_SLOT): New macros. (simFORBIDDENSLOT, FP_R6CMP_*, FP_R6CLASS_*): New defines. (fp_r6_cmp, fp_classify, fp_rint, fp_min, fp_max, fp_mina, fp_maxa, fp_fmadd, fp_fmsub): New declarations. (R6Compare, Classify, RoundToIntegralExact, Min, Max, MinA, MaxA, FusedMultiplyAdd, FusedMultiplySub): New macros. Wrapping previous declarations. sim/testsuite/mips/ChangeLog: * basic.exp: Add r6-*.s tests. (run_r6_removed_test): New function. (run_endian_tests): New function. * hilo-hazard-3.s: Skip for mips*r6. * r2-fpu.s: New test. * r6-64.s: New test. * r6-branch.s: New test. * r6-forbidden.s: New test. * r6-fpu.s: New test. * r6-llsc-dp.s: New test. * r6-llsc-wp.s: New test. * r6-removed.csv: New test. * r6-removed.s: New test. * r6.s: New test. * utils-r6.inc: New inc.
2022-02-02 18:17:25 +08:00
# mips r6 branch tests (non FPU)
# mach: mips32r6 mips64r6
# as: -mabi=eabi
# ld: -N -Ttext=0x80010000
# output: *\\npass\\n
.include "testutils.inc"
.include "utils-r6.inc"
setup
.set noreorder
.ent DIAG
DIAG:
li $14, 0xffffffff
li $13, 0x123
li $12, 0x45
li $7, 0x45
li $8, 0xfffffffe
li $9, 2147483647
li $11, 0
writemsg "[1] Test BOVC"
bovc $12, $13, Lfail
nop
bovc $9, $13, L2
nop
fail
L2:
writemsg "[2] Test BNVC"
bnvc $9, $13, Lfail
nop
bnvc $12, $13, L3
nop
fail
L3:
writemsg "[3] Test BEQC"
beqc $12, $13, Lfail
nop
beqc $12, $7, L4
nop
fail
L4:
writemsg "[4] Test BNEC"
bnec $12, $7, Lfail
nop
bnec $12, $13, L5
nop
fail
L5:
writemsg "[5] Test BLTC"
bltc $13, $12, Lfail
nop
bltc $12, $13, L6
nop
fail
L6:
# writemsg "[6] Test BLEC"
# blec $13, $12, Lfail
# nop
# blec $7, $12, L7
# nop
# fail
L7:
writemsg "[7] Test BGEC"
bgec $12, $13, Lfail
nop
bgec $13, $12, L8
nop
fail
L8:
# writemsg "[8] Test BGTC"
# bgtc $12, $13, Lfail
# nop
# bgtc $13, $12, L9
# nop
# fail
L9:
writemsg "[9] Test BLTUC"
bltuc $14, $13, Lfail
nop
bltuc $8, $14, L10
nop
fail
L10:
# writemsg "[10] Test BLEUC"
# bleuc $14, $13, Lfail
# nop
# bleuc $8, $14, L11
# nop
# fail
L11:
writemsg "[11] Test BGEUC"
bgeuc $13, $14, Lfail
nop
bgeuc $14, $8, L12
nop
fail
L12:
# writemsg "[12] Test BGTUC"
# bgtuc $13, $14, Lfail
# nop
# bgtuc $14, $8, L13
# nop
# fail
L13:
writemsg "[13] Test BLTZC"
bltzc $13, Lfail
nop
bltzc $11, Lfail
nop
bltzc $14, L14
nop
fail
L14:
writemsg "[14] Test BLEZC"
blezc $13, Lfail
nop
blezc $11, L145
nop
fail
L145:
blezc $14, L15
nop
fail
L15:
writemsg "[15] Test BGEZC"
bgezc $8, Lfail
nop
bgezc $11, L155
nop
fail
L155:
bgezc $13, L16
nop
fail
L16:
writemsg "[16] Test BGTZC"
bgtzc $8, Lfail
nop
bgtzc $11, Lfail
nop
bgtzc $13, L17
nop
fail
li $10, 0
L17:
writemsg "[17] Test BLEZALC"
blezalc $12, Lfail
nop
blezalc $11, Lret
li $10, 1
beqzc $10, L175
nop
fail
L175:
blezalc $14, Lret
li $10, 1
beqzc $10, L18
nop
fail
L18:
writemsg "[18] Test BGEZALC"
bgezalc $14, Lfail
nop
bgezalc $11, Lret
li $10, 1
beqzc $10, L185
nop
fail
L185:
bgezalc $12, Lret
li $10, 1
beqzc $10, L19
nop
fail
L19:
writemsg "[19] Test BGTZALC"
bgtzalc $14, Lfail
nop
bgtzalc $11, Lfail
nop
bgtzalc $12, Lret
li $10, 1
beqzc $10, L20
nop
fail
L20:
writemsg "[20] Test BLTZALC"
bltzalc $12, Lfail
nop
bltzalc $11, Lfail
nop
bltzalc $14, Lret
li $10, 1
beqzc $10, L21
nop
fail
L21:
writemsg "[21] Test BC"
bc L22
fail
L22:
writemsg "[22] Test BALC"
balc Lret
li $10, 1
beqzc $10, L23
nop
fail
L23:
writemsg "[23] Test JIC"
jal GetPC
nop
jic $6, 4
nop
fail
L24:
writemsg "[24] Test JIALC"
li $10, 1
jal GetPC
nop
jialc $6, 20
nop
beqzc $10, L25
nop
fail
LJIALCRET:
li $10, 0
jr $ra
nop
L25:
writemsg "[25] Test NAL"
jal GetPC
nop
move $11, $6
nal
nop
addiu $11, 12
beqc $11, $31, L26
nop
fail
L26:
writemsg "[26] Test BAL"
balc Lret
li $10, 1
beqzc $10, Lend
nop
fail
Lend:
pass
Lfail:
fail
.end DIAG
Lret:
li $10, 0
addiu $ra, 4
jr $ra
nop
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