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binutils-gdb/sim/riscv/interp.c

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sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
/* RISC-V simulator.
Copyright (C) 2005-2021 Free Software Foundation, Inc.
Contributed by Mike Frysinger.
This file is part of simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
sim: switch config.h usage to defs.h The defs.h header will take care of including the various config.h headers. For now, it's just config.h, but we'll add more when we integrate gnulib in. This header should be used instead of config.h, and should be the first include in every .c file. We won't rely on the old behavior where we expected files to include the port's sim-main.h which then includes the common sim-basics.h which then includes config.h. We have a ton of code that includes things before sim-main.h, and it sometimes needs to be that way. Creating a dedicated header avoids the ordering mess and implicit inclusion that shows up otherwise.
2021-05-02 06:05:23 +08:00
/* This must come before any other includes. */
#include "defs.h"
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
#include "sim-main.h"
#include "sim-options.h"
void
sim_engine_run (SIM_DESC sd,
int next_cpu_nr, /* ignore */
int nr_cpus, /* ignore */
int siggnal) /* ignore */
{
SIM_CPU *cpu;
SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
cpu = STATE_CPU (sd, 0);
while (1)
{
step_once (cpu);
if (sim_events_tick (sd))
sim_events_process (sd);
}
}
static void
free_state (SIM_DESC sd)
{
if (STATE_MODULES (sd) != NULL)
sim_module_uninstall (sd);
sim_cpu_free_all (sd);
sim_state_free (sd);
}
sim: namespace sim_machs We want to do a single build with all arches in one binary which means we need to namespace sim_machs on a per-arch basis. Move it from a global variable to the sim description structure so it can be setup at runtime. Changing the SIM_MODEL->num from an enum to an int is unfortunate, but we specifically don't want to maintain a centralized list anymore, and this was never used directly in common code, just passed to per-arch callbacks.
2021-06-29 09:42:56 +08:00
extern const SIM_MACH * const riscv_sim_machs[];
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
SIM_DESC
sim_open (SIM_OPEN_KIND kind, host_callback *callback,
struct bfd *abfd, char * const *argv)
{
char c;
int i;
sim: riscv: invert sim_state storage
2021-05-13 17:44:02 +08:00
SIM_DESC sd = sim_state_alloc_extra (kind, callback,
sizeof (struct riscv_sim_state));
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
sim: overhaul & unify endian settings management The m4 macro has 2 args: the "wire" settings (which represents the hardwired port behavior), and the default settings (which are used if nothing else is specified). If none are specified, the arch is expected to support both, and the value will be probed based on the user runtime options or the input program. Only two arches today set the default value (bpf & mips). We can probably let this go as it only shows up in one scenario: the sim is invoked, but with no inputs, and no user endian selection. This means bpf will not behave like the other arches: an error is shown and forces the user to make a choice. If an input program is used though, we'll still switch the default to that. This allows us to remove the WITH_DEFAULT_TARGET_BYTE_ORDER setting. For the ports that set a "wire" endian, move it to the runtime init of the respective sim_open calls. This allows us to change the WITH_TARGET_BYTE_ORDER to purely a user-selected configure setting if they want to force a specific endianness. With all the endian logic moved to runtime selection, we can move the configure call up to the common dir so we only process it once across all ports. The ppc arch was picking the wire endian based on the target used, but since we weren't doing that for other biendian arches, we can let this go too. We'll rely on the input selecting the endian, or make the user decide.
2021-06-16 07:51:52 +08:00
/* Set default options before parsing user options. */
sim: namespace sim_machs We want to do a single build with all arches in one binary which means we need to namespace sim_machs on a per-arch basis. Move it from a global variable to the sim description structure so it can be setup at runtime. Changing the SIM_MODEL->num from an enum to an int is unfortunate, but we specifically don't want to maintain a centralized list anymore, and this was never used directly in common code, just passed to per-arch callbacks.
2021-06-29 09:42:56 +08:00
STATE_MACHS (sd) = riscv_sim_machs;
sim: move default model to the runtime sim state This kills off another compile-time option by moving the setting to the individual arch runtimes. This will allow dynamic selection by the arch when doing a single build with multiple arches. The sim_model_init rework is a little funky. In the past it was disabled entirely if no default model was set. We maintain the spirit of the logic by gating the fallback logic on whether the port has defined any models.
2021-06-29 10:07:44 +08:00
STATE_MODEL_NAME (sd) = WITH_TARGET_WORD_BITSIZE == 32 ? "RV32G" : "RV64G";
sim: overhaul & unify endian settings management The m4 macro has 2 args: the "wire" settings (which represents the hardwired port behavior), and the default settings (which are used if nothing else is specified). If none are specified, the arch is expected to support both, and the value will be probed based on the user runtime options or the input program. Only two arches today set the default value (bpf & mips). We can probably let this go as it only shows up in one scenario: the sim is invoked, but with no inputs, and no user endian selection. This means bpf will not behave like the other arches: an error is shown and forces the user to make a choice. If an input program is used though, we'll still switch the default to that. This allows us to remove the WITH_DEFAULT_TARGET_BYTE_ORDER setting. For the ports that set a "wire" endian, move it to the runtime init of the respective sim_open calls. This allows us to change the WITH_TARGET_BYTE_ORDER to purely a user-selected configure setting if they want to force a specific endianness. With all the endian logic moved to runtime selection, we can move the configure call up to the common dir so we only process it once across all ports. The ppc arch was picking the wire endian based on the target used, but since we weren't doing that for other biendian arches, we can let this go too. We'll rely on the input selecting the endian, or make the user decide.
2021-06-16 07:51:52 +08:00
current_target_byte_order = BFD_ENDIAN_LITTLE;
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
/* The cpu data is kept in a separately allocated chunk of memory. */
sim: cgen: move cgen_cpu_max_extra_bytes logic into the common code Every arch handles this the same way, so move it to the common code. This will also make unifying the sim_cpu structure easier.
2016-08-12 22:12:41 +08:00
if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK)
sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better.
2015-05-21 23:16:45 +08:00
{
free_state (sd);
return 0;
}
if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
{
free_state (sd);
return 0;
}
/* XXX: Default to the Virtual environment. */
if (STATE_ENVIRONMENT (sd) == ALL_ENVIRONMENT)
STATE_ENVIRONMENT (sd) = VIRTUAL_ENVIRONMENT;
/* The parser will print an error message for us, so we silently return. */
if (sim_parse_args (sd, argv) != SIM_RC_OK)
{
free_state (sd);
return 0;
}
/* Check for/establish the a reference program image. */
if (sim_analyze_program (sd,
(STATE_PROG_ARGV (sd) != NULL
? *STATE_PROG_ARGV (sd)
: NULL), abfd) != SIM_RC_OK)
{
free_state (sd);
return 0;
}
/* Establish any remaining configuration options. */
if (sim_config (sd) != SIM_RC_OK)
{
free_state (sd);
return 0;
}
if (sim_post_argv_init (sd) != SIM_RC_OK)
{
free_state (sd);
return 0;
}
/* CPU specific initialization. */
for (i = 0; i < MAX_NR_PROCESSORS; ++i)
{
SIM_CPU *cpu = STATE_CPU (sd, i);
initialize_cpu (sd, cpu, i);
}
/* Allocate external memory if none specified by user.
Use address 4 here in case the user wanted address 0 unmapped. */
if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0)
sim_do_commandf (sd, "memory-size %#x", DEFAULT_MEM_SIZE);
return sd;
}
SIM_RC
sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
char * const *argv, char * const *env)
{
SIM_CPU *cpu = STATE_CPU (sd, 0);
SIM_ADDR addr;
/* Set the PC. */
if (abfd != NULL)
addr = bfd_get_start_address (abfd);
else
addr = 0;
sim_pc_set (cpu, addr);
/* Standalone mode (i.e. `run`) will take care of the argv for us in
sim_open() -> sim_parse_args(). But in debug mode (i.e. 'target sim'
with `gdb`), we need to handle it because the user can change the
argv on the fly via gdb's 'run'. */
if (STATE_PROG_ARGV (sd) != argv)
{
freeargv (STATE_PROG_ARGV (sd));
STATE_PROG_ARGV (sd) = dupargv (argv);
}
initialize_env (sd, (void *)argv, (void *)env);
return SIM_RC_OK;
}
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