binutils-gdb/sim/testsuite/msp430/rrux.s

# check that rrux (synthesized as rrc with ZC bit set) works.
# mach: msp430

.include "testutils.inc"

	start

	setc		; set the carry bit to ensure ZC bit is obeyed
	mov.w	#16, r10
	rrux.w	r10
	cmp.w	#8, r10
	jeq 1f
	fail
	1: pass
MSP430: Fix simulator execution of RRUX instruction The MSP430X RRUX instruction (unsigned right shift) is synthesized as the RRC (rotate right through carry) instruction, but with the ZC (zero carry) bit of the opcode extention word set. Ensure the carry flag is ignored when the ZC bit is set. sim/msp430/ChangeLog: 2020-01-22 Jozef Lawrynowicz <jozef.l@mittosystems.com> * msp430-sim.c (msp430_step_once): Ignore the carry flag when executing an RRC instruction, if the ZC bit of the extension word is set. sim/testsuite/sim/msp430/ChangeLog: 2020-01-22 Jozef Lawrynowicz <jozef.l@mittosystems.com> * rrux.s: New test. 2020-01-23 05:44:54 +08:00			`# check that rrux (synthesized as rrc with ZC bit set) works.`
			`# mach: msp430`

			`.include "testutils.inc"`

			`start`

			`setc ; set the carry bit to ensure ZC bit is obeyed`
			`mov.w #16, r10`
			`rrux.w r10`
			`cmp.w #8, r10`
			`jeq 1f`
			`fail`
			`1: pass`