binutils-gdb/ld/testsuite/ld-riscv-elf/c-lui-2.s

	.option nopic
	.text
	.align 1
	.globl _start
	.type _start, @function
_start:
	lui a0,%hi(foo)
	addi a0,a0,%lo(foo)
	.skip 0x7f8
foo:
	ret
	.size _start, .-_start
RISC-V: Fix lui relaxation issue with code at address 0. This fixes a problem originally reported at https://github.com/riscv/riscv-binutils-gdb/issues/173 If you have code linked at address zero, you can have a lui instruction loading a value 0x800 which gets relaxed to a c.lui which is valid (c.lui 0x1 followed by addi -0x800). Relaxation can reduce the value below 0x800 at which point the c.lui 0x0 is no longer valid. We can fix this by converting the c.lui to a c.li which can load 0. bfd/ * elfnn-riscv.c (perform_relocation) <R_RISCV_RVC_LUI>: If RISCV_CONST_HIGH_PART (value) is zero, then convert c.lui instruction to c.li instruction, and use ENCODE_RVC_IMM to set value. ld/ * testsuite/ld-riscv-elf/c-lui-2.d: New. * testsuite/ld-riscv-elf/c-lui-2.ld: New. * testsuite/ld-riscv-elf/c-lui-2.s: New. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Run the c-lui-2 test. 2019-08-16 03:01:13 +08:00			`.option nopic`
			`.text`
			`.align 1`
			`.globl _start`
			`.type _start, @function`
			`_start:`
			`lui a0,%hi(foo)`
			`addi a0,a0,%lo(foo)`
			`.skip 0x7f8`
			`foo:`
			`ret`
			`.size _start, .-_start`