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binutils-gdb/opcodes/ChangeLog

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Add missing ChangeLog files for previous patch.
2019-02-09 05:21:52 +08:00
2019-02-08 Jim Wilson <jimw@sifive.com>
* riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
<bne>: Likewise.
Arm: Backport hlt to all architectures. The software trap instruction HLT that was introduced in Armv8-a is used as the semihosting trap instruction in AArch64. In order to allow systems configured to run AArch64 code to also run AArch32 with semihosting it was decided that AArch32 should also use HLT in the case of the "mixed mode" environment. This requires that HLT also be backported to all earlier architectures. The instruction is in the undefined encoding space earlier architectures but must trigger a semihosting trap [3]. The Arm Architectural Reference Manual [1] doesn't explicitly mention this however this is an explicit requirement in the Semihosting-v2 protocol [2]. [1] https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile [2] https://developer.arm.com/docs/100863/latest/the-semihosting-interface [3] https://github.com/qemu/qemu/commit/19a6e31c9d2701ef648b70ddcfc3bf64cec8c37e gas/ChangeLog: * config/tc-arm.c (insns): Redefine THUMB_VARIANT and ARM_VARIANT for hlt to armv1. * testsuite/gas/arm/armv8a-automatic-hlt.d: Update TAGs * testsuite/gas/arm/hlt.d: New test. * testsuite/gas/arm/hlt.s: New test. opcodes/ChangeLog: * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2019-02-08 01:12:23 +08:00
2019-02-07 Tamar Christina <tamar.christina@arm.com>
* arm-dis.c (arm_opcodes): Redefine hlt to armv1.
AArch64: Add verifier for By elem Single and Double sized instructions. The AArch64 instruction set has cut-outs inside instructions encodings for when a given encoding that would normally fall within the encoding space of an instruction is instead undefined. This updates the first few instructions FMLA, FMLA, FMUL and FMULX in the case where sz:L == 11. gas/ChangeLog: PR binutils/23212 * testsuite/gas/aarch64/undefined_by_elem_sz_l.s: New test. * testsuite/gas/aarch64/undefined_by_elem_sz_l.d: New test. opcodes/ChangeLog: PR binutils/23212 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz. * aarch64-opc.c (verify_elem_sd): New. (fields): Add FLD_sz entr. * aarch64-tbl.h (_SIMD_INSN): New. (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and fmulx scalar and vector by element isns.
2019-02-08 00:55:23 +08:00
2019-02-07 Tamar Christina <tamar.christina@arm.com>
PR binutils/23212
* aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
* aarch64-opc.c (verify_elem_sd): New.
(fields): Add FLD_sz entr.
* aarch64-tbl.h (_SIMD_INSN): New.
(aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
fmulx scalar and vector by element isns.
Updated Swedish translation for the opcodes sub-directory
2019-02-07 22:49:38 +08:00
2019-02-07 Nick Clifton <nickc@redhat.com>
* po/sv.po: Updated Swedish translation.
S/390: Implement instruction set extensions opcodes/ChangeLog: 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com> * s390-mkopc.c (main): Accept arch13 as cpu string. * s390-opc.c: Add new instruction formats and instruction opcode masks. * s390-opc.txt: Add new arch13 instructions. include/ChangeLog: 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com> * opcode/s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_ARCH13. gas/ChangeLog: 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com> * config/tc-s390.c (s390_parse_cpu): New entry for arch13. * doc/c-s390.texi: Document arch13 march option. * testsuite/gas/s390/s390.exp: Run the arch13 related tests. * testsuite/gas/s390/zarch-arch13.d: New test. * testsuite/gas/s390/zarch-arch13.s: New test. * testsuite/gas/s390/zarch-z13.d: Expect the renamed mnemonics also for z13.
2019-02-01 00:01:27 +08:00
2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
* s390-mkopc.c (main): Accept arch13 as cpu string.
* s390-opc.c: Add new instruction formats and instruction opcode
masks.
* s390-opc.txt: Add new arch13 instructions.
AArch64: Add missing changelog for Update encodings for stg, st2g, stzg and st2zg
2019-01-25 23:50:01 +08:00
2019-01-25 Sudakshina Das <sudi.das@arm.com>
* aarch64-tbl.h (QL_LDST_AT): Update macro.
(aarch64_opcode): Change encoding for stg, stzg
st2g and st2zg.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
AArch64: Add new STZGM instruction for Armv8.5-A Memory Tagging Extension. This patch is part of a series of patches to introduce a few changes to the Armv8.5-A Memory Tagging Extension. This patch adds the new STZGM instruction. STGZM Xt, [<Xn|SP>] Committed on behalf of Sudakshina Das. *** gas/ChangeLog *** * testsuite/gas/aarch64/armv8_5-a-memtag.d: New tests for stzgm. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. *** opcodes/ChangeLog *** * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2019-01-25 22:15:45 +08:00
2019-01-25 Sudakshina Das <sudi.das@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Likewise.
* aarch64-opc-2.c: Likewise.
* aarch64-tbl.h (aarch64_opcode): Add new stzgm.
AArch64: Remove ldgv and stgv instructions from Armv8.5-A Memory Tagging Extension. This patch is part of a series of patches to introduce a few changes to the Armv8.5-A Memory Tagging Extension. This patch removes the LDGV and STGV instructions. These instructions needed special infrastructure to support [base]! style for addressing mode. That is also removed now. Committed on behalf of Sudakshina Das. *** gas/ChangeLog *** * config/tc-aarch64.c (parse_address_main): Remove support for [base]! address expression. (parse_operands): Remove support for AARCH64_OPND_ADDR_SIMPLE_2. (warn_unpredictable_ldst): Remove support for ldstgv_indexed. * testsuite/gas/aarch64/armv8_5-a-memtag.d: Remove tests for ldgv and stgv. * testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise. * testsuite/gas/aarch64/illegal-memtag.l: Likewise. * testsuite/gas/aarch64/illegal-memtag.s: Likewise. *** include/ChangeLog *** * opcode/aarch64.h (enum aarch64_opnd): Remove AARCH64_OPND_ADDR_SIMPLE_2. (enum aarch64_insn_class): Remove ldstgv_indexed. *** opcodes/ChangeLog *** * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove. * aarch64-asm.h (ins_addr_simple_2): Likeiwse. * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise. * aarch64-dis.h (ext_addr_simple_2): Likewise. * aarch64-opc.c (operand_general_constraint_met_p): Remove case for ldstgv_indexed. (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2. * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv. (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
2019-01-25 21:57:14 +08:00
2019-01-25 Sudakshina Das <sudi.das@arm.com>
Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
* aarch64-asm.h (ins_addr_simple_2): Likeiwse.
* aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
* aarch64-dis.h (ext_addr_simple_2): Likewise.
* aarch64-opc.c (operand_general_constraint_met_p): Remove
case for ldstgv_indexed.
(aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
* aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
(AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
Updated translations for some of the binutils subdirectory.
2019-01-23 18:26:54 +08:00
2019-01-23 Nick Clifton <nickc@redhat.com>
* po/pt_BR.po: Updated Brazilian Portuguese translation.
Updated translations for various binutils subdirectories.
2019-01-21 20:59:20 +08:00
2019-01-21 Nick Clifton <nickc@redhat.com>
* po/de.po: Updated German translation.
* po/uk.po: Updated Ukranian translation.
[MIPS] fix typo in mips_arch_choices. opcodes/ * mips-dis.c (mips_arch_choices): Fix typo in gs464, gs464e and gs264e descriptors.
2019-01-20 09:51:30 +08:00
2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
* mips-dis.c (mips_arch_choices): Fix typo in
gs464, gs464e and gs264e descriptors.
Change version to 2.32.51 and regenerate configure and pot files.
2019-01-20 00:51:42 +08:00
2019-01-19 Nick Clifton <nickc@redhat.com>
* configure: Regenerate.
* po/opcodes.pot: Regenerate.
Add markers for 2.32 branch to NEWS and ChangeLog files.
2019-01-19 23:55:50 +08:00
2018-06-24 Nick Clifton <nickc@redhat.com>
2.32 branch created.
S12Z: Fix disassembly of indexed OPR operands with zero index. gas/ * testsuite/gas/s12z/jsr.s: New case. * testsuite/gas/s12z/jsr.d: New case. opcodes/ * s12z-dis.c (opr_emit_disassembly): Do not omit an index if it is zero.
2018-12-31 15:48:10 +08:00
2019-01-09 John Darrington <john@darrington.wattle.id.au>
S12Z: Don't crash when disassembling invalid instructions. Check for null before dereferencing an operand pointer. Normally this situation should never arise, but could happen if a "partial" instruction is encountered at the end of a file or section. opcodes/ * s12z-dis.c (print_insn_s12z): Do not dereference an operand if it is null.
2019-01-04 16:44:58 +08:00
* s12z-dis.c (print_insn_s12z): Do not dereference an operand
if it is null.
-dis.c (opr_emit_disassembly): Do not omit an index if it is
S12Z: Fix disassembly of indexed OPR operands with zero index. gas/ * testsuite/gas/s12z/jsr.s: New case. * testsuite/gas/s12z/jsr.d: New case. opcodes/ * s12z-dis.c (opr_emit_disassembly): Do not omit an index if it is zero.
2018-12-31 15:48:10 +08:00
zero.
Adjust bfd/warning.m4 egrep patterns Adjust the `bfd/warning.m4` `egrep` patterns to handle preprocessors that do not define `__GNUC__`, leaving the string in the output. bfd/ * warning.m4: Adjust egrep pattern for non-GNU compilers. * configure: Regenerate. binutils/ * configure: Regenerate. gas/ * configure: Regenerate. gold/ * configure: Regenerate. gprof/ * configure: Regenerate. ld/ * configure: Regenerate. opcodes/ * configure: Regenerate.
2019-01-09 11:21:08 +08:00
2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
* configure: Regenerate.
s12z regen * configure: Regenerate. * po/POTFILES.in: Regenerate.
2019-01-07 12:33:43 +08:00
2019-01-07 Alan Modra <amodra@gmail.com>
* configure: Regenerate.
* po/POTFILES.in: Regenerate.
S12Z: opcodes: Separate the decoding of operations from their display. This change adds an abstraction layer between the decoding of machine operations and their disassembled textual representation. This allows the decoding routines to be re-used for other purposes (at the expense) of slightly slower running time. ChangeLog: opcodes/ * s12z-opc.c: New file. * s12z-opc.h: New file. * s12z-dis.c: Removed all code not directly related to display of instructions. Used the interface provided by the new files instead. * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c. * Makefile.in: regenerate. * configure.ac (bfd_s12z_arch): Correct the dependencies. * configure: regenerate.
2019-01-04 01:30:40 +08:00
2019-01-03 John Darrington <john@darrington.wattle.id.au>
* s12z-opc.c: New file.
* s12z-opc.h: New file.
* s12z-dis.c: Removed all code not directly related to display
of instructions. Used the interface provided by the new files
instead.
* Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
s12z regen * configure: Regenerate. * po/POTFILES.in: Regenerate.
2019-01-07 12:33:43 +08:00
* Makefile.in: Regenerate.
S12Z: opcodes: Separate the decoding of operations from their display. This change adds an abstraction layer between the decoding of machine operations and their disassembled textual representation. This allows the decoding routines to be re-used for other purposes (at the expense) of slightly slower running time. ChangeLog: opcodes/ * s12z-opc.c: New file. * s12z-opc.h: New file. * s12z-dis.c: Removed all code not directly related to display of instructions. Used the interface provided by the new files instead. * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c. * Makefile.in: regenerate. * configure.ac (bfd_s12z_arch): Correct the dependencies. * configure: regenerate.
2019-01-04 01:30:40 +08:00
* configure.ac (bfd_s12z_arch): Correct the dependencies.
s12z regen * configure: Regenerate. * po/POTFILES.in: Regenerate.
2019-01-07 12:33:43 +08:00
* configure: Regenerate.
S12Z: opcodes: Separate the decoding of operations from their display. This change adds an abstraction layer between the decoding of machine operations and their disassembled textual representation. This allows the decoding routines to be re-used for other purposes (at the expense) of slightly slower running time. ChangeLog: opcodes/ * s12z-opc.c: New file. * s12z-opc.h: New file. * s12z-dis.c: Removed all code not directly related to display of instructions. Used the interface provided by the new files instead. * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c. * Makefile.in: regenerate. * configure.ac (bfd_s12z_arch): Correct the dependencies. * configure: regenerate.
2019-01-04 01:30:40 +08:00
Update year range in copyright notice of binutils files
2019-01-01 18:31:27 +08:00
2019-01-01 Alan Modra <amodra@gmail.com>
Update year range in copyright notice of all files.
ChangeLog rotation
2019-01-01 18:53:15 +08:00
For older changes see ChangeLog-2018
New 2016 binutils ChangeLog files Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog and include/*/ChangeLog files.
2016-01-01 18:44:31 +08:00
ChangeLog rotation
2019-01-01 18:53:15 +08:00
Copyright (C) 2019 Free Software Foundation, Inc.
New 2016 binutils ChangeLog files Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog and include/*/ChangeLog files.
2016-01-01 18:44:31 +08:00
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.
Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
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