Five fixes, for fcsel, fcvtz, fminnm, mls, and non-widening mul.
sim/aarch64/
* cpustate.c: Include math.h.
(aarch64_set_FP_float): Use signbit to check for signed zero.
(aarch64_set_FP_double): Likewise.
* simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break.
(do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth
args same size as third arg.
(fmaxnm): Use isnan instead of fpclassify.
(fminnm, dmaxnm, dminnm): Likewise.
(do_vec_MLS): Reverse order of subtraction operands.
(dexSimpleFPCondSelect): Call aarch64_get_FP_double or
aarch64_get_FP_float to get source register contents.
(UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN,
DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN,
DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New.
(do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in
raise_exception calls.
sim/testsuite/sim/aarch64/
* fcsel.s: New.
* fcvtz.s: New.
* fminnm.s: New.
* mls.s: New.
* mul.s: New.
2017-01-05 08:05:27 +08:00
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# mach: aarch64
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# Check the vector multiply subtract instruction: mls.
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.include "testutils.inc"
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Fix ldn/stn multiple instructions. Fix testcases with unaligned data.
sim/aarch64/
* simulator.c (vec_load): Add M argument. Rewrite to iterate over
registers based on structure size.
(LD4, LD3, LD2, LD1_2, LD1_3, LD1_4): Pass new arg to vec_load.
(LD1_1): Replace with call to vec_load.
(vec_store): Add new M argument. Rewrite to iterate over registers
based on structure size.
(ST4, ST3, ST2, ST1_2, ST1_3, ST1_4): Pass new arg to vec_store.
(ST1_1): Replace with call to vec_store.
sim/testsuite/sim/aarch64/
* fcvtz.s, fstur.s, ldn_single.s, ldnr.s, mla.s, mls.s, uzp.s: Align
data.
* sumulh.s: Delete unnecessary data alignment.
* stn_single.s: Align data. Fix unaligned ldr insns. Adjust cmp
arguments to match change.
* ldn_multiple.s, stn_multiple.s: New.
2017-04-23 07:36:01 +08:00
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.data
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.align 4
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Five fixes, for fcsel, fcvtz, fminnm, mls, and non-widening mul.
sim/aarch64/
* cpustate.c: Include math.h.
(aarch64_set_FP_float): Use signbit to check for signed zero.
(aarch64_set_FP_double): Likewise.
* simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break.
(do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth
args same size as third arg.
(fmaxnm): Use isnan instead of fpclassify.
(fminnm, dmaxnm, dminnm): Likewise.
(do_vec_MLS): Reverse order of subtraction operands.
(dexSimpleFPCondSelect): Call aarch64_get_FP_double or
aarch64_get_FP_float to get source register contents.
(UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN,
DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN,
DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New.
(do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in
raise_exception calls.
sim/testsuite/sim/aarch64/
* fcsel.s: New.
* fcvtz.s: New.
* fminnm.s: New.
* mls.s: New.
* mul.s: New.
2017-01-05 08:05:27 +08:00
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input:
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.word 0x04030201
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.word 0x08070605
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.word 0x0c0b0a09
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.word 0x100f0e0d
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m8b:
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.word 0xf1f8fd00
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.word 0xc1d0dde8
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m16b:
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.word 0xf1f8fd00
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.word 0xc1d0dde8
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.word 0x71889db0
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.word 0x01203d58
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m4h:
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.word 0xe7f8fc00
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.word 0x8fd0c3e8
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m8h:
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.word 0xe7f8fc00
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.word 0x8fd0c3e8
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.word 0xf7884bb0
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.word 0x1f209358
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m2s:
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.word 0xebf5fc00
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.word 0x5b95c3e8
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m4s:
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.word 0xebf5fc00
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.word 0x5b95c3e8
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.word 0x4ad54bb0
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.word 0xb9b49358
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start
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adrp x0, input
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ldr q0, [x0, #:lo12:input]
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movi v1.8b, #1
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mls v1.8b, v0.8b, v0.8b
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mov x1, v1.d[0]
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adrp x3, m8b
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ldr x4, [x3, #:lo12:m8b]
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cmp x1, x4
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bne .Lfailure
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movi v1.16b, #1
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mls v1.16b, v0.16b, v0.16b
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mov x1, v1.d[0]
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mov x2, v1.d[1]
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adrp x3, m16b
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ldr x4, [x3, #:lo12:m16b]
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cmp x1, x4
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bne .Lfailure
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ldr x5, [x3, #:lo12:m16b+8]
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cmp x2, x5
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bne .Lfailure
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movi v1.4h, #1
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mls v1.4h, v0.4h, v0.4h
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mov x1, v1.d[0]
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adrp x3, m4h
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ldr x4, [x3, #:lo12:m4h]
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cmp x1, x4
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bne .Lfailure
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movi v1.8h, #1
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mls v1.8h, v0.8h, v0.8h
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mov x1, v1.d[0]
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mov x2, v1.d[1]
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adrp x3, m8h
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ldr x4, [x3, #:lo12:m8h]
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cmp x1, x4
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bne .Lfailure
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ldr x5, [x3, #:lo12:m8h+8]
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cmp x2, x5
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bne .Lfailure
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movi v1.2s, #1
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mls v1.2s, v0.2s, v0.2s
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mov x1, v1.d[0]
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adrp x3, m2s
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ldr x4, [x3, #:lo12:m2s]
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cmp x1, x4
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bne .Lfailure
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movi v1.4s, #1
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mls v1.4s, v0.4s, v0.4s
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mov x1, v1.d[0]
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mov x2, v1.d[1]
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adrp x3, m4s
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ldr x4, [x3, #:lo12:m4s]
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cmp x1, x4
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bne .Lfailure
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ldr x5, [x3, #:lo12:m4s+8]
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cmp x2, x5
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bne .Lfailure
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pass
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.Lfailure:
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fail
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