2016-12-14 00:35:31 +08:00
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# mach: aarch64
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# Check the FP store unscaled offset instructions: fsturs, fsturd, fsturq.
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# Check the values -1, and XXX_MAX, which tests all bits.
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# Check with offsets -256 and 255, which tests all bits.
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# Also tests the FP load unscaled offset instructions: fldurs, fldurd, fldurq.
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.include "testutils.inc"
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.data
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Fix ldn/stn multiple instructions. Fix testcases with unaligned data.
sim/aarch64/
* simulator.c (vec_load): Add M argument. Rewrite to iterate over
registers based on structure size.
(LD4, LD3, LD2, LD1_2, LD1_3, LD1_4): Pass new arg to vec_load.
(LD1_1): Replace with call to vec_load.
(vec_store): Add new M argument. Rewrite to iterate over registers
based on structure size.
(ST4, ST3, ST2, ST1_2, ST1_3, ST1_4): Pass new arg to vec_store.
(ST1_1): Replace with call to vec_store.
sim/testsuite/sim/aarch64/
* fcvtz.s, fstur.s, ldn_single.s, ldnr.s, mla.s, mls.s, uzp.s: Align
data.
* sumulh.s: Delete unnecessary data alignment.
* stn_single.s: Align data. Fix unaligned ldr insns. Adjust cmp
arguments to match change.
* ldn_multiple.s, stn_multiple.s: New.
2017-04-23 07:36:01 +08:00
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.align 4
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2016-12-14 00:35:31 +08:00
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fm1:
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.word 3212836864
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fmax:
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.word 2139095039
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ftmp:
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.word 0
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dm1:
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.word 0
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.word -1074790400
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dmax:
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.word 4294967295
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.word 2146435071
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dtmp:
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.word 0
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.word 0
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ldm1:
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.word 0
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.word 0
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.word 0
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.word -1073807360
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ldmax:
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.word 4294967295
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.word 4294967295
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.word 4294967295
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.word 2147418111
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ldtmp:
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.word 0
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.word 0
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.word 0
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.word 0
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start
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adrp x1, ftmp
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add x1, x1, :lo12:ftmp
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adrp x0, fm1
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add x0, x0, :lo12:fm1
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sub x5, x0, #255
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sub x6, x1, #255
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movi d2, #0
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ldur s2, [x5, #255]
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stur s2, [x6, #255]
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ldr w3, [x0]
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ldr w4, [x1]
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cmp w3, w4
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bne .Lfailure
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adrp x0, fmax
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add x0, x0, :lo12:fmax
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add x5, x0, #256
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add x6, x1, #256
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movi d2, #0
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ldur s2, [x5, #-256]
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stur s2, [x6, #-256]
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ldr w3, [x0]
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ldr w4, [x1]
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cmp w3, w4
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bne .Lfailure
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adrp x1, dtmp
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add x1, x1, :lo12:dtmp
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adrp x0, dm1
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add x0, x0, :lo12:dm1
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sub x5, x0, #255
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sub x6, x1, #255
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movi d2, #0
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ldur d2, [x5, #255]
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stur d2, [x6, #255]
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ldr x3, [x0]
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ldr x4, [x1]
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cmp x3, x4
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bne .Lfailure
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adrp x0, dmax
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add x0, x0, :lo12:dmax
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add x5, x0, #256
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add x6, x1, #256
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movi d2, #0
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ldur d2, [x5, #-256]
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stur d2, [x6, #-256]
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ldr x3, [x0]
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ldr x4, [x1]
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cmp x3, x4
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bne .Lfailure
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adrp x1, ldtmp
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add x1, x1, :lo12:ldtmp
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adrp x0, ldm1
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add x0, x0, :lo12:ldm1
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sub x5, x0, #255
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sub x6, x1, #255
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movi v2.2d, #0
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ldur q2, [x5, #255]
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stur q2, [x6, #255]
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ldr x3, [x0]
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ldr x4, [x1]
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cmp x3, x4
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bne .Lfailure
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ldr x3, [x0, 8]
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ldr x4, [x1, 8]
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cmp x3, x4
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bne .Lfailure
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adrp x0, ldmax
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add x0, x0, :lo12:ldmax
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add x5, x0, #256
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add x6, x1, #256
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movi v2.2d, #0
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ldur q2, [x5, #-256]
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stur q2, [x6, #-256]
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ldr x3, [x0]
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ldr x4, [x1]
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cmp x3, x4
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bne .Lfailure
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ldr x3, [x0, 8]
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ldr x4, [x1, 8]
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cmp x3, x4
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bne .Lfailure
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pass
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.Lfailure:
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fail
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