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binutils-gdb/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp

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RISC-V: Only relax to C.LUI when imm != 0 and rd != 0/2 This matches the ISA specification. This also adds two tests: one to make sure the assembler rejects invalid 'c.lui's, and one to make sure we only relax valid 'c.lui's. bfd/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * elfnn-riscv.c (_bfd_riscv_relax_lui): Don't relax to c.lui when rd is x0. include/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * opcode/riscv.h (VALID_RVC_LUI_IMM): c.lui can't load the immediate 0. gas/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * testsuite/gas/riscv/c-lui-fail.d: New testcase. gas/testsuite/gas/riscv/c-lui-fail.l: Likewise. gas/testsuite/gas/riscv/c-lui-fail.s: Likewise. gas/testsuite/gas/riscv/riscv.exp: Likewise. ld/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * ld/testsuite/ld-riscv-elf/c-lui.d: New testcase. ld/testsuite/ld-riscv-elf/c-lui.s: Likewise. ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp: New test suite.
2017-09-24 09:04:16 +08:00
# Expect script for RISC-V ELF linker tests
Update year range in copyright notice of binutils files The result of running etc/update-copyright.py --this-year, fixing all the files whose mode is changed by the script, plus a build with --enable-maintainer-mode --enable-cgen-maint=yes, then checking out */po/*.pot which we don't update frequently. The copy of cgen was with commit d1dd5fcc38ead reverted as that commit breaks building of bfp opcodes files.
2022-01-02 06:30:17 +08:00
# Copyright (C) 2017-2022 Free Software Foundation, Inc.
RISC-V: Only relax to C.LUI when imm != 0 and rd != 0/2 This matches the ISA specification. This also adds two tests: one to make sure the assembler rejects invalid 'c.lui's, and one to make sure we only relax valid 'c.lui's. bfd/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * elfnn-riscv.c (_bfd_riscv_relax_lui): Don't relax to c.lui when rd is x0. include/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * opcode/riscv.h (VALID_RVC_LUI_IMM): c.lui can't load the immediate 0. gas/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * testsuite/gas/riscv/c-lui-fail.d: New testcase. gas/testsuite/gas/riscv/c-lui-fail.l: Likewise. gas/testsuite/gas/riscv/c-lui-fail.s: Likewise. gas/testsuite/gas/riscv/riscv.exp: Likewise. ld/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * ld/testsuite/ld-riscv-elf/c-lui.d: New testcase. ld/testsuite/ld-riscv-elf/c-lui.s: Likewise. ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp: New test suite.
2017-09-24 09:04:16 +08:00
#
# This file is part of the GNU Binutils.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
# MA 02110-1301, USA.
#
RISC-V: Fix riscv gas/ld testsuites failures for big endian. Add riscv_choose_[ilp32|lp64]_emul, and use them to choose the correct linker script rather than set elf[32|64]lriscv directly. gas/ * testsuite/gas/riscv/li32.d: Accept bigriscv in addition to littleriscv. * testsuite/gas/riscv/li64.d: Likewise. * testsuite/gas/riscv/lla32.d: Likewise. * testsuite/gas/riscv/lla64.d: Likewise. * testsuite/gas/riscv/march-ok-g2.d: Likewise. * testsuite/gas/riscv/march-ok-g2_p1.d: Likewise. * testsuite/gas/riscv/march-ok-g2p0.d: Likewise. * testsuite/gas/riscv/march-ok-i2p0.d: Likewise. * testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d: Likewise. * testsuite/gas/riscv/march-ok-nse-with-version.d: Likewise. * testsuite/gas/riscv/march-ok-two-nse.d: Likewise. ld/ * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Added riscv_choose_[ilp32|lp64]_emul to choose the correct linker script. * testsuite/ld-riscv-elf/attr-merge-arch-01.d: Call riscv_choose_[ilp32|lp64]_emul instead of hardcoding elf[32|64]lriscv. * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d: Likewise. * testsuite/ld-riscv-elf/c-lui-2.d: Likewise. * testsuite/ld-riscv-elf/c-lui.d: Likewise. * testsuite/ld-riscv-elf/call-relax.d: Likewise. * testsuite/ld-riscv-elf/pcrel-lo-addend-2.d: Likewise. * testsuite/ld-riscv-elf/pcrel-lo-addend.d: Likewise. * testsuite/ld-riscv-elf/weakref32.d: Accept bigriscv in addition to littleriscv. * testsuite/ld-riscv-elf/weakref64.d: Likewise.
2021-01-06 05:50:39 +08:00
proc riscv_choose_ilp32_emul {} {
if { [istarget "riscvbe-*"] \
|| [istarget "riscv32be-*"] \
|| [istarget "riscv64be-*"] } {
return "elf32briscv"
}
return "elf32lriscv"
}
proc riscv_choose_lp64_emul {} {
if { [istarget "riscvbe-*"] \
|| [istarget "riscv32be-*"] \
|| [istarget "riscv64be-*"] } {
return "elf64briscv"
}
return "elf64lriscv"
}
RISC-V: Support GNU indirect functions. Generally, glibc dynamic linker should have two ways to deal with ifunc - one is to handle the IRELATIVE relocations for the non-preemtive ifunc symbols, the other is to handle the R_RISCV_32/64 and R_RISCV_JUMP_SLOT relocations with the STT_IFUNC preemtive symbols. No matter which method is used, both of them should get the resolved ifunc symbols at runtime. Therefore, linker needs to generate the correct dynamic relocations for ifunc to make sure the the dynamic linker works well. For now, there are thirteen relocations are supported for ifunc in GNU ld, * R_RISCV_CALL and R_RISCV_CALL_PLT: The RISC-V compiler won't generate R_RISCV_JAL directly to jump to an ifunc. Besides, we disable the relaxations for the relocation referenced to ifunc, so just handling the R_RISCV_CALL and R_RISCV_CALL_PLT should be enough. Linker should generate a .plt entry and a .got.plt entry for it, and also needs to insert a dynamic IRELATIVE in the .got.plt enrty, or insert a R_RISCV_JUMP_SLOT when generating shared library. * R_RISCV_PCREL_HI20 and R_RISCV_PCREL_LO12_I/S: LA/LLA pattern with local fPIC ifunc symbol, or any non-PIC ifunc symbol. The PC-relative relocation. The current linker will deal with them in the same way as R_RISCV_CALL_PLT. * R_RISCV_GOT_HI20 and R_RISCV_PCREL_LO12_I/S: LA pattern with global PIC ifunc symbol. Linker should insert a dynamic IRELATIVE in the .got entry, or insert a R_RISCV_32/64 when generating shared library. * R_RISCV_32 and R_RISCV_64: Store the ifunc symbol into the data section. Linker should insert a dynamic IRELATIVE in the data section, or insert a R_RISCV_32/64 when generating shared library. * R_RISCV_HI20 and R_RISCV_LO12_I/S: The LUI + ADDI/LW/SW patterns. The absolute access relocation. The medlow model without the -fPIC compiler option should generate them. The ld ifunc testsuites "Build pr23169a" and "Build pr23169d" need the relocations, they are in the ld/testsuite/ld-ifunc/, and need compiler support. However, we also made some optimizations with reference to x86, * If GOT and PLT relocations refer to the same ifunc symbol when generating pie, then they can actually share a .got entry without creating two entries to store the same value and relocation. * If GOT, PLT and DATA relocations refer to the same ifunc symbol when generating position dependency executable, then linker will fill the address of .plt entry into the corresponding .got entry and data section, without insert any dynamic relocations for the GOT and DATA relocations. For the ifunc testcases, there are three types of them, 1. ifunc-reloc-*: Only check the single type of relocation refers to ifunc symbol. * ifunc-reloc-call: R_RISCV_CALL and R_RISCV_CALL_PLT. * ifunc-reloc-data: R_RISCV_32 and R_RISCV_64. * ifunc-reloc-got: R_RISCV_GOT_HI20 and R_RISCV_PCREL_LO_I/S. * ifunc-reloc-pcrel: R_RISCV_PCREL_HI20 and R_RISCV_PCREL_LO_I/S. 2. ifunc-[nonplt|plt]-*: If we don't have PLT relocs, then don't need to create the PLT and it's .plt entries. * ifunc-nonplt: Combine R_RISCV_GOT_HI20 and R_RISCV_32/64. * ifunc-plt: Combine all ifunc relocations. 3. ifunc-seperate-*: If we link the ifunc caller and resolver into the same module (link the objects), then the results are the same as the ifunc-reloc-* and ifunc-[noplt|plt]-* testcases. Consider the cases that the ifunc callers and resolver are in the different modules, that is, we compile the ifunc resolver to the shared library first, and then link it with the ifunc callers. The output of ifunc callers should be the same as the normal STT_FUNC cases, and the shared ifunc resolver should define the symbols as STT_IFUNC. The R_RISCV_PCREL_HI20 reloc is special. It should be linked and resolved locally, so if the ifunc resolver is defined in other modules (other shared libraries), then the R_RISCV_PCREL_HI20 is unresolvable, and linker should issue an unresolvable reloc error. bfd/ * elfnn-riscv.c: Include "objalloc.h" since we need objalloc_alloc. (riscv_elf_link_hash_table): Add loc_hash_table and loc_hash_memory for local STT_GNU_IFUNC symbols. (riscv_elf_got_plt_val): Removed. (riscv_elf_local_htab_hash, riscv_elf_local_htab_eq): New functions. Use to compare local hash entries. (riscv_elf_get_local_sym_hash): New function. Find a hash entry for local symbol, and create a new one if needed. (riscv_elf_link_hash_table_free): New function. Destroy an riscv elf linker hash table. (riscv_elf_link_hash_table_create): Create hash table for local ifunc. (riscv_elf_check_relocs): Create a fake global symbol to track the local ifunc symbol. Add support to check and handle the relocations reference to ifunc symbols. (allocate_dynrelocs): Let allocate_ifunc_dynrelocs and allocate_local_ifunc_dynrelocs to handle the ifunc symbols if they are defined and referenced in a non-shared object. (allocate_ifunc_dynrelocs): New function. Allocate space in .plt, .got and associated reloc sections for ifunc dynamic relocs. (allocate_local_ifunc_dynrelocs): Likewise, but for local ifunc dynamic relocs. (riscv_elf_relocate_section): Add support to handle the relocation referenced to ifunc symbols. (riscv_elf_size_dynamic_sections): Updated. (riscv_elf_adjust_dynamic_symbol): Updated. (riscv_elf_finish_dynamic_symbol): Finish up the ifunc handling, including fill the PLT and GOT entries for ifunc symbols. (riscv_elf_finish_local_dynamic_symbol): New function. Called by riscv_elf_finish_dynamic_symbol to handle the local ifunc symbols. (_bfd_riscv_relax_section): Don't do the relaxation for ifunc. * elfxx-riscv.c: Add R_RISCV_IRELATIVE. * configure.ac: Link elf-ifunc.lo to use the generic ifunc support. * configure: Regenerated. include/ * elf/riscv.h: Add R_RISCV_IRELATIVE to 58. ld/ * emulparams/elf32lriscv-defs.sh: Add IREL_IN_PLT. * testsuite/ld-ifunc/ifunc.exp: Enable ifunc tests for RISC-V. * testsuite/ld-riscv-elf/ld-riscv-elf.exp (run_dump_test_ifunc): New dump test for ifunc. There are two arguments, 'target` and `output`. The `target` is rv32 or rv64, and the `output` is used to choose which output you want to test (exe, pie or .so). * testsuite/ld-riscv-elf/ifunc-reloc-call-01.s: New testcase. * testsuite/ld-riscv-elf/ifunc-reloc-call-01.d: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-call-01-exe.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-call-01-pic.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-call-01-pie.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-call-02.s: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-call-02.d: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-call-02-exe.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-call-02-pic.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-call-02-pie.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-data.s: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-data.d: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-data-exe.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-data-pic.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-data-pie.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-got.s: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-got.d: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-got-exe.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-got-pic.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-got-pie.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-pcrel.s: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-pcrel.d: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-pcrel-exe.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-pcrel-pic.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-pcrel-pie.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-nonplt.s: Likewise. * testsuite/ld-riscv-elf/ifunc-nonplt.d: Likewise. * testsuite/ld-riscv-elf/ifunc-nonplt-exe.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-nonplt-pic.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-nonplt-pie.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-01.s: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-01.d: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-01-exe.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-01-pic.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-01-pie.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-02.s: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-02.d: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-02-exe.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-02-pic.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-02-pie.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-seperate-resolver.s: Likewise. * testsuite/ld-riscv-elf/ifunc-seperate-caller.s: Likewise. * testsuite/ld-riscv-elf/ifunc-seperate-exe.d: Likewise. * testsuite/ld-riscv-elf/ifunc-seperate-pic.d: Likewise. * testsuite/ld-riscv-elf/ifunc-seperate-pie.d: Likewise. * testsuite/ld-riscv-elf/ifunc-seperate-caller-pcrel.s: Likewise. * testsuite/ld-riscv-elf/ifunc-seperate-pcrel-pic.d: Likewise. * testsuite/ld-riscv-elf/ifunc-seperate-pcrel-pie.d: Likewise.
2020-10-07 11:48:22 +08:00
# target: rv32 or rv64.
# output: Which output you want? (exe, pie, .so)
proc run_dump_test_ifunc { name target output} {
set asflags ""
set ldflags "-z nocombreloc"
switch -- $output {
exe {
set ext "exe"
}
pie {
set ext "pie"
set ldflags "$ldflags -pie"
}
pic {
set ext "so"
set ldflags "$ldflags -shared"
}
}
switch -- $target {
rv32 {
set asflags "$asflags -march=rv32i -mabi=ilp32"
RISC-V: Fix riscv gas/ld testsuites failures for big endian. Add riscv_choose_[ilp32|lp64]_emul, and use them to choose the correct linker script rather than set elf[32|64]lriscv directly. gas/ * testsuite/gas/riscv/li32.d: Accept bigriscv in addition to littleriscv. * testsuite/gas/riscv/li64.d: Likewise. * testsuite/gas/riscv/lla32.d: Likewise. * testsuite/gas/riscv/lla64.d: Likewise. * testsuite/gas/riscv/march-ok-g2.d: Likewise. * testsuite/gas/riscv/march-ok-g2_p1.d: Likewise. * testsuite/gas/riscv/march-ok-g2p0.d: Likewise. * testsuite/gas/riscv/march-ok-i2p0.d: Likewise. * testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d: Likewise. * testsuite/gas/riscv/march-ok-nse-with-version.d: Likewise. * testsuite/gas/riscv/march-ok-two-nse.d: Likewise. ld/ * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Added riscv_choose_[ilp32|lp64]_emul to choose the correct linker script. * testsuite/ld-riscv-elf/attr-merge-arch-01.d: Call riscv_choose_[ilp32|lp64]_emul instead of hardcoding elf[32|64]lriscv. * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d: Likewise. * testsuite/ld-riscv-elf/c-lui-2.d: Likewise. * testsuite/ld-riscv-elf/c-lui.d: Likewise. * testsuite/ld-riscv-elf/call-relax.d: Likewise. * testsuite/ld-riscv-elf/pcrel-lo-addend-2.d: Likewise. * testsuite/ld-riscv-elf/pcrel-lo-addend.d: Likewise. * testsuite/ld-riscv-elf/weakref32.d: Accept bigriscv in addition to littleriscv. * testsuite/ld-riscv-elf/weakref64.d: Likewise.
2021-01-06 05:50:39 +08:00
set ldflags "$ldflags -m[riscv_choose_ilp32_emul]"
RISC-V: Support GNU indirect functions. Generally, glibc dynamic linker should have two ways to deal with ifunc - one is to handle the IRELATIVE relocations for the non-preemtive ifunc symbols, the other is to handle the R_RISCV_32/64 and R_RISCV_JUMP_SLOT relocations with the STT_IFUNC preemtive symbols. No matter which method is used, both of them should get the resolved ifunc symbols at runtime. Therefore, linker needs to generate the correct dynamic relocations for ifunc to make sure the the dynamic linker works well. For now, there are thirteen relocations are supported for ifunc in GNU ld, * R_RISCV_CALL and R_RISCV_CALL_PLT: The RISC-V compiler won't generate R_RISCV_JAL directly to jump to an ifunc. Besides, we disable the relaxations for the relocation referenced to ifunc, so just handling the R_RISCV_CALL and R_RISCV_CALL_PLT should be enough. Linker should generate a .plt entry and a .got.plt entry for it, and also needs to insert a dynamic IRELATIVE in the .got.plt enrty, or insert a R_RISCV_JUMP_SLOT when generating shared library. * R_RISCV_PCREL_HI20 and R_RISCV_PCREL_LO12_I/S: LA/LLA pattern with local fPIC ifunc symbol, or any non-PIC ifunc symbol. The PC-relative relocation. The current linker will deal with them in the same way as R_RISCV_CALL_PLT. * R_RISCV_GOT_HI20 and R_RISCV_PCREL_LO12_I/S: LA pattern with global PIC ifunc symbol. Linker should insert a dynamic IRELATIVE in the .got entry, or insert a R_RISCV_32/64 when generating shared library. * R_RISCV_32 and R_RISCV_64: Store the ifunc symbol into the data section. Linker should insert a dynamic IRELATIVE in the data section, or insert a R_RISCV_32/64 when generating shared library. * R_RISCV_HI20 and R_RISCV_LO12_I/S: The LUI + ADDI/LW/SW patterns. The absolute access relocation. The medlow model without the -fPIC compiler option should generate them. The ld ifunc testsuites "Build pr23169a" and "Build pr23169d" need the relocations, they are in the ld/testsuite/ld-ifunc/, and need compiler support. However, we also made some optimizations with reference to x86, * If GOT and PLT relocations refer to the same ifunc symbol when generating pie, then they can actually share a .got entry without creating two entries to store the same value and relocation. * If GOT, PLT and DATA relocations refer to the same ifunc symbol when generating position dependency executable, then linker will fill the address of .plt entry into the corresponding .got entry and data section, without insert any dynamic relocations for the GOT and DATA relocations. For the ifunc testcases, there are three types of them, 1. ifunc-reloc-*: Only check the single type of relocation refers to ifunc symbol. * ifunc-reloc-call: R_RISCV_CALL and R_RISCV_CALL_PLT. * ifunc-reloc-data: R_RISCV_32 and R_RISCV_64. * ifunc-reloc-got: R_RISCV_GOT_HI20 and R_RISCV_PCREL_LO_I/S. * ifunc-reloc-pcrel: R_RISCV_PCREL_HI20 and R_RISCV_PCREL_LO_I/S. 2. ifunc-[nonplt|plt]-*: If we don't have PLT relocs, then don't need to create the PLT and it's .plt entries. * ifunc-nonplt: Combine R_RISCV_GOT_HI20 and R_RISCV_32/64. * ifunc-plt: Combine all ifunc relocations. 3. ifunc-seperate-*: If we link the ifunc caller and resolver into the same module (link the objects), then the results are the same as the ifunc-reloc-* and ifunc-[noplt|plt]-* testcases. Consider the cases that the ifunc callers and resolver are in the different modules, that is, we compile the ifunc resolver to the shared library first, and then link it with the ifunc callers. The output of ifunc callers should be the same as the normal STT_FUNC cases, and the shared ifunc resolver should define the symbols as STT_IFUNC. The R_RISCV_PCREL_HI20 reloc is special. It should be linked and resolved locally, so if the ifunc resolver is defined in other modules (other shared libraries), then the R_RISCV_PCREL_HI20 is unresolvable, and linker should issue an unresolvable reloc error. bfd/ * elfnn-riscv.c: Include "objalloc.h" since we need objalloc_alloc. (riscv_elf_link_hash_table): Add loc_hash_table and loc_hash_memory for local STT_GNU_IFUNC symbols. (riscv_elf_got_plt_val): Removed. (riscv_elf_local_htab_hash, riscv_elf_local_htab_eq): New functions. Use to compare local hash entries. (riscv_elf_get_local_sym_hash): New function. Find a hash entry for local symbol, and create a new one if needed. (riscv_elf_link_hash_table_free): New function. Destroy an riscv elf linker hash table. (riscv_elf_link_hash_table_create): Create hash table for local ifunc. (riscv_elf_check_relocs): Create a fake global symbol to track the local ifunc symbol. Add support to check and handle the relocations reference to ifunc symbols. (allocate_dynrelocs): Let allocate_ifunc_dynrelocs and allocate_local_ifunc_dynrelocs to handle the ifunc symbols if they are defined and referenced in a non-shared object. (allocate_ifunc_dynrelocs): New function. Allocate space in .plt, .got and associated reloc sections for ifunc dynamic relocs. (allocate_local_ifunc_dynrelocs): Likewise, but for local ifunc dynamic relocs. (riscv_elf_relocate_section): Add support to handle the relocation referenced to ifunc symbols. (riscv_elf_size_dynamic_sections): Updated. (riscv_elf_adjust_dynamic_symbol): Updated. (riscv_elf_finish_dynamic_symbol): Finish up the ifunc handling, including fill the PLT and GOT entries for ifunc symbols. (riscv_elf_finish_local_dynamic_symbol): New function. Called by riscv_elf_finish_dynamic_symbol to handle the local ifunc symbols. (_bfd_riscv_relax_section): Don't do the relaxation for ifunc. * elfxx-riscv.c: Add R_RISCV_IRELATIVE. * configure.ac: Link elf-ifunc.lo to use the generic ifunc support. * configure: Regenerated. include/ * elf/riscv.h: Add R_RISCV_IRELATIVE to 58. ld/ * emulparams/elf32lriscv-defs.sh: Add IREL_IN_PLT. * testsuite/ld-ifunc/ifunc.exp: Enable ifunc tests for RISC-V. * testsuite/ld-riscv-elf/ld-riscv-elf.exp (run_dump_test_ifunc): New dump test for ifunc. There are two arguments, 'target` and `output`. The `target` is rv32 or rv64, and the `output` is used to choose which output you want to test (exe, pie or .so). * testsuite/ld-riscv-elf/ifunc-reloc-call-01.s: New testcase. * testsuite/ld-riscv-elf/ifunc-reloc-call-01.d: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-call-01-exe.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-call-01-pic.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-call-01-pie.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-call-02.s: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-call-02.d: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-call-02-exe.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-call-02-pic.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-call-02-pie.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-data.s: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-data.d: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-data-exe.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-data-pic.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-data-pie.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-got.s: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-got.d: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-got-exe.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-got-pic.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-got-pie.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-pcrel.s: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-pcrel.d: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-pcrel-exe.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-pcrel-pic.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-pcrel-pie.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-nonplt.s: Likewise. * testsuite/ld-riscv-elf/ifunc-nonplt.d: Likewise. * testsuite/ld-riscv-elf/ifunc-nonplt-exe.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-nonplt-pic.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-nonplt-pie.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-01.s: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-01.d: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-01-exe.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-01-pic.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-01-pie.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-02.s: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-02.d: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-02-exe.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-02-pic.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-02-pie.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-seperate-resolver.s: Likewise. * testsuite/ld-riscv-elf/ifunc-seperate-caller.s: Likewise. * testsuite/ld-riscv-elf/ifunc-seperate-exe.d: Likewise. * testsuite/ld-riscv-elf/ifunc-seperate-pic.d: Likewise. * testsuite/ld-riscv-elf/ifunc-seperate-pie.d: Likewise. * testsuite/ld-riscv-elf/ifunc-seperate-caller-pcrel.s: Likewise. * testsuite/ld-riscv-elf/ifunc-seperate-pcrel-pic.d: Likewise. * testsuite/ld-riscv-elf/ifunc-seperate-pcrel-pie.d: Likewise.
2020-10-07 11:48:22 +08:00
}
rv64 {
set asflags "$asflags -march=rv64i -mabi=lp64 -defsym __64_bit__=1"
RISC-V: Fix riscv gas/ld testsuites failures for big endian. Add riscv_choose_[ilp32|lp64]_emul, and use them to choose the correct linker script rather than set elf[32|64]lriscv directly. gas/ * testsuite/gas/riscv/li32.d: Accept bigriscv in addition to littleriscv. * testsuite/gas/riscv/li64.d: Likewise. * testsuite/gas/riscv/lla32.d: Likewise. * testsuite/gas/riscv/lla64.d: Likewise. * testsuite/gas/riscv/march-ok-g2.d: Likewise. * testsuite/gas/riscv/march-ok-g2_p1.d: Likewise. * testsuite/gas/riscv/march-ok-g2p0.d: Likewise. * testsuite/gas/riscv/march-ok-i2p0.d: Likewise. * testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d: Likewise. * testsuite/gas/riscv/march-ok-nse-with-version.d: Likewise. * testsuite/gas/riscv/march-ok-two-nse.d: Likewise. ld/ * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Added riscv_choose_[ilp32|lp64]_emul to choose the correct linker script. * testsuite/ld-riscv-elf/attr-merge-arch-01.d: Call riscv_choose_[ilp32|lp64]_emul instead of hardcoding elf[32|64]lriscv. * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d: Likewise. * testsuite/ld-riscv-elf/c-lui-2.d: Likewise. * testsuite/ld-riscv-elf/c-lui.d: Likewise. * testsuite/ld-riscv-elf/call-relax.d: Likewise. * testsuite/ld-riscv-elf/pcrel-lo-addend-2.d: Likewise. * testsuite/ld-riscv-elf/pcrel-lo-addend.d: Likewise. * testsuite/ld-riscv-elf/weakref32.d: Accept bigriscv in addition to littleriscv. * testsuite/ld-riscv-elf/weakref64.d: Likewise.
2021-01-06 05:50:39 +08:00
set ldflags "$ldflags -m[riscv_choose_lp64_emul]"
RISC-V: Support GNU indirect functions. Generally, glibc dynamic linker should have two ways to deal with ifunc - one is to handle the IRELATIVE relocations for the non-preemtive ifunc symbols, the other is to handle the R_RISCV_32/64 and R_RISCV_JUMP_SLOT relocations with the STT_IFUNC preemtive symbols. No matter which method is used, both of them should get the resolved ifunc symbols at runtime. Therefore, linker needs to generate the correct dynamic relocations for ifunc to make sure the the dynamic linker works well. For now, there are thirteen relocations are supported for ifunc in GNU ld, * R_RISCV_CALL and R_RISCV_CALL_PLT: The RISC-V compiler won't generate R_RISCV_JAL directly to jump to an ifunc. Besides, we disable the relaxations for the relocation referenced to ifunc, so just handling the R_RISCV_CALL and R_RISCV_CALL_PLT should be enough. Linker should generate a .plt entry and a .got.plt entry for it, and also needs to insert a dynamic IRELATIVE in the .got.plt enrty, or insert a R_RISCV_JUMP_SLOT when generating shared library. * R_RISCV_PCREL_HI20 and R_RISCV_PCREL_LO12_I/S: LA/LLA pattern with local fPIC ifunc symbol, or any non-PIC ifunc symbol. The PC-relative relocation. The current linker will deal with them in the same way as R_RISCV_CALL_PLT. * R_RISCV_GOT_HI20 and R_RISCV_PCREL_LO12_I/S: LA pattern with global PIC ifunc symbol. Linker should insert a dynamic IRELATIVE in the .got entry, or insert a R_RISCV_32/64 when generating shared library. * R_RISCV_32 and R_RISCV_64: Store the ifunc symbol into the data section. Linker should insert a dynamic IRELATIVE in the data section, or insert a R_RISCV_32/64 when generating shared library. * R_RISCV_HI20 and R_RISCV_LO12_I/S: The LUI + ADDI/LW/SW patterns. The absolute access relocation. The medlow model without the -fPIC compiler option should generate them. The ld ifunc testsuites "Build pr23169a" and "Build pr23169d" need the relocations, they are in the ld/testsuite/ld-ifunc/, and need compiler support. However, we also made some optimizations with reference to x86, * If GOT and PLT relocations refer to the same ifunc symbol when generating pie, then they can actually share a .got entry without creating two entries to store the same value and relocation. * If GOT, PLT and DATA relocations refer to the same ifunc symbol when generating position dependency executable, then linker will fill the address of .plt entry into the corresponding .got entry and data section, without insert any dynamic relocations for the GOT and DATA relocations. For the ifunc testcases, there are three types of them, 1. ifunc-reloc-*: Only check the single type of relocation refers to ifunc symbol. * ifunc-reloc-call: R_RISCV_CALL and R_RISCV_CALL_PLT. * ifunc-reloc-data: R_RISCV_32 and R_RISCV_64. * ifunc-reloc-got: R_RISCV_GOT_HI20 and R_RISCV_PCREL_LO_I/S. * ifunc-reloc-pcrel: R_RISCV_PCREL_HI20 and R_RISCV_PCREL_LO_I/S. 2. ifunc-[nonplt|plt]-*: If we don't have PLT relocs, then don't need to create the PLT and it's .plt entries. * ifunc-nonplt: Combine R_RISCV_GOT_HI20 and R_RISCV_32/64. * ifunc-plt: Combine all ifunc relocations. 3. ifunc-seperate-*: If we link the ifunc caller and resolver into the same module (link the objects), then the results are the same as the ifunc-reloc-* and ifunc-[noplt|plt]-* testcases. Consider the cases that the ifunc callers and resolver are in the different modules, that is, we compile the ifunc resolver to the shared library first, and then link it with the ifunc callers. The output of ifunc callers should be the same as the normal STT_FUNC cases, and the shared ifunc resolver should define the symbols as STT_IFUNC. The R_RISCV_PCREL_HI20 reloc is special. It should be linked and resolved locally, so if the ifunc resolver is defined in other modules (other shared libraries), then the R_RISCV_PCREL_HI20 is unresolvable, and linker should issue an unresolvable reloc error. bfd/ * elfnn-riscv.c: Include "objalloc.h" since we need objalloc_alloc. (riscv_elf_link_hash_table): Add loc_hash_table and loc_hash_memory for local STT_GNU_IFUNC symbols. (riscv_elf_got_plt_val): Removed. (riscv_elf_local_htab_hash, riscv_elf_local_htab_eq): New functions. Use to compare local hash entries. (riscv_elf_get_local_sym_hash): New function. Find a hash entry for local symbol, and create a new one if needed. (riscv_elf_link_hash_table_free): New function. Destroy an riscv elf linker hash table. (riscv_elf_link_hash_table_create): Create hash table for local ifunc. (riscv_elf_check_relocs): Create a fake global symbol to track the local ifunc symbol. Add support to check and handle the relocations reference to ifunc symbols. (allocate_dynrelocs): Let allocate_ifunc_dynrelocs and allocate_local_ifunc_dynrelocs to handle the ifunc symbols if they are defined and referenced in a non-shared object. (allocate_ifunc_dynrelocs): New function. Allocate space in .plt, .got and associated reloc sections for ifunc dynamic relocs. (allocate_local_ifunc_dynrelocs): Likewise, but for local ifunc dynamic relocs. (riscv_elf_relocate_section): Add support to handle the relocation referenced to ifunc symbols. (riscv_elf_size_dynamic_sections): Updated. (riscv_elf_adjust_dynamic_symbol): Updated. (riscv_elf_finish_dynamic_symbol): Finish up the ifunc handling, including fill the PLT and GOT entries for ifunc symbols. (riscv_elf_finish_local_dynamic_symbol): New function. Called by riscv_elf_finish_dynamic_symbol to handle the local ifunc symbols. (_bfd_riscv_relax_section): Don't do the relaxation for ifunc. * elfxx-riscv.c: Add R_RISCV_IRELATIVE. * configure.ac: Link elf-ifunc.lo to use the generic ifunc support. * configure: Regenerated. include/ * elf/riscv.h: Add R_RISCV_IRELATIVE to 58. ld/ * emulparams/elf32lriscv-defs.sh: Add IREL_IN_PLT. * testsuite/ld-ifunc/ifunc.exp: Enable ifunc tests for RISC-V. * testsuite/ld-riscv-elf/ld-riscv-elf.exp (run_dump_test_ifunc): New dump test for ifunc. There are two arguments, 'target` and `output`. The `target` is rv32 or rv64, and the `output` is used to choose which output you want to test (exe, pie or .so). * testsuite/ld-riscv-elf/ifunc-reloc-call-01.s: New testcase. * testsuite/ld-riscv-elf/ifunc-reloc-call-01.d: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-call-01-exe.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-call-01-pic.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-call-01-pie.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-call-02.s: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-call-02.d: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-call-02-exe.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-call-02-pic.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-call-02-pie.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-data.s: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-data.d: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-data-exe.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-data-pic.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-data-pie.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-got.s: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-got.d: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-got-exe.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-got-pic.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-got-pie.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-pcrel.s: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-pcrel.d: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-pcrel-exe.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-pcrel-pic.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-pcrel-pie.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-nonplt.s: Likewise. * testsuite/ld-riscv-elf/ifunc-nonplt.d: Likewise. * testsuite/ld-riscv-elf/ifunc-nonplt-exe.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-nonplt-pic.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-nonplt-pie.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-01.s: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-01.d: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-01-exe.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-01-pic.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-01-pie.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-02.s: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-02.d: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-02-exe.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-02-pic.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-02-pie.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-seperate-resolver.s: Likewise. * testsuite/ld-riscv-elf/ifunc-seperate-caller.s: Likewise. * testsuite/ld-riscv-elf/ifunc-seperate-exe.d: Likewise. * testsuite/ld-riscv-elf/ifunc-seperate-pic.d: Likewise. * testsuite/ld-riscv-elf/ifunc-seperate-pie.d: Likewise. * testsuite/ld-riscv-elf/ifunc-seperate-caller-pcrel.s: Likewise. * testsuite/ld-riscv-elf/ifunc-seperate-pcrel-pic.d: Likewise. * testsuite/ld-riscv-elf/ifunc-seperate-pcrel-pie.d: Likewise.
2020-10-07 11:48:22 +08:00
}
}
run_ld_link_tests [list \
[list "$name ($target-$output)" \
"$ldflags" "" \
"$asflags" \
[list "$name.s"] \
[concat [list "readelf -rW $name-$output.rd"] \
[list "objdump -dw $name.d"]] \
"$name-$target.$ext"]]
}
elf/riscv: Fix relaxation with aliases [PR28021] the fix for PR22756 only changed behaviour for hidden aliases, but the same situation exists for non-hidden aliases: sym_hashes[] can contain multiple entries pointing to the same symbol structure leading to relaxation adjustment to be applied twice. Fix this by testing for duplicates for everything that looks like it has a version. PR ld/28021 bfd/ * elfnn-riscv.c (riscv_relax_delete_bytes): Check for any versioning. ld/ * testsuite/ld-riscv-elf/relax-twice.ver: New. * testsuite/ld-riscv-elf/relax-twice-1.s: New. * testsuite/ld-riscv-elf/relax-twice-2.s: New. * testsuite/ld-riscv-elf/ld-riscv-elf.exp (run_relax_twice_test): New, and call it.
2021-06-28 23:57:17 +08:00
proc run_relax_twice_test {} {
global as
global ld
global nm
global nm_output
global srcdir
global subdir
global runtests
set testname "relax-twice"
if ![runtest_file_p $runtests $testname] then {
return
}
# assemble and link the two input files with a version script, then
# capture output of nm and compare addresses of the two symbols
# 'foobar_new' and 'foobar@@New'. They must be equal.
# Bitness doesn't matter so we simply force 64bit.
if { ![ld_assemble_flags $as "-march=rv64i" $srcdir/$subdir/relax-twice-1.s tmpdir/relax-twice-1.o ]
|| ![ld_assemble_flags $as "-march=rv64i" $srcdir/$subdir/relax-twice-2.s tmpdir/relax-twice-2.o]
|| ![ld_link $ld tmpdir/relax-twice.so "-m[riscv_choose_lp64_emul] -shared --relax --version-script $srcdir/$subdir/relax-twice.ver tmpdir/relax-twice-1.o tmpdir/relax-twice-2.o"] } {
fail $testname
} elseif { ![ld_nm $nm "" tmpdir/relax-twice.so] } {
fail $testname
} elseif { ![info exists nm_output(foobar_new)]
|| ![info exists nm_output(foobar@@New)]} {
send_log "bad output from nm\n"
verbose "bad output from nm"
fail $testname
} elseif {$nm_output(foobar_new) != $nm_output(foobar@@New)} {
send_log "foobar_new == $nm_output(foobar_new)\n"
verbose "foobar_new == $nm_output(foobar_new)"
send_log "foobar@@New == $nm_output(foobar@@New)\n"
verbose "foobar@@New == $nm_output(foobar@@New)"
fail $testname
} else {
pass $testname
}
}
Riscv shared libraries should not export __global_pointer$. ld/ * emulparams/elf32lriscv-defs.sh (SDATA_START_SYMBOLS): Mark __global_pointer$ as HIDDEN. * testsuite/ld-riscv-elf/gp-hidden-64.rd: New. * testsuite/ld-riscv-elf/gp-hidden-lib.rd: New. * testsuite/ld-riscv-elf/gp-hidden-lib.s: New. * testsuite/ld-riscv-elf/gp-hidden-ver-64.rd: New. * testsuite/ld-riscv-elf/gp-hidden-ver.rd: New. * testsuite/ld-riscv-elf/gp-hidden-ver.s: New. * testsuite/ld-riscv-elf/gp-hidder-ver.ver: New. * testsuite/ld-riscv-elf/gp-hidden.rd: New. * testsuite/ld-riscv-elf/gp-hidden.s: New. * testsuite/ld-riscv-elf/gp-hidden.sd: New. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Change riscv to riscv*. Run the new tests with run_ld_link_tests.
2017-12-05 09:37:55 +08:00
if [istarget "riscv*-*-*"] {
RISC-V: Don't separate pcgp relaxation to another relax pass. Commit abd20cb637008da9d32018b4b03973e119388a0a and ebdcad3fddf6ec21f6d4dcc702379a12718cf0c4 introduced additional complexity into the paths run by the RISC-V relaxation pass in order to resolve the issue of accurately keeping track of pcrel_hi and pcrel_lo pairs. The first commit split up relaxation of these relocs into a pass which occurred after other relaxations in order to prevent the situation where bytes were deleted in between a pcrel_lo/pcrel_hi pair, inhibiting our ability to find the corresponding pcrel_hi relocation from the address attached to the pcrel_lo. Since the relaxation was split into two passes the 'again' parameter could not be used to perform the entire relaxation process again and so the second commit added a way to restart ldelf_map_segments, thus starting the whole process again. Unfortunately this process could not account for the fact that we were not finished with the relaxation process so in some cases - such as the case where code would not fit in a memory region before the R_RISCV_ALIGN relocation was relaxed - sanity checks in generic code would fail. This patch fixes all three of these concerns by reverting back to a system of having only one target relax pass but updating entries in the table of pcrel_hi/pcrel_lo relocs every time any bytes are deleted. Thus we can keep track of the pairs accurately, and we can use the 'again' parameter to restart the entire target relax pass, behaving in the way that generic code expects. Unfortunately we must still have an additional pass to delay deleting AUIPC bytes to avoid ambiguity between pcrel_hi relocs stored in the table after deletion. This pass can only be run once so we may potentially miss out on relaxation opportunities but this is likely to be rare. https://sourceware.org/bugzilla/show_bug.cgi?id=28410 bfd/ * elfnn-riscv.c (riscv_elf_link_hash_table): Removed restart_relax. (riscv_elf_link_hash_table_create): Updated. (riscv_relax_delete_bytes): Moved after the riscv_update_pcgp_relocs. Update the pcgp_relocs table whenever bytes are deleted. (riscv_update_pcgp_relocs): Add function to update the section offset of pcrel_hi and pcrel_lo, and also update the symbol value of pcrel_hi. (_bfd_riscv_relax_call): Need to update the pcgp_relocs table when deleting codes. (_bfd_riscv_relax_lui): Likewise. (_bfd_riscv_relax_tls_le): Likewise. (_bfd_riscv_relax_align): Once we've handled an R_RISCV_ALIGN, we can't relax anything else, so set the sec->sec_flg0 to true. Besides, we don't need to update the pcgp_relocs table at this stage, so just pass NULL pointer as the pcgp_relocs table for riscv_relax_delete_bytes. (_bfd_riscv_relax_section): Use only one pass for all target relaxations. (_bfd_riscv_relax_delete): Likewise, we don't need to update the pcgp_relocs table at this stage, and don't need to set the `again' since restart_relax mechanism is abandoned. (bfd_elfNN_riscv_restart_relax_sections): Removed. (_bfd_riscv_relax_section): Updated. * elfxx-riscv.h (bfd_elf32_riscv_restart_relax_sections): Removed. (bfd_elf64_riscv_restart_relax_sections): Likewise. ld/ * emultempl/riscvelf.em: Revert restart_relax changes and set relax_pass to 3. * testsuite/ld-riscv-elf/align-small-region.d: New testcase. * testsuite/ld-riscv-elf/align-small-region.ld: Likewise. * testsuite/ld-riscv-elf/align-small-region.s: Likewise. * testsuite/ld-riscv-elf/restart-relax.d: Removed sine the restart_relax mechanism is abandoned. * testsuite/ld-riscv-elf/restart-relax.s: Likewise. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
2021-10-21 11:15:47 +08:00
run_dump_test "align-small-region"
RISC-V: Fix ld relax failure with calls and align directives. Make _bfd_riscv_relax_call handle section alignment padding same as the _bfd_riscv_relax_lui and _bfd_riscv_relax_pc functions already do. Use the max section alignment if section boundaries are crossed, otherwise the alignment of the containing section. bfd/ PR 25181 * elfnn-riscv.c (_bfd_riscv_relax_call): Always add max_alignment to foff. If sym_sec->output_section and sec->output_section are the same and not *ABS* then set max_alignment to that section's alignment. ld/ PR 25181 * testsuite/ld-riscv-elf/call-relax-0.s: New file. * testsuite/ld-riscv-elf/call-relax-1.s: New file. * testsuite/ld-riscv-elf/call-relax-2.s: New file. * testsuite/ld-riscv-elf/call-relax-3.s: New file. * testsuite/ld-riscv-elf/call-relax.d: New test. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Run call-relax test. Change-Id: Iaf65cee52345abf1955f36e8e72c4f6cc0db8d9a
2019-11-13 07:50:48 +08:00
run_dump_test "call-relax"
RISC-V: Added ld testcase for pcgp relaxation. Consider the the pcgp-relax-02 testcase, .text .globl _start _start: .L1: auipc a0, %pcrel_hi(data_a) .L2: auipc a1, %pcrel_hi(data_b) addi a0, a0, %pcrel_lo(.L1) addi a1, a1, %pcrel_lo(.L2) .data .word 0x0 .globl data_a data_a: .word 0x1 .section .rodata .globl data_b data_b: .word 0x2 If the first auipc is deleted, but we are still building the pcgp table (connect the high and low pcrel relocations), then there is an aliasing issue that we need some way to disambiguate which of the two symbols we are targeting. Therefore, Palmer thought of a way to use R_RISCV_DELETE to split this into two phases, so we could resolve the addresses before creating the ambiguities. This patch just add the ld testcase for the above case, in case we have changed something but break this. ld/ * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Renamed pcgp-relax to pcgp-relax-01, and added pcgp-relax-02. * testsuite/ld-riscv-elf/pcgp-relax-01.d: Renmaed from pcgp-relax. * testsuite/ld-riscv-elf/pcgp-relax-01.s: Likewise. * testsuite/ld-riscv-elf/pcgp-relax-02.d: New testcase. * testsuite/ld-riscv-elf/pcgp-relax-02.s: Likewise.
2021-10-22 11:32:46 +08:00
run_dump_test "pcgp-relax-01"
run_dump_test "pcgp-relax-02"
RISC-V: Only relax to C.LUI when imm != 0 and rd != 0/2 This matches the ISA specification. This also adds two tests: one to make sure the assembler rejects invalid 'c.lui's, and one to make sure we only relax valid 'c.lui's. bfd/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * elfnn-riscv.c (_bfd_riscv_relax_lui): Don't relax to c.lui when rd is x0. include/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * opcode/riscv.h (VALID_RVC_LUI_IMM): c.lui can't load the immediate 0. gas/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * testsuite/gas/riscv/c-lui-fail.d: New testcase. gas/testsuite/gas/riscv/c-lui-fail.l: Likewise. gas/testsuite/gas/riscv/c-lui-fail.s: Likewise. gas/testsuite/gas/riscv/riscv.exp: Likewise. ld/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * ld/testsuite/ld-riscv-elf/c-lui.d: New testcase. ld/testsuite/ld-riscv-elf/c-lui.s: Likewise. ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp: New test suite.
2017-09-24 09:04:16 +08:00
run_dump_test "c-lui"
RISC-V: Fix lui relaxation issue with code at address 0. This fixes a problem originally reported at https://github.com/riscv/riscv-binutils-gdb/issues/173 If you have code linked at address zero, you can have a lui instruction loading a value 0x800 which gets relaxed to a c.lui which is valid (c.lui 0x1 followed by addi -0x800). Relaxation can reduce the value below 0x800 at which point the c.lui 0x0 is no longer valid. We can fix this by converting the c.lui to a c.li which can load 0. bfd/ * elfnn-riscv.c (perform_relocation) <R_RISCV_RVC_LUI>: If RISCV_CONST_HIGH_PART (value) is zero, then convert c.lui instruction to c.li instruction, and use ENCODE_RVC_IMM to set value. ld/ * testsuite/ld-riscv-elf/c-lui-2.d: New. * testsuite/ld-riscv-elf/c-lui-2.ld: New. * testsuite/ld-riscv-elf/c-lui-2.s: New. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Run the c-lui-2 test.
2019-08-16 03:01:13 +08:00
run_dump_test "c-lui-2"
RISC-V: Print symbol address for jalr w/ zero offset. ld/ * testsuite/ld-riscv-elf/disas-jalr.d: New. * testsuite/ld-riscv-elf/disas-jalr.s: New. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Run new testcase. opcodes/ * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a jalr.
2018-01-06 09:51:23 +08:00
run_dump_test "disas-jalr"
RISC-V: Give error for ignored pcrel_lo addend. bfd/ * elfnn-riscv.c (riscv_elf_relocate_section): Use bfd_reloc_dangerous when pcrel_lo reloc has an addend. Use reloc_dangerous callback for bfd_reloc_dangerous. Use einfo instead of warning callback for errors. Add %X%P to error messages. ld/ * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Run pcrel-lo-addend test. * testsuite/ld-riscv-elf/pcrel-lo-addend.d: New. * testsuite/ld-riscv-elf/pcrel-lo-addend.s: New.
2018-02-16 02:53:46 +08:00
run_dump_test "pcrel-lo-addend"
RISC-V: Check the overflow for %pcrel_lo addend more strictly. The %pcrel_lo addend may causes the overflow, and need more than one %pcrel_hi values. But there may be only one auipc, shared by those %pcrel_lo with addends. However, the existing check method in the riscv_resolve_pcrel_lo_relocs, may not be able to work for some special/corner cases. Consider the testcases pcrel-lo-addend-2b. Before applying this patch, I can compile it successfully. But in fact the addend cause the value of %pcrel_hi to be different. This patch try to check the value of %pcrel_hi directly, to make sure it won't be changed. Otherwise, linker will report the following errors, (.text+0xa): dangerous relocation: %pcrel_lo overflow with an addend, the value of %pcrel_hi is 0x1000 without any addend, but may be 0x2000 after adding the %pcrel_lo addend The toolchain regressions, rv64gc-linux/rv64gc-elf/rv32gc-linux/rv32i-elf, pass expectedly and looks fine. bfd/ * elfnn-riscv.c (riscv_resolve_pcrel_lo_relocs): Check the values of %pcrel_hi, before and after adding the addend. Make sure the value won't be changed, otherwise, report dangerous error. ld/ * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated. * testsuite/ld-riscv-elf/pcrel-lo-addend-2a.d: Renamed from pcrel-lo-addend-2. * testsuite/ld-riscv-elf/pcrel-lo-addend-2a.s: Likewise. * testsuite/ld-riscv-elf/pcrel-lo-addend-2b.d: New testcase. * testsuite/ld-riscv-elf/pcrel-lo-addend-2b.s: Likewise.
2021-05-14 13:30:02 +08:00
run_dump_test "pcrel-lo-addend-2a"
run_dump_test "pcrel-lo-addend-2b"
RISC-V: Clarify the addends of pc-relative access. The original discussion was here, https://github.com/riscv/riscv-elf-psabi-doc/issues/184 After discussing with Kito Cheng, I think the addends of %pcrel_hi and %pcrel_lo are both allowed in GNU toolchain. However, both of the them mean the offset of symbols, rather than the pc address. But the addends of %got_pcrel_hi and it's %pcrel_lo do not look reasonable. I believe gcc won't generate the got patterns with addends, so linker should report dangerous relocation errors, in case the assembly code use them. Another issue was here, https://sourceware.org/pipermail/binutils/2021-June/116983.html At the beginnig, I suppose %pcrel_hi and %pcrel_lo are valid only when they are in the same input section. But Jim Wilson points out that gcc may generate %hi and %lo in the different input sections, when -freorder-blocks-and-partition option is used. So that a memory references for a loop may have the %hi outside the loop, but the %lo remain in the loop. However, it is hard to create the testcases, to see if %pcrel_hi and %pcrel_lo have the same behavior. Unfortunately, I notice that the current pcrel resolver cannot work for the above case. For now we build a hash table for pcrel at the start of riscv_elf_relocate_section, and then free the hash at the end. But riscv_elf_relocate_section only handles an input section at a time, so that means we can only resolve the %pcrel_hi and %pcrel_lo which are in the same input section. Otherwise, like the above case, we will report "%pcrel_lo missing matching %pcrel_hi" for them. I have no plan to improve this in the short-term, so maybe we can wait until someone meets the problem before we deal with it. bfd/ * elfnn-riscv.c (riscv_pcrel_hi_reloc): Added field to store the original relocation type, in case the type is converted to R_RISCV_HI20. (riscv_pcrel_lo_reloc): Removed unused name field. (riscv_pcrel_relocs): Added comments. (riscv_zero_pcrel_hi_reloc): Removed unused input_bfd. (riscv_record_pcrel_hi_reloc): Updated. (riscv_record_pcrel_lo_reloc): Likewise. (riscv_resolve_pcrel_lo_relocs): Likewise. Check the original type of auipc, to make sure the %pcrel_lo without any addends. Otherwise, report dangerous relocation error. (riscv_elf_relocate_section): Updated above functions are changed. For R_RISCV_GOT_HI20, report dangerous relocation error when addend isn't zero. ld/ * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated. * testsuite/ld-riscv-elf/pcrel-lo-addend-3a.d: New testcase. * testsuite/ld-riscv-elf/pcrel-lo-addend-3a.s: Likewise. * testsuite/ld-riscv-elf/pcrel-lo-addend-3b.d: New testcase. Should report error since the %pcrel_lo with addend refers to %got_pcrel_hi. * testsuite/ld-riscv-elf/pcrel-lo-addend-3b.s: Likewise. * testsuite/ld-riscv-elf/pcrel-lo-addend-3c.d: New testcase. Should report error since the %got_pcrel_hi with addend. * testsuite/ld-riscv-elf/pcrel-lo-addend-3c.s: Likewise. * testsuite/ld-riscv-elf/pcrel-lo-addend-3.ld: Likewise.
2021-06-22 12:02:52 +08:00
run_dump_test "pcrel-lo-addend-3a"
run_dump_test "pcrel-lo-addend-3b"
run_dump_test "pcrel-lo-addend-3c"
RISC-V: Added ld testcases for the medlow and medany code models. There are two linker scripts, code-model-01.ld and code-model-02.ld, which are corresponding to the two different memory layouts, * code-model-01.ld: the text section is in the 32-bit address range, but the data section is far away from the text section, which means the data section is over the 32-bit address range. * code-model-02.ld: the text section is over the 32-bit address range, but the data section is placed nearly zero address. We use the two linker scripts, to test the current medlow and medany behaviors of GNU ld, including the weak symbol references and the relaxations behaviors. Besides, these testcases also show the limits of the current medlow and medany code models, that is - we may get the truncated to fit errors when linking with the above two linker scripts. ld/ * testsuite/ld-riscv-elf/code-model-01.ld: New testcases to test the behaviors of the current medlow and medany code models. * testsuite/ld-riscv-elf/code-model-02.ld: Likewise. * testsuite/ld-riscv-elf/code-model-medany-01.d: Likewise. * testsuite/ld-riscv-elf/code-model-medany-02.d: Likewise. * testsuite/ld-riscv-elf/code-model-medany-weakref-01.d: Likewise. * testsuite/ld-riscv-elf/code-model-medany-weakref-02.d: Likewise. * testsuite/ld-riscv-elf/code-model-medlow-01.d: Likewise. * testsuite/ld-riscv-elf/code-model-medlow-02.d: Likewise. * testsuite/ld-riscv-elf/code-model-medlow-weakref-01.d: Likewise. * testsuite/ld-riscv-elf/code-model-medlow-weakref-02.d: Likewise. * testsuite/ld-riscv-elf/code-model-relax-medany-01.d: Likewise. * testsuite/ld-riscv-elf/code-model-relax-medany-02.d: Likewise. * testsuite/ld-riscv-elf/code-model-relax-medany-weakref-01.d: Likewise. * testsuite/ld-riscv-elf/code-model-relax-medany-weakref-02.d: Likewise. * testsuite/ld-riscv-elf/code-model-relax-medlow-01.d: Likewise. * testsuite/ld-riscv-elf/code-model-relax-medlow-02.d: Likewise. * testsuite/ld-riscv-elf/code-model-relax-medlow-weakref-01.d: Likewise. * testsuite/ld-riscv-elf/code-model-relax-medlow-weakref-02.d: Likewise. * testsuite/ld-riscv-elf/code-model.s: Likewise. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
2021-12-14 12:53:48 +08:00
run_dump_test "code-model-medlow-01"
run_dump_test "code-model-medlow-02"
run_dump_test "code-model-medlow-weakref-01"
run_dump_test "code-model-medlow-weakref-02"
run_dump_test "code-model-medany-01"
run_dump_test "code-model-medany-02"
run_dump_test "code-model-medany-weakref-01"
run_dump_test "code-model-medany-weakref-02"
run_dump_test "code-model-relax-medlow-01"
run_dump_test "code-model-relax-medlow-02"
run_dump_test "code-model-relax-medlow-weakref-01"
run_dump_test "code-model-relax-medlow-weakref-02"
run_dump_test "code-model-relax-medany-01"
run_dump_test "code-model-relax-medany-02"
run_dump_test "code-model-relax-medany-weakref-01"
run_dump_test "code-model-relax-medany-weakref-02"
RISC-V: Merge ELF attribute for ld. 2019-01-16 Kito Cheng <kito@andestech.com> Nelson Chu <nelson@andestech.com> bfd/ * elfnn-riscv.c (in_subsets): New. (out_subsets): Likewise. (merged_subsets): Likewise. (riscv_std_ext_p): Likewise. (riscv_non_std_ext_p): Likewise. (riscv_std_sv_ext_p): Likewise. (riscv_non_std_sv_ext_p): Likewise. (riscv_version_mismatch): Likewise. (riscv_i_or_e_p): Likewise. (riscv_merge_std_ext): Likewise. (riscv_merge_non_std_and_sv_ext): Likewise. (riscv_merge_arch_attr_info): Likewise. (riscv_merge_attributes): Likewise. (_bfd_riscv_elf_merge_private_bfd_data): Merge attribute. ld/ * testsuite/ld-elf/orphan-region.d: XFAIL for RISC-V, because add new section. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Add new tests. * testsuite/ld-riscv-elf/attr-merge-arch-01.d: New test. * testsuite/ld-riscv-elf/attr-merge-arch-01a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-01b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-02a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-02b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-failed-01a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-failed-01b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-stack-align-a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-stack-align-b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-stack-align-failed-a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-stack-align-failed-b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-stack-align-failed.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-01a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-01b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-02a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-02b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-03a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-03b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-04a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-04b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-05a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-05b.s: Likewise.
2019-01-17 05:28:35 +08:00
run_dump_test "attr-merge-arch-01"
run_dump_test "attr-merge-arch-02"
run_dump_test "attr-merge-arch-03"
run_dump_test "attr-merge-strict-align-01"
run_dump_test "attr-merge-strict-align-02"
run_dump_test "attr-merge-strict-align-03"
run_dump_test "attr-merge-strict-align-04"
run_dump_test "attr-merge-strict-align-05"
run_dump_test "attr-merge-stack-align"
RISC-V: The object without priv spec attributes can be linked with any object. bfd/ * elfnn-riscv.c (riscv_merge_attributes): Add new boolean priv_may_conflict, in_priv_zero and out_priv_zero to decide whether the object can be linked according to it's priv attributes. The object without any priv spec attributes can be linked with others. If the first input object doesn't contain any priv attributes, then we need to copy the setting from the next input one. Also report more detailed error messages to user. ld/ * testsuite/ld-riscv-elf/attr-merge-priv-spec.d: Rename to attr-merge-priv-spec-01.d. * testsuite/ld-riscv-elf/attr-merge-priv-spec-c.s: Set priv spec to 1.11. * testsuite/ld-riscv-elf/attr-merge-priv-spec-d.s: Empty priv spec setting. * testsuite/ld-riscv-elf/attr-merge-priv-spec-02.d: New testcase. * testsuite/ld-riscv-elf/attr-merge-priv-spec-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-01.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-04.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-05.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-06.d: Likewise. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
2020-05-29 16:56:36 +08:00
run_dump_test "attr-merge-priv-spec-01"
run_dump_test "attr-merge-priv-spec-02"
run_dump_test "attr-merge-priv-spec-03"
RISC-V: Merge ELF attribute for ld. 2019-01-16 Kito Cheng <kito@andestech.com> Nelson Chu <nelson@andestech.com> bfd/ * elfnn-riscv.c (in_subsets): New. (out_subsets): Likewise. (merged_subsets): Likewise. (riscv_std_ext_p): Likewise. (riscv_non_std_ext_p): Likewise. (riscv_std_sv_ext_p): Likewise. (riscv_non_std_sv_ext_p): Likewise. (riscv_version_mismatch): Likewise. (riscv_i_or_e_p): Likewise. (riscv_merge_std_ext): Likewise. (riscv_merge_non_std_and_sv_ext): Likewise. (riscv_merge_arch_attr_info): Likewise. (riscv_merge_attributes): Likewise. (_bfd_riscv_elf_merge_private_bfd_data): Merge attribute. ld/ * testsuite/ld-elf/orphan-region.d: XFAIL for RISC-V, because add new section. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Add new tests. * testsuite/ld-riscv-elf/attr-merge-arch-01.d: New test. * testsuite/ld-riscv-elf/attr-merge-arch-01a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-01b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-02a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-02b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-failed-01a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-failed-01b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-stack-align-a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-stack-align-b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-stack-align-failed-a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-stack-align-failed-b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-stack-align-failed.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-01a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-01b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-02a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-02b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-03a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-03b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-04a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-04b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-05a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-05b.s: Likewise.
2019-01-17 05:28:35 +08:00
run_dump_test "attr-merge-arch-failed-01"
RISC-V: Report warnings rather than errors for the mis-matched ISA versions. Same as the privileged spec attributes check - different ISA versions should be compatible, unless there are some known conflicts. Therefore, we should allow to link objects with different ISA versions, and update the output ISA versions once the corresponding input ones are newer. But it's better to also warn people that the conflicts may happen when the ISA versions are mis-matched. bfd/ * elfnn-riscv.c (riscv_version_mismatch): Change the return type from void to bfd_boolean. Report warnings rather than errors when the ISA versions are mis-matched. Afterwards, remember to update the output ISA versions to the newest ones. (riscv_merge_std_ext): Allow to link objects with different standard ISA versions. Try to add output ISA versions to merged_subsets first. (riscv_merge_multi_letter_ext): Likewise. But for standard additional ISA and non-standard ISA versions. ld/ * testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d: Update the message from error to warning. * testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d: New testcases. * testsuite/ld-riscv-elf/attr-merge-arch-failed-02a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-failed-02b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-failed-02c.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-failed-02d.s: Likewise. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
2020-08-18 17:48:34 +08:00
run_dump_test "attr-merge-arch-failed-02"
RISC-V: Merge ELF attribute for ld. 2019-01-16 Kito Cheng <kito@andestech.com> Nelson Chu <nelson@andestech.com> bfd/ * elfnn-riscv.c (in_subsets): New. (out_subsets): Likewise. (merged_subsets): Likewise. (riscv_std_ext_p): Likewise. (riscv_non_std_ext_p): Likewise. (riscv_std_sv_ext_p): Likewise. (riscv_non_std_sv_ext_p): Likewise. (riscv_version_mismatch): Likewise. (riscv_i_or_e_p): Likewise. (riscv_merge_std_ext): Likewise. (riscv_merge_non_std_and_sv_ext): Likewise. (riscv_merge_arch_attr_info): Likewise. (riscv_merge_attributes): Likewise. (_bfd_riscv_elf_merge_private_bfd_data): Merge attribute. ld/ * testsuite/ld-elf/orphan-region.d: XFAIL for RISC-V, because add new section. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Add new tests. * testsuite/ld-riscv-elf/attr-merge-arch-01.d: New test. * testsuite/ld-riscv-elf/attr-merge-arch-01a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-01b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-02a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-02b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-failed-01a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-failed-01b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-stack-align-a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-stack-align-b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-stack-align-failed-a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-stack-align-failed-b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-stack-align-failed.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-01a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-01b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-02a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-02b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-03a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-03b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-04a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-04b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-05a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-05b.s: Likewise.
2019-01-17 05:28:35 +08:00
run_dump_test "attr-merge-stack-align-failed"
RISC-V: The object without priv spec attributes can be linked with any object. bfd/ * elfnn-riscv.c (riscv_merge_attributes): Add new boolean priv_may_conflict, in_priv_zero and out_priv_zero to decide whether the object can be linked according to it's priv attributes. The object without any priv spec attributes can be linked with others. If the first input object doesn't contain any priv attributes, then we need to copy the setting from the next input one. Also report more detailed error messages to user. ld/ * testsuite/ld-riscv-elf/attr-merge-priv-spec.d: Rename to attr-merge-priv-spec-01.d. * testsuite/ld-riscv-elf/attr-merge-priv-spec-c.s: Set priv spec to 1.11. * testsuite/ld-riscv-elf/attr-merge-priv-spec-d.s: Empty priv spec setting. * testsuite/ld-riscv-elf/attr-merge-priv-spec-02.d: New testcase. * testsuite/ld-riscv-elf/attr-merge-priv-spec-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-01.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-04.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-05.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-06.d: Likewise. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
2020-05-29 16:56:36 +08:00
run_dump_test "attr-merge-priv-spec-failed-01"
run_dump_test "attr-merge-priv-spec-failed-02"
run_dump_test "attr-merge-priv-spec-failed-03"
run_dump_test "attr-merge-priv-spec-failed-04"
run_dump_test "attr-merge-priv-spec-failed-05"
run_dump_test "attr-merge-priv-spec-failed-06"
RISC-V: Add PT_RISCV_ATTRIBUTES and add it to PHDR. We added PT_RISCV_ATTRIBUTES to program header to make .riscv.attribute easier to find in dynamic loader or kernel. Ref: https://github.com/riscv/riscv-elf-psabi-doc/pull/71 ChangeLog: bfd/ * elfnn-riscv.c(RISCV_ATTRIBUTES_SECTION_NAME): New. (riscv_elf_additional_program_headers): Ditto. (riscv_elf_modify_segment_map): Ditto. (elf_backend_additional_program_headers): Ditto. (elf_backend_modify_segment_map): Ditto. (elf_backend_obj_attrs_section): Use RISCV_ATTRIBUTES_SECTION_NAME rather than string literal. binutils/ * readelf.c(get_riscv_segment_type): New. (get_segment_type): Handle EM_RISCV. include/ * elf/riscv.h (PT_RISCV_ATTRIBUTES): New. * testsuite/ld-elf/orphan-region.ld: Discard .riscv.attributes section for simplify testcase. * testsuite/ld-riscv-elf/attr-phdr.d: New. * testsuite/ld-riscv-elf/attr-phdr.s: Ditto. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Add attr-phdr to testcase.
2021-06-29 14:36:35 +08:00
run_dump_test "attr-phdr"
RISC-V: Fix riscv gas/ld testsuites failures for big endian. Add riscv_choose_[ilp32|lp64]_emul, and use them to choose the correct linker script rather than set elf[32|64]lriscv directly. gas/ * testsuite/gas/riscv/li32.d: Accept bigriscv in addition to littleriscv. * testsuite/gas/riscv/li64.d: Likewise. * testsuite/gas/riscv/lla32.d: Likewise. * testsuite/gas/riscv/lla64.d: Likewise. * testsuite/gas/riscv/march-ok-g2.d: Likewise. * testsuite/gas/riscv/march-ok-g2_p1.d: Likewise. * testsuite/gas/riscv/march-ok-g2p0.d: Likewise. * testsuite/gas/riscv/march-ok-i2p0.d: Likewise. * testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d: Likewise. * testsuite/gas/riscv/march-ok-nse-with-version.d: Likewise. * testsuite/gas/riscv/march-ok-two-nse.d: Likewise. ld/ * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Added riscv_choose_[ilp32|lp64]_emul to choose the correct linker script. * testsuite/ld-riscv-elf/attr-merge-arch-01.d: Call riscv_choose_[ilp32|lp64]_emul instead of hardcoding elf[32|64]lriscv. * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d: Likewise. * testsuite/ld-riscv-elf/c-lui-2.d: Likewise. * testsuite/ld-riscv-elf/c-lui.d: Likewise. * testsuite/ld-riscv-elf/call-relax.d: Likewise. * testsuite/ld-riscv-elf/pcrel-lo-addend-2.d: Likewise. * testsuite/ld-riscv-elf/pcrel-lo-addend.d: Likewise. * testsuite/ld-riscv-elf/weakref32.d: Accept bigriscv in addition to littleriscv. * testsuite/ld-riscv-elf/weakref64.d: Likewise.
2021-01-06 05:50:39 +08:00
run_ld_link_tests [list \
[list "Weak reference 32" "-T weakref.ld -m[riscv_choose_ilp32_emul]" "" \
"-march=rv32i -mabi=ilp32" {weakref32.s} \
{{objdump -d weakref32.d}} "weakref32"] \
[list "Weak reference 64" "-T weakref.ld -m[riscv_choose_lp64_emul]" "" \
"-march=rv64i -mabi=lp64" {weakref64.s} \
{{objdump -d weakref64.d}} "weakref64"]]
Riscv shared libraries should not export __global_pointer$. ld/ * emulparams/elf32lriscv-defs.sh (SDATA_START_SYMBOLS): Mark __global_pointer$ as HIDDEN. * testsuite/ld-riscv-elf/gp-hidden-64.rd: New. * testsuite/ld-riscv-elf/gp-hidden-lib.rd: New. * testsuite/ld-riscv-elf/gp-hidden-lib.s: New. * testsuite/ld-riscv-elf/gp-hidden-ver-64.rd: New. * testsuite/ld-riscv-elf/gp-hidden-ver.rd: New. * testsuite/ld-riscv-elf/gp-hidden-ver.s: New. * testsuite/ld-riscv-elf/gp-hidder-ver.ver: New. * testsuite/ld-riscv-elf/gp-hidden.rd: New. * testsuite/ld-riscv-elf/gp-hidden.s: New. * testsuite/ld-riscv-elf/gp-hidden.sd: New. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Change riscv to riscv*. Run the new tests with run_ld_link_tests.
2017-12-05 09:37:55 +08:00
RISC-V: Fix accidental embedded -shared regressions. ld/ * testsuite/ld-riscv-elf/c-lui.d: Don't use -shared. Check for _start instead of .text. * testsuite/ld-riscv-elf/c-lui.s: Add _start label. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Before __global_pointer$ tests, add call to check_shared_lib_support.
2018-01-09 09:55:29 +08:00
# The following tests require shared library support.
if ![check_shared_lib_support] {
return
}
RISC-V: PR27566, Do not relax when data segment phase is exp_seg_relro_adjust. 2021-05-31 Nelson Chu <nelson.chu@sifive.com> Lifang Xia <lifang_xia@c-sky.com> The data segment phase exp_seg_relro_adjust means we are still adjusting the relro segments, so we will get the symbol values which havn't consider the relro. It is dangerous and we shouldn't do the relaxations at this stage. Otherwise, we may get the truncated fails when the relax range crossing the data segment. One of the solution is that, we use a pointer to monitor the data segment phase while relaxing, to know whether the relro has been handled or not. Once we check the phase is exp_seg_relro_adjust, we should skip this round of relaxations, since the incorrect symbol values will affect the correctness of relaxations. I think we probably need to record more information about data segment or alignments in the future, to make sure it is safe to doing relaxations. For the two new testcases, relro-relax-lui and relro-relax-pcrel, we get the following truncated errors when using toolchains, which enable relro: (.text+0x0): relocation truncated to fit: R_RISCV_GPREL_I against symbol `SymbolRodata' defined in .rodata section in test1.o After applying this patch, the truncated errors should be resolved. However, only linux toolchains support -z relro, so we only test these two testcases when supporting shared library. bfd/ PR 27566 * elfnn-riscv.c (struct riscv_elf_link_hash_table): New integer pointer to monitor the data segment phase. (bfd_elfNN_riscv_set_data_segment_info): New function called by after_allocation, to set the data_segment_phase from expld.dataseg. (_bfd_riscv_relax_section): Don't relax when data_segment_phase is exp_seg_relro_adjust (0x4). * elfxx-riscv.h (bfd_elf32_riscv_set_data_segment_info): New extern. (bfd_elf64_riscv_set_data_segment_info): Likewise. ld/ PR 27566 * emultempl/riscvelf.em (after_allocation): Call riscv_set_data_segment_info to set data segment phase before relaxing. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated. * testsuite/ld-riscv-elf/relro-relax-lui.d: New testcase. * testsuite/ld-riscv-elf/relro-relax-lui.s: Likewise. * testsuite/ld-riscv-elf/relro-relax-pcrel.d: Likewise. * testsuite/ld-riscv-elf/relro-relax-pcrel.s: Likewise.
2021-05-12 23:26:33 +08:00
run_dump_test "relro-relax-lui"
run_dump_test "relro-relax-pcrel"
RISC-V: Support STO_RISCV_VARIANT_CC and DT_RISCV_VARIANT_CC. This is the original discussion, https://github.com/riscv/riscv-elf-psabi-doc/pull/190 And here is the glibc part, https://sourceware.org/pipermail/libc-alpha/2021-August/129931.html For binutils part, we need to support a new direcitve: .variant_cc. The function symbol marked by .variant_cc means it need to be resolved directly without resolver for dynamic linker. We also add a new dynamic entry, STO_RISCV_VARIANT_CC, to indicate there are symbols with the special attribute in the dynamic symbol table of the object. I heard that llvm already have supported this in their mainline, so I think it's time to commit this. bfd/ * elfnn-riscv.c (riscv_elf_link_hash_table): Added variant_cc flag. It is used to check if relocations for variant CC symbols may be present. (allocate_dynrelocs): If the symbol has STO_RISCV_VARIANT_CC flag, then raise the variant_cc flag of riscv_elf_link_hash_table. (riscv_elf_size_dynamic_sections): Added dynamic entry for variant_cc. (riscv_elf_merge_symbol_attribute): New function, used to merge non-visibility st_other attributes, including STO_RISCV_VARIANT_CC. binutils/ * readelf.c (get_riscv_dynamic_type): New function. (get_dynamic_type): Called get_riscv_dynamic_type for riscv targets. (get_riscv_symbol_other): New function. (get_symbol_other): Called get_riscv_symbol_other for riscv targets. gas/ * config/tc-riscv.c (s_variant_cc): Marked symbol that it follows a variant CC convention. (riscv_elf_copy_symbol_attributes): Same as elf_copy_symbol_attributes, but without copying st_other. If a function symbol has special st_other value set via directives, then attaching an IFUNC resolver to that symbol should not override the st_other setting. (riscv_pseudo_table): Support variant_cc diretive. * config/tc-riscv.h (OBJ_COPY_SYMBOL_ATTRIBUTES): Defined. * testsuite/gas/riscv/variant_cc-set.d: New testcase. * testsuite/gas/riscv/variant_cc-set.s: Likewise. * testsuite/gas/riscv/variant_cc.d: Likewise. * testsuite/gas/riscv/variant_cc.s: Likewise. include/ * elf/riscv.h (DT_RISCV_VARIANT_CC): Defined to (DT_LOPROC + 1). (STO_RISCV_VARIANT_CC): Defined to 0x80. ld/ * testsuite/ld-riscv-elf/variant_cc-1.s: New testcase. * testsuite/ld-riscv-elf/variant_cc-2.s: Likewise. * testsuite/ld-riscv-elf/variant_cc-now.d: Likewise. * testsuite/ld-riscv-elf/variant_cc-r.d: Likewise. * testsuite/ld-riscv-elf/variant_cc-shared.d: Likewise. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
2021-08-11 16:26:39 +08:00
run_dump_test "variant_cc-now"
run_dump_test "variant_cc-shared"
run_dump_test "variant_cc-r"
elf/riscv: Fix relaxation with aliases [PR28021] the fix for PR22756 only changed behaviour for hidden aliases, but the same situation exists for non-hidden aliases: sym_hashes[] can contain multiple entries pointing to the same symbol structure leading to relaxation adjustment to be applied twice. Fix this by testing for duplicates for everything that looks like it has a version. PR ld/28021 bfd/ * elfnn-riscv.c (riscv_relax_delete_bytes): Check for any versioning. ld/ * testsuite/ld-riscv-elf/relax-twice.ver: New. * testsuite/ld-riscv-elf/relax-twice-1.s: New. * testsuite/ld-riscv-elf/relax-twice-2.s: New. * testsuite/ld-riscv-elf/ld-riscv-elf.exp (run_relax_twice_test): New, and call it.
2021-06-28 23:57:17 +08:00
run_relax_twice_test
RISC-V: PR27566, Do not relax when data segment phase is exp_seg_relro_adjust. 2021-05-31 Nelson Chu <nelson.chu@sifive.com> Lifang Xia <lifang_xia@c-sky.com> The data segment phase exp_seg_relro_adjust means we are still adjusting the relro segments, so we will get the symbol values which havn't consider the relro. It is dangerous and we shouldn't do the relaxations at this stage. Otherwise, we may get the truncated fails when the relax range crossing the data segment. One of the solution is that, we use a pointer to monitor the data segment phase while relaxing, to know whether the relro has been handled or not. Once we check the phase is exp_seg_relro_adjust, we should skip this round of relaxations, since the incorrect symbol values will affect the correctness of relaxations. I think we probably need to record more information about data segment or alignments in the future, to make sure it is safe to doing relaxations. For the two new testcases, relro-relax-lui and relro-relax-pcrel, we get the following truncated errors when using toolchains, which enable relro: (.text+0x0): relocation truncated to fit: R_RISCV_GPREL_I against symbol `SymbolRodata' defined in .rodata section in test1.o After applying this patch, the truncated errors should be resolved. However, only linux toolchains support -z relro, so we only test these two testcases when supporting shared library. bfd/ PR 27566 * elfnn-riscv.c (struct riscv_elf_link_hash_table): New integer pointer to monitor the data segment phase. (bfd_elfNN_riscv_set_data_segment_info): New function called by after_allocation, to set the data_segment_phase from expld.dataseg. (_bfd_riscv_relax_section): Don't relax when data_segment_phase is exp_seg_relro_adjust (0x4). * elfxx-riscv.h (bfd_elf32_riscv_set_data_segment_info): New extern. (bfd_elf64_riscv_set_data_segment_info): Likewise. ld/ PR 27566 * emultempl/riscvelf.em (after_allocation): Call riscv_set_data_segment_info to set data segment phase before relaxing. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated. * testsuite/ld-riscv-elf/relro-relax-lui.d: New testcase. * testsuite/ld-riscv-elf/relro-relax-lui.s: Likewise. * testsuite/ld-riscv-elf/relro-relax-pcrel.d: Likewise. * testsuite/ld-riscv-elf/relro-relax-pcrel.s: Likewise.
2021-05-12 23:26:33 +08:00
RISC-V: Fix riscv gas/ld testsuites failures for big endian. Add riscv_choose_[ilp32|lp64]_emul, and use them to choose the correct linker script rather than set elf[32|64]lriscv directly. gas/ * testsuite/gas/riscv/li32.d: Accept bigriscv in addition to littleriscv. * testsuite/gas/riscv/li64.d: Likewise. * testsuite/gas/riscv/lla32.d: Likewise. * testsuite/gas/riscv/lla64.d: Likewise. * testsuite/gas/riscv/march-ok-g2.d: Likewise. * testsuite/gas/riscv/march-ok-g2_p1.d: Likewise. * testsuite/gas/riscv/march-ok-g2p0.d: Likewise. * testsuite/gas/riscv/march-ok-i2p0.d: Likewise. * testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d: Likewise. * testsuite/gas/riscv/march-ok-nse-with-version.d: Likewise. * testsuite/gas/riscv/march-ok-two-nse.d: Likewise. ld/ * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Added riscv_choose_[ilp32|lp64]_emul to choose the correct linker script. * testsuite/ld-riscv-elf/attr-merge-arch-01.d: Call riscv_choose_[ilp32|lp64]_emul instead of hardcoding elf[32|64]lriscv. * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d: Likewise. * testsuite/ld-riscv-elf/c-lui-2.d: Likewise. * testsuite/ld-riscv-elf/c-lui.d: Likewise. * testsuite/ld-riscv-elf/call-relax.d: Likewise. * testsuite/ld-riscv-elf/pcrel-lo-addend-2.d: Likewise. * testsuite/ld-riscv-elf/pcrel-lo-addend.d: Likewise. * testsuite/ld-riscv-elf/weakref32.d: Accept bigriscv in addition to littleriscv. * testsuite/ld-riscv-elf/weakref64.d: Likewise.
2021-01-06 05:50:39 +08:00
set abis [list rv32gc ilp32 [riscv_choose_ilp32_emul] rv64gc lp64 [riscv_choose_lp64_emul]]
Riscv shared libraries should not export __global_pointer$. ld/ * emulparams/elf32lriscv-defs.sh (SDATA_START_SYMBOLS): Mark __global_pointer$ as HIDDEN. * testsuite/ld-riscv-elf/gp-hidden-64.rd: New. * testsuite/ld-riscv-elf/gp-hidden-lib.rd: New. * testsuite/ld-riscv-elf/gp-hidden-lib.s: New. * testsuite/ld-riscv-elf/gp-hidden-ver-64.rd: New. * testsuite/ld-riscv-elf/gp-hidden-ver.rd: New. * testsuite/ld-riscv-elf/gp-hidden-ver.s: New. * testsuite/ld-riscv-elf/gp-hidder-ver.ver: New. * testsuite/ld-riscv-elf/gp-hidden.rd: New. * testsuite/ld-riscv-elf/gp-hidden.s: New. * testsuite/ld-riscv-elf/gp-hidden.sd: New. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Change riscv to riscv*. Run the new tests with run_ld_link_tests.
2017-12-05 09:37:55 +08:00
foreach { arch abi emul } $abis {
Really fix riscv shared library __global_pointer$ problem. ld/ * emulparams/elf32lriscv-defs.sh (SDATA_START_SYMBOLS): Remove HIDDEN. Don't define __global_pointer$ when CREATE_SHLIB. * testsuite/ld-riscv-elf/gp-hidden-64.rd, * testsuite/ld-riscv-elf/gp-hidden-lib.rd, * testsuite/ld-riscv-elf/gp-hidden-lib.s, * testsuite/ld-riscv-elf/gp-hidden-ver-64.rd, * testsuite/ld-riscv-elf/gp-hidden-ver.rd, * testsuite/ld-riscv-elf/gp-hidden-ver.s, * testsuite/ld-riscv-elf/gp-hidden-ver.ver, * testsuite/ld-riscv-elf/gp-hidden.rd, * testsuite/ld-riscv-elf/gp-hidden.s, * testsuite/ld-riscv-elf/gp-hidden.sd: Delete. * testsuite/ld-riscv-elf/gp-test-lib.sd, * testsuite/ld-riscv-elf/gp-test.s, * testsuite/ld-riscv-elf/gp-test.sd: New. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Rewrite gp tests.
2017-12-06 06:42:12 +08:00
# This checks whether our linker scripts handle __global_pointer$
# correctly. It should be defined in executables and PIE, but not
# in shared libraries.
Riscv shared libraries should not export __global_pointer$. ld/ * emulparams/elf32lriscv-defs.sh (SDATA_START_SYMBOLS): Mark __global_pointer$ as HIDDEN. * testsuite/ld-riscv-elf/gp-hidden-64.rd: New. * testsuite/ld-riscv-elf/gp-hidden-lib.rd: New. * testsuite/ld-riscv-elf/gp-hidden-lib.s: New. * testsuite/ld-riscv-elf/gp-hidden-ver-64.rd: New. * testsuite/ld-riscv-elf/gp-hidden-ver.rd: New. * testsuite/ld-riscv-elf/gp-hidden-ver.s: New. * testsuite/ld-riscv-elf/gp-hidder-ver.ver: New. * testsuite/ld-riscv-elf/gp-hidden.rd: New. * testsuite/ld-riscv-elf/gp-hidden.s: New. * testsuite/ld-riscv-elf/gp-hidden.sd: New. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Change riscv to riscv*. Run the new tests with run_ld_link_tests.
2017-12-05 09:37:55 +08:00
set suff64 [string map {ilp32 "" lp64 -64} $abi]
run_ld_link_tests [list \
Really fix riscv shared library __global_pointer$ problem. ld/ * emulparams/elf32lriscv-defs.sh (SDATA_START_SYMBOLS): Remove HIDDEN. Don't define __global_pointer$ when CREATE_SHLIB. * testsuite/ld-riscv-elf/gp-hidden-64.rd, * testsuite/ld-riscv-elf/gp-hidden-lib.rd, * testsuite/ld-riscv-elf/gp-hidden-lib.s, * testsuite/ld-riscv-elf/gp-hidden-ver-64.rd, * testsuite/ld-riscv-elf/gp-hidden-ver.rd, * testsuite/ld-riscv-elf/gp-hidden-ver.s, * testsuite/ld-riscv-elf/gp-hidden-ver.ver, * testsuite/ld-riscv-elf/gp-hidden.rd, * testsuite/ld-riscv-elf/gp-hidden.s, * testsuite/ld-riscv-elf/gp-hidden.sd: Delete. * testsuite/ld-riscv-elf/gp-test-lib.sd, * testsuite/ld-riscv-elf/gp-test.s, * testsuite/ld-riscv-elf/gp-test.sd: New. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Rewrite gp tests.
2017-12-06 06:42:12 +08:00
[list "gp test ($abi shared library)" \
Riscv shared libraries should not export __global_pointer$. ld/ * emulparams/elf32lriscv-defs.sh (SDATA_START_SYMBOLS): Mark __global_pointer$ as HIDDEN. * testsuite/ld-riscv-elf/gp-hidden-64.rd: New. * testsuite/ld-riscv-elf/gp-hidden-lib.rd: New. * testsuite/ld-riscv-elf/gp-hidden-lib.s: New. * testsuite/ld-riscv-elf/gp-hidden-ver-64.rd: New. * testsuite/ld-riscv-elf/gp-hidden-ver.rd: New. * testsuite/ld-riscv-elf/gp-hidden-ver.s: New. * testsuite/ld-riscv-elf/gp-hidder-ver.ver: New. * testsuite/ld-riscv-elf/gp-hidden.rd: New. * testsuite/ld-riscv-elf/gp-hidden.s: New. * testsuite/ld-riscv-elf/gp-hidden.sd: New. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Change riscv to riscv*. Run the new tests with run_ld_link_tests.
2017-12-05 09:37:55 +08:00
"-m$emul -shared" "" \
"-march=$arch -mabi=$abi -fpic" \
Really fix riscv shared library __global_pointer$ problem. ld/ * emulparams/elf32lriscv-defs.sh (SDATA_START_SYMBOLS): Remove HIDDEN. Don't define __global_pointer$ when CREATE_SHLIB. * testsuite/ld-riscv-elf/gp-hidden-64.rd, * testsuite/ld-riscv-elf/gp-hidden-lib.rd, * testsuite/ld-riscv-elf/gp-hidden-lib.s, * testsuite/ld-riscv-elf/gp-hidden-ver-64.rd, * testsuite/ld-riscv-elf/gp-hidden-ver.rd, * testsuite/ld-riscv-elf/gp-hidden-ver.s, * testsuite/ld-riscv-elf/gp-hidden-ver.ver, * testsuite/ld-riscv-elf/gp-hidden.rd, * testsuite/ld-riscv-elf/gp-hidden.s, * testsuite/ld-riscv-elf/gp-hidden.sd: Delete. * testsuite/ld-riscv-elf/gp-test-lib.sd, * testsuite/ld-riscv-elf/gp-test.s, * testsuite/ld-riscv-elf/gp-test.sd: New. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Rewrite gp tests.
2017-12-06 06:42:12 +08:00
{ gp-test.s } \
[list "readelf --syms gp-test-lib.sd"] \
"gp-test-lib-${abi}.so"] \
[list "gp test ($abi executable)" \
"-m$emul" "" \
Riscv shared libraries should not export __global_pointer$. ld/ * emulparams/elf32lriscv-defs.sh (SDATA_START_SYMBOLS): Mark __global_pointer$ as HIDDEN. * testsuite/ld-riscv-elf/gp-hidden-64.rd: New. * testsuite/ld-riscv-elf/gp-hidden-lib.rd: New. * testsuite/ld-riscv-elf/gp-hidden-lib.s: New. * testsuite/ld-riscv-elf/gp-hidden-ver-64.rd: New. * testsuite/ld-riscv-elf/gp-hidden-ver.rd: New. * testsuite/ld-riscv-elf/gp-hidden-ver.s: New. * testsuite/ld-riscv-elf/gp-hidder-ver.ver: New. * testsuite/ld-riscv-elf/gp-hidden.rd: New. * testsuite/ld-riscv-elf/gp-hidden.s: New. * testsuite/ld-riscv-elf/gp-hidden.sd: New. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Change riscv to riscv*. Run the new tests with run_ld_link_tests.
2017-12-05 09:37:55 +08:00
"-march=$arch -mabi=$abi" \
Really fix riscv shared library __global_pointer$ problem. ld/ * emulparams/elf32lriscv-defs.sh (SDATA_START_SYMBOLS): Remove HIDDEN. Don't define __global_pointer$ when CREATE_SHLIB. * testsuite/ld-riscv-elf/gp-hidden-64.rd, * testsuite/ld-riscv-elf/gp-hidden-lib.rd, * testsuite/ld-riscv-elf/gp-hidden-lib.s, * testsuite/ld-riscv-elf/gp-hidden-ver-64.rd, * testsuite/ld-riscv-elf/gp-hidden-ver.rd, * testsuite/ld-riscv-elf/gp-hidden-ver.s, * testsuite/ld-riscv-elf/gp-hidden-ver.ver, * testsuite/ld-riscv-elf/gp-hidden.rd, * testsuite/ld-riscv-elf/gp-hidden.s, * testsuite/ld-riscv-elf/gp-hidden.sd: Delete. * testsuite/ld-riscv-elf/gp-test-lib.sd, * testsuite/ld-riscv-elf/gp-test.s, * testsuite/ld-riscv-elf/gp-test.sd: New. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Rewrite gp tests.
2017-12-06 06:42:12 +08:00
{ gp-test.s } \
[list "readelf --syms gp-test.sd"] \
"gp-test-${abi}"]]
Riscv shared libraries should not export __global_pointer$. ld/ * emulparams/elf32lriscv-defs.sh (SDATA_START_SYMBOLS): Mark __global_pointer$ as HIDDEN. * testsuite/ld-riscv-elf/gp-hidden-64.rd: New. * testsuite/ld-riscv-elf/gp-hidden-lib.rd: New. * testsuite/ld-riscv-elf/gp-hidden-lib.s: New. * testsuite/ld-riscv-elf/gp-hidden-ver-64.rd: New. * testsuite/ld-riscv-elf/gp-hidden-ver.rd: New. * testsuite/ld-riscv-elf/gp-hidden-ver.s: New. * testsuite/ld-riscv-elf/gp-hidder-ver.ver: New. * testsuite/ld-riscv-elf/gp-hidden.rd: New. * testsuite/ld-riscv-elf/gp-hidden.s: New. * testsuite/ld-riscv-elf/gp-hidden.sd: New. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Change riscv to riscv*. Run the new tests with run_ld_link_tests.
2017-12-05 09:37:55 +08:00
}
RISC-V: Report unresolved relocation error via linker's callback function. Two patches from Nelson Chu. It is better to use the linker's callback functions to handle the link time error when relocating. The unresolved relocation error can be regarded as an unsupported relocation. To make user easier to understand different errors, we need to extend the current error message format of the callback function since the format is fixed. bfd/ * elfnn-riscv.c (riscv_elf_relocate_section): Use asprintf to extend the error message if needed, and then store the result into the `msg_buf`. Finally, remember to free the unused `msg_buf`. All error message for the dangerous relocation should be set before we call the callback function. If we miss the error message since linker runs out of memory, we should set the default error message for the error. ld/ * testsuite/ld-riscv-elf/lib-nopic-01a.s: Create the shared library lib-nopic-01a.so, it will be linked with lib-nopic-01b.s. * testsuite/ld-riscv-elf/lib-nopic-01b.s: Add new test for the unresolved relocation. Link the non-pic code into a shared library may cause the error. * testsuite/ld-riscv-elf/lib-nopic-01b.d: Likewise. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Run the new test only when the shared library is supported. R_RISCV_CALL, R_RISCV_JAL and R_RISCV_RVC_JUMP are pc-relative relocation. For now, we do not allow the object with these relocation links into a shared library since the referenced symbols may be loaded to the places that too far from the pc. We can improve the error message for these unsupported relocation to notice user that they should recompile their code with `fPIC`. bfd/ * elfnn-riscv.c (riscv_elf_relocate_section): Report the error message that user should recompile their code with `fPIC` when linking non-pic code into shared library. ld/ * testsuite/ld-riscv-elf/lib-nopic-01b.d: Update the error message. Change-Id: Ib3347a0a6fa1c2b20a9647c314d5bec2c322ff04
2019-10-18 06:38:27 +08:00
run_ld_link_tests {
{ "Link non-pic code into a shared library (setup)"
"-shared" "" "" {lib-nopic-01a.s}
{} "lib-nopic-01a.so" }
}
run_dump_test "lib-nopic-01b"
RISC-V: Support GNU indirect functions. Generally, glibc dynamic linker should have two ways to deal with ifunc - one is to handle the IRELATIVE relocations for the non-preemtive ifunc symbols, the other is to handle the R_RISCV_32/64 and R_RISCV_JUMP_SLOT relocations with the STT_IFUNC preemtive symbols. No matter which method is used, both of them should get the resolved ifunc symbols at runtime. Therefore, linker needs to generate the correct dynamic relocations for ifunc to make sure the the dynamic linker works well. For now, there are thirteen relocations are supported for ifunc in GNU ld, * R_RISCV_CALL and R_RISCV_CALL_PLT: The RISC-V compiler won't generate R_RISCV_JAL directly to jump to an ifunc. Besides, we disable the relaxations for the relocation referenced to ifunc, so just handling the R_RISCV_CALL and R_RISCV_CALL_PLT should be enough. Linker should generate a .plt entry and a .got.plt entry for it, and also needs to insert a dynamic IRELATIVE in the .got.plt enrty, or insert a R_RISCV_JUMP_SLOT when generating shared library. * R_RISCV_PCREL_HI20 and R_RISCV_PCREL_LO12_I/S: LA/LLA pattern with local fPIC ifunc symbol, or any non-PIC ifunc symbol. The PC-relative relocation. The current linker will deal with them in the same way as R_RISCV_CALL_PLT. * R_RISCV_GOT_HI20 and R_RISCV_PCREL_LO12_I/S: LA pattern with global PIC ifunc symbol. Linker should insert a dynamic IRELATIVE in the .got entry, or insert a R_RISCV_32/64 when generating shared library. * R_RISCV_32 and R_RISCV_64: Store the ifunc symbol into the data section. Linker should insert a dynamic IRELATIVE in the data section, or insert a R_RISCV_32/64 when generating shared library. * R_RISCV_HI20 and R_RISCV_LO12_I/S: The LUI + ADDI/LW/SW patterns. The absolute access relocation. The medlow model without the -fPIC compiler option should generate them. The ld ifunc testsuites "Build pr23169a" and "Build pr23169d" need the relocations, they are in the ld/testsuite/ld-ifunc/, and need compiler support. However, we also made some optimizations with reference to x86, * If GOT and PLT relocations refer to the same ifunc symbol when generating pie, then they can actually share a .got entry without creating two entries to store the same value and relocation. * If GOT, PLT and DATA relocations refer to the same ifunc symbol when generating position dependency executable, then linker will fill the address of .plt entry into the corresponding .got entry and data section, without insert any dynamic relocations for the GOT and DATA relocations. For the ifunc testcases, there are three types of them, 1. ifunc-reloc-*: Only check the single type of relocation refers to ifunc symbol. * ifunc-reloc-call: R_RISCV_CALL and R_RISCV_CALL_PLT. * ifunc-reloc-data: R_RISCV_32 and R_RISCV_64. * ifunc-reloc-got: R_RISCV_GOT_HI20 and R_RISCV_PCREL_LO_I/S. * ifunc-reloc-pcrel: R_RISCV_PCREL_HI20 and R_RISCV_PCREL_LO_I/S. 2. ifunc-[nonplt|plt]-*: If we don't have PLT relocs, then don't need to create the PLT and it's .plt entries. * ifunc-nonplt: Combine R_RISCV_GOT_HI20 and R_RISCV_32/64. * ifunc-plt: Combine all ifunc relocations. 3. ifunc-seperate-*: If we link the ifunc caller and resolver into the same module (link the objects), then the results are the same as the ifunc-reloc-* and ifunc-[noplt|plt]-* testcases. Consider the cases that the ifunc callers and resolver are in the different modules, that is, we compile the ifunc resolver to the shared library first, and then link it with the ifunc callers. The output of ifunc callers should be the same as the normal STT_FUNC cases, and the shared ifunc resolver should define the symbols as STT_IFUNC. The R_RISCV_PCREL_HI20 reloc is special. It should be linked and resolved locally, so if the ifunc resolver is defined in other modules (other shared libraries), then the R_RISCV_PCREL_HI20 is unresolvable, and linker should issue an unresolvable reloc error. bfd/ * elfnn-riscv.c: Include "objalloc.h" since we need objalloc_alloc. (riscv_elf_link_hash_table): Add loc_hash_table and loc_hash_memory for local STT_GNU_IFUNC symbols. (riscv_elf_got_plt_val): Removed. (riscv_elf_local_htab_hash, riscv_elf_local_htab_eq): New functions. Use to compare local hash entries. (riscv_elf_get_local_sym_hash): New function. Find a hash entry for local symbol, and create a new one if needed. (riscv_elf_link_hash_table_free): New function. Destroy an riscv elf linker hash table. (riscv_elf_link_hash_table_create): Create hash table for local ifunc. (riscv_elf_check_relocs): Create a fake global symbol to track the local ifunc symbol. Add support to check and handle the relocations reference to ifunc symbols. (allocate_dynrelocs): Let allocate_ifunc_dynrelocs and allocate_local_ifunc_dynrelocs to handle the ifunc symbols if they are defined and referenced in a non-shared object. (allocate_ifunc_dynrelocs): New function. Allocate space in .plt, .got and associated reloc sections for ifunc dynamic relocs. (allocate_local_ifunc_dynrelocs): Likewise, but for local ifunc dynamic relocs. (riscv_elf_relocate_section): Add support to handle the relocation referenced to ifunc symbols. (riscv_elf_size_dynamic_sections): Updated. (riscv_elf_adjust_dynamic_symbol): Updated. (riscv_elf_finish_dynamic_symbol): Finish up the ifunc handling, including fill the PLT and GOT entries for ifunc symbols. (riscv_elf_finish_local_dynamic_symbol): New function. Called by riscv_elf_finish_dynamic_symbol to handle the local ifunc symbols. (_bfd_riscv_relax_section): Don't do the relaxation for ifunc. * elfxx-riscv.c: Add R_RISCV_IRELATIVE. * configure.ac: Link elf-ifunc.lo to use the generic ifunc support. * configure: Regenerated. include/ * elf/riscv.h: Add R_RISCV_IRELATIVE to 58. ld/ * emulparams/elf32lriscv-defs.sh: Add IREL_IN_PLT. * testsuite/ld-ifunc/ifunc.exp: Enable ifunc tests for RISC-V. * testsuite/ld-riscv-elf/ld-riscv-elf.exp (run_dump_test_ifunc): New dump test for ifunc. There are two arguments, 'target` and `output`. The `target` is rv32 or rv64, and the `output` is used to choose which output you want to test (exe, pie or .so). * testsuite/ld-riscv-elf/ifunc-reloc-call-01.s: New testcase. * testsuite/ld-riscv-elf/ifunc-reloc-call-01.d: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-call-01-exe.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-call-01-pic.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-call-01-pie.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-call-02.s: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-call-02.d: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-call-02-exe.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-call-02-pic.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-call-02-pie.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-data.s: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-data.d: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-data-exe.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-data-pic.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-data-pie.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-got.s: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-got.d: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-got-exe.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-got-pic.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-got-pie.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-pcrel.s: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-pcrel.d: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-pcrel-exe.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-pcrel-pic.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-pcrel-pie.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-nonplt.s: Likewise. * testsuite/ld-riscv-elf/ifunc-nonplt.d: Likewise. * testsuite/ld-riscv-elf/ifunc-nonplt-exe.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-nonplt-pic.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-nonplt-pie.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-01.s: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-01.d: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-01-exe.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-01-pic.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-01-pie.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-02.s: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-02.d: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-02-exe.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-02-pic.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-02-pie.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-seperate-resolver.s: Likewise. * testsuite/ld-riscv-elf/ifunc-seperate-caller.s: Likewise. * testsuite/ld-riscv-elf/ifunc-seperate-exe.d: Likewise. * testsuite/ld-riscv-elf/ifunc-seperate-pic.d: Likewise. * testsuite/ld-riscv-elf/ifunc-seperate-pie.d: Likewise. * testsuite/ld-riscv-elf/ifunc-seperate-caller-pcrel.s: Likewise. * testsuite/ld-riscv-elf/ifunc-seperate-pcrel-pic.d: Likewise. * testsuite/ld-riscv-elf/ifunc-seperate-pcrel-pie.d: Likewise.
2020-10-07 11:48:22 +08:00
# IFUNC testcases.
# Check IFUNC by single type relocs.
run_dump_test_ifunc "ifunc-reloc-call-01" rv32 exe
run_dump_test_ifunc "ifunc-reloc-call-01" rv32 pie
run_dump_test_ifunc "ifunc-reloc-call-01" rv32 pic
run_dump_test_ifunc "ifunc-reloc-call-02" rv32 exe
run_dump_test_ifunc "ifunc-reloc-call-02" rv32 pie
run_dump_test_ifunc "ifunc-reloc-call-02" rv32 pic
run_dump_test_ifunc "ifunc-reloc-pcrel" rv32 exe
run_dump_test_ifunc "ifunc-reloc-pcrel" rv32 pie
run_dump_test_ifunc "ifunc-reloc-pcrel" rv32 pic
run_dump_test_ifunc "ifunc-reloc-data" rv32 exe
run_dump_test_ifunc "ifunc-reloc-data" rv32 pie
run_dump_test_ifunc "ifunc-reloc-data" rv32 pic
run_dump_test_ifunc "ifunc-reloc-got" rv32 exe
run_dump_test_ifunc "ifunc-reloc-got" rv32 pie
run_dump_test_ifunc "ifunc-reloc-got" rv32 pic
run_dump_test_ifunc "ifunc-reloc-pcrel" rv64 exe
run_dump_test_ifunc "ifunc-reloc-pcrel" rv64 pie
run_dump_test_ifunc "ifunc-reloc-pcrel" rv64 pic
run_dump_test_ifunc "ifunc-reloc-data" rv64 exe
run_dump_test_ifunc "ifunc-reloc-data" rv64 pie
run_dump_test_ifunc "ifunc-reloc-data" rv64 pic
run_dump_test_ifunc "ifunc-reloc-got" rv64 exe
run_dump_test_ifunc "ifunc-reloc-got" rv64 pie
run_dump_test_ifunc "ifunc-reloc-got" rv64 pic
# Check the IFUNC PLT and non-PLT relocs.
run_dump_test_ifunc "ifunc-nonplt" rv32 exe
run_dump_test_ifunc "ifunc-nonplt" rv32 pie
run_dump_test_ifunc "ifunc-nonplt" rv32 pic
run_dump_test_ifunc "ifunc-plt-01" rv32 exe
run_dump_test_ifunc "ifunc-plt-01" rv32 pie
run_dump_test_ifunc "ifunc-plt-01" rv32 pic
run_dump_test_ifunc "ifunc-plt-02" rv32 exe
run_dump_test_ifunc "ifunc-plt-02" rv32 pie
run_dump_test_ifunc "ifunc-plt-02" rv32 pic
run_dump_test_ifunc "ifunc-nonplt" rv64 exe
run_dump_test_ifunc "ifunc-nonplt" rv64 pie
run_dump_test_ifunc "ifunc-nonplt" rv64 pic
run_dump_test_ifunc "ifunc-plt-01" rv64 exe
run_dump_test_ifunc "ifunc-plt-01" rv64 pie
run_dump_test_ifunc "ifunc-plt-01" rv64 pic
run_dump_test_ifunc "ifunc-plt-02" rv64 exe
run_dump_test_ifunc "ifunc-plt-02" rv64 pie
run_dump_test_ifunc "ifunc-plt-02" rv64 pic
RISC-V: Fix that IRELATIVE relocs may be inserted to the wrong place. For the ifunc symbol, which is referenced by GOT rather than PLT relocs, we should add the dynamic reloc (usually IRELATIVE) into the .rel.iplt when generating the static executable. But if we use riscv_elf_append_rela to add the dynamic relocs into .rela.iplt, this may cause the overwrite problem. The reason is that we don't handle the `reloc_index` of .rela.iplt, but the riscv_elf_append_rela adds the relocs to the place that are calculated from the reloc_index (in seqential). Therefore, we may overwrite the dynamic relocs when the `reloc_index` of .rela.iplt isn't handled correctly. One solution is that we can add these dynamic relocs (GOT ifunc) from the last of .rela.iplt section. But I'm not sure if it is the best way. bfd/ * elfnn-riscv.c (riscv_elf_link_hash_table): Add last_iplt_index. (riscv_elf_size_dynamic_sections): Initialize the last_iplt_index. (riscv_elf_relocate_section): Use riscv_elf_append_rela. (riscv_elf_finish_dynamic_symbol): If the use_elf_append_rela is false, then we should add the dynamic relocs from the last of the .rela.iplt, and don't use the riscv_elf_append_rela to add. ld/ * testsuite/ld-riscv-elf/ifunc-plt-got-overwrite.s: New testcase. * testsuite/ld-riscv-elf/ifunc-plt-got-overwrite.d: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-got-overwrite-exe.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-got-overwrite-pic.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-got-overwrite-pie.rd: Likewise. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
2020-10-07 11:48:23 +08:00
# Check the .rela.iplt overwrite issue.
run_dump_test_ifunc "ifunc-plt-got-overwrite" rv32 exe
run_dump_test_ifunc "ifunc-plt-got-overwrite" rv32 pie
run_dump_test_ifunc "ifunc-plt-got-overwrite" rv32 pic
run_dump_test_ifunc "ifunc-plt-got-overwrite" rv64 exe
run_dump_test_ifunc "ifunc-plt-got-overwrite" rv64 pie
run_dump_test_ifunc "ifunc-plt-got-overwrite" rv64 pic
RISC-V: Support GNU indirect functions. Generally, glibc dynamic linker should have two ways to deal with ifunc - one is to handle the IRELATIVE relocations for the non-preemtive ifunc symbols, the other is to handle the R_RISCV_32/64 and R_RISCV_JUMP_SLOT relocations with the STT_IFUNC preemtive symbols. No matter which method is used, both of them should get the resolved ifunc symbols at runtime. Therefore, linker needs to generate the correct dynamic relocations for ifunc to make sure the the dynamic linker works well. For now, there are thirteen relocations are supported for ifunc in GNU ld, * R_RISCV_CALL and R_RISCV_CALL_PLT: The RISC-V compiler won't generate R_RISCV_JAL directly to jump to an ifunc. Besides, we disable the relaxations for the relocation referenced to ifunc, so just handling the R_RISCV_CALL and R_RISCV_CALL_PLT should be enough. Linker should generate a .plt entry and a .got.plt entry for it, and also needs to insert a dynamic IRELATIVE in the .got.plt enrty, or insert a R_RISCV_JUMP_SLOT when generating shared library. * R_RISCV_PCREL_HI20 and R_RISCV_PCREL_LO12_I/S: LA/LLA pattern with local fPIC ifunc symbol, or any non-PIC ifunc symbol. The PC-relative relocation. The current linker will deal with them in the same way as R_RISCV_CALL_PLT. * R_RISCV_GOT_HI20 and R_RISCV_PCREL_LO12_I/S: LA pattern with global PIC ifunc symbol. Linker should insert a dynamic IRELATIVE in the .got entry, or insert a R_RISCV_32/64 when generating shared library. * R_RISCV_32 and R_RISCV_64: Store the ifunc symbol into the data section. Linker should insert a dynamic IRELATIVE in the data section, or insert a R_RISCV_32/64 when generating shared library. * R_RISCV_HI20 and R_RISCV_LO12_I/S: The LUI + ADDI/LW/SW patterns. The absolute access relocation. The medlow model without the -fPIC compiler option should generate them. The ld ifunc testsuites "Build pr23169a" and "Build pr23169d" need the relocations, they are in the ld/testsuite/ld-ifunc/, and need compiler support. However, we also made some optimizations with reference to x86, * If GOT and PLT relocations refer to the same ifunc symbol when generating pie, then they can actually share a .got entry without creating two entries to store the same value and relocation. * If GOT, PLT and DATA relocations refer to the same ifunc symbol when generating position dependency executable, then linker will fill the address of .plt entry into the corresponding .got entry and data section, without insert any dynamic relocations for the GOT and DATA relocations. For the ifunc testcases, there are three types of them, 1. ifunc-reloc-*: Only check the single type of relocation refers to ifunc symbol. * ifunc-reloc-call: R_RISCV_CALL and R_RISCV_CALL_PLT. * ifunc-reloc-data: R_RISCV_32 and R_RISCV_64. * ifunc-reloc-got: R_RISCV_GOT_HI20 and R_RISCV_PCREL_LO_I/S. * ifunc-reloc-pcrel: R_RISCV_PCREL_HI20 and R_RISCV_PCREL_LO_I/S. 2. ifunc-[nonplt|plt]-*: If we don't have PLT relocs, then don't need to create the PLT and it's .plt entries. * ifunc-nonplt: Combine R_RISCV_GOT_HI20 and R_RISCV_32/64. * ifunc-plt: Combine all ifunc relocations. 3. ifunc-seperate-*: If we link the ifunc caller and resolver into the same module (link the objects), then the results are the same as the ifunc-reloc-* and ifunc-[noplt|plt]-* testcases. Consider the cases that the ifunc callers and resolver are in the different modules, that is, we compile the ifunc resolver to the shared library first, and then link it with the ifunc callers. The output of ifunc callers should be the same as the normal STT_FUNC cases, and the shared ifunc resolver should define the symbols as STT_IFUNC. The R_RISCV_PCREL_HI20 reloc is special. It should be linked and resolved locally, so if the ifunc resolver is defined in other modules (other shared libraries), then the R_RISCV_PCREL_HI20 is unresolvable, and linker should issue an unresolvable reloc error. bfd/ * elfnn-riscv.c: Include "objalloc.h" since we need objalloc_alloc. (riscv_elf_link_hash_table): Add loc_hash_table and loc_hash_memory for local STT_GNU_IFUNC symbols. (riscv_elf_got_plt_val): Removed. (riscv_elf_local_htab_hash, riscv_elf_local_htab_eq): New functions. Use to compare local hash entries. (riscv_elf_get_local_sym_hash): New function. Find a hash entry for local symbol, and create a new one if needed. (riscv_elf_link_hash_table_free): New function. Destroy an riscv elf linker hash table. (riscv_elf_link_hash_table_create): Create hash table for local ifunc. (riscv_elf_check_relocs): Create a fake global symbol to track the local ifunc symbol. Add support to check and handle the relocations reference to ifunc symbols. (allocate_dynrelocs): Let allocate_ifunc_dynrelocs and allocate_local_ifunc_dynrelocs to handle the ifunc symbols if they are defined and referenced in a non-shared object. (allocate_ifunc_dynrelocs): New function. Allocate space in .plt, .got and associated reloc sections for ifunc dynamic relocs. (allocate_local_ifunc_dynrelocs): Likewise, but for local ifunc dynamic relocs. (riscv_elf_relocate_section): Add support to handle the relocation referenced to ifunc symbols. (riscv_elf_size_dynamic_sections): Updated. (riscv_elf_adjust_dynamic_symbol): Updated. (riscv_elf_finish_dynamic_symbol): Finish up the ifunc handling, including fill the PLT and GOT entries for ifunc symbols. (riscv_elf_finish_local_dynamic_symbol): New function. Called by riscv_elf_finish_dynamic_symbol to handle the local ifunc symbols. (_bfd_riscv_relax_section): Don't do the relaxation for ifunc. * elfxx-riscv.c: Add R_RISCV_IRELATIVE. * configure.ac: Link elf-ifunc.lo to use the generic ifunc support. * configure: Regenerated. include/ * elf/riscv.h: Add R_RISCV_IRELATIVE to 58. ld/ * emulparams/elf32lriscv-defs.sh: Add IREL_IN_PLT. * testsuite/ld-ifunc/ifunc.exp: Enable ifunc tests for RISC-V. * testsuite/ld-riscv-elf/ld-riscv-elf.exp (run_dump_test_ifunc): New dump test for ifunc. There are two arguments, 'target` and `output`. The `target` is rv32 or rv64, and the `output` is used to choose which output you want to test (exe, pie or .so). * testsuite/ld-riscv-elf/ifunc-reloc-call-01.s: New testcase. * testsuite/ld-riscv-elf/ifunc-reloc-call-01.d: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-call-01-exe.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-call-01-pic.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-call-01-pie.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-call-02.s: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-call-02.d: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-call-02-exe.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-call-02-pic.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-call-02-pie.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-data.s: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-data.d: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-data-exe.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-data-pic.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-data-pie.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-got.s: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-got.d: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-got-exe.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-got-pic.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-got-pie.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-pcrel.s: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-pcrel.d: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-pcrel-exe.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-pcrel-pic.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-reloc-pcrel-pie.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-nonplt.s: Likewise. * testsuite/ld-riscv-elf/ifunc-nonplt.d: Likewise. * testsuite/ld-riscv-elf/ifunc-nonplt-exe.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-nonplt-pic.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-nonplt-pie.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-01.s: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-01.d: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-01-exe.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-01-pic.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-01-pie.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-02.s: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-02.d: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-02-exe.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-02-pic.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-02-pie.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-seperate-resolver.s: Likewise. * testsuite/ld-riscv-elf/ifunc-seperate-caller.s: Likewise. * testsuite/ld-riscv-elf/ifunc-seperate-exe.d: Likewise. * testsuite/ld-riscv-elf/ifunc-seperate-pic.d: Likewise. * testsuite/ld-riscv-elf/ifunc-seperate-pie.d: Likewise. * testsuite/ld-riscv-elf/ifunc-seperate-caller-pcrel.s: Likewise. * testsuite/ld-riscv-elf/ifunc-seperate-pcrel-pic.d: Likewise. * testsuite/ld-riscv-elf/ifunc-seperate-pcrel-pie.d: Likewise.
2020-10-07 11:48:22 +08:00
# Setup shared libraries.
run_ld_link_tests {
{ "Build shared library for IFUNC non-PLT caller"
"-shared" "" "" {ifunc-seperate-caller-nonplt.s}
{} "ifunc-seperate-caller.so" }
{ "Build shared library for IFUNC PLT caller"
"-shared" "" "" {ifunc-seperate-caller-plt.s}
{} "ifunc-seperate-caller.so" }
{ "Build shared library for IFUNC resolver"
"-shared" "" "" {ifunc-seperate-resolver.s}
{} "ifunc-seperate-resolver.so" }
}
# The IFUNC resolver and caller are in the seperate modules.
# If IFUNC resolver and caller are linked to the same module,
# then the result are the same as the run_dump_test_ifunc.
run_dump_test "ifunc-seperate-nonplt-exe"
run_dump_test "ifunc-seperate-nonplt-pie"
run_dump_test "ifunc-seperate-nonplt-pic"
run_dump_test "ifunc-seperate-plt-exe"
run_dump_test "ifunc-seperate-plt-pie"
run_dump_test "ifunc-seperate-plt-pic"
run_dump_test "ifunc-seperate-pcrel-pie"
run_dump_test "ifunc-seperate-pcrel-pic"
RISC-V: Only relax to C.LUI when imm != 0 and rd != 0/2 This matches the ISA specification. This also adds two tests: one to make sure the assembler rejects invalid 'c.lui's, and one to make sure we only relax valid 'c.lui's. bfd/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * elfnn-riscv.c (_bfd_riscv_relax_lui): Don't relax to c.lui when rd is x0. include/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * opcode/riscv.h (VALID_RVC_LUI_IMM): c.lui can't load the immediate 0. gas/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * testsuite/gas/riscv/c-lui-fail.d: New testcase. gas/testsuite/gas/riscv/c-lui-fail.l: Likewise. gas/testsuite/gas/riscv/c-lui-fail.s: Likewise. gas/testsuite/gas/riscv/riscv.exp: Likewise. ld/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * ld/testsuite/ld-riscv-elf/c-lui.d: New testcase. ld/testsuite/ld-riscv-elf/c-lui.s: Likewise. ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp: New test suite.
2017-09-24 09:04:16 +08:00
}
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