binutils-gdb/sim/riscv/ChangeLog

2021-02-04  Mike Frysinger  <vapier@gentoo.org>

	* sim-main.c: Include gdb/sim-riscv.h.
	(reg_fetch, reg_store): Define.
	(initialize_cpu): Assign reg_fetch & reg_store.

2021-02-04  Mike Frysinger  <vapier@gentoo.org>

	* Makefile.in, configure.ac, interp.c, machs.c, machs.h,
	model_list.def, sim-main.c, sim-main.h: New files.
	* aclocal.m4, config.in, configure: Regenerated.
gdb: riscv: enable sim integration Now the simulator can be loaded via gdb using "target sim". 2015-06-16 23:44:48 +08:00			`2021-02-04 Mike Frysinger <vapier@gentoo.org>`

			`* sim-main.c: Include gdb/sim-riscv.h.`
			`(reg_fetch, reg_store): Define.`
			`(initialize_cpu): Assign reg_fetch & reg_store.`

sim: riscv: new port This is a hand-written implementation that should have fairly complete coverage for the base integer instruction set ("i"), and for the atomic ("a") and integer multiplication+division ("m") extensions. It also covers 32-bit & 64-bit targets. The unittest coverage is a bit weak atm, but should get better. 2015-05-21 23:16:45 +08:00			`2021-02-04 Mike Frysinger <vapier@gentoo.org>`

			`* Makefile.in, configure.ac, interp.c, machs.c, machs.h,`
			`model_list.def, sim-main.c, sim-main.h: New files.`
			`* aclocal.m4, config.in, configure: Regenerated.`