binutils-gdb/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie.s

	.global	var
	.section	.tdata
var:
	.word	2
	.text
	adrp	x0, :tlsdesc:var
	ldr	x17, [x0, #:tlsdesc_lo12:var]
	add	x0, x0, :tlsdesc_lo12:var
	.tlsdesccall	var
	blr	x1
	mrs	x1, tpidr_el0
	add	x0, x1, x0
	ldr	w0, [x0]
Add support for 64-bit ARM architecture: AArch64 2012-08-13 22:52:54 +08:00			`.global var`
			`.section .tdata`
			`var:`
			`.word 2`
			`.text`
			`adrp x0, :tlsdesc:var`
[AArch64] Fix off by one error in instruction relaxation mask. The AArch64 TLSDESC to IE relaxation code uses a bit mask intended to ensure that destination register in a relaxed ldr instruction is always X0. The mask has an off by one error resulting in the most significant bit of the destination register being retained in the relaxed instruction. The issue generally appears when the compiler emits TLS accesses code under high register pressure resulting in a broken code sequence. 2014-04-16 00:46:07 +08:00			`ldr x17, [x0, #:tlsdesc_lo12:var]`
Add support for 64-bit ARM architecture: AArch64 2012-08-13 22:52:54 +08:00			`add x0, x0, :tlsdesc_lo12:var`
			`.tlsdesccall var`
			`blr x1`
			`mrs x1, tpidr_el0`
			`add x0, x1, x0`
			`ldr w0, [x0]`