2022-12-23 12:15:39 +08:00
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/* Example synacor simulator.
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2024-01-12 23:30:44 +08:00
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Copyright (C) 2005-2024 Free Software Foundation, Inc.
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2022-12-23 12:15:39 +08:00
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Contributed by Mike Frysinger.
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This file is part of the GNU simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef EXAMPLE_SYNACOR_SIM_H
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#define EXAMPLE_SYNACOR_SIM_H
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struct example_sim_cpu {
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uint16_t regs[8];
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sim_cia pc;
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/* This isn't a real register, and the stack is not directly addressable,
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so use memory outside of the 16-bit address space. */
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uint32_t sp;
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};
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#define EXAMPLE_SIM_CPU(cpu) ((struct example_sim_cpu *) CPU_ARCH_DATA (cpu))
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extern void step_once (SIM_CPU *);
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extern void initialize_cpu (SIM_DESC, SIM_CPU *);
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#endif
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