1999-04-16 09:35:26 +08:00
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/* armvirt.c -- ARMulator virtual memory interace: ARM6 Instruction Emulator.
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Copyright (C) 1994 Advanced RISC Machines Ltd.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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2005-05-12 15:36:59 +08:00
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
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1999-04-16 09:35:26 +08:00
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/* This file contains a complete ARMulator memory model, modelling a
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"virtual memory" system. A much simpler model can be found in armfast.c,
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and that model goes faster too, but has a fixed amount of memory. This
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model's memory has 64K pages, allocated on demand from a 64K entry page
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table. The routines PutWord and GetWord implement this. Pages are never
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freed as they might be needed again. A single area of memory may be
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defined to generate aborts. */
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#include "armopts.h"
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2001-02-28 09:04:24 +08:00
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#include "armos.h"
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1999-04-16 09:35:26 +08:00
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#include "armdefs.h"
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2000-02-09 04:54:27 +08:00
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#include "ansidecl.h"
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1999-04-16 09:35:26 +08:00
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2000-02-05 15:30:26 +08:00
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#ifdef VALIDATE /* for running the validate suite */
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#define TUBE 48 * 1024 * 1024 /* write a char on the screen */
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1999-04-16 09:35:26 +08:00
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#define ABORTS 1
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#endif
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2000-07-04 16:00:19 +08:00
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/* #define ABORTS */
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1999-04-16 09:35:26 +08:00
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2000-02-05 15:30:26 +08:00
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#ifdef ABORTS /* the memory system will abort */
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1999-04-16 09:35:26 +08:00
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/* For the old test suite Abort between 32 Kbytes and 32 Mbytes
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For the new test suite Abort between 8 Mbytes and 26 Mbytes */
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/* #define LOWABORT 32 * 1024
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#define HIGHABORT 32 * 1024 * 1024 */
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#define LOWABORT 8 * 1024 * 1024
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#define HIGHABORT 26 * 1024 * 1024
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#endif
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#define NUMPAGES 64 * 1024
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#define PAGESIZE 64 * 1024
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#define PAGEBITS 16
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#define OFFSETBITS 0xffff
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2001-02-01 08:14:40 +08:00
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int SWI_vector_installed = FALSE;
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1999-04-16 09:35:26 +08:00
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/***************************************************************************\
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* Get a Word from Virtual Memory, maybe allocating the page *
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\***************************************************************************/
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static ARMword
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2001-02-28 09:04:24 +08:00
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GetWord (ARMul_State * state, ARMword address, int check)
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1999-04-16 09:35:26 +08:00
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{
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2000-02-05 15:30:26 +08:00
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ARMword page;
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ARMword offset;
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ARMword **pagetable;
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ARMword *pageptr;
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1999-04-16 09:35:26 +08:00
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2003-04-13 16:54:06 +08:00
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if (check && state->is_XScale)
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2002-05-27 22:12:00 +08:00
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XScale_check_memacc (state, &address, 0);
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* XScale coprocessor support.
2001-04-18 matthew green <mrg@redhat.com>
* armcopro.c (write_cp15_reg): Set CHANGEMODE if endianness changes.
(read_cp15_reg): Make non-static.
(XScale_cp15_LDC): Update for write_cp15_reg() change.
(XScale_cp15_MCR): Likewise.
(XScale_cp15_write_reg): Likewise.
(XScale_check_memacc): New function. Check for breakpoints being
activated by memory accesses. Does not support the Branch Target
Buffer.
(XScale_set_fsr_far): New function. Set FSR and FAR for XScale.
(XScale_debug_moe): New function. Set the debug Method Of Entry,
if configured.
(write_cp14_reg): Reset count counter if requested.
* armdefs.h (struct ARMul_State): New members `LastTime' and
`CP14R0_CCD' used for the timer/counters.
(ARMul_CP13_R0_FIQ, ARMul_CP13_R0_IRQ, ARMul_CP13_R8_PMUS,
ARMul_CP14_R0_ENABLE, ARMul_CP14_R0_CLKRST, ARMul_CP14_R0_CCD,
ARMul_CP14_R0_INTEN0, ARMul_CP14_R0_INTEN1, ARMul_CP14_R0_INTEN2,
ARMul_CP14_R0_FLAG0, ARMul_CP14_R0_FLAG1, ARMul_CP14_R0_FLAG2,
ARMul_CP14_R10_MOE_IB, ARMul_CP14_R10_MOE_DB, ARMul_CP14_R10_MOE_BT,
ARMul_CP15_R1_ENDIAN, ARMul_CP15_R1_ALIGN, ARMul_CP15_R5_X,
ARMul_CP15_R5_ST_ALIGN, ARMul_CP15_R5_IMPRE, ARMul_CP15_R5_MMU_EXCPT,
ARMul_CP15_DBCON_M, ARMul_CP15_DBCON_E1, ARMul_CP15_DBCON_E0): New
defines for XScale registers.
(XScale_check_memacc, XScale_set_fsr_far, XScale_debug_moe): Prototype.
(ARMul_Emulate32, ARMul_Emulate26): Clean up function definition.
(ARMul_Emulate32): Handle the clock counter and hardware instruction
breakpoints. Call XScale_set_fsr_far() for software breakpoints and
software interrupts.
(LoadMult): Call XScale_set_fsr_far() for data aborts.
(LoadSMult): Likewise.
(StoreMult): Likewise.
(StoreSMult): Likewise.
* armemu.h (write_cp15_reg): Update prototype.
* arminit.c (ARMul_NewState): Initialise CP14R0_CCD and LastTime.
(ARMul_Abort): If XScale, check for FIQ and IRQ being enabled in CP13
register 0.
* armvirt.c (GetWord): Call XScale_check_memacc().
(PutWord): Likewise.
2001-04-19 00:39:37 +08:00
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2000-02-05 15:30:26 +08:00
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page = address >> PAGEBITS;
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offset = (address & OFFSETBITS) >> 2;
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1999-04-16 09:35:26 +08:00
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pagetable = (ARMword **) state->MemDataPtr;
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2000-02-05 15:30:26 +08:00
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pageptr = *(pagetable + page);
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1999-04-16 09:35:26 +08:00
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if (pageptr == NULL)
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{
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pageptr = (ARMword *) malloc (PAGESIZE);
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2000-02-05 15:30:26 +08:00
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1999-04-16 09:35:26 +08:00
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if (pageptr == NULL)
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{
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perror ("ARMulator can't allocate VM page");
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exit (12);
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}
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2000-02-05 15:30:26 +08:00
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1999-04-16 09:35:26 +08:00
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*(pagetable + page) = pageptr;
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}
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2000-02-05 15:30:26 +08:00
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1999-04-16 09:35:26 +08:00
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return *(pageptr + offset);
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}
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/***************************************************************************\
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* Put a Word into Virtual Memory, maybe allocating the page *
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\***************************************************************************/
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static void
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2001-02-28 09:04:24 +08:00
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PutWord (ARMul_State * state, ARMword address, ARMword data, int check)
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1999-04-16 09:35:26 +08:00
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{
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2000-02-05 15:30:26 +08:00
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ARMword page;
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ARMword offset;
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ARMword **pagetable;
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ARMword *pageptr;
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2003-04-13 16:54:06 +08:00
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if (check && state->is_XScale)
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2002-05-27 22:12:00 +08:00
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XScale_check_memacc (state, &address, 1);
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* XScale coprocessor support.
2001-04-18 matthew green <mrg@redhat.com>
* armcopro.c (write_cp15_reg): Set CHANGEMODE if endianness changes.
(read_cp15_reg): Make non-static.
(XScale_cp15_LDC): Update for write_cp15_reg() change.
(XScale_cp15_MCR): Likewise.
(XScale_cp15_write_reg): Likewise.
(XScale_check_memacc): New function. Check for breakpoints being
activated by memory accesses. Does not support the Branch Target
Buffer.
(XScale_set_fsr_far): New function. Set FSR and FAR for XScale.
(XScale_debug_moe): New function. Set the debug Method Of Entry,
if configured.
(write_cp14_reg): Reset count counter if requested.
* armdefs.h (struct ARMul_State): New members `LastTime' and
`CP14R0_CCD' used for the timer/counters.
(ARMul_CP13_R0_FIQ, ARMul_CP13_R0_IRQ, ARMul_CP13_R8_PMUS,
ARMul_CP14_R0_ENABLE, ARMul_CP14_R0_CLKRST, ARMul_CP14_R0_CCD,
ARMul_CP14_R0_INTEN0, ARMul_CP14_R0_INTEN1, ARMul_CP14_R0_INTEN2,
ARMul_CP14_R0_FLAG0, ARMul_CP14_R0_FLAG1, ARMul_CP14_R0_FLAG2,
ARMul_CP14_R10_MOE_IB, ARMul_CP14_R10_MOE_DB, ARMul_CP14_R10_MOE_BT,
ARMul_CP15_R1_ENDIAN, ARMul_CP15_R1_ALIGN, ARMul_CP15_R5_X,
ARMul_CP15_R5_ST_ALIGN, ARMul_CP15_R5_IMPRE, ARMul_CP15_R5_MMU_EXCPT,
ARMul_CP15_DBCON_M, ARMul_CP15_DBCON_E1, ARMul_CP15_DBCON_E0): New
defines for XScale registers.
(XScale_check_memacc, XScale_set_fsr_far, XScale_debug_moe): Prototype.
(ARMul_Emulate32, ARMul_Emulate26): Clean up function definition.
(ARMul_Emulate32): Handle the clock counter and hardware instruction
breakpoints. Call XScale_set_fsr_far() for software breakpoints and
software interrupts.
(LoadMult): Call XScale_set_fsr_far() for data aborts.
(LoadSMult): Likewise.
(StoreMult): Likewise.
(StoreSMult): Likewise.
* armemu.h (write_cp15_reg): Update prototype.
* arminit.c (ARMul_NewState): Initialise CP14R0_CCD and LastTime.
(ARMul_Abort): If XScale, check for FIQ and IRQ being enabled in CP13
register 0.
* armvirt.c (GetWord): Call XScale_check_memacc().
(PutWord): Likewise.
2001-04-19 00:39:37 +08:00
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2000-02-05 15:30:26 +08:00
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page = address >> PAGEBITS;
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offset = (address & OFFSETBITS) >> 2;
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pagetable = (ARMword **) state->MemDataPtr;
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pageptr = *(pagetable + page);
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1999-04-16 09:35:26 +08:00
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if (pageptr == NULL)
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{
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pageptr = (ARMword *) malloc (PAGESIZE);
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if (pageptr == NULL)
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{
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perror ("ARMulator can't allocate VM page");
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2000-02-05 15:30:26 +08:00
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exit (13);
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1999-04-16 09:35:26 +08:00
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}
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2000-02-05 15:30:26 +08:00
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1999-04-16 09:35:26 +08:00
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*(pagetable + page) = pageptr;
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}
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2000-02-05 15:30:26 +08:00
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2001-02-01 08:14:40 +08:00
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if (address == 0x8)
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SWI_vector_installed = TRUE;
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1999-04-16 09:35:26 +08:00
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*(pageptr + offset) = data;
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}
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/***************************************************************************\
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* Initialise the memory interface *
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\***************************************************************************/
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unsigned
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ARMul_MemoryInit (ARMul_State * state, unsigned long initmemsize)
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{
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2000-02-05 15:30:26 +08:00
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ARMword **pagetable;
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unsigned page;
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1999-04-16 09:35:26 +08:00
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if (initmemsize)
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state->MemSize = initmemsize;
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2000-02-05 15:30:26 +08:00
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2005-09-19 22:21:09 +08:00
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pagetable = (ARMword **) malloc (sizeof (ARMword *) * NUMPAGES);
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2000-02-05 15:30:26 +08:00
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1999-04-16 09:35:26 +08:00
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if (pagetable == NULL)
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return FALSE;
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2000-02-05 15:30:26 +08:00
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for (page = 0; page < NUMPAGES; page++)
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1999-04-16 09:35:26 +08:00
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*(pagetable + page) = NULL;
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2000-02-05 15:30:26 +08:00
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state->MemDataPtr = (unsigned char *) pagetable;
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1999-04-16 09:35:26 +08:00
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ARMul_ConsolePrint (state, ", 4 Gb memory");
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2000-02-05 15:30:26 +08:00
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return TRUE;
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1999-04-16 09:35:26 +08:00
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}
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/***************************************************************************\
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* Remove the memory interface *
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\***************************************************************************/
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void
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ARMul_MemoryExit (ARMul_State * state)
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{
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2000-02-05 15:30:26 +08:00
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ARMword page;
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ARMword **pagetable;
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ARMword *pageptr;
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1999-04-16 09:35:26 +08:00
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2000-02-05 15:30:26 +08:00
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pagetable = (ARMword **) state->MemDataPtr;
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for (page = 0; page < NUMPAGES; page++)
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1999-04-16 09:35:26 +08:00
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{
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pageptr = *(pagetable + page);
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if (pageptr != NULL)
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2000-02-05 15:30:26 +08:00
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free ((char *) pageptr);
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1999-04-16 09:35:26 +08:00
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}
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2000-02-05 15:30:26 +08:00
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free ((char *) pagetable);
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1999-04-16 09:35:26 +08:00
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return;
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}
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/***************************************************************************\
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* ReLoad Instruction *
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\***************************************************************************/
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ARMword
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ARMul_ReLoadInstr (ARMul_State * state, ARMword address, ARMword isize)
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{
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#ifdef ABORTS
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2000-02-05 15:30:26 +08:00
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if (address >= LOWABORT && address < HIGHABORT)
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1999-04-16 09:35:26 +08:00
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{
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ARMul_PREFETCHABORT (address);
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return ARMul_ABORTWORD;
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}
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2000-02-05 15:30:26 +08:00
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else
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{
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ARMul_CLEARABORT;
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}
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1999-04-16 09:35:26 +08:00
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#endif
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2000-02-05 15:30:26 +08:00
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if ((isize == 2) && (address & 0x2))
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{
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/* We return the next two halfwords: */
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2001-03-21 01:48:02 +08:00
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ARMword lo = GetWord (state, address, FALSE);
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ARMword hi = GetWord (state, address + 4, FALSE);
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1999-04-16 09:35:26 +08:00
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2000-02-05 15:30:26 +08:00
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if (state->bigendSig == HIGH)
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return (lo << 16) | (hi >> 16);
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else
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return ((hi & 0xFFFF) << 16) | (lo >> 16);
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}
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1999-04-16 09:35:26 +08:00
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2001-02-28 09:04:24 +08:00
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return GetWord (state, address, TRUE);
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1999-04-16 09:35:26 +08:00
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}
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/***************************************************************************\
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* Load Instruction, Sequential Cycle *
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\***************************************************************************/
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2000-02-05 15:30:26 +08:00
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ARMword ARMul_LoadInstrS (ARMul_State * state, ARMword address, ARMword isize)
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1999-04-16 09:35:26 +08:00
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{
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2000-02-05 15:30:26 +08:00
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state->NumScycles++;
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1999-04-16 09:35:26 +08:00
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#ifdef HOURGLASS
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2000-02-05 15:30:26 +08:00
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if ((state->NumScycles & HOURGLASS_RATE) == 0)
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1999-04-16 09:35:26 +08:00
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{
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HOURGLASS;
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}
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#endif
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return ARMul_ReLoadInstr (state, address, isize);
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}
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/***************************************************************************\
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* Load Instruction, Non Sequential Cycle *
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\***************************************************************************/
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2000-02-05 15:30:26 +08:00
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ARMword ARMul_LoadInstrN (ARMul_State * state, ARMword address, ARMword isize)
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1999-04-16 09:35:26 +08:00
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{
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2000-02-05 15:30:26 +08:00
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state->NumNcycles++;
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1999-04-16 09:35:26 +08:00
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return ARMul_ReLoadInstr (state, address, isize);
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}
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/***************************************************************************\
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* Read Word (but don't tell anyone!) *
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\***************************************************************************/
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2000-02-05 15:30:26 +08:00
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ARMword ARMul_ReadWord (ARMul_State * state, ARMword address)
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1999-04-16 09:35:26 +08:00
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{
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#ifdef ABORTS
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if (address >= LOWABORT && address < HIGHABORT)
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{
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ARMul_DATAABORT (address);
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return ARMul_ABORTWORD;
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}
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else
|
|
|
|
{
|
|
|
|
ARMul_CLEARABORT;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2001-02-28 09:04:24 +08:00
|
|
|
return GetWord (state, address, TRUE);
|
1999-04-16 09:35:26 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/***************************************************************************\
|
|
|
|
* Load Word, Sequential Cycle *
|
|
|
|
\***************************************************************************/
|
|
|
|
|
2000-02-05 15:30:26 +08:00
|
|
|
ARMword ARMul_LoadWordS (ARMul_State * state, ARMword address)
|
1999-04-16 09:35:26 +08:00
|
|
|
{
|
2000-02-05 15:30:26 +08:00
|
|
|
state->NumScycles++;
|
1999-04-16 09:35:26 +08:00
|
|
|
|
|
|
|
return ARMul_ReadWord (state, address);
|
|
|
|
}
|
|
|
|
|
|
|
|
/***************************************************************************\
|
|
|
|
* Load Word, Non Sequential Cycle *
|
|
|
|
\***************************************************************************/
|
|
|
|
|
2000-02-05 15:30:26 +08:00
|
|
|
ARMword ARMul_LoadWordN (ARMul_State * state, ARMword address)
|
1999-04-16 09:35:26 +08:00
|
|
|
{
|
2000-02-05 15:30:26 +08:00
|
|
|
state->NumNcycles++;
|
|
|
|
|
1999-04-16 09:35:26 +08:00
|
|
|
return ARMul_ReadWord (state, address);
|
|
|
|
}
|
|
|
|
|
|
|
|
/***************************************************************************\
|
|
|
|
* Load Halfword, (Non Sequential Cycle) *
|
|
|
|
\***************************************************************************/
|
|
|
|
|
2000-02-05 15:30:26 +08:00
|
|
|
ARMword ARMul_LoadHalfWord (ARMul_State * state, ARMword address)
|
1999-04-16 09:35:26 +08:00
|
|
|
{
|
|
|
|
ARMword temp, offset;
|
|
|
|
|
2000-02-05 15:30:26 +08:00
|
|
|
state->NumNcycles++;
|
1999-04-16 09:35:26 +08:00
|
|
|
|
2000-02-05 15:30:26 +08:00
|
|
|
temp = ARMul_ReadWord (state, address);
|
|
|
|
offset = (((ARMword) state->bigendSig * 2) ^ (address & 2)) << 3; /* bit offset into the word */
|
1999-04-16 09:35:26 +08:00
|
|
|
|
|
|
|
return (temp >> offset) & 0xffff;
|
|
|
|
}
|
|
|
|
|
|
|
|
/***************************************************************************\
|
|
|
|
* Read Byte (but don't tell anyone!) *
|
|
|
|
\***************************************************************************/
|
|
|
|
|
2000-02-05 15:30:26 +08:00
|
|
|
ARMword ARMul_ReadByte (ARMul_State * state, ARMword address)
|
1999-04-16 09:35:26 +08:00
|
|
|
{
|
|
|
|
ARMword temp, offset;
|
|
|
|
|
2000-02-05 15:30:26 +08:00
|
|
|
temp = ARMul_ReadWord (state, address);
|
|
|
|
offset = (((ARMword) state->bigendSig * 3) ^ (address & 3)) << 3; /* bit offset into the word */
|
1999-04-16 09:35:26 +08:00
|
|
|
|
2000-02-05 15:30:26 +08:00
|
|
|
return (temp >> offset & 0xffL);
|
1999-04-16 09:35:26 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/***************************************************************************\
|
|
|
|
* Load Byte, (Non Sequential Cycle) *
|
|
|
|
\***************************************************************************/
|
|
|
|
|
2000-02-05 15:30:26 +08:00
|
|
|
ARMword ARMul_LoadByte (ARMul_State * state, ARMword address)
|
1999-04-16 09:35:26 +08:00
|
|
|
{
|
2000-02-05 15:30:26 +08:00
|
|
|
state->NumNcycles++;
|
1999-04-16 09:35:26 +08:00
|
|
|
|
|
|
|
return ARMul_ReadByte (state, address);
|
|
|
|
}
|
|
|
|
|
|
|
|
/***************************************************************************\
|
|
|
|
* Write Word (but don't tell anyone!) *
|
|
|
|
\***************************************************************************/
|
|
|
|
|
|
|
|
void
|
|
|
|
ARMul_WriteWord (ARMul_State * state, ARMword address, ARMword data)
|
|
|
|
{
|
|
|
|
#ifdef ABORTS
|
|
|
|
if (address >= LOWABORT && address < HIGHABORT)
|
|
|
|
{
|
|
|
|
ARMul_DATAABORT (address);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
ARMul_CLEARABORT;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2001-02-28 09:04:24 +08:00
|
|
|
PutWord (state, address, data, TRUE);
|
1999-04-16 09:35:26 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/***************************************************************************\
|
|
|
|
* Store Word, Sequential Cycle *
|
|
|
|
\***************************************************************************/
|
|
|
|
|
|
|
|
void
|
|
|
|
ARMul_StoreWordS (ARMul_State * state, ARMword address, ARMword data)
|
|
|
|
{
|
2000-02-05 15:30:26 +08:00
|
|
|
state->NumScycles++;
|
1999-04-16 09:35:26 +08:00
|
|
|
|
|
|
|
ARMul_WriteWord (state, address, data);
|
|
|
|
}
|
|
|
|
|
|
|
|
/***************************************************************************\
|
|
|
|
* Store Word, Non Sequential Cycle *
|
|
|
|
\***************************************************************************/
|
|
|
|
|
|
|
|
void
|
|
|
|
ARMul_StoreWordN (ARMul_State * state, ARMword address, ARMword data)
|
|
|
|
{
|
2000-02-05 15:30:26 +08:00
|
|
|
state->NumNcycles++;
|
1999-04-16 09:35:26 +08:00
|
|
|
|
|
|
|
ARMul_WriteWord (state, address, data);
|
|
|
|
}
|
|
|
|
|
|
|
|
/***************************************************************************\
|
|
|
|
* Store HalfWord, (Non Sequential Cycle) *
|
|
|
|
\***************************************************************************/
|
|
|
|
|
|
|
|
void
|
|
|
|
ARMul_StoreHalfWord (ARMul_State * state, ARMword address, ARMword data)
|
|
|
|
{
|
|
|
|
ARMword temp, offset;
|
|
|
|
|
2000-02-05 15:30:26 +08:00
|
|
|
state->NumNcycles++;
|
|
|
|
|
1999-04-16 09:35:26 +08:00
|
|
|
#ifdef VALIDATE
|
|
|
|
if (address == TUBE)
|
|
|
|
{
|
|
|
|
if (data == 4)
|
|
|
|
state->Emulate = FALSE;
|
|
|
|
else
|
2000-02-05 15:30:26 +08:00
|
|
|
(void) putc ((char) data, stderr); /* Write Char */
|
1999-04-16 09:35:26 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2000-02-05 15:30:26 +08:00
|
|
|
temp = ARMul_ReadWord (state, address);
|
|
|
|
offset = (((ARMword) state->bigendSig * 2) ^ (address & 2)) << 3; /* bit offset into the word */
|
|
|
|
|
|
|
|
PutWord (state, address,
|
2001-02-28 09:04:24 +08:00
|
|
|
(temp & ~(0xffffL << offset)) | ((data & 0xffffL) << offset),
|
|
|
|
TRUE);
|
1999-04-16 09:35:26 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/***************************************************************************\
|
|
|
|
* Write Byte (but don't tell anyone!) *
|
|
|
|
\***************************************************************************/
|
|
|
|
|
|
|
|
void
|
|
|
|
ARMul_WriteByte (ARMul_State * state, ARMword address, ARMword data)
|
|
|
|
{
|
|
|
|
ARMword temp, offset;
|
|
|
|
|
2000-02-05 15:30:26 +08:00
|
|
|
temp = ARMul_ReadWord (state, address);
|
|
|
|
offset = (((ARMword) state->bigendSig * 3) ^ (address & 3)) << 3; /* bit offset into the word */
|
|
|
|
|
|
|
|
PutWord (state, address,
|
2001-02-28 09:04:24 +08:00
|
|
|
(temp & ~(0xffL << offset)) | ((data & 0xffL) << offset),
|
|
|
|
TRUE);
|
1999-04-16 09:35:26 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/***************************************************************************\
|
|
|
|
* Store Byte, (Non Sequential Cycle) *
|
|
|
|
\***************************************************************************/
|
|
|
|
|
|
|
|
void
|
|
|
|
ARMul_StoreByte (ARMul_State * state, ARMword address, ARMword data)
|
|
|
|
{
|
2000-02-05 15:30:26 +08:00
|
|
|
state->NumNcycles++;
|
1999-04-16 09:35:26 +08:00
|
|
|
|
|
|
|
#ifdef VALIDATE
|
|
|
|
if (address == TUBE)
|
|
|
|
{
|
|
|
|
if (data == 4)
|
|
|
|
state->Emulate = FALSE;
|
|
|
|
else
|
2000-02-05 15:30:26 +08:00
|
|
|
(void) putc ((char) data, stderr); /* Write Char */
|
1999-04-16 09:35:26 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
ARMul_WriteByte (state, address, data);
|
|
|
|
}
|
|
|
|
|
|
|
|
/***************************************************************************\
|
|
|
|
* Swap Word, (Two Non Sequential Cycles) *
|
|
|
|
\***************************************************************************/
|
|
|
|
|
2000-02-05 15:30:26 +08:00
|
|
|
ARMword ARMul_SwapWord (ARMul_State * state, ARMword address, ARMword data)
|
1999-04-16 09:35:26 +08:00
|
|
|
{
|
|
|
|
ARMword temp;
|
|
|
|
|
2000-02-05 15:30:26 +08:00
|
|
|
state->NumNcycles++;
|
1999-04-16 09:35:26 +08:00
|
|
|
|
|
|
|
temp = ARMul_ReadWord (state, address);
|
2000-02-05 15:30:26 +08:00
|
|
|
|
|
|
|
state->NumNcycles++;
|
|
|
|
|
2001-02-28 09:04:24 +08:00
|
|
|
PutWord (state, address, data, TRUE);
|
2000-02-05 15:30:26 +08:00
|
|
|
|
1999-04-16 09:35:26 +08:00
|
|
|
return temp;
|
|
|
|
}
|
|
|
|
|
|
|
|
/***************************************************************************\
|
|
|
|
* Swap Byte, (Two Non Sequential Cycles) *
|
|
|
|
\***************************************************************************/
|
|
|
|
|
2000-02-05 15:30:26 +08:00
|
|
|
ARMword ARMul_SwapByte (ARMul_State * state, ARMword address, ARMword data)
|
1999-04-16 09:35:26 +08:00
|
|
|
{
|
|
|
|
ARMword temp;
|
|
|
|
|
|
|
|
temp = ARMul_LoadByte (state, address);
|
|
|
|
ARMul_StoreByte (state, address, data);
|
2000-02-05 15:30:26 +08:00
|
|
|
|
1999-04-16 09:35:26 +08:00
|
|
|
return temp;
|
|
|
|
}
|
|
|
|
|
|
|
|
/***************************************************************************\
|
|
|
|
* Count I Cycles *
|
|
|
|
\***************************************************************************/
|
|
|
|
|
|
|
|
void
|
2000-02-09 04:54:27 +08:00
|
|
|
ARMul_Icycles (ARMul_State * state, unsigned number, ARMword address ATTRIBUTE_UNUSED)
|
1999-04-16 09:35:26 +08:00
|
|
|
{
|
|
|
|
state->NumIcycles += number;
|
|
|
|
ARMul_CLEARABORT;
|
|
|
|
}
|
|
|
|
|
|
|
|
/***************************************************************************\
|
|
|
|
* Count C Cycles *
|
|
|
|
\***************************************************************************/
|
|
|
|
|
|
|
|
void
|
2000-02-09 04:54:27 +08:00
|
|
|
ARMul_Ccycles (ARMul_State * state, unsigned number, ARMword address ATTRIBUTE_UNUSED)
|
1999-04-16 09:35:26 +08:00
|
|
|
{
|
|
|
|
state->NumCcycles += number;
|
|
|
|
ARMul_CLEARABORT;
|
|
|
|
}
|
2001-02-28 09:04:24 +08:00
|
|
|
|
|
|
|
|
|
|
|
/* Read a byte. Do not check for alignment or access errors. */
|
|
|
|
|
|
|
|
ARMword
|
|
|
|
ARMul_SafeReadByte (ARMul_State * state, ARMword address)
|
|
|
|
{
|
|
|
|
ARMword temp, offset;
|
|
|
|
|
|
|
|
temp = GetWord (state, address, FALSE);
|
|
|
|
offset = (((ARMword) state->bigendSig * 3) ^ (address & 3)) << 3;
|
|
|
|
|
|
|
|
return (temp >> offset & 0xffL);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
ARMul_SafeWriteByte (ARMul_State * state, ARMword address, ARMword data)
|
|
|
|
{
|
|
|
|
ARMword temp, offset;
|
|
|
|
|
|
|
|
temp = GetWord (state, address, FALSE);
|
|
|
|
offset = (((ARMword) state->bigendSig * 3) ^ (address & 3)) << 3;
|
|
|
|
|
|
|
|
PutWord (state, address,
|
|
|
|
(temp & ~(0xffL << offset)) | ((data & 0xffL) << offset),
|
|
|
|
FALSE);
|
|
|
|
}
|