mirror of
https://sourceware.org/git/binutils-gdb.git
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297 lines
6.1 KiB
ArmAsm
297 lines
6.1 KiB
ArmAsm
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//Original:/proj/frio/dv/testcases/seq/se_bug_ui2/se_bug_ui2.dsp
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// Description: 16 bit special cases Undefined Instructions in Supervisor Mode
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# mach: bfin
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# sim: --environment operating
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#include "test.h"
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.include "testutils.inc"
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start
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//
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// Constants and Defines
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//
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include(gen_int.inc)
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include(selfcheck.inc)
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include(std.inc)
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include(mmrs.inc)
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include(symtable.inc)
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#ifndef STACKSIZE
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#define STACKSIZE 0x10 // change for how much stack you need
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#endif
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#ifndef ITABLE
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#define ITABLE 0xF0000000
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#endif
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GEN_INT_INIT(ITABLE) // set location for interrupt table
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//
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// Reset/Bootstrap Code
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// (Here we should set the processor operating modes, initialize registers,
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// etc.)
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//
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BOOT:
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INIT_R_REGS(0); // initialize general purpose regs
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INIT_P_REGS(0); // initialize the pointers
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INIT_I_REGS(0); // initialize the dsp address regs
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INIT_M_REGS(0);
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INIT_L_REGS(0);
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INIT_B_REGS(0);
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CLI R1; // inhibit events during MMR writes
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LD32_LABEL(sp, USTACK); // setup the user stack pointer
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USP = SP;
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LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer
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FP = SP; // and frame pointer
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LD32(p0, EVT0); // Setup Event Vectors and Handlers
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P0 += 4; // EVT0 not used (Emulation)
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P0 += 4; // EVT1 not used (Reset)
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LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
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[ P0 ++ ] = R0;
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P0 += 4; // EVT4 not used (Global Interrupt Enable)
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LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
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[ P0 ++ ] = R0;
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LD32(p0, EVT_OVERRIDE);
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R0 = 0;
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[ P0 ++ ] = R0;
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R1 = -1; // Change this to mask interrupts (*)
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CSYNC; // wait for MMR writes to finish
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STI R1; // sync and reenable events (implicit write to IMASK)
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DUMMY:
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R0 = 0 (Z);
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LT0 = r0; // set loop counters to something deterministic
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LB0 = r0;
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LC0 = r0;
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LT1 = r0;
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LB1 = r0;
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LC1 = r0;
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ASTAT = r0; // reset other internal regs
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SYSCFG = r0;
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RETS = r0; // prevent X's breaking LINK instruction
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// The following code sets up the test for running in USER mode
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LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
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// ReturnFromInterrupt (RTI)
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RETI = r0; // We need to load the return address
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// Comment the following line for a USER Mode test
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JUMP STARTSUP; // jump to code start for SUPERVISOR mode
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RTI;
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STARTSUP:
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LD32_LABEL(p1, BEGIN);
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LD32(p0, EVT15);
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CLI R1; // inhibit events during write to MMR
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[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
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CSYNC; // wait for it
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STI R1; // reenable events with proper imask
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RAISE 15; // after we RTI, INT 15 should be taken
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RTI;
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//
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// The Main Program
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//
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STARTUSER:
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LINK 0; // change for how much stack frame space you need.
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JUMP BEGIN;
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//*********************************************************************
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BEGIN:
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// COMMENT the following line for USER MODE tests
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[ -- SP ] = RETI; // enable interrupts in supervisor mode
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// **** YOUR CODE GOES HERE ****
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// count of UI's will be in r5, which was initialized to 0 by header
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// .dw 0x41FD ;
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// .dw 0x41FE ;
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// .dw 0x41FF ;
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.dw 0x9040 ;
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.dw 0x9049 ;
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.dw 0x9052 ;
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.dw 0x905B ;
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.dw 0x9064 ;
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.dw 0x906D ;
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.dw 0x9076 ;
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.dw 0x907F ;
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.dw 0x90C0 ;
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.dw 0x90C9 ;
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.dw 0x90D2 ;
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.dw 0x90DB ;
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.dw 0x90E4 ;
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.dw 0x90ED ;
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.dw 0x90F6 ;
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.dw 0x90FF ;
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.dw 0x9180 ;
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CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC);
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// Xhandler counts all EXCAUSE = 0x21;
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CHECKREG(r5, 17); // count of all 16 bit UI's.
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END:
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dbg_pass; // End the test
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//*********************************************************************
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//
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// Handlers for Events
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//
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NHANDLE: // NMI Handler 2
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RTN;
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XHANDLE: // Exception Handler 3
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// 16 bit illegal opcode handler - skips bad instruction
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// handler MADE LEAN and destructive so test runs more quckly
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// se_undefinedinstruction1.dsp tests using a "nice" handler
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// [--sp] = ASTAT; // save what we damage
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// [--sp] = (r7 - r6);
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R7 = SEQSTAT;
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R7 <<= 26;
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R7 >>= 26; // only want EXCAUSE
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R6 = 0x21; // EXCAUSE 0x21 means I-Fetch Undefined Instruction
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CC = r7 == r6;
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IF CC JUMP UNDEFINEDINSTRUCTION; // If EXCAUSE != 0x21 then leave
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R6 = 0x22; // Also accept illegal insn combo
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CC = r7 == r6;
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IF CC JUMP UNDEFINEDINSTRUCTION; // If EXCAUSE != 0x21 then leave
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dbg_fail;
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UNDEFINEDINSTRUCTION:
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R7 = RETX; // Fix up return address
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R7 += 2; // skip offending 16 bit instruction
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RETX = r7; // and put back in RETX
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R5 += 1; // Increment global counter
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OUT:
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// (r7 - r6) = [sp++];
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// ASTAT = [sp++];
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RTX;
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HWHANDLE: // HW Error Handler 5
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RTI;
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THANDLE: // Timer Handler 6
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RTI;
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I7HANDLE: // IVG 7 Handler
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RTI;
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I8HANDLE: // IVG 8 Handler
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RTI;
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I9HANDLE: // IVG 9 Handler
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RTI;
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I10HANDLE: // IVG 10 Handler
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RTI;
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I11HANDLE: // IVG 11 Handler
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RTI;
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I12HANDLE: // IVG 12 Handler
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RTI;
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I13HANDLE: // IVG 13 Handler
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RTI;
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I14HANDLE: // IVG 14 Handler
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RTI;
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I15HANDLE: // IVG 15 Handler
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RTI;
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// padding for the icache
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EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0;
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//
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// Data Segment
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//
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.data
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DATA:
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.space (0x10);
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// Stack Segments (Both Kernel and User)
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.space (STACKSIZE);
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KSTACK:
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.space (STACKSIZE);
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USTACK:
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