2011-06-05 01:44:22 +08:00
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//Original:/testcases/core/c_dsp32shift_vmaxvmax/c_dsp32shift_vmaxvmax.dsp
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// Spec Reference: dsp32shift vmax / vmax
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# mach: bfin
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.include "testutils.inc"
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start
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imm32 r0, 0x11002001;
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imm32 r1, 0x12001001;
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imm32 r2, 0x11301302;
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imm32 r3, 0x43001003;
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imm32 r4, 0x11601604;
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imm32 r5, 0x71001705;
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imm32 r6, 0x81008006;
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imm32 r7, 0x1900b007;
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A0 = R3;
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R1 = VIT_MAX( R1 , R0 ) (ASL);
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R2 = VIT_MAX( R2 , R1 ) (ASL);
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R3 = VIT_MAX( R3 , R2 ) (ASL);
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R4 = VIT_MAX( R4 , R3 ) (ASL);
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R5 = VIT_MAX( R5 , R4 ) (ASL);
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R6 = VIT_MAX( R6 , R5 ) (ASL);
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R7 = VIT_MAX( R7 , R6 ) (ASL);
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R0 = VIT_MAX( R0 , R7 ) (ASL);
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CHECKREG r0, 0x20018100;
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CHECKREG r1, 0x12002001;
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CHECKREG r2, 0x13022001;
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CHECKREG r3, 0x43002001;
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CHECKREG r4, 0x16044300;
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CHECKREG r5, 0x71004300;
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CHECKREG r6, 0x81007100;
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CHECKREG r7, 0x19008100;
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2012-03-25 14:43:43 +08:00
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imm32 r0, 0x11002001;
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2011-06-05 01:44:22 +08:00
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imm32 r1, 0xd2001001;
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imm32 r2, 0x14301302;
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imm32 r3, 0x43001003;
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imm32 r4, 0x11f01604;
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imm32 r5, 0xb1001705;
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imm32 r6, 0xd1008006;
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imm32 r7, 0x39056707;
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R1 = VIT_MAX( R1 , R3 ) (ASL);
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R2 = VIT_MAX( R2 , R4 ) (ASL);
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R3 = VIT_MAX( R3 , R6 ) (ASL);
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R4 = VIT_MAX( R4 , R5 ) (ASL);
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R5 = VIT_MAX( R5 , R7 ) (ASL);
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R6 = VIT_MAX( R6 , R0 ) (ASL);
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R7 = VIT_MAX( R7 , R1 ) (ASL);
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R0 = VIT_MAX( R0 , R2 ) (ASL);
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CHECKREG r0, 0x20011604;
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CHECKREG r1, 0x10014300;
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CHECKREG r2, 0x14301604;
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CHECKREG r3, 0x4300D100;
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CHECKREG r4, 0x16041705;
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CHECKREG r5, 0x17056707;
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CHECKREG r6, 0xD1002001;
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CHECKREG r7, 0x67074300;
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imm32 r0, 0xa1011001;
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imm32 r1, 0x1b002001;
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imm32 r2, 0x81c01302;
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imm32 r3, 0x910d1403;
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imm32 r4, 0x2100e504;
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imm32 r5, 0x31007f65;
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imm32 r6, 0x41007006;
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imm32 r7, 0x15001801;
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R1 = VIT_MAX( R1 , R0 ) (ASR);
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R2 = VIT_MAX( R2 , R1 ) (ASR);
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R3 = VIT_MAX( R3 , R2 ) (ASR);
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R4 = VIT_MAX( R4 , R3 ) (ASR);
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R5 = VIT_MAX( R5 , R4 ) (ASR);
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R6 = VIT_MAX( R6 , R5 ) (ASR);
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R7 = VIT_MAX( R7 , R6 ) (ASR);
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R0 = VIT_MAX( R0 , R7 ) (ASR);
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CHECKREG r0, 0x1001910D;
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CHECKREG r1, 0x20011001;
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CHECKREG r2, 0x81C02001;
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CHECKREG r3, 0x910D81C0;
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CHECKREG r4, 0x2100910D;
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CHECKREG r5, 0x7F65910D;
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CHECKREG r6, 0x7006910D;
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CHECKREG r7, 0x1801910D;
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imm32 r0, 0xe1011001;
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imm32 r1, 0x4b002001;
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imm32 r2, 0x8fc01302;
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imm32 r3, 0x910d1403;
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imm32 r4, 0xb100e504;
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imm32 r5, 0x41007f65;
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imm32 r6, 0xaf007006;
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imm32 r7, 0x16001801;
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R0 = VIT_MAX( R4 , R0 ) (ASR);
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R1 = VIT_MAX( R5 , R1 ) (ASR);
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R2 = VIT_MAX( R6 , R2 ) (ASR);
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R3 = VIT_MAX( R7 , R3 ) (ASR);
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R4 = VIT_MAX( R0 , R4 ) (ASR);
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R5 = VIT_MAX( R1 , R5 ) (ASR);
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R6 = VIT_MAX( R2 , R6 ) (ASR);
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R7 = VIT_MAX( R3 , R7 ) (ASR);
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CHECKREG r0, 0xE5041001;
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CHECKREG r1, 0x7F654B00;
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CHECKREG r2, 0xAF008FC0;
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CHECKREG r3, 0x1801910D;
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CHECKREG r4, 0x1001E504;
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CHECKREG r5, 0x7F657F65;
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CHECKREG r6, 0xAF00AF00;
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CHECKREG r7, 0x910D1801;
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pass
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