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binutils-gdb/sim/testsuite/bfin/c_dsp32alu_rl_rnd12_m.s

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sim: bfin: import testsuite Now that the common sim testsuite code supports .S and .c files, we can import the Blackfin testsuite. There are about ~800 tests here, so I'm only attaching a compressed patch of them. Other than adding files to sim/testsuite/sim/bfin/, the sim/configure.tgt file was updated to mark Blackfin as having a testsuite, and sim/configure regenerated. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-05 01:44:22 +08:00
//Original:/proj/frio/dv/testcases/core/c_dsp32alu_rl_rnd12_m/c_dsp32alu_rl_rnd12_m.dsp
// Spec Reference: dsp32alu dreg (half)
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x85678911;
imm32 r1, 0x9189ab1d;
imm32 r2, 0xa4245515;
imm32 r3, 0xb6637717;
imm32 r4, 0xc678491b;
imm32 r5, 0x6789a51d;
imm32 r6, 0xe4445565;
imm32 r7, 0x86667777;
R0.L = R0 - R0 (RND12);
R1.L = R0 - R1 (RND12);
R2.L = R0 - R2 (RND12);
R3.L = R0 - R3 (RND12);
R4.L = R0 - R4 (RND12);
R5.L = R0 - R5 (RND12);
R6.L = R0 - R6 (RND12);
R7.L = R0 - R7 (RND12);
CHECKREG r0, 0x85670000;
CHECKREG r1, 0x91898000;
CHECKREG r2, 0xA4248000;
CHECKREG r3, 0xB6638000;
CHECKREG r4, 0xC6788000;
CHECKREG r5, 0x67898000;
CHECKREG r6, 0xE4448000;
CHECKREG r7, 0x8666F009;
imm32 r0, 0x75678921;
imm32 r1, 0x2789ab14;
imm32 r2, 0xd4745515;
imm32 r3, 0x4d677767;
imm32 r4, 0x56d8791b;
imm32 r5, 0x678dab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86a6d777;
R0.L = R1 - R0 (RND12);
R1.L = R1 - R1 (RND12);
R2.L = R1 - R2 (RND12);
R3.L = R1 - R3 (RND12);
R4.L = R1 - R4 (RND12);
R5.L = R1 - R5 (RND12);
R6.L = R1 - R6 (RND12);
R7.L = R1 - R7 (RND12);
CHECKREG r0, 0x75678000;
CHECKREG r1, 0x27890000;
CHECKREG r2, 0xD4747FFF;
CHECKREG r3, 0x4D678000;
CHECKREG r4, 0x56D88000;
CHECKREG r5, 0x678D8000;
CHECKREG r6, 0x74448000;
CHECKREG r7, 0x86A67fff;
imm32 r0, 0x55678911;
imm32 r1, 0x2689ab1d;
imm32 r2, 0x3d445515;
imm32 r3, 0x46967717;
imm32 r4, 0xa67a891b;
imm32 r5, 0x6789bb1d;
imm32 r6, 0x7444d515;
imm32 r7, 0x8666c777;
R0.L = R2 - R0 (RND12);
R1.L = R2 - R1 (RND12);
R2.L = R2 - R2 (RND12);
R3.L = R2 - R3 (RND12);
R4.L = R2 - R4 (RND12);
R5.L = R2 - R5 (RND12);
R6.L = R2 - R6 (RND12);
R7.L = R2 - R7 (RND12);
CHECKREG r0, 0x55678000;
CHECKREG r1, 0x26897fff;
CHECKREG r2, 0x3D440000;
CHECKREG r3, 0x46968000;
CHECKREG r4, 0xA67A7fff;
CHECKREG r5, 0x67898000;
CHECKREG r6, 0x74448000;
CHECKREG r7, 0x86667fff;
imm32 r0, 0xf5678911;
imm32 r1, 0xd789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0xe6667717;
imm32 r4, 0x5678891b;
imm32 r5, 0x6d89ab1d;
imm32 r6, 0x7444d515;
imm32 r7, 0xe6667b77;
R0.L = R3 - R0 (RND12);
R1.L = R3 - R1 (RND12);
R2.L = R3 - R2 (RND12);
R3.L = R3 - R3 (RND12);
R4.L = R3 - R4 (RND12);
R5.L = R3 - R5 (RND12);
R6.L = R3 - R6 (RND12);
R7.L = R3 - R7 (RND12);
CHECKREG r0, 0xF5678000;
CHECKREG r1, 0xD7897fff;
CHECKREG r2, 0x34448000;
CHECKREG r3, 0xE6660000;
CHECKREG r4, 0x56788000;
CHECKREG r5, 0x6D898000;
CHECKREG r6, 0x74448000;
CHECKREG r7, 0xE666FFF8;
imm32 r0, 0xa5678911;
imm32 r1, 0x2b89ab1d;
imm32 r2, 0x34c45515;
imm32 r3, 0x46d67717;
imm32 r4, 0x56e8891b;
imm32 r5, 0x67f9ab1d;
imm32 r6, 0x74445515;
imm32 r7, 0x86687777;
R0.L = R4 - R0 (RND12);
R1.L = R4 - R1 (RND12);
R2.L = R4 - R2 (RND12);
R3.L = R4 - R3 (RND12);
R4.L = R4 - R4 (RND12);
R5.L = R4 - R5 (RND12);
R6.L = R4 - R6 (RND12);
R7.L = R4 - R7 (RND12);
CHECKREG r0, 0xa5677fff;
CHECKREG r1, 0x2b897fff;
CHECKREG r2, 0x34c47fff;
CHECKREG r3, 0x46d67fff;
CHECKREG r4, 0x56E80000;
CHECKREG r5, 0x67F98000;
CHECKREG r6, 0x74448000;
CHECKREG r7, 0x86687fff;
imm32 r0, 0xe5678911;
imm32 r1, 0x2789ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0xd6667717;
imm32 r4, 0x5ff8891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x744e5515;
imm32 r7, 0x8666a7b7;
R0.L = R5 - R0 (RND12);
R1.L = R5 - R1 (RND12);
R2.L = R5 - R2 (RND12);
R3.L = R5 - R3 (RND12);
R4.L = R5 - R4 (RND12);
R5.L = R5 - R5 (RND12);
R6.L = R5 - R6 (RND12);
R7.L = R5 - R7 (RND12);
CHECKREG r0, 0xE5677fff;
CHECKREG r1, 0x27897fff;
CHECKREG r2, 0x34447fff;
CHECKREG r3, 0xD6667fff;
CHECKREG r4, 0x5FF87912;
CHECKREG r5, 0x67890000;
CHECKREG r6, 0x744E8000;
CHECKREG r7, 0x86667fff;
imm32 r0, 0x15678911;
imm32 r1, 0x2789ae1d;
imm32 r2, 0x344455e5;
imm32 r3, 0x4666771d;
imm32 r4, 0x5678891b;
imm32 r5, 0x6789abdd;
imm32 r6, 0x74a45515;
imm32 r7, 0x866c77b7;
R0.L = R6 - R0 (RND12);
R1.L = R6 - R1 (RND12);
R2.L = R6 - R2 (RND12);
R3.L = R6 - R3 (RND12);
R4.L = R6 - R4 (RND12);
R5.L = R6 - R5 (RND12);
R6.L = R6 - R6 (RND12);
R7.L = R6 - R7 (RND12);
CHECKREG r0, 0x15677fff;
CHECKREG r1, 0x27897fff;
CHECKREG r2, 0x34447fff;
CHECKREG r3, 0x46667fff;
CHECKREG r4, 0x56787fff;
CHECKREG r5, 0x67897fff;
CHECKREG r6, 0x74A40000;
CHECKREG r7, 0x866C7fff;
imm32 r0, 0x25678911;
imm32 r1, 0x2389ab1d;
imm32 r2, 0x34445515;
imm32 r3, 0x46567717;
imm32 r4, 0x5678891b;
imm32 r5, 0x678dab1d;
imm32 r6, 0x7444b515;
imm32 r7, 0xb666a777;
R0.L = R7 - R0 (RND12);
R1.L = R7 - R1 (RND12);
R2.L = R7 - R2 (RND12);
R3.L = R7 - R3 (RND12);
R4.L = R7 - R4 (RND12);
R5.L = R7 - R5 (RND12);
R6.L = R7 - R6 (RND12);
R7.L = R7 - R7 (RND12);
CHECKREG r0, 0x25678000;
CHECKREG r1, 0x23898000;
CHECKREG r2, 0x34448000;
CHECKREG r3, 0x46568000;
CHECKREG r4, 0x56788000;
CHECKREG r5, 0x678D8000;
CHECKREG r6, 0x74448000;
CHECKREG r7, 0xB6660000;
imm32 r0, 0xaa678911;
imm32 r1, 0x27ddab1d;
imm32 r2, 0x344bb515;
imm32 r3, 0x46667717;
imm32 r4, 0x56dd891b;
imm32 r5, 0x6789ab1d;
imm32 r6, 0x7444bb15;
imm32 r7, 0x86ff7777;
R6.L = R2 - R3 (RND12);
R1.L = R4 - R5 (RND12);
R5.L = R7 - R2 (RND12);
R3.L = R0 - R0 (RND12);
R0.L = R3 - R4 (RND12);
R2.L = R5 - R7 (RND12);
R7.L = R6 - R7 (RND12);
R4.L = R1 - R6 (RND12);
CHECKREG r0, 0xAA678000;
CHECKREG r1, 0x27DD8000;
CHECKREG r2, 0x344B7fff;
CHECKREG r3, 0x46660000;
CHECKREG r4, 0x56DD8000;
CHECKREG r5, 0x67898000;
CHECKREG r6, 0x74448000;
CHECKREG r7, 0x86FF7fff;
imm32 r0, 0x95678911;
imm32 r1, 0x2d89ab1d;
imm32 r2, 0x34b45515;
imm32 r3, 0x46c67717;
imm32 r4, 0x567e891b;
imm32 r5, 0x678fab1d;
imm32 r6, 0x744e5515;
imm32 r7, 0x8b66a777;
R3.L = R4 - R0 (RND12);
R1.L = R6 - R3 (RND12);
R4.L = R3 - R2 (RND12);
R6.L = R7 - R1 (RND12);
R2.L = R5 - R4 (RND12);
R7.L = R2 - R7 (RND12);
R0.L = R1 - R6 (RND12);
R5.L = R0 - R5 (RND12);
CHECKREG r0, 0x95678000;
CHECKREG r1, 0x2D897fff;
CHECKREG r2, 0x34B47fff;
CHECKREG r3, 0x46C67fff;
CHECKREG r4, 0x567E7fff;
CHECKREG r5, 0x678F8000;
CHECKREG r6, 0x744E8000;
CHECKREG r7, 0x8B667FFF;
pass
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