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https://sourceware.org/git/binutils-gdb.git
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129 lines
2.4 KiB
ArmAsm
129 lines
2.4 KiB
ArmAsm
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//Original:/proj/frio/dv/testcases/core/c_dsp32alu_alhwx/c_dsp32alu_alhwx.dsp
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// Spec Reference: dsp32alu alhwx
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# mach: bfin
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.include "testutils.inc"
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start
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R0 = 0;
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ASTAT = R0;
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A1 = A0 = 0;
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imm32 r0, 0xa5678911;
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imm32 r1, 0xaa89ab1d;
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imm32 r2, 0xd4b45515;
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imm32 r3, 0xf66e7717;
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imm32 r4, 0xe567f91b;
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imm32 r5, 0x6789ae1d;
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imm32 r6, 0xb4445515;
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imm32 r7, 0x8666a7d7;
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A0.L = R0.L;
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A0.H = R0.H;
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A0.x = R1.L;
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R7 = A0.w;
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R6 = A0.x;
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R5.L = A0.x;
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A1.L = R4.L;
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A1.H = R4.H;
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A1.x = R3.L;
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R0 = A1.w;
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R1 = A1.x;
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R2.L = A1.x;
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CHECKREG r0, 0xE567F91B;
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CHECKREG r1, 0x00000017;
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CHECKREG r2, 0xD4B40017;
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CHECKREG r3, 0xF66E7717;
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CHECKREG r4, 0xE567F91B;
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CHECKREG r5, 0x6789001D;
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CHECKREG r6, 0x0000001D;
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CHECKREG r7, 0xA5678911;
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imm32 r0, 0xe5678911;
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imm32 r1, 0xaa89ab1d;
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imm32 r2, 0xdfb45515;
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imm32 r3, 0xf66e7717;
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imm32 r4, 0xe5d7f91b;
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imm32 r5, 0x67e9ae1d;
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imm32 r6, 0xb4445515;
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imm32 r7, 0x866aa7b7;
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A0.L = R1.L;
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A0.H = R1.H;
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A0.x = R2.L;
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R5 = A0.w;
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R7 = A0.x;
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R6.L = A0.x;
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A1.L = R3.L;
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A1.H = R3.H;
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A1.x = R4.L;
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R1 = A1.w;
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R2 = A1.x;
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R0.L = A1.x;
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CHECKREG r0, 0xE567001B;
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CHECKREG r1, 0xF66E7717;
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CHECKREG r2, 0x0000001B;
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CHECKREG r3, 0xF66E7717;
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CHECKREG r4, 0xE5D7F91B;
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CHECKREG r5, 0xAA89AB1D;
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CHECKREG r6, 0xB4440015;
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CHECKREG r7, 0x00000015;
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imm32 r0, 0x35678911;
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imm32 r1, 0xa489ab1d;
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imm32 r2, 0xd4545515;
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imm32 r3, 0xf6667717;
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imm32 r4, 0x9567f91b;
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imm32 r5, 0x6a89ae1d;
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imm32 r6, 0xb4445515;
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imm32 r7, 0x8666a7d7;
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A0.L = R3.L;
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A0.H = R3.H;
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A0.x = R4.L;
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R0 = A0.w;
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R1 = A0.x;
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R2.L = A0.x;
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A1.L = R5.L;
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A1.H = R6.H;
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A1.x = R7.L;
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R7 = A1.w;
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R5 = A1.x;
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R5.L = A1.x;
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CHECKREG r0, 0xF6667717;
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CHECKREG r1, 0x0000001B;
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CHECKREG r2, 0xD454001B;
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CHECKREG r3, 0xF6667717;
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CHECKREG r4, 0x9567F91B;
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CHECKREG r5, 0xffffffD7;
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CHECKREG r6, 0xB4445515;
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CHECKREG r7, 0xB444AE1D;
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imm32 r0, 0xd5678911;
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imm32 r1, 0x2a89ab1d;
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imm32 r2, 0xd3b45515;
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imm32 r3, 0xf66e7717;
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imm32 r4, 0xe5d7f91b;
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imm32 r5, 0x67e9ae1d;
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imm32 r6, 0xb4445515;
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imm32 r7, 0x889aa7b7;
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A0.L = R4.L;
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A0.H = R5.H;
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A0.x = R6.L;
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R1 = A0.w;
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R2 = A0.x;
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R3.L = A0.x;
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A1.L = R0.L;
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A1.H = R0.H;
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A1.x = R7.L;
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R4 = A1.w;
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R5 = A1.x;
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R6.L = A1.x;
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CHECKREG r0, 0xD5678911;
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CHECKREG r1, 0x67E9F91B;
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CHECKREG r2, 0x00000015;
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CHECKREG r3, 0xF66E0015;
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CHECKREG r4, 0xD5678911;
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CHECKREG r5, 0xffffffB7;
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CHECKREG r6, 0xB444ffB7;
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CHECKREG r7, 0x889AA7B7;
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pass
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